1 /*****************************************************************************
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4 * Portable Hitachi SH-2 (SH7600 family) emulator
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6 * Copyright Juergen Buchmueller <pullmoll@t-online.de>,
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7 * all rights reserved.
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9 * - This source code is released as freeware for non-commercial purposes.
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10 * - You are free to use and redistribute this code in modified or
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11 * unmodified form, provided you list me in the credits.
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12 * - If you modify this source code, you must add a notice to each modified
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13 * source file that it has been changed. If you're a nice person, you
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14 * will clearly mark each change too. :)
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15 * - If you wish to use this for commercial purposes, please contact me at
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16 * pullmoll@t-online.de
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17 * - The author of this copywritten work reserves the right to change the
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18 * terms of its usage and license at any time, including retroactively
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19 * - This entire notice must remain in the source code.
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21 * This work is based on <tiraniddo@hotmail.com> C/C++ implementation of
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22 * the SH-2 CPU core and was adapted to the MAME CPU core requirements.
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23 * Thanks also go to Chuck Mason <chukjr@sundail.net> and Olivier Galibert
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24 * <galibert@pobox.com> for letting me peek into their SEMU code :-)
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26 *****************************************************************************/
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28 /*****************************************************************************
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30 20130129 Angelo Salese
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31 - added illegal opcode exception handling, side effect of some Saturn games
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32 on loading like Feda or Falcom Classics Vol. 1
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33 (i.e. Master CPU Incautiously transfers memory from CD to work RAM H, and
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34 wipes out Slave CPU program code too while at it).
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36 20051129 Mariusz Wojcieszek
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37 - introduced memory_decrypted_read_word() for opcode fetching
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39 20050813 Mariusz Wojcieszek
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40 - fixed 64 bit / 32 bit division in division unit
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42 20031015 O. Galibert
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43 - dma fixes, thanks to sthief
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45 20031013 O. Galibert, A. Giles
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47 - multi-cpu simplifications
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49 20030915 O. Galibert
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50 - fix DMA1 irq vector
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51 - ignore writes to DRCRx
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52 - fix cpu number issues
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53 - fix slave/master recognition
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54 - fix wrong-cpu-in-context problem with the timers
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56 20021020 O. Galibert
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57 - DMA implementation, lightly tested
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58 - delay slot in debugger fixed
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59 - add divide box mirrors
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60 - Nicola-ify the indentation
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61 - Uncrapify sh2_internal_*
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62 - Put back nmi support that had been lost somehow
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65 - Initial SH2 internal timers implementation, based on code by O. Galibert.
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66 Makes music work in galspanic4/s/s2, panic street, cyvern, other SKNS games.
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67 - Fix to external division, thanks to "spice" on the E2J board.
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68 Corrects behavior of s1945ii turret boss.
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70 20020302 Olivier Galibert (galibert@mame.net)
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71 - Fixed interrupt in delay slot
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78 - Fixed external division
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80 20020225 Olivier Galibert (galibert@mame.net)
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81 - Fixed interrupt handling
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83 20010207 Sylvain Glaize (mokona@puupuu.org)
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85 - Bug fix in INLINE void MOVBM(UINT32 m, UINT32 n) (see comment)
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86 - Support of full 32 bit addressing (RB, RW, RL and WB, WW, WL functions)
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87 reason : when the two high bits of the address are set, access is
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88 done directly in the cache data array. The SUPER KANEKO NOVA SYSTEM
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89 sets the stack pointer here, using these addresses as usual RAM access.
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91 No real cache support has been added.
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92 - Read/Write memory format correction (_bew to _bedw) (see also SH2
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93 definition in cpuintrf.c and DasmSH2(..) in sh2dasm.c )
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95 20010623 James Forshaw (TyRaNiD@totalise.net)
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97 - Modified operation of sh2_exception. Done cause mame irq system is stupid, and
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98 doesnt really seem designed for any more than 8 interrupt lines.
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100 20010701 James Forshaw (TyRaNiD@totalise.net)
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102 - Fixed DIV1 operation. Q bit now correctly generated
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104 20020218 Added save states (mokona@puupuu.org)
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106 *****************************************************************************/
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108 //#include "debugger.h"
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110 //#include "sh2comn.h"
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111 #define INLINE static
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113 //CPU_DISASSEMBLE( sh2 );
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117 /* speed up delay loops, bail out of tight loops */
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118 #define BUSY_LOOP_HACKS 1
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122 #define LOG(x) do { if (VERBOSE) logerror x; } while (0)
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125 INLINE UINT8 RB(sh2_state *sh2, offs_t A)
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127 if (A >= 0xe0000000)
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128 return sh2_internal_r(*sh2->internal, (A & 0x1fc)>>2, 0xff << (((~A) & 3)*8)) >> (((~A) & 3)*8);
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130 if (A >= 0xc0000000)
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131 return sh2->program->read_byte(A);
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133 if (A >= 0x40000000)
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136 return sh2->program->read_byte(A & AM);
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139 INLINE UINT16 RW(sh2_state *sh2, offs_t A)
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141 if (A >= 0xe0000000)
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142 return sh2_internal_r(*sh2->internal, (A & 0x1fc)>>2, 0xffff << (((~A) & 2)*8)) >> (((~A) & 2)*8);
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144 if (A >= 0xc0000000)
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145 return sh2->program->read_word(A);
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147 if (A >= 0x40000000)
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150 return sh2->program->read_word(A & AM);
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153 INLINE UINT32 RL(sh2_state *sh2, offs_t A)
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155 if (A >= 0xe0000000)
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156 return sh2_internal_r(*sh2->internal, (A & 0x1fc)>>2, 0xffffffff);
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158 if (A >= 0xc0000000)
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159 return sh2->program->read_dword(A);
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161 if (A >= 0x40000000)
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164 return sh2->program->read_dword(A & AM);
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167 INLINE void WB(sh2_state *sh2, offs_t A, UINT8 V)
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169 if (A >= 0xe0000000)
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171 sh2_internal_w(*sh2->internal, (A & 0x1fc)>>2, V << (((~A) & 3)*8), 0xff << (((~A) & 3)*8));
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175 if (A >= 0xc0000000)
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177 sh2->program->write_byte(A,V);
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181 if (A >= 0x40000000)
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184 sh2->program->write_byte(A & AM,V);
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187 INLINE void WW(sh2_state *sh2, offs_t A, UINT16 V)
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189 if (A >= 0xe0000000)
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191 sh2_internal_w(*sh2->internal, (A & 0x1fc)>>2, V << (((~A) & 2)*8), 0xffff << (((~A) & 2)*8));
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195 if (A >= 0xc0000000)
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197 sh2->program->write_word(A,V);
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201 if (A >= 0x40000000)
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204 sh2->program->write_word(A & AM,V);
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207 INLINE void WL(sh2_state *sh2, offs_t A, UINT32 V)
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209 if (A >= 0xe0000000)
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211 sh2_internal_w(*sh2->internal, (A & 0x1fc)>>2, V, 0xffffffff);
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215 if (A >= 0xc0000000)
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217 sh2->program->write_dword(A,V);
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221 if (A >= 0x40000000)
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224 sh2->program->write_dword(A & AM,V);
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228 /* code cycles t-bit
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229 * 0011 nnnn mmmm 1100 1 -
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232 INLINE void ADD(sh2_state *sh2, UINT32 m, UINT32 n)
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234 sh2->r[n] += sh2->r[m];
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237 /* code cycles t-bit
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238 * 0111 nnnn iiii iiii 1 -
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241 INLINE void ADDI(sh2_state *sh2, UINT32 i, UINT32 n)
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243 sh2->r[n] += (INT32)(INT16)(INT8)i;
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246 /* code cycles t-bit
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247 * 0011 nnnn mmmm 1110 1 carry
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250 INLINE void ADDC(sh2_state *sh2, UINT32 m, UINT32 n)
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254 tmp1 = sh2->r[n] + sh2->r[m];
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256 sh2->r[n] = tmp1 + (sh2->sr & T);
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261 if (tmp1 > sh2->r[n])
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265 /* code cycles t-bit
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266 * 0011 nnnn mmmm 1111 1 overflow
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269 INLINE void ADDV(sh2_state *sh2, UINT32 m, UINT32 n)
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271 INT32 dest, src, ans;
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273 if ((INT32) sh2->r[n] >= 0)
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277 if ((INT32) sh2->r[m] >= 0)
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282 sh2->r[n] += sh2->r[m];
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283 if ((INT32) sh2->r[n] >= 0)
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288 if (src == 0 || src == 2)
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299 /* code cycles t-bit
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300 * 0010 nnnn mmmm 1001 1 -
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303 INLINE void AND(sh2_state *sh2, UINT32 m, UINT32 n)
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305 sh2->r[n] &= sh2->r[m];
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309 /* code cycles t-bit
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310 * 1100 1001 iiii iiii 1 -
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313 INLINE void ANDI(sh2_state *sh2, UINT32 i)
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318 /* code cycles t-bit
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319 * 1100 1101 iiii iiii 1 -
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320 * AND.B #imm,@(R0,GBR)
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322 INLINE void ANDM(sh2_state *sh2, UINT32 i)
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326 sh2->ea = sh2->gbr + sh2->r[0];
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327 temp = i & RB( sh2, sh2->ea );
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328 WB( sh2, sh2->ea, temp );
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332 /* code cycles t-bit
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333 * 1000 1011 dddd dddd 3/1 -
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336 INLINE void BF(sh2_state *sh2, UINT32 d)
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338 if ((sh2->sr & T) == 0)
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340 INT32 disp = ((INT32)d << 24) >> 24;
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341 sh2->pc = sh2->ea = sh2->pc + disp * 2 + 2;
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346 /* code cycles t-bit
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347 * 1000 1111 dddd dddd 3/1 -
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350 INLINE void BFS(sh2_state *sh2, UINT32 d)
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352 if ((sh2->sr & T) == 0)
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354 INT32 disp = ((INT32)d << 24) >> 24;
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355 sh2->delay = sh2->pc;
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356 sh2->pc = sh2->ea = sh2->pc + disp * 2 + 2;
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361 /* code cycles t-bit
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362 * 1010 dddd dddd dddd 2 -
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365 INLINE void BRA(sh2_state *sh2, UINT32 d)
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367 INT32 disp = ((INT32)d << 20) >> 20;
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369 #if BUSY_LOOP_HACKS
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372 UINT32 next_opcode = RW( sh2, sh2->ppc & AM );
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376 if (next_opcode == 0x0009)
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377 sh2->icount %= 3; /* cycles for BRA $ and NOP taken (3) */
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380 sh2->delay = sh2->pc;
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381 sh2->pc = sh2->ea = sh2->pc + disp * 2 + 2;
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385 /* code cycles t-bit
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386 * 0000 mmmm 0010 0011 2 -
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389 INLINE void BRAF(sh2_state *sh2, UINT32 m)
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391 sh2->delay = sh2->pc;
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392 sh2->pc += sh2->r[m] + 2;
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396 /* code cycles t-bit
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397 * 1011 dddd dddd dddd 2 -
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400 INLINE void BSR(sh2_state *sh2, UINT32 d)
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402 INT32 disp = ((INT32)d << 20) >> 20;
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404 sh2->pr = sh2->pc + 2;
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405 sh2->delay = sh2->pc;
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406 sh2->pc = sh2->ea = sh2->pc + disp * 2 + 2;
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410 /* code cycles t-bit
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411 * 0000 mmmm 0000 0011 2 -
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414 INLINE void BSRF(sh2_state *sh2, UINT32 m)
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416 sh2->pr = sh2->pc + 2;
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417 sh2->delay = sh2->pc;
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418 sh2->pc += sh2->r[m] + 2;
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422 /* code cycles t-bit
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423 * 1000 1001 dddd dddd 3/1 -
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426 INLINE void BT(sh2_state *sh2, UINT32 d)
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428 if ((sh2->sr & T) != 0)
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430 INT32 disp = ((INT32)d << 24) >> 24;
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431 sh2->pc = sh2->ea = sh2->pc + disp * 2 + 2;
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436 /* code cycles t-bit
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437 * 1000 1101 dddd dddd 2/1 -
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440 INLINE void BTS(sh2_state *sh2, UINT32 d)
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442 if ((sh2->sr & T) != 0)
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444 INT32 disp = ((INT32)d << 24) >> 24;
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445 sh2->delay = sh2->pc;
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446 sh2->pc = sh2->ea = sh2->pc + disp * 2 + 2;
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451 /* code cycles t-bit
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452 * 0000 0000 0010 1000 1 -
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455 INLINE void CLRMAC(sh2_state *sh2)
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461 /* code cycles t-bit
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462 * 0000 0000 0000 1000 1 -
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465 INLINE void CLRT(sh2_state *sh2)
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470 /* code cycles t-bit
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471 * 0011 nnnn mmmm 0000 1 comparison result
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474 INLINE void CMPEQ(sh2_state *sh2, UINT32 m, UINT32 n)
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476 if (sh2->r[n] == sh2->r[m])
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482 /* code cycles t-bit
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483 * 0011 nnnn mmmm 0011 1 comparison result
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486 INLINE void CMPGE(sh2_state *sh2, UINT32 m, UINT32 n)
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488 if ((INT32) sh2->r[n] >= (INT32) sh2->r[m])
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494 /* code cycles t-bit
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495 * 0011 nnnn mmmm 0111 1 comparison result
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498 INLINE void CMPGT(sh2_state *sh2, UINT32 m, UINT32 n)
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500 if ((INT32) sh2->r[n] > (INT32) sh2->r[m])
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506 /* code cycles t-bit
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507 * 0011 nnnn mmmm 0110 1 comparison result
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510 INLINE void CMPHI(sh2_state *sh2, UINT32 m, UINT32 n)
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512 if ((UINT32) sh2->r[n] > (UINT32) sh2->r[m])
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518 /* code cycles t-bit
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519 * 0011 nnnn mmmm 0010 1 comparison result
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522 INLINE void CMPHS(sh2_state *sh2, UINT32 m, UINT32 n)
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524 if ((UINT32) sh2->r[n] >= (UINT32) sh2->r[m])
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531 /* code cycles t-bit
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532 * 0100 nnnn 0001 0101 1 comparison result
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535 INLINE void CMPPL(sh2_state *sh2, UINT32 n)
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537 if ((INT32) sh2->r[n] > 0)
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543 /* code cycles t-bit
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544 * 0100 nnnn 0001 0001 1 comparison result
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547 INLINE void CMPPZ(sh2_state *sh2, UINT32 n)
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549 if ((INT32) sh2->r[n] >= 0)
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555 /* code cycles t-bit
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556 * 0010 nnnn mmmm 1100 1 comparison result
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559 INLINE void CMPSTR(sh2_state *sh2, UINT32 m, UINT32 n)
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562 INT32 HH, HL, LH, LL;
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563 temp = sh2->r[n] ^ sh2->r[m];
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564 HH = (temp >> 24) & 0xff;
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565 HL = (temp >> 16) & 0xff;
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566 LH = (temp >> 8) & 0xff;
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568 if (HH && HL && LH && LL)
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575 /* code cycles t-bit
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576 * 1000 1000 iiii iiii 1 comparison result
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579 INLINE void CMPIM(sh2_state *sh2, UINT32 i)
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581 UINT32 imm = (UINT32)(INT32)(INT16)(INT8)i;
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583 if (sh2->r[0] == imm)
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589 /* code cycles t-bit
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590 * 0010 nnnn mmmm 0111 1 calculation result
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593 INLINE void DIV0S(sh2_state *sh2, UINT32 m, UINT32 n)
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595 if ((sh2->r[n] & 0x80000000) == 0)
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599 if ((sh2->r[m] & 0x80000000) == 0)
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603 if ((sh2->r[m] ^ sh2->r[n]) & 0x80000000)
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609 /* code cycles t-bit
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610 * 0000 0000 0001 1001 1 0
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613 INLINE void DIV0U(sh2_state *sh2)
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615 sh2->sr &= ~(M | Q | T);
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618 /* code cycles t-bit
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619 * 0011 nnnn mmmm 0100 1 calculation result
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622 INLINE void DIV1(sh2_state *sh2, UINT32 m, UINT32 n)
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627 old_q = sh2->sr & Q;
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628 if (0x80000000 & sh2->r[n])
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633 sh2->r[n] = (sh2->r[n] << 1) | (sh2->sr & T);
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637 if (!(sh2->sr & M))
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640 sh2->r[n] -= sh2->r[m];
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642 if(sh2->r[n] > tmp0)
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647 if(sh2->r[n] > tmp0)
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655 sh2->r[n] += sh2->r[m];
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658 if(sh2->r[n] < tmp0)
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665 if(sh2->r[n] < tmp0)
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674 if (!(sh2->sr & M))
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677 sh2->r[n] += sh2->r[m];
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679 if(sh2->r[n] < tmp0)
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684 if(sh2->r[n] < tmp0)
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692 sh2->r[n] -= sh2->r[m];
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694 if(sh2->r[n] > tmp0)
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699 if(sh2->r[n] > tmp0)
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706 tmp0 = (sh2->sr & (Q | M));
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707 if((!tmp0) || (tmp0 == 0x300)) /* if Q == M set T else clear T */
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713 /* DMULS.L Rm,Rn */
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714 INLINE void DMULS(sh2_state *sh2, UINT32 m, UINT32 n)
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716 UINT32 RnL, RnH, RmL, RmH, Res0, Res1, Res2;
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717 UINT32 temp0, temp1, temp2, temp3;
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718 INT32 tempm, tempn, fnLmL;
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720 tempn = (INT32) sh2->r[n];
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721 tempm = (INT32) sh2->r[m];
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726 if ((INT32) (sh2->r[n] ^ sh2->r[m]) < 0)
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730 temp1 = (UINT32) tempn;
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731 temp2 = (UINT32) tempm;
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732 RnL = temp1 & 0x0000ffff;
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733 RnH = (temp1 >> 16) & 0x0000ffff;
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734 RmL = temp2 & 0x0000ffff;
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735 RmH = (temp2 >> 16) & 0x0000ffff;
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741 Res1 = temp1 + temp2;
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743 Res2 += 0x00010000;
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744 temp1 = (Res1 << 16) & 0xffff0000;
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745 Res0 = temp0 + temp1;
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748 Res2 = Res2 + ((Res1 >> 16) & 0x0000ffff) + temp3;
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755 Res0 = (~Res0) + 1;
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762 /* DMULU.L Rm,Rn */
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763 INLINE void DMULU(sh2_state *sh2, UINT32 m, UINT32 n)
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765 UINT32 RnL, RnH, RmL, RmH, Res0, Res1, Res2;
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766 UINT32 temp0, temp1, temp2, temp3;
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768 RnL = sh2->r[n] & 0x0000ffff;
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769 RnH = (sh2->r[n] >> 16) & 0x0000ffff;
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770 RmL = sh2->r[m] & 0x0000ffff;
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771 RmH = (sh2->r[m] >> 16) & 0x0000ffff;
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777 Res1 = temp1 + temp2;
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779 Res2 += 0x00010000;
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780 temp1 = (Res1 << 16) & 0xffff0000;
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781 Res0 = temp0 + temp1;
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784 Res2 = Res2 + ((Res1 >> 16) & 0x0000ffff) + temp3;
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791 INLINE void DT(sh2_state *sh2, UINT32 n)
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794 if (sh2->r[n] == 0)
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798 #if BUSY_LOOP_HACKS
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800 UINT32 next_opcode = RW( sh2, sh2->ppc & AM );
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804 if (next_opcode == 0x8bfd)
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806 while (sh2->r[n] > 1 && sh2->icount > 4)
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809 sh2->icount -= 4; /* cycles for DT (1) and BF taken (3) */
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817 INLINE void EXTSB(sh2_state *sh2, UINT32 m, UINT32 n)
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819 sh2->r[n] = ((INT32)sh2->r[m] << 24) >> 24;
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823 INLINE void EXTSW(sh2_state *sh2, UINT32 m, UINT32 n)
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825 sh2->r[n] = ((INT32)sh2->r[m] << 16) >> 16;
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829 INLINE void EXTUB(sh2_state *sh2, UINT32 m, UINT32 n)
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831 sh2->r[n] = sh2->r[m] & 0x000000ff;
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835 INLINE void EXTUW(sh2_state *sh2, UINT32 m, UINT32 n)
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837 sh2->r[n] = sh2->r[m] & 0x0000ffff;
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841 INLINE void ILLEGAL(sh2_state *sh2)
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843 logerror("SH2: Illegal opcode at %08x\n", sh2->pc - 2);
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845 WL( sh2, sh2->r[15], sh2->sr ); /* push SR onto stack */
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847 WL( sh2, sh2->r[15], sh2->pc - 2 ); /* push PC onto stack */
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850 sh2->pc = RL( sh2, sh2->vbr + 4 * 4 );
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852 /* TODO: timing is a guess */
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858 INLINE void JMP(sh2_state *sh2, UINT32 m)
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860 sh2->delay = sh2->pc;
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861 sh2->pc = sh2->ea = sh2->r[m];
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866 INLINE void JSR(sh2_state *sh2, UINT32 m)
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868 sh2->delay = sh2->pc;
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869 sh2->pr = sh2->pc + 2;
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870 sh2->pc = sh2->ea = sh2->r[m];
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876 INLINE void LDCSR(sh2_state *sh2, UINT32 m)
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878 sh2->sr = sh2->r[m] & FLAGS;
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883 INLINE void LDCGBR(sh2_state *sh2, UINT32 m)
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885 sh2->gbr = sh2->r[m];
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889 INLINE void LDCVBR(sh2_state *sh2, UINT32 m)
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891 sh2->vbr = sh2->r[m];
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894 /* LDC.L @Rm+,SR */
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895 INLINE void LDCMSR(sh2_state *sh2, UINT32 m)
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897 sh2->ea = sh2->r[m];
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898 sh2->sr = RL( sh2, sh2->ea ) & FLAGS;
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904 /* LDC.L @Rm+,GBR */
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905 INLINE void LDCMGBR(sh2_state *sh2, UINT32 m)
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907 sh2->ea = sh2->r[m];
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908 sh2->gbr = RL( sh2, sh2->ea );
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913 /* LDC.L @Rm+,VBR */
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914 INLINE void LDCMVBR(sh2_state *sh2, UINT32 m)
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916 sh2->ea = sh2->r[m];
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917 sh2->vbr = RL( sh2, sh2->ea );
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923 INLINE void LDSMACH(sh2_state *sh2, UINT32 m)
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925 sh2->mach = sh2->r[m];
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929 INLINE void LDSMACL(sh2_state *sh2, UINT32 m)
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931 sh2->macl = sh2->r[m];
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935 INLINE void LDSPR(sh2_state *sh2, UINT32 m)
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937 sh2->pr = sh2->r[m];
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940 /* LDS.L @Rm+,MACH */
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941 INLINE void LDSMMACH(sh2_state *sh2, UINT32 m)
\r
943 sh2->ea = sh2->r[m];
\r
944 sh2->mach = RL( sh2, sh2->ea );
\r
948 /* LDS.L @Rm+,MACL */
\r
949 INLINE void LDSMMACL(sh2_state *sh2, UINT32 m)
\r
951 sh2->ea = sh2->r[m];
\r
952 sh2->macl = RL( sh2, sh2->ea );
\r
956 /* LDS.L @Rm+,PR */
\r
957 INLINE void LDSMPR(sh2_state *sh2, UINT32 m)
\r
959 sh2->ea = sh2->r[m];
\r
960 sh2->pr = RL( sh2, sh2->ea );
\r
964 /* MAC.L @Rm+,@Rn+ */
\r
965 INLINE void MAC_L(sh2_state *sh2, UINT32 m, UINT32 n)
\r
967 UINT32 RnL, RnH, RmL, RmH, Res0, Res1, Res2;
\r
968 UINT32 temp0, temp1, temp2, temp3;
\r
969 INT32 tempm, tempn, fnLmL;
\r
971 tempn = (INT32) RL( sh2, sh2->r[n] );
\r
973 tempm = (INT32) RL( sh2, sh2->r[m] );
\r
975 if ((INT32) (tempn ^ tempm) < 0)
\r
983 temp1 = (UINT32) tempn;
\r
984 temp2 = (UINT32) tempm;
\r
985 RnL = temp1 & 0x0000ffff;
\r
986 RnH = (temp1 >> 16) & 0x0000ffff;
\r
987 RmL = temp2 & 0x0000ffff;
\r
988 RmH = (temp2 >> 16) & 0x0000ffff;
\r
994 Res1 = temp1 + temp2;
\r
996 Res2 += 0x00010000;
\r
997 temp1 = (Res1 << 16) & 0xffff0000;
\r
998 Res0 = temp0 + temp1;
\r
1001 Res2 = Res2 + ((Res1 >> 16) & 0x0000ffff) + temp3;
\r
1008 Res0 = (~Res0) + 1;
\r
1012 Res0 = sh2->macl + Res0;
\r
1013 if (sh2->macl > Res0)
\r
1015 Res2 += (sh2->mach & 0x0000ffff);
\r
1016 if (((INT32) Res2 < 0) && (Res2 < 0xffff8000))
\r
1018 Res2 = 0x00008000;
\r
1019 Res0 = 0x00000000;
\r
1021 else if (((INT32) Res2 > 0) && (Res2 > 0x00007fff))
\r
1023 Res2 = 0x00007fff;
\r
1024 Res0 = 0xffffffff;
\r
1031 Res0 = sh2->macl + Res0;
\r
1032 if (sh2->macl > Res0)
\r
1034 Res2 += sh2->mach;
\r
1041 /* MAC.W @Rm+,@Rn+ */
\r
1042 INLINE void MAC_W(sh2_state *sh2, UINT32 m, UINT32 n)
\r
1044 INT32 tempm, tempn, dest, src, ans;
\r
1047 tempn = (INT32) RW( sh2, sh2->r[n] );
\r
1049 tempm = (INT32) RW( sh2, sh2->r[m] );
\r
1051 templ = sh2->macl;
\r
1052 tempm = ((INT32) (short) tempn * (INT32) (short) tempm);
\r
1053 if ((INT32) sh2->macl >= 0)
\r
1057 if ((INT32) tempm >= 0)
\r
1065 tempn = 0xffffffff;
\r
1068 sh2->macl += tempm;
\r
1069 if ((INT32) sh2->macl >= 0)
\r
1079 sh2->macl = 0x7fffffff;
\r
1081 sh2->macl = 0x80000000;
\r
1086 sh2->mach += tempn;
\r
1087 if (templ > sh2->macl)
\r
1094 INLINE void MOV(sh2_state *sh2, UINT32 m, UINT32 n)
\r
1096 sh2->r[n] = sh2->r[m];
\r
1099 /* MOV.B Rm,@Rn */
\r
1100 INLINE void MOVBS(sh2_state *sh2, UINT32 m, UINT32 n)
\r
1102 sh2->ea = sh2->r[n];
\r
1103 WB( sh2, sh2->ea, sh2->r[m] & 0x000000ff);
\r
1106 /* MOV.W Rm,@Rn */
\r
1107 INLINE void MOVWS(sh2_state *sh2, UINT32 m, UINT32 n)
\r
1109 sh2->ea = sh2->r[n];
\r
1110 WW( sh2, sh2->ea, sh2->r[m] & 0x0000ffff);
\r
1113 /* MOV.L Rm,@Rn */
\r
1114 INLINE void MOVLS(sh2_state *sh2, UINT32 m, UINT32 n)
\r
1116 sh2->ea = sh2->r[n];
\r
1117 WL( sh2, sh2->ea, sh2->r[m] );
\r
1120 /* MOV.B @Rm,Rn */
\r
1121 INLINE void MOVBL(sh2_state *sh2, UINT32 m, UINT32 n)
\r
1123 sh2->ea = sh2->r[m];
\r
1124 sh2->r[n] = (UINT32)(INT32)(INT16)(INT8) RB( sh2, sh2->ea );
\r
1127 /* MOV.W @Rm,Rn */
\r
1128 INLINE void MOVWL(sh2_state *sh2, UINT32 m, UINT32 n)
\r
1130 sh2->ea = sh2->r[m];
\r
1131 sh2->r[n] = (UINT32)(INT32)(INT16) RW( sh2, sh2->ea );
\r
1134 /* MOV.L @Rm,Rn */
\r
1135 INLINE void MOVLL(sh2_state *sh2, UINT32 m, UINT32 n)
\r
1137 sh2->ea = sh2->r[m];
\r
1138 sh2->r[n] = RL( sh2, sh2->ea );
\r
1141 /* MOV.B Rm,@-Rn */
\r
1142 INLINE void MOVBM(sh2_state *sh2, UINT32 m, UINT32 n)
\r
1144 /* SMG : bug fix, was reading sh2->r[n] */
\r
1145 UINT32 data = sh2->r[m] & 0x000000ff;
\r
1148 WB( sh2, sh2->r[n], data );
\r
1151 /* MOV.W Rm,@-Rn */
\r
1152 INLINE void MOVWM(sh2_state *sh2, UINT32 m, UINT32 n)
\r
1154 UINT32 data = sh2->r[m] & 0x0000ffff;
\r
1157 WW( sh2, sh2->r[n], data );
\r
1160 /* MOV.L Rm,@-Rn */
\r
1161 INLINE void MOVLM(sh2_state *sh2, UINT32 m, UINT32 n)
\r
1163 UINT32 data = sh2->r[m];
\r
1166 WL( sh2, sh2->r[n], data );
\r
1169 /* MOV.B @Rm+,Rn */
\r
1170 INLINE void MOVBP(sh2_state *sh2, UINT32 m, UINT32 n)
\r
1172 sh2->r[n] = (UINT32)(INT32)(INT16)(INT8) RB( sh2, sh2->r[m] );
\r
1177 /* MOV.W @Rm+,Rn */
\r
1178 INLINE void MOVWP(sh2_state *sh2, UINT32 m, UINT32 n)
\r
1180 sh2->r[n] = (UINT32)(INT32)(INT16) RW( sh2, sh2->r[m] );
\r
1185 /* MOV.L @Rm+,Rn */
\r
1186 INLINE void MOVLP(sh2_state *sh2, UINT32 m, UINT32 n)
\r
1188 sh2->r[n] = RL( sh2, sh2->r[m] );
\r
1193 /* MOV.B Rm,@(R0,Rn) */
\r
1194 INLINE void MOVBS0(sh2_state *sh2, UINT32 m, UINT32 n)
\r
1196 sh2->ea = sh2->r[n] + sh2->r[0];
\r
1197 WB( sh2, sh2->ea, sh2->r[m] & 0x000000ff );
\r
1200 /* MOV.W Rm,@(R0,Rn) */
\r
1201 INLINE void MOVWS0(sh2_state *sh2, UINT32 m, UINT32 n)
\r
1203 sh2->ea = sh2->r[n] + sh2->r[0];
\r
1204 WW( sh2, sh2->ea, sh2->r[m] & 0x0000ffff );
\r
1207 /* MOV.L Rm,@(R0,Rn) */
\r
1208 INLINE void MOVLS0(sh2_state *sh2, UINT32 m, UINT32 n)
\r
1210 sh2->ea = sh2->r[n] + sh2->r[0];
\r
1211 WL( sh2, sh2->ea, sh2->r[m] );
\r
1214 /* MOV.B @(R0,Rm),Rn */
\r
1215 INLINE void MOVBL0(sh2_state *sh2, UINT32 m, UINT32 n)
\r
1217 sh2->ea = sh2->r[m] + sh2->r[0];
\r
1218 sh2->r[n] = (UINT32)(INT32)(INT16)(INT8) RB( sh2, sh2->ea );
\r
1221 /* MOV.W @(R0,Rm),Rn */
\r
1222 INLINE void MOVWL0(sh2_state *sh2, UINT32 m, UINT32 n)
\r
1224 sh2->ea = sh2->r[m] + sh2->r[0];
\r
1225 sh2->r[n] = (UINT32)(INT32)(INT16) RW( sh2, sh2->ea );
\r
1228 /* MOV.L @(R0,Rm),Rn */
\r
1229 INLINE void MOVLL0(sh2_state *sh2, UINT32 m, UINT32 n)
\r
1231 sh2->ea = sh2->r[m] + sh2->r[0];
\r
1232 sh2->r[n] = RL( sh2, sh2->ea );
\r
1236 INLINE void MOVI(sh2_state *sh2, UINT32 i, UINT32 n)
\r
1238 sh2->r[n] = (UINT32)(INT32)(INT16)(INT8) i;
\r
1241 /* MOV.W @(disp8,PC),Rn */
\r
1242 INLINE void MOVWI(sh2_state *sh2, UINT32 d, UINT32 n)
\r
1244 UINT32 disp = d & 0xff;
\r
1245 sh2->ea = sh2->pc + disp * 2 + 2;
\r
1246 sh2->r[n] = (UINT32)(INT32)(INT16) RW( sh2, sh2->ea );
\r
1249 /* MOV.L @(disp8,PC),Rn */
\r
1250 INLINE void MOVLI(sh2_state *sh2, UINT32 d, UINT32 n)
\r
1252 UINT32 disp = d & 0xff;
\r
1253 sh2->ea = ((sh2->pc + 2) & ~3) + disp * 4;
\r
1254 sh2->r[n] = RL( sh2, sh2->ea );
\r
1257 /* MOV.B @(disp8,GBR),R0 */
\r
1258 INLINE void MOVBLG(sh2_state *sh2, UINT32 d)
\r
1260 UINT32 disp = d & 0xff;
\r
1261 sh2->ea = sh2->gbr + disp;
\r
1262 sh2->r[0] = (UINT32)(INT32)(INT16)(INT8) RB( sh2, sh2->ea );
\r
1265 /* MOV.W @(disp8,GBR),R0 */
\r
1266 INLINE void MOVWLG(sh2_state *sh2, UINT32 d)
\r
1268 UINT32 disp = d & 0xff;
\r
1269 sh2->ea = sh2->gbr + disp * 2;
\r
1270 sh2->r[0] = (INT32)(INT16) RW( sh2, sh2->ea );
\r
1273 /* MOV.L @(disp8,GBR),R0 */
\r
1274 INLINE void MOVLLG(sh2_state *sh2, UINT32 d)
\r
1276 UINT32 disp = d & 0xff;
\r
1277 sh2->ea = sh2->gbr + disp * 4;
\r
1278 sh2->r[0] = RL( sh2, sh2->ea );
\r
1281 /* MOV.B R0,@(disp8,GBR) */
\r
1282 INLINE void MOVBSG(sh2_state *sh2, UINT32 d)
\r
1284 UINT32 disp = d & 0xff;
\r
1285 sh2->ea = sh2->gbr + disp;
\r
1286 WB( sh2, sh2->ea, sh2->r[0] & 0x000000ff );
\r
1289 /* MOV.W R0,@(disp8,GBR) */
\r
1290 INLINE void MOVWSG(sh2_state *sh2, UINT32 d)
\r
1292 UINT32 disp = d & 0xff;
\r
1293 sh2->ea = sh2->gbr + disp * 2;
\r
1294 WW( sh2, sh2->ea, sh2->r[0] & 0x0000ffff );
\r
1297 /* MOV.L R0,@(disp8,GBR) */
\r
1298 INLINE void MOVLSG(sh2_state *sh2, UINT32 d)
\r
1300 UINT32 disp = d & 0xff;
\r
1301 sh2->ea = sh2->gbr + disp * 4;
\r
1302 WL( sh2, sh2->ea, sh2->r[0] );
\r
1305 /* MOV.B R0,@(disp4,Rn) */
\r
1306 INLINE void MOVBS4(sh2_state *sh2, UINT32 d, UINT32 n)
\r
1308 UINT32 disp = d & 0x0f;
\r
1309 sh2->ea = sh2->r[n] + disp;
\r
1310 WB( sh2, sh2->ea, sh2->r[0] & 0x000000ff );
\r
1313 /* MOV.W R0,@(disp4,Rn) */
\r
1314 INLINE void MOVWS4(sh2_state *sh2, UINT32 d, UINT32 n)
\r
1316 UINT32 disp = d & 0x0f;
\r
1317 sh2->ea = sh2->r[n] + disp * 2;
\r
1318 WW( sh2, sh2->ea, sh2->r[0] & 0x0000ffff );
\r
1321 /* MOV.L Rm,@(disp4,Rn) */
\r
1322 INLINE void MOVLS4(sh2_state *sh2, UINT32 m, UINT32 d, UINT32 n)
\r
1324 UINT32 disp = d & 0x0f;
\r
1325 sh2->ea = sh2->r[n] + disp * 4;
\r
1326 WL( sh2, sh2->ea, sh2->r[m] );
\r
1329 /* MOV.B @(disp4,Rm),R0 */
\r
1330 INLINE void MOVBL4(sh2_state *sh2, UINT32 m, UINT32 d)
\r
1332 UINT32 disp = d & 0x0f;
\r
1333 sh2->ea = sh2->r[m] + disp;
\r
1334 sh2->r[0] = (UINT32)(INT32)(INT16)(INT8) RB( sh2, sh2->ea );
\r
1337 /* MOV.W @(disp4,Rm),R0 */
\r
1338 INLINE void MOVWL4(sh2_state *sh2, UINT32 m, UINT32 d)
\r
1340 UINT32 disp = d & 0x0f;
\r
1341 sh2->ea = sh2->r[m] + disp * 2;
\r
1342 sh2->r[0] = (UINT32)(INT32)(INT16) RW( sh2, sh2->ea );
\r
1345 /* MOV.L @(disp4,Rm),Rn */
\r
1346 INLINE void MOVLL4(sh2_state *sh2, UINT32 m, UINT32 d, UINT32 n)
\r
1348 UINT32 disp = d & 0x0f;
\r
1349 sh2->ea = sh2->r[m] + disp * 4;
\r
1350 sh2->r[n] = RL( sh2, sh2->ea );
\r
1353 /* MOVA @(disp8,PC),R0 */
\r
1354 INLINE void MOVA(sh2_state *sh2, UINT32 d)
\r
1356 UINT32 disp = d & 0xff;
\r
1357 sh2->ea = ((sh2->pc + 2) & ~3) + disp * 4;
\r
1358 sh2->r[0] = sh2->ea;
\r
1362 INLINE void MOVT(sh2_state *sh2, UINT32 n)
\r
1364 sh2->r[n] = sh2->sr & T;
\r
1368 INLINE void MULL(sh2_state *sh2, UINT32 m, UINT32 n)
\r
1370 sh2->macl = sh2->r[n] * sh2->r[m];
\r
1375 INLINE void MULS(sh2_state *sh2, UINT32 m, UINT32 n)
\r
1377 sh2->macl = (INT16) sh2->r[n] * (INT16) sh2->r[m];
\r
1381 INLINE void MULU(sh2_state *sh2, UINT32 m, UINT32 n)
\r
1383 sh2->macl = (UINT16) sh2->r[n] * (UINT16) sh2->r[m];
\r
1387 INLINE void NEG(sh2_state *sh2, UINT32 m, UINT32 n)
\r
1389 sh2->r[n] = 0 - sh2->r[m];
\r
1393 INLINE void NEGC(sh2_state *sh2, UINT32 m, UINT32 n)
\r
1398 sh2->r[n] = -temp - (sh2->sr & T);
\r
1399 if (temp || (sh2->sr & T))
\r
1406 INLINE void NOP(void)
\r
1411 INLINE void NOT(sh2_state *sh2, UINT32 m, UINT32 n)
\r
1413 sh2->r[n] = ~sh2->r[m];
\r
1417 INLINE void OR(sh2_state *sh2, UINT32 m, UINT32 n)
\r
1419 sh2->r[n] |= sh2->r[m];
\r
1423 INLINE void ORI(sh2_state *sh2, UINT32 i)
\r
1428 /* OR.B #imm,@(R0,GBR) */
\r
1429 INLINE void ORM(sh2_state *sh2, UINT32 i)
\r
1433 sh2->ea = sh2->gbr + sh2->r[0];
\r
1434 temp = RB( sh2, sh2->ea );
\r
1436 WB( sh2, sh2->ea, temp );
\r
1441 INLINE void ROTCL(sh2_state *sh2, UINT32 n)
\r
1445 temp = (sh2->r[n] >> 31) & T;
\r
1446 sh2->r[n] = (sh2->r[n] << 1) | (sh2->sr & T);
\r
1447 sh2->sr = (sh2->sr & ~T) | temp;
\r
1451 INLINE void ROTCR(sh2_state *sh2, UINT32 n)
\r
1454 temp = (sh2->sr & T) << 31;
\r
1455 if (sh2->r[n] & T)
\r
1459 sh2->r[n] = (sh2->r[n] >> 1) | temp;
\r
1463 INLINE void ROTL(sh2_state *sh2, UINT32 n)
\r
1465 sh2->sr = (sh2->sr & ~T) | ((sh2->r[n] >> 31) & T);
\r
1466 sh2->r[n] = (sh2->r[n] << 1) | (sh2->r[n] >> 31);
\r
1470 INLINE void ROTR(sh2_state *sh2, UINT32 n)
\r
1472 sh2->sr = (sh2->sr & ~T) | (sh2->r[n] & T);
\r
1473 sh2->r[n] = (sh2->r[n] >> 1) | (sh2->r[n] << 31);
\r
1477 INLINE void RTE(sh2_state *sh2)
\r
1479 sh2->ea = sh2->r[15];
\r
1480 sh2->delay = sh2->pc;
\r
1481 sh2->pc = RL( sh2, sh2->ea );
\r
1483 sh2->ea = sh2->r[15];
\r
1484 sh2->sr = RL( sh2, sh2->ea ) & FLAGS;
\r
1487 sh2->test_irq = 1;
\r
1491 INLINE void RTS(sh2_state *sh2)
\r
1493 sh2->delay = sh2->pc;
\r
1494 sh2->pc = sh2->ea = sh2->pr;
\r
1499 INLINE void SETT(sh2_state *sh2)
\r
1504 /* SHAL Rn (same as SHLL) */
\r
1505 INLINE void SHAL(sh2_state *sh2, UINT32 n)
\r
1507 sh2->sr = (sh2->sr & ~T) | ((sh2->r[n] >> 31) & T);
\r
1512 INLINE void SHAR(sh2_state *sh2, UINT32 n)
\r
1514 sh2->sr = (sh2->sr & ~T) | (sh2->r[n] & T);
\r
1515 sh2->r[n] = (UINT32)((INT32)sh2->r[n] >> 1);
\r
1518 /* SHLL Rn (same as SHAL) */
\r
1519 INLINE void SHLL(sh2_state *sh2, UINT32 n)
\r
1521 sh2->sr = (sh2->sr & ~T) | ((sh2->r[n] >> 31) & T);
\r
1526 INLINE void SHLL2(sh2_state *sh2, UINT32 n)
\r
1532 INLINE void SHLL8(sh2_state *sh2, UINT32 n)
\r
1538 INLINE void SHLL16(sh2_state *sh2, UINT32 n)
\r
1544 INLINE void SHLR(sh2_state *sh2, UINT32 n)
\r
1546 sh2->sr = (sh2->sr & ~T) | (sh2->r[n] & T);
\r
1551 INLINE void SHLR2(sh2_state *sh2, UINT32 n)
\r
1557 INLINE void SHLR8(sh2_state *sh2, UINT32 n)
\r
1563 INLINE void SHLR16(sh2_state *sh2, UINT32 n)
\r
1569 INLINE void SLEEP(sh2_state *sh2)
\r
1571 //if(sh2->sleep_mode != 2)
\r
1574 /* Wait_for_exception; */
\r
1575 /*if(sh2->sleep_mode == 0)
\r
1576 sh2->sleep_mode = 1;
\r
1577 else if(sh2->sleep_mode == 2)
\r
1578 sh2->sleep_mode = 0;*/
\r
1582 INLINE void STCSR(sh2_state *sh2, UINT32 n)
\r
1584 sh2->r[n] = sh2->sr;
\r
1588 INLINE void STCGBR(sh2_state *sh2, UINT32 n)
\r
1590 sh2->r[n] = sh2->gbr;
\r
1594 INLINE void STCVBR(sh2_state *sh2, UINT32 n)
\r
1596 sh2->r[n] = sh2->vbr;
\r
1599 /* STC.L SR,@-Rn */
\r
1600 INLINE void STCMSR(sh2_state *sh2, UINT32 n)
\r
1603 sh2->ea = sh2->r[n];
\r
1604 WL( sh2, sh2->ea, sh2->sr );
\r
1608 /* STC.L GBR,@-Rn */
\r
1609 INLINE void STCMGBR(sh2_state *sh2, UINT32 n)
\r
1612 sh2->ea = sh2->r[n];
\r
1613 WL( sh2, sh2->ea, sh2->gbr );
\r
1617 /* STC.L VBR,@-Rn */
\r
1618 INLINE void STCMVBR(sh2_state *sh2, UINT32 n)
\r
1621 sh2->ea = sh2->r[n];
\r
1622 WL( sh2, sh2->ea, sh2->vbr );
\r
1627 INLINE void STSMACH(sh2_state *sh2, UINT32 n)
\r
1629 sh2->r[n] = sh2->mach;
\r
1633 INLINE void STSMACL(sh2_state *sh2, UINT32 n)
\r
1635 sh2->r[n] = sh2->macl;
\r
1639 INLINE void STSPR(sh2_state *sh2, UINT32 n)
\r
1641 sh2->r[n] = sh2->pr;
\r
1644 /* STS.L MACH,@-Rn */
\r
1645 INLINE void STSMMACH(sh2_state *sh2, UINT32 n)
\r
1648 sh2->ea = sh2->r[n];
\r
1649 WL( sh2, sh2->ea, sh2->mach );
\r
1652 /* STS.L MACL,@-Rn */
\r
1653 INLINE void STSMMACL(sh2_state *sh2, UINT32 n)
\r
1656 sh2->ea = sh2->r[n];
\r
1657 WL( sh2, sh2->ea, sh2->macl );
\r
1660 /* STS.L PR,@-Rn */
\r
1661 INLINE void STSMPR(sh2_state *sh2, UINT32 n)
\r
1664 sh2->ea = sh2->r[n];
\r
1665 WL( sh2, sh2->ea, sh2->pr );
\r
1669 INLINE void SUB(sh2_state *sh2, UINT32 m, UINT32 n)
\r
1671 sh2->r[n] -= sh2->r[m];
\r
1675 INLINE void SUBC(sh2_state *sh2, UINT32 m, UINT32 n)
\r
1677 UINT32 tmp0, tmp1;
\r
1679 tmp1 = sh2->r[n] - sh2->r[m];
\r
1681 sh2->r[n] = tmp1 - (sh2->sr & T);
\r
1686 if (tmp1 < sh2->r[n])
\r
1691 INLINE void SUBV(sh2_state *sh2, UINT32 m, UINT32 n)
\r
1693 INT32 dest, src, ans;
\r
1695 if ((INT32) sh2->r[n] >= 0)
\r
1699 if ((INT32) sh2->r[m] >= 0)
\r
1704 sh2->r[n] -= sh2->r[m];
\r
1705 if ((INT32) sh2->r[n] >= 0)
\r
1721 /* SWAP.B Rm,Rn */
\r
1722 INLINE void SWAPB(sh2_state *sh2, UINT32 m, UINT32 n)
\r
1724 UINT32 temp0, temp1;
\r
1726 temp0 = sh2->r[m] & 0xffff0000;
\r
1727 temp1 = (sh2->r[m] & 0x000000ff) << 8;
\r
1728 sh2->r[n] = (sh2->r[m] >> 8) & 0x000000ff;
\r
1729 sh2->r[n] = sh2->r[n] | temp1 | temp0;
\r
1732 /* SWAP.W Rm,Rn */
\r
1733 INLINE void SWAPW(sh2_state *sh2, UINT32 m, UINT32 n)
\r
1737 temp = (sh2->r[m] >> 16) & 0x0000ffff;
\r
1738 sh2->r[n] = (sh2->r[m] << 16) | temp;
\r
1742 INLINE void TAS(sh2_state *sh2, UINT32 n)
\r
1745 sh2->ea = sh2->r[n];
\r
1746 /* Bus Lock enable */
\r
1747 temp = RB( sh2, sh2->ea );
\r
1753 /* Bus Lock disable */
\r
1754 WB( sh2, sh2->ea, temp );
\r
1759 INLINE void TRAPA(sh2_state *sh2, UINT32 i)
\r
1761 UINT32 imm = i & 0xff;
\r
1763 sh2->ea = sh2->vbr + imm * 4;
\r
1766 WL( sh2, sh2->r[15], sh2->sr );
\r
1768 WL( sh2, sh2->r[15], sh2->pc );
\r
1770 sh2->pc = RL( sh2, sh2->ea );
\r
1776 INLINE void TST(sh2_state *sh2, UINT32 m, UINT32 n)
\r
1778 if ((sh2->r[n] & sh2->r[m]) == 0)
\r
1785 INLINE void TSTI(sh2_state *sh2, UINT32 i)
\r
1787 UINT32 imm = i & 0xff;
\r
1789 if ((imm & sh2->r[0]) == 0)
\r
1795 /* TST.B #imm,@(R0,GBR) */
\r
1796 INLINE void TSTM(sh2_state *sh2, UINT32 i)
\r
1798 UINT32 imm = i & 0xff;
\r
1800 sh2->ea = sh2->gbr + sh2->r[0];
\r
1801 if ((imm & RB( sh2, sh2->ea )) == 0)
\r
1809 INLINE void XOR(sh2_state *sh2, UINT32 m, UINT32 n)
\r
1811 sh2->r[n] ^= sh2->r[m];
\r
1815 INLINE void XORI(sh2_state *sh2, UINT32 i)
\r
1817 UINT32 imm = i & 0xff;
\r
1821 /* XOR.B #imm,@(R0,GBR) */
\r
1822 INLINE void XORM(sh2_state *sh2, UINT32 i)
\r
1824 UINT32 imm = i & 0xff;
\r
1827 sh2->ea = sh2->gbr + sh2->r[0];
\r
1828 temp = RB( sh2, sh2->ea );
\r
1830 WB( sh2, sh2->ea, temp );
\r
1835 INLINE void XTRCT(sh2_state *sh2, UINT32 m, UINT32 n)
\r
1839 temp = (sh2->r[m] << 16) & 0xffff0000;
\r
1840 sh2->r[n] = (sh2->r[n] >> 16) & 0x0000ffff;
\r
1841 sh2->r[n] |= temp;
\r
1844 /*****************************************************************************
\r
1845 * OPCODE DISPATCHERS
\r
1846 *****************************************************************************/
\r
1848 INLINE void op0000(sh2_state *sh2, UINT16 opcode)
\r
1850 switch (opcode & 0x3F)
\r
1852 case 0x00: ILLEGAL(sh2); rlog(0); break;
\r
1853 case 0x01: ILLEGAL(sh2); rlog(0); break;
\r
1854 case 0x02: STCSR(sh2, Rn); rlog(LRN); break;
\r
1855 case 0x03: BSRF(sh2, Rn); rlog(LRN); break;
\r
1856 case 0x04: MOVBS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;
\r
1857 case 0x05: MOVWS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;
\r
1858 case 0x06: MOVLS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;
\r
1859 case 0x07: MULL(sh2, Rm, Rn); rlog(LRNM); rlog1(SHR_MACL); break;
\r
1860 case 0x08: CLRT(sh2); rlog(0); break;
\r
1861 case 0x09: NOP(); rlog(0); break;
\r
1862 case 0x0a: STSMACH(sh2, Rn); rlog(LRN); rlog1(SHR_MACH); break;
\r
1863 case 0x0b: RTS(sh2); rlog(0); rlog1(SHR_PR); break;
\r
1864 case 0x0c: MOVBL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;
\r
1865 case 0x0d: MOVWL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;
\r
1866 case 0x0e: MOVLL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;
\r
1867 case 0x0f: MAC_L(sh2, Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;
\r
1869 case 0x10: ILLEGAL(sh2); rlog(0); break;
\r
1870 case 0x11: ILLEGAL(sh2); rlog(0); break;
\r
1871 case 0x12: STCGBR(sh2, Rn); rlog(LRN); rlog1(SHR_GBR); break;
\r
1872 case 0x13: ILLEGAL(sh2); rlog(0); break;
\r
1873 case 0x14: MOVBS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;
\r
1874 case 0x15: MOVWS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;
\r
1875 case 0x16: MOVLS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;
\r
1876 case 0x17: MULL(sh2, Rm, Rn); rlog(LRNM); rlog1(SHR_MACL); break;
\r
1877 case 0x18: SETT(sh2); rlog(0); break;
\r
1878 case 0x19: DIV0U(sh2); rlog(0); break;
\r
1879 case 0x1a: STSMACL(sh2, Rn); rlog(LRN); rlog1(SHR_MACL); break;
\r
1880 case 0x1b: SLEEP(sh2); rlog(0); break;
\r
1881 case 0x1c: MOVBL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;
\r
1882 case 0x1d: MOVWL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;
\r
1883 case 0x1e: MOVLL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;
\r
1884 case 0x1f: MAC_L(sh2, Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;
\r
1886 case 0x20: ILLEGAL(sh2); rlog(0); break;
\r
1887 case 0x21: ILLEGAL(sh2); rlog(0); break;
\r
1888 case 0x22: STCVBR(sh2, Rn); rlog(LRN); rlog1(SHR_VBR); break;
\r
1889 case 0x23: BRAF(sh2, Rn); rlog(LRN); break;
\r
1890 case 0x24: MOVBS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;
\r
1891 case 0x25: MOVWS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;
\r
1892 case 0x26: MOVLS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;
\r
1893 case 0x27: MULL(sh2, Rm, Rn); rlog(LRNM); rlog1(SHR_MACL); break;
\r
1894 case 0x28: CLRMAC(sh2); rlog(0); rlog2(SHR_MACL,SHR_MACH); break;
\r
1895 case 0x29: MOVT(sh2, Rn); rlog(LRN); break;
\r
1896 case 0x2a: STSPR(sh2, Rn); rlog(LRN); rlog1(SHR_PR); break;
\r
1897 case 0x2b: RTE(sh2); rlog(0); break;
\r
1898 case 0x2c: MOVBL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;
\r
1899 case 0x2d: MOVWL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;
\r
1900 case 0x2e: MOVLL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;
\r
1901 case 0x2f: MAC_L(sh2, Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;
\r
1903 case 0x30: ILLEGAL(sh2); rlog(0); break;
\r
1904 case 0x31: ILLEGAL(sh2); rlog(0); break;
\r
1905 case 0x32: ILLEGAL(sh2); rlog(0); break;
\r
1906 case 0x33: ILLEGAL(sh2); rlog(0); break;
\r
1907 case 0x34: MOVBS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;
\r
1908 case 0x35: MOVWS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;
\r
1909 case 0x36: MOVLS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;
\r
1910 case 0x37: MULL(sh2, Rm, Rn); rlog(LRNM); rlog1(SHR_MACL); break;
\r
1911 case 0x38: ILLEGAL(sh2); rlog(0); break;
\r
1912 case 0x39: ILLEGAL(sh2); rlog(0); break;
\r
1913 case 0x3c: MOVBL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;
\r
1914 case 0x3d: MOVWL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;
\r
1915 case 0x3e: MOVLL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;
\r
1916 case 0x3f: MAC_L(sh2, Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;
\r
1917 case 0x3a: ILLEGAL(sh2); rlog(0); break;
\r
1918 case 0x3b: ILLEGAL(sh2); rlog(0); break;
\r
1922 INLINE void op0001(sh2_state *sh2, UINT16 opcode)
\r
1924 MOVLS4(sh2, Rm, opcode & 0x0f, Rn);
\r
1928 INLINE void op0010(sh2_state *sh2, UINT16 opcode)
\r
1930 switch (opcode & 15)
\r
1932 case 0: MOVBS(sh2, Rm, Rn); rlog(LRNM); break;
\r
1933 case 1: MOVWS(sh2, Rm, Rn); rlog(LRNM); break;
\r
1934 case 2: MOVLS(sh2, Rm, Rn); rlog(LRNM); break;
\r
1935 case 3: ILLEGAL(sh2); rlog(0); break;
\r
1936 case 4: MOVBM(sh2, Rm, Rn); rlog(LRNM); break;
\r
1937 case 5: MOVWM(sh2, Rm, Rn); rlog(LRNM); break;
\r
1938 case 6: MOVLM(sh2, Rm, Rn); rlog(LRNM); break;
\r
1939 case 7: DIV0S(sh2, Rm, Rn); rlog(LRNM); break;
\r
1940 case 8: TST(sh2, Rm, Rn); rlog(LRNM); break;
\r
1941 case 9: AND(sh2, Rm, Rn); rlog(LRNM); break;
\r
1942 case 10: XOR(sh2, Rm, Rn); rlog(LRNM); break;
\r
1943 case 11: OR(sh2, Rm, Rn); rlog(LRNM); break;
\r
1944 case 12: CMPSTR(sh2, Rm, Rn); rlog(LRNM); break;
\r
1945 case 13: XTRCT(sh2, Rm, Rn); rlog(LRNM); break;
\r
1946 case 14: MULU(sh2, Rm, Rn); rlog(LRNM); rlog1(SHR_MACL); break;
\r
1947 case 15: MULS(sh2, Rm, Rn); rlog(LRNM); rlog1(SHR_MACL); break;
\r
1951 INLINE void op0011(sh2_state *sh2, UINT16 opcode)
\r
1953 switch (opcode & 15)
\r
1955 case 0: CMPEQ(sh2, Rm, Rn); rlog(LRNM); break;
\r
1956 case 1: ILLEGAL(sh2); rlog(0); break;
\r
1957 case 2: CMPHS(sh2, Rm, Rn); rlog(LRNM); break;
\r
1958 case 3: CMPGE(sh2, Rm, Rn); rlog(LRNM); break;
\r
1959 case 4: DIV1(sh2, Rm, Rn); rlog(LRNM); break;
\r
1960 case 5: DMULU(sh2, Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;
\r
1961 case 6: CMPHI(sh2, Rm, Rn); rlog(LRNM); break;
\r
1962 case 7: CMPGT(sh2, Rm, Rn); rlog(LRNM); break;
\r
1963 case 8: SUB(sh2, Rm, Rn); rlog(LRNM); break;
\r
1964 case 9: ILLEGAL(sh2); rlog(0); break;
\r
1965 case 10: SUBC(sh2, Rm, Rn); rlog(LRNM); break;
\r
1966 case 11: SUBV(sh2, Rm, Rn); rlog(LRNM); break;
\r
1967 case 12: ADD(sh2, Rm, Rn); rlog(LRNM); break;
\r
1968 case 13: DMULS(sh2, Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;
\r
1969 case 14: ADDC(sh2, Rm, Rn); rlog(LRNM); break;
\r
1970 case 15: ADDV(sh2, Rm, Rn); rlog(LRNM); break;
\r
1974 INLINE void op0100(sh2_state *sh2, UINT16 opcode)
\r
1976 switch (opcode & 0x3F)
\r
1978 case 0x00: SHLL(sh2, Rn); rlog(LRN); break;
\r
1979 case 0x01: SHLR(sh2, Rn); rlog(LRN); break;
\r
1980 case 0x02: STSMMACH(sh2, Rn); rlog(LRN); rlog1(SHR_MACH); break;
\r
1981 case 0x03: STCMSR(sh2, Rn); rlog(LRN); break;
\r
1982 case 0x04: ROTL(sh2, Rn); rlog(LRN); break;
\r
1983 case 0x05: ROTR(sh2, Rn); rlog(LRN); break;
\r
1984 case 0x06: LDSMMACH(sh2, Rn); rlog(LRN); rlog1(SHR_MACH); break;
\r
1985 case 0x07: LDCMSR(sh2, Rn); rlog(LRN); break;
\r
1986 case 0x08: SHLL2(sh2, Rn); rlog(LRN); break;
\r
1987 case 0x09: SHLR2(sh2, Rn); rlog(LRN); break;
\r
1988 case 0x0a: LDSMACH(sh2, Rn); rlog(LRN); rlog1(SHR_MACH); break;
\r
1989 case 0x0b: JSR(sh2, Rn); rlog(LRN); rlog1(SHR_PR); break;
\r
1990 case 0x0c: ILLEGAL(sh2); rlog(0); break;
\r
1991 case 0x0d: ILLEGAL(sh2); rlog(0); break;
\r
1992 case 0x0e: LDCSR(sh2, Rn); rlog(LRN); break;
\r
1993 case 0x0f: MAC_W(sh2, Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;
\r
1995 case 0x10: DT(sh2, Rn); rlog(LRN); break;
\r
1996 case 0x11: CMPPZ(sh2, Rn); rlog(LRN); break;
\r
1997 case 0x12: STSMMACL(sh2, Rn); rlog(LRN); rlog1(SHR_MACL); break;
\r
1998 case 0x13: STCMGBR(sh2, Rn); rlog(LRN); rlog1(SHR_GBR); break;
\r
1999 case 0x14: ILLEGAL(sh2); rlog(0); break;
\r
2000 case 0x15: CMPPL(sh2, Rn); rlog(LRN); break;
\r
2001 case 0x16: LDSMMACL(sh2, Rn); rlog(LRN); rlog1(SHR_MACL); break;
\r
2002 case 0x17: LDCMGBR(sh2, Rn); rlog(LRN); rlog1(SHR_GBR); break;
\r
2003 case 0x18: SHLL8(sh2, Rn); rlog(LRN); break;
\r
2004 case 0x19: SHLR8(sh2, Rn); rlog(LRN); break;
\r
2005 case 0x1a: LDSMACL(sh2, Rn); rlog(LRN); rlog1(SHR_MACL); break;
\r
2006 case 0x1b: TAS(sh2, Rn); rlog(LRN); break;
\r
2007 case 0x1c: ILLEGAL(sh2); rlog(0); break;
\r
2008 case 0x1d: ILLEGAL(sh2); rlog(0); break;
\r
2009 case 0x1e: LDCGBR(sh2, Rn); rlog(LRN); rlog1(SHR_GBR); break;
\r
2010 case 0x1f: MAC_W(sh2, Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;
\r
2012 case 0x20: SHAL(sh2, Rn); rlog(LRN); break;
\r
2013 case 0x21: SHAR(sh2, Rn); rlog(LRN); break;
\r
2014 case 0x22: STSMPR(sh2, Rn); rlog(LRN); rlog1(SHR_PR); break;
\r
2015 case 0x23: STCMVBR(sh2, Rn); rlog(LRN); rlog1(SHR_VBR); break;
\r
2016 case 0x24: ROTCL(sh2, Rn); rlog(LRN); break;
\r
2017 case 0x25: ROTCR(sh2, Rn); rlog(LRN); break;
\r
2018 case 0x26: LDSMPR(sh2, Rn); rlog(LRN); rlog1(SHR_PR); break;
\r
2019 case 0x27: LDCMVBR(sh2, Rn); rlog(LRN); rlog1(SHR_VBR); break;
\r
2020 case 0x28: SHLL16(sh2, Rn); rlog(LRN); break;
\r
2021 case 0x29: SHLR16(sh2, Rn); rlog(LRN); break;
\r
2022 case 0x2a: LDSPR(sh2, Rn); rlog(LRN); rlog1(SHR_PR); break;
\r
2023 case 0x2b: JMP(sh2, Rn); rlog(LRN); break;
\r
2024 case 0x2c: ILLEGAL(sh2); rlog(0); break;
\r
2025 case 0x2d: ILLEGAL(sh2); rlog(0); break;
\r
2026 case 0x2e: LDCVBR(sh2, Rn); rlog(LRN); rlog1(SHR_VBR); break;
\r
2027 case 0x2f: MAC_W(sh2, Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;
\r
2043 case 0x3e: ILLEGAL(sh2); rlog(0); break;
\r
2044 case 0x3f: MAC_W(sh2, Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;
\r
2048 INLINE void op0101(sh2_state *sh2, UINT16 opcode)
\r
2050 MOVLL4(sh2, Rm, opcode & 0x0f, Rn);
\r
2054 INLINE void op0110(sh2_state *sh2, UINT16 opcode)
\r
2056 switch (opcode & 15)
\r
2058 case 0: MOVBL(sh2, Rm, Rn); break;
\r
2059 case 1: MOVWL(sh2, Rm, Rn); break;
\r
2060 case 2: MOVLL(sh2, Rm, Rn); break;
\r
2061 case 3: MOV(sh2, Rm, Rn); break;
\r
2062 case 4: MOVBP(sh2, Rm, Rn); break;
\r
2063 case 5: MOVWP(sh2, Rm, Rn); break;
\r
2064 case 6: MOVLP(sh2, Rm, Rn); break;
\r
2065 case 7: NOT(sh2, Rm, Rn); break;
\r
2066 case 8: SWAPB(sh2, Rm, Rn); break;
\r
2067 case 9: SWAPW(sh2, Rm, Rn); break;
\r
2068 case 10: NEGC(sh2, Rm, Rn); break;
\r
2069 case 11: NEG(sh2, Rm, Rn); break;
\r
2070 case 12: EXTUB(sh2, Rm, Rn); break;
\r
2071 case 13: EXTUW(sh2, Rm, Rn); break;
\r
2072 case 14: EXTSB(sh2, Rm, Rn); break;
\r
2073 case 15: EXTSW(sh2, Rm, Rn); break;
\r
2078 INLINE void op0111(sh2_state *sh2, UINT16 opcode)
\r
2080 ADDI(sh2, opcode & 0xff, Rn);
\r
2084 INLINE void op1000(sh2_state *sh2, UINT16 opcode)
\r
2086 switch ( opcode & (15<<8) )
\r
2088 case 0<< 8: MOVBS4(sh2, opcode & 0x0f, Rm); rlog(LRM); rlog1(0); break;
\r
2089 case 1<< 8: MOVWS4(sh2, opcode & 0x0f, Rm); rlog(LRM); rlog1(0); break;
\r
2090 case 2<< 8: ILLEGAL(sh2); rlog(0); break;
\r
2091 case 3<< 8: ILLEGAL(sh2); rlog(0); break;
\r
2092 case 4<< 8: MOVBL4(sh2, Rm, opcode & 0x0f); rlog(LRM); rlog1(0); break;
\r
2093 case 5<< 8: MOVWL4(sh2, Rm, opcode & 0x0f); rlog(LRM); rlog1(0); break;
\r
2094 case 6<< 8: ILLEGAL(sh2); rlog(0); break;
\r
2095 case 7<< 8: ILLEGAL(sh2); rlog(0); break;
\r
2096 case 8<< 8: CMPIM(sh2, opcode & 0xff); rlog(0); rlog1(0); break;
\r
2097 case 9<< 8: BT(sh2, opcode & 0xff); rlog(0); break;
\r
2098 case 10<< 8: ILLEGAL(sh2); rlog(0); break;
\r
2099 case 11<< 8: BF(sh2, opcode & 0xff); rlog(0); break;
\r
2100 case 12<< 8: ILLEGAL(sh2); rlog(0); break;
\r
2101 case 13<< 8: BTS(sh2, opcode & 0xff); rlog(0); break;
\r
2102 case 14<< 8: ILLEGAL(sh2); rlog(0); break;
\r
2103 case 15<< 8: BFS(sh2, opcode & 0xff); rlog(0); break;
\r
2108 INLINE void op1001(sh2_state *sh2, UINT16 opcode)
\r
2110 MOVWI(sh2, opcode & 0xff, Rn);
\r
2114 INLINE void op1010(sh2_state *sh2, UINT16 opcode)
\r
2116 BRA(sh2, opcode & 0xfff);
\r
2120 INLINE void op1011(sh2_state *sh2, UINT16 opcode)
\r
2122 BSR(sh2, opcode & 0xfff);
\r
2127 INLINE void op1100(sh2_state *sh2, UINT16 opcode)
\r
2129 switch (opcode & (15<<8))
\r
2131 case 0<<8: MOVBSG(sh2, opcode & 0xff); rlog2(0, SHR_GBR); break;
\r
2132 case 1<<8: MOVWSG(sh2, opcode & 0xff); rlog2(0, SHR_GBR); break;
\r
2133 case 2<<8: MOVLSG(sh2, opcode & 0xff); rlog2(0, SHR_GBR); break;
\r
2134 case 3<<8: TRAPA(sh2, opcode & 0xff); rlog1(SHR_VBR); break;
\r
2135 case 4<<8: MOVBLG(sh2, opcode & 0xff); rlog2(0, SHR_GBR); break;
\r
2136 case 5<<8: MOVWLG(sh2, opcode & 0xff); rlog2(0, SHR_GBR); break;
\r
2137 case 6<<8: MOVLLG(sh2, opcode & 0xff); rlog2(0, SHR_GBR); break;
\r
2138 case 7<<8: MOVA(sh2, opcode & 0xff); rlog1(0); break;
\r
2139 case 8<<8: TSTI(sh2, opcode & 0xff); rlog1(0); break;
\r
2140 case 9<<8: ANDI(sh2, opcode & 0xff); rlog1(0); break;
\r
2141 case 10<<8: XORI(sh2, opcode & 0xff); rlog1(0); break;
\r
2142 case 11<<8: ORI(sh2, opcode & 0xff); rlog1(0); break;
\r
2143 case 12<<8: TSTM(sh2, opcode & 0xff); rlog2(0, SHR_GBR); break;
\r
2144 case 13<<8: ANDM(sh2, opcode & 0xff); rlog2(0, SHR_GBR); break;
\r
2145 case 14<<8: XORM(sh2, opcode & 0xff); rlog2(0, SHR_GBR); break;
\r
2146 case 15<<8: ORM(sh2, opcode & 0xff); rlog2(0, SHR_GBR); break;
\r
2151 INLINE void op1101(sh2_state *sh2, UINT16 opcode)
\r
2153 MOVLI(sh2, opcode & 0xff, Rn);
\r
2157 INLINE void op1110(sh2_state *sh2, UINT16 opcode)
\r
2159 MOVI(sh2, opcode & 0xff, Rn);
\r
2163 INLINE void op1111(sh2_state *sh2, UINT16 opcode)
\r