drz80: don't use swp

swp is not available and sometimes emulated on newer ARMs
on older ARMs it does some bus locking that we don't need

diff --git a/cpu/DrZ80/drz80.s b/cpu/DrZ80/drz80.s
index ff2a6b8..b92b2c2 100644 (file)
--- a/cpu/DrZ80/drz80.s
+++ b/cpu/DrZ80/drz80.s
@@ -4294,10 +4294,12 @@ opcode_0_7:
        fetch 4\r
 ;@EX AF,AF'\r
 opcode_0_8:\r
-       add r1,cpucontext,#z80a2\r
-       swp z80a,z80a,[r1]\r
-       add r1,cpucontext,#z80f2\r
-       swp z80f,z80f,[r1]\r
+       ldr r0,[cpucontext,#z80a2]\r
+       ldr r1,[cpucontext,#z80f2]\r
+       str z80a,[cpucontext,#z80a2]\r
+       str z80f,[cpucontext,#z80f2]\r
+       mov z80a,r0\r
+       mov z80f,r1\r
        fetch 4\r
 ;@ADD HL,BC\r
 opcode_0_9:\r
@@ -5336,12 +5338,15 @@ opcode_D_8:
        fetch 5\r
 ;@EXX\r
 opcode_D_9:\r
-       add r1,cpucontext,#z80bc2\r
-       swp z80bc,z80bc,[r1]\r
-       add r1,cpucontext,#z80de2\r
-       swp z80de,z80de,[r1]\r
-       add r1,cpucontext,#z80hl2\r
-       swp z80hl,z80hl,[r1]\r
+       ldr r0,[cpucontext,#z80bc2]\r
+       ldr r1,[cpucontext,#z80de2]\r
+       ldr r2,[cpucontext,#z80hl2]\r
+       str z80bc,[cpucontext,#z80bc2]\r
+       str z80de,[cpucontext,#z80de2]\r
+       str z80hl,[cpucontext,#z80hl2]\r
+       mov z80bc,r0\r
+       mov z80de,r1\r
+       mov z80hl,r2\r
        fetch 4\r
 ;@JP C,$+3\r
 opcode_D_A:\r