return;
bank = b << 20;
- if ((Pico.m.sram_reg & SRR_MAPPED) && bank == SRam.start) {
+ if ((Pico.m.sram_reg & SRR_MAPPED) && bank == Pico.sv.start) {
bank_map_handler();
return;
}
p32x_pwm_ctl_changed();
// for old savestates
- cycles_diff_sh2 = SekCycleCnt * 3 - Pico32x.pwm_cycle_p;
+ cycles_diff_sh2 = Pico.t.m68c_cnt * 3 - Pico32x.pwm_cycle_p;
if (cycles_diff_sh2 >= pwm_cycles || cycles_diff_sh2 < 0) {
Pico32x.pwm_irq_cnt = pwm_irq_reload;
- Pico32x.pwm_cycle_p = SekCycleCnt * 3;
- p32x_pwm_schedule(SekCycleCnt);
+ Pico32x.pwm_cycle_p = Pico.t.m68c_cnt * 3;
+ p32x_pwm_schedule(Pico.t.m68c_cnt);
}
}
Pico.rom=rom;\r
Pico.romsize=romsize;\r
\r
- if (SRam.data) {\r
- free(SRam.data);\r
- SRam.data = NULL;\r
+ if (Pico.sv.data) {\r
+ free(Pico.sv.data);\r
+ Pico.sv.data = NULL;\r
}\r
\r
if (PicoCartUnloadHook != NULL) {\r
elprintf(EL_STATUS, "carthw:%d: bad sram_range: %08x - %08x", line, start, end);\r
goto bad_nomsg;\r
}\r
- SRam.start = start;\r
- SRam.end = end;\r
+ Pico.sv.start = start;\r
+ Pico.sv.end = end;\r
continue;\r
}\r
else if (is_expr("prop", &p)) {\r
rstrip(p);\r
\r
if (strcmp(p, "no_sram") == 0)\r
- SRam.flags &= ~SRF_ENABLED;\r
+ Pico.sv.flags &= ~SRF_ENABLED;\r
else if (strcmp(p, "no_eeprom") == 0)\r
- SRam.flags &= ~SRF_EEPROM;\r
+ Pico.sv.flags &= ~SRF_EEPROM;\r
else if (strcmp(p, "filled_sram") == 0)\r
*fill_sram = 1;\r
else if (strcmp(p, "force_6btn") == 0)\r
type = strtoul(p, &r, 0);\r
if (r == p || type < 0)\r
goto bad;\r
- SRam.eeprom_type = type;\r
- SRam.flags |= SRF_EEPROM;\r
+ Pico.sv.eeprom_type = type;\r
+ Pico.sv.flags |= SRF_EEPROM;\r
continue;\r
}\r
else if (is_expr("eeprom_lines", &p)) {\r
sda_out < 0 || sda_out > 15)\r
goto bad;\r
\r
- SRam.eeprom_bit_cl = scl;\r
- SRam.eeprom_bit_in = sda_in;\r
- SRam.eeprom_bit_out= sda_out;\r
+ Pico.sv.eeprom_bit_cl = scl;\r
+ Pico.sv.eeprom_bit_in = sda_in;\r
+ Pico.sv.eeprom_bit_out= sda_out;\r
continue;\r
}\r
else if ((tmp = is_expr("prot_ro_value16", &p)) || is_expr("prot_rw_value16", &p)) {\r
{\r
int fill_sram = 0;\r
\r
- memset(&SRam, 0, sizeof(SRam));\r
+ memset(&Pico.sv, 0, sizeof(Pico.sv));\r
if (Pico.rom[0x1B1] == 'R' && Pico.rom[0x1B0] == 'A')\r
{\r
- SRam.start = rom_read32(0x1B4) & ~0xff000001; // align\r
- SRam.end = (rom_read32(0x1B8) & ~0xff000000) | 1;\r
+ Pico.sv.start = rom_read32(0x1B4) & ~0xff000001; // align\r
+ Pico.sv.end = (rom_read32(0x1B8) & ~0xff000000) | 1;\r
if (Pico.rom[0x1B2] & 0x40)\r
// EEPROM\r
- SRam.flags |= SRF_EEPROM;\r
- SRam.flags |= SRF_ENABLED;\r
+ Pico.sv.flags |= SRF_EEPROM;\r
+ Pico.sv.flags |= SRF_ENABLED;\r
}\r
- if (SRam.end == 0 || SRam.start > SRam.end)\r
+ if (Pico.sv.end == 0 || Pico.sv.start > Pico.sv.end)\r
{\r
// some games may have bad headers, like S&K and Sonic3\r
// note: majority games use 0x200000 as starting address, but there are some which\r
// use something else (0x300000 by HardBall '95). Luckily they have good headers.\r
- SRam.start = 0x200000;\r
- SRam.end = 0x203FFF;\r
- SRam.flags |= SRF_ENABLED;\r
+ Pico.sv.start = 0x200000;\r
+ Pico.sv.end = 0x203FFF;\r
+ Pico.sv.flags |= SRF_ENABLED;\r
}\r
\r
// set EEPROM defaults, in case it gets detected\r
- SRam.eeprom_type = 0; // 7bit (24C01)\r
- SRam.eeprom_bit_cl = 1;\r
- SRam.eeprom_bit_in = 0;\r
- SRam.eeprom_bit_out= 0;\r
+ Pico.sv.eeprom_type = 0; // 7bit (24C01)\r
+ Pico.sv.eeprom_bit_cl = 1;\r
+ Pico.sv.eeprom_bit_in = 0;\r
+ Pico.sv.eeprom_bit_out= 0;\r
\r
if (carthw_cfg != NULL)\r
parse_carthw(carthw_cfg, &fill_sram);\r
\r
- if (SRam.flags & SRF_ENABLED)\r
+ if (Pico.sv.flags & SRF_ENABLED)\r
{\r
- if (SRam.flags & SRF_EEPROM)\r
- SRam.size = 0x2000;\r
+ if (Pico.sv.flags & SRF_EEPROM)\r
+ Pico.sv.size = 0x2000;\r
else\r
- SRam.size = SRam.end - SRam.start + 1;\r
+ Pico.sv.size = Pico.sv.end - Pico.sv.start + 1;\r
\r
- SRam.data = calloc(SRam.size, 1);\r
- if (SRam.data == NULL)\r
- SRam.flags &= ~SRF_ENABLED;\r
+ Pico.sv.data = calloc(Pico.sv.size, 1);\r
+ if (Pico.sv.data == NULL)\r
+ Pico.sv.flags &= ~SRF_ENABLED;\r
\r
- if (SRam.eeprom_type == 1) // 1 == 0 in PD EEPROM code\r
- SRam.eeprom_type = 0;\r
+ if (Pico.sv.eeprom_type == 1) // 1 == 0 in PD EEPROM code\r
+ Pico.sv.eeprom_type = 0;\r
}\r
\r
- if ((SRam.flags & SRF_ENABLED) && fill_sram)\r
+ if ((Pico.sv.flags & SRF_ENABLED) && fill_sram)\r
{\r
elprintf(EL_STATUS, "SRAM fill");\r
- memset(SRam.data, 0xff, SRam.size);\r
+ memset(Pico.sv.data, 0xff, Pico.sv.size);\r
}\r
\r
// Unusual region 'code'\r
base = d << 19;
goto do_map;
case 0x09:
- SRam.changed = 1;
+ Pico.sv.changed = 1;
eeprom_spi_write(d);
break;
case 0x0b:
// save EEPROM
eeprom_state = eeprom_spi_init(&eeprom_size);
- SRam.flags = 0;
- SRam.size = 0x10000;
- SRam.data = calloc(1, SRam.size);
- if (!SRam.data)
- SRam.size = 0;
+ Pico.sv.flags = 0;
+ Pico.sv.size = 0x10000;
+ Pico.sv.data = calloc(1, Pico.sv.size);
+ if (!Pico.sv.data)
+ Pico.sv.size = 0;
carthw_pier_state[2].ptr = eeprom_state;
carthw_pier_state[2].size = eeprom_size;
if (spi_eeprom.opcode & 0x01)
{
/* READ operation */
- spi_eeprom.buffer = SRam.data[spi_eeprom.addr];
+ spi_eeprom.buffer = Pico.sv.data[spi_eeprom.addr];
spi_eeprom.state = READ_BYTE;
}
else
/* $C000-$FFFF (sector #3) is protected */
if (spi_eeprom.addr < 0xC000)
{
- SRam.data[spi_eeprom.addr] = spi_eeprom.buffer;
+ Pico.sv.data[spi_eeprom.addr] = spi_eeprom.buffer;
}
break;
}
/* $8000-$FFFF (sectors #2 and #3) is protected */
if (spi_eeprom.addr < 0x8000)
{
- SRam.data[spi_eeprom.addr] = spi_eeprom.buffer;
+ Pico.sv.data[spi_eeprom.addr] = spi_eeprom.buffer;
}
break;
}
default:
{
/* no sectors protected */
- SRam.data[spi_eeprom.addr] = spi_eeprom.buffer;
+ Pico.sv.data[spi_eeprom.addr] = spi_eeprom.buffer;
break;
}
}
{
/* read next array byte */
spi_eeprom.addr = (spi_eeprom.addr + 1) & SIZE_MASK;
- spi_eeprom.buffer = SRam.data[spi_eeprom.addr];
+ spi_eeprom.buffer = Pico.sv.data[spi_eeprom.addr];
}
}
}
switch (Pico.video.type)
{
case 1: // vram
- r = Pico.vram;
+ r = PicoMem.vram;
for(; len; len--)
{
asrc = cell_map(source >> 2) << 2;
case 3: // cram
Pico.m.dirtyPal = 1;
- r = Pico.cram;
+ r = PicoMem.cram;
for(a2=a&0x7f; len; len--)
{
asrc = cell_map(source >> 2) << 2;
break;
case 5: // vsram[a&0x003f]=d;
- r = Pico.vsram;
+ r = PicoMem.vsram;
for(a2=a&0x7f; len; len--)
{
asrc = cell_map(source >> 2) << 2;
{
// reset button doesn't affect MCD hardware
- // use SRam.data for RAM cart
+ // use Pico.sv.data for RAM cart
if (PicoOpt & POPT_EN_MCD_RAMCART) {
- if (SRam.data == NULL)
- SRam.data = calloc(1, 0x12000);
+ if (Pico.sv.data == NULL)
+ Pico.sv.data = calloc(1, 0x12000);
}
- else if (SRam.data != NULL) {
- free(SRam.data);
- SRam.data = NULL;
+ else if (Pico.sv.data != NULL) {
+ free(Pico.sv.data);
+ Pico.sv.data = NULL;
}
- SRam.start = SRam.end = 0; // unused
+ Pico.sv.start = Pico.sv.end = 0; // unused
return 0;
}
int cyc_do;
pevt_log_m68k_o(EVT_RUN_START);
- if ((cyc_do = SekCycleAim - SekCycleCnt) > 0) {
- SekCycleCnt += cyc_do;
+ if ((cyc_do = Pico.t.m68c_aim - Pico.t.m68c_cnt) > 0) {
+ Pico.t.m68c_cnt += cyc_do;
#if defined(EMU_C68K)
PicoCpuCM68k.cycles = cyc_do;
CycloneRun(&PicoCpuCM68k);
- SekCycleCnt -= PicoCpuCM68k.cycles;
+ Pico.t.m68c_cnt -= PicoCpuCM68k.cycles;
#elif defined(EMU_M68K)
- SekCycleCnt += m68k_execute(cyc_do) - cyc_do;
+ Pico.t.m68c_cnt += m68k_execute(cyc_do) - cyc_do;
#elif defined(EMU_F68K)
- SekCycleCnt += fm68k_emulate(cyc_do, 0) - cyc_do;
+ Pico.t.m68c_cnt += fm68k_emulate(cyc_do, 0) - cyc_do;
#endif
}
void pcd_run_cpus_normal(int m68k_cycles)
{
- SekCycleAim += m68k_cycles;
+ Pico.t.m68c_aim += m68k_cycles;
if (SekShouldInterrupt() || Pico_mcd->m.m68k_poll_cnt < 12)
Pico_mcd->m.m68k_poll_cnt = 0;
else if (Pico_mcd->m.m68k_poll_cnt >= 16) {
- int s68k_left = pcd_sync_s68k(SekCycleAim, 1);
+ int s68k_left = pcd_sync_s68k(Pico.t.m68c_aim, 1);
if (s68k_left <= 0) {
elprintf(EL_CDPOLL, "m68k poll [%02x] x%d @%06x",
Pico_mcd->m.m68k_poll_a, Pico_mcd->m.m68k_poll_cnt, SekPc);
- SekCycleCnt = SekCycleAim;
+ Pico.t.m68c_cnt = Pico.t.m68c_aim;
return;
}
- SekCycleCnt = SekCycleAim - (s68k_left * 40220 >> 16);
+ Pico.t.m68c_cnt = Pico.t.m68c_aim - (s68k_left * 40220 >> 16);
}
- while (CYCLES_GT(SekCycleAim, SekCycleCnt)) {
+ while (CYCLES_GT(Pico.t.m68c_aim, Pico.t.m68c_cnt)) {
SekRunM68kOnce();
if (Pico_mcd->m.need_sync) {
Pico_mcd->m.need_sync = 0;
- pcd_sync_s68k(SekCycleCnt, 0);
+ pcd_sync_s68k(Pico.t.m68c_cnt, 0);
}
}
}
void pcd_run_cpus_lockstep(int m68k_cycles)
{
- unsigned int target = SekCycleAim + m68k_cycles;
+ unsigned int target = Pico.t.m68c_aim + m68k_cycles;
do {
- SekCycleAim += 8;
+ Pico.t.m68c_aim += 8;
SekSyncM68k();
- pcd_sync_s68k(SekCycleAim, 0);
- } while (CYCLES_GT(target, SekCycleAim));
+ pcd_sync_s68k(Pico.t.m68c_aim, 0);
+ } while (CYCLES_GT(target, Pico.t.m68c_aim));
- SekCycleAim = target;
+ Pico.t.m68c_aim = target;
}
#define PICO_CD
// need this because we can't have direct mapping between
// master<->slave cycle counters because of overflows
- mcd_m68k_cycle_base = SekCycleAim;
+ mcd_m68k_cycle_base = Pico.t.m68c_aim;
mcd_s68k_cycle_base = SekCycleAimS68k;
}
Pico_mcd->pcm_regs_dirty = 1;
// old savestates..
- cycles = pcd_cycles_m68k_to_s68k(SekCycleAim);
+ cycles = pcd_cycles_m68k_to_s68k(Pico.t.m68c_aim);
diff = cycles - SekCycleAimS68k;
if (diff < -1000 || diff > 1000) {
SekCycleCntS68k = SekCycleAimS68k = cycles;
{\r
u32 d = 0;\r
if (a == 0x400001) {\r
- if (SRam.data != NULL)\r
+ if (Pico.sv.data != NULL)\r
d = 3; // 64k cart\r
return d;\r
}\r
\r
if ((a & 0xfe0000) == 0x600000) {\r
- if (SRam.data != NULL)\r
- d = SRam.data[((a >> 1) & 0xffff) + 0x2000];\r
+ if (Pico.sv.data != NULL)\r
+ d = Pico.sv.data[((a >> 1) & 0xffff) + 0x2000];\r
return d;\r
}\r
\r
static void PicoWriteM68k8_ramc(u32 a, u32 d)\r
{\r
if ((a & 0xfe0000) == 0x600000) {\r
- if (SRam.data != NULL && (Pico_mcd->m.bcram_reg & 1)) {\r
- SRam.data[((a>>1) & 0xffff) + 0x2000] = d;\r
- SRam.changed = 1;\r
+ if (Pico.sv.data != NULL && (Pico_mcd->m.bcram_reg & 1)) {\r
+ Pico.sv.data[((a>>1) & 0xffff) + 0x2000] = d;\r
+ Pico.sv.changed = 1;\r
}\r
return;\r
}\r
static void PicoWriteS68k8_bram(u32 a, u32 d)\r
{\r
Pico_mcd->bram[(a >> 1) & 0x1fff] = d;\r
- SRam.changed = 1;\r
+ Pico.sv.changed = 1;\r
}\r
\r
static void PicoWriteS68k16_bram(u32 a, u32 d)\r
a = (a >> 1) & 0x1fff;\r
Pico_mcd->bram[a++] = d;\r
Pico_mcd->bram[a++] = d >> 8; // TODO: verify..\r
- SRam.changed = 1;\r
+ Pico.sv.changed = 1;\r
}\r
\r
#ifndef _ASM_CD_MEMORY_C\r
PicoCpuFM68k.Fetch[i] = (unsigned long)Pico.rom;\r
// .. and RAM\r
for (i = M68K_FETCHBANK1*14/16; i < M68K_FETCHBANK1; i++)\r
- PicoCpuFM68k.Fetch[i] = (unsigned long)Pico.ram - (i<<(24-FAMEC_FETCHBITS));\r
+ PicoCpuFM68k.Fetch[i] = (unsigned long)PicoMem.ram - (i<<(24-FAMEC_FETCHBITS));\r
// S68k\r
// PRG RAM is default\r
for (i = 0; i < M68K_FETCHBANK1; i++)\r
@* See COPYING file in the top-level directory.
@*
+#include "../pico_int_o32.h"
+
.equiv PCM_STEP_SHIFT, 11
.text
mov r3, #0x0e0000
0:
cell_map
- ldr r1, =(Pico+0x22200)
+ ldr r1, =Pico
add r0, r0, r3
- ldr r1, [r1]
+ ldr r1, [r1, #OFS_Pico_rom] @ Pico.mcd (used everywhere)
eor r0, r0, #1
ldrb r0, [r1, r0]
bx lr
cmp r1, #0x2000 @ a120xx?
bne PicoRead8_io
- ldr r1, =(Pico+0x22200)
+ ldr r1, =Pico
and r0, r0, #0x3f
- ldr r1, [r1] @ Pico.mcd (used everywhere)
+ ldr r1, [r1, #OFS_Pico_rom] @ Pico.mcd
cmp r0, #0x0e
ldrlt pc, [pc, r0, lsl #2]
b m_m68k_read8_hi
mov r3, #0x0e0000
0:
cell_map
- ldr r1, =(Pico+0x22200)
+ ldr r1, =Pico
add r0, r0, r3
- ldr r1, [r1]
+ ldr r1, [r1, #OFS_Pico_rom] @ Pico.mcd
bic r0, r0, #1
ldrh r0, [r1, r0]
bx lr
bne PicoRead16_io
m_m68k_read16_m68k_regs:
- ldr r1, =(Pico+0x22200)
+ ldr r1, =Pico
and r0, r0, #0x3e
- ldr r1, [r1] @ Pico.mcd (used everywhere)
+ ldr r1, [r1, #OFS_Pico_rom] @ Pico.mcd
cmp r0, #0x0e
ldrlt pc, [pc, r0, lsl #1]
b m_m68k_read16_hi
0:
mov r3, r1
cell_map
- ldr r2, =(Pico+0x22200)
+ ldr r2, =Pico
add r0, r0, r12
+ ldr r2, [r2, #OFS_Pico_rom] @ Pico.mcd
ldr r2, [r2]
eor r0, r0, #1
strb r3, [r2, r0]
0:
mov r3, r1
cell_map
- ldr r1, =(Pico+0x22200)
+ ldr r1, =Pico
add r0, r0, r12
- ldr r1, [r1]
+ ldr r1, [r1, #OFS_Pico_rom] @ Pico.mcd
bic r0, r0, #1
strh r3, [r1, r0]
bx lr
PicoReadS68k8_dec1:
mov r3, #0x0a0000 @ + ^ / 2
0:
- ldr r2, =(Pico+0x22200)
+ ldr r2, =Pico
eor r0, r0, #2
- ldr r2, [r2]
+ ldr r2, [r2, #OFS_Pico_rom] @ Pico.mcd
movs r0, r0, lsr #1 @ +4-6 <<16
add r2, r2, r3 @ map to our address
ldrb r0, [r2, r0]
bx lr
m_s68k_read8_comm:
- ldr r1, =(Pico+0x22200)
- ldr r1, [r1]
+ ldr r1, =Pico
+ ldr r1, [r1, #OFS_Pico_rom] @ Pico.mcd
add r1, r1, #0x110000
ldrb r1, [r1, r0]
bic r0, r0, #1
bne m_read_null
@ must not trash r3 and r12
- ldr r1, =(Pico+0x22200)
+ ldr r1, =Pico
bic r0, r0, #0xff0000
- ldr r1, [r1]
+ ldr r1, [r1, #OFS_Pico_rom] @ Pico.mcd
mov r2, #0x110000
orr r2, r2, #0x002200
cmp r0, #0x2000
PicoReadS68k16_dec1:
mov r3, #0x0a0000 @ + ^ / 2
0:
- ldr r2, =(Pico+0x22200)
+ ldr r2, =Pico
eor r0, r0, #2
- ldr r2, [r2]
+ ldr r2, [r2, #OFS_Pico_rom] @ Pico.mcd
mov r0, r0, lsr #1 @ +4-6 <<16
add r2, r2, r3 @ map to our address
ldrb r0, [r2, r0]
.macro m_s68k_write8_2M_decode
- ldr r2, =(Pico+0x22200)
+ ldr r2, =Pico
eor r0, r0, #2
- ldr r2, [r2] @ Pico.rom
+ ldr r2, [r2, #OFS_Pico_rom] @ Pico.mcd
movs r0, r0, lsr #1 @ +4-6 <<16
add r2, r2, r3 @ map to our address
.endm
bxlt lr
m_s68k_write8_pcm_ram:
- ldr r3, =(Pico+0x22200)
+ ldr r3, =Pico
bic r0, r0, #0x00e000
- ldr r3, [r3]
+ ldr r3, [r3, #OFS_Pico_rom] @ Pico.mcd
mov r0, r0, lsr #1
add r2, r3, #0x110000
add r2, r2, #0x002200
.macro m_s68k_write16_2M_decode
- ldr r2, =(Pico+0x22200)
+ ldr r2, =Pico
eor r0, r0, #2
- ldr r2, [r2]
+ ldr r2, [r2, #OFS_Pico_rom] @ Pico.mcd
mov r0, r0, lsr #1 @ +4-6 <<16
add r2, r2, r3 @ map to our address
.endm
bne s68k_reg_write16
m_s68k_write16_regs_spec: @ special case
- ldr r2, =(Pico+0x22200)
+ ldr r2, =Pico
mov r0, #0x110000
- ldr r2, [r2]
+ ldr r2, [r2, #OFS_Pico_rom] @ Pico.mcd
add r0, r0, #0x00000f
strb r1, [r2, r0] @ if (a == 0xe) s68k_regs[0xf] = d;
bx lr
sprintf(dstrp, "mode set 4: %02x\n", (r=reg[0xC])); MVP;
sprintf(dstrp, "interlace: %i%i, cells: %i, shadow: %i\n", bit(r,2), bit(r,1), (r&0x80) ? 40 : 32, bit(r,3)); MVP;
sprintf(dstrp, "scroll size: w: %i, h: %i SRAM: %i; eeprom: %i (%i)\n", reg[0x10]&3, (reg[0x10]&0x30)>>4,
- !!(SRam.flags & SRF_ENABLED), !!(SRam.flags & SRF_EEPROM), SRam.eeprom_type); MVP;
- sprintf(dstrp, "sram range: %06x-%06x, reg: %02x\n", SRam.start, SRam.end, Pico.m.sram_reg); MVP;
+ !!(Pico.sv.flags & SRF_ENABLED), !!(Pico.sv.flags & SRF_EEPROM), Pico.sv.eeprom_type); MVP;
+ sprintf(dstrp, "sram range: %06x-%06x, reg: %02x\n", Pico.sv.start, Pico.sv.end, Pico.m.sram_reg); MVP;
sprintf(dstrp, "pend int: v:%i, h:%i, vdp status: %04x\n", bit(pv->pending_ints,5), bit(pv->pending_ints,4), pv->status); MVP;
sprintf(dstrp, "pal: %i, hw: %02x, frame#: %i, cycles: %u\n", Pico.m.pal, Pico.m.hardware, Pico.m.frame_count, SekCyclesDone()); MVP;
sprintf(dstrp, "M68k: PC: %06x, SR: %04x, irql: %i\n", SekPc, SekSr, SekIrqLevel); MVP;
unsigned int *sprite;
int code, code2, sx, sy, height;
- sprite=(unsigned int *)(Pico.vram+((table+(link<<2))&0x7ffc)); // Find sprite
+ sprite=(unsigned int *)(PicoMem.vram+((table+(link<<2))&0x7ffc)); // Find sprite
// get sprite info
code = sprite[0];
for (u=0; u < max_sprites && u <= which; u++)
{
- sprite=(int *)(Pico.vram+((table+(link<<2))&0x7ffc)); // Find sprite
+ sprite=(int *)(PicoMem.vram+((table+(link<<2))&0x7ffc)); // Find sprite
link=(sprite[0]>>16)&0x7f;
if (!link) break; // End of sprites
}
if (u >= max_sprites) return;
- fsprite = (int *)(Pico.vram+(table&0x7ffc));
+ fsprite = (int *)(PicoMem.vram+(table&0x7ffc));
oldsprite[0] = fsprite[0];
oldsprite[1] = fsprite[1];
fsprite[0] = (sprite[0] & ~0x007f01ff) | 0x000080;
fsprite[1] = (sprite[1] & ~0x01ff8000) | 0x800000;
oldreg = pvid->reg[7];
- oldcol = Pico.cram[0];
+ oldcol = PicoMem.cram[0];
olddbg = pvid->debug_p;
pvid->reg[7] = 0;
- Pico.cram[0] = 0;
+ PicoMem.cram[0] = 0;
pvid->debug_p = PVD_KILL_A | PVD_KILL_B;
PicoFrameFull();
fsprite[0] = oldsprite[0];
fsprite[1] = oldsprite[1];
pvid->reg[7] = oldreg;
- Pico.cram[0] = oldcol;
+ PicoMem.cram[0] = oldcol;
pvid->debug_p = olddbg;
}
dump_ram_m(buf, "dumps/cart.bin", a ? "ab" : "wb");
}
#endif
- dump_ram_noswab(Pico.zram, "dumps/zram.bin");
- dump_ram(Pico.cram, "dumps/cram.bin");
+ dump_ram_noswab(PicoMem.zram, "dumps/zram.bin");
+ dump_ram(PicoMem.cram, "dumps/cram.bin");
if (PicoAHW & PAHW_SMS)
{
- dump_ram_noswab(Pico.vramb, "dumps/vram.bin");
+ dump_ram_noswab(PicoMem.vramb, "dumps/vram.bin");
}
else
{
- dump_ram(Pico.ram, "dumps/ram.bin");
- dump_ram(Pico.vram, "dumps/vram.bin");
- dump_ram(Pico.vsram,"dumps/vsram.bin");
+ dump_ram(PicoMem.ram, "dumps/ram.bin");
+ dump_ram(PicoMem.vram, "dumps/vram.bin");
+ dump_ram(PicoMem.vsram,"dumps/vsram.bin");
}
if (PicoAHW & PAHW_MCD)
PsndStartFrame();
if (/*Pico.m.z80Run &&*/ !Pico.m.z80_reset && (PicoOpt&POPT_EN_Z80))
- PicoSyncZ80(SekCycleCnt + line_sample * 488);
+ PicoSyncZ80(Pico.t.m68c_cnt + line_sample * 488);
if (PsndOut)
PsndGetSamples(line_sample);
if (/*Pico.m.z80Run &&*/ !Pico.m.z80_reset && (PicoOpt&POPT_EN_Z80)) {
- PicoSyncZ80(SekCycleCnt + 224 * 488);
+ PicoSyncZ80(Pico.t.m68c_cnt + 224 * 488);
z80_int();
}
if (PsndOut)
// sync z80
if (/*Pico.m.z80Run &&*/ !Pico.m.z80_reset && (PicoOpt&POPT_EN_Z80)) {
- SekCycleCnt += Pico.m.pal ? 151809 : 127671; // cycles adjusted for converter
- PicoSyncZ80(SekCycleCnt);
+ Pico.t.m68c_cnt += Pico.m.pal ? 151809 : 127671; // cycles adjusted for converter
+ PicoSyncZ80(Pico.t.m68c_cnt);
}
if (PsndOut && ym2612.dacen && PsndDacLine < lines)
PsndDoDAC(lines - 1);
PsndDoPSG(lines - 1);
timers_cycle();
- SekCycleAim = SekCycleCnt;
+ Pico.t.m68c_aim = Pico.t.m68c_cnt;
}
void PDebugCPUStep(void)
{\r
unsigned int pack;\r
\r
- code = Pico.vram[ts->nametab + (tilex & ts->xmask)];\r
+ code = PicoMem.vram[ts->nametab + (tilex & ts->xmask)];\r
if (code == blank)\r
continue;\r
if ((code >> 15) | (lflags & LF_FORCE)) { // high priority tile\r
pal=((code>>9)&0x30)|sh;\r
}\r
\r
- pack = *(unsigned int *)(Pico.vram + addr);\r
+ pack = *(unsigned int *)(PicoMem.vram + addr);\r
if (!pack) {\r
blank = code;\r
continue;\r
//if((cell&1)==0)\r
{\r
int line,vscroll;\r
- vscroll=Pico.vsram[(plane_sh&1)+(cell&~1)];\r
+ vscroll=PicoMem.vsram[(plane_sh&1)+(cell&~1)];\r
\r
// Find the line in the name table\r
line=(vscroll+scan)&ts->line&0xffff; // ts->line is really ymask ..\r
ty=(line&7)<<1; // Y-Offset into tile\r
}\r
\r
- code=Pico.vram[ts->nametab+nametabadd+(tilex&ts->xmask)];\r
+ code=PicoMem.vram[ts->nametab+nametabadd+(tilex&ts->xmask)];\r
if (code==blank) continue;\r
if (code>>15) { // high priority tile\r
int cval = code | (dx<<16) | (ty<<25);\r
pal=((code>>9)&0x30)|((plane_sh<<5)&0x40);\r
}\r
\r
- pack = *(unsigned int *)(Pico.vram + addr);\r
+ pack = *(unsigned int *)(PicoMem.vram + addr);\r
if (!pack) {\r
blank = code;\r
continue;\r
{\r
unsigned int pack;\r
\r
- code=Pico.vram[ts->nametab+(tilex&ts->xmask)];\r
+ code = PicoMem.vram[ts->nametab + (tilex & ts->xmask)];\r
if (code==blank) continue;\r
if (code>>15) { // high priority tile\r
int cval = (code&0xfc00) | (dx<<16) | (ty<<25);\r
pal=((code>>9)&0x30);\r
}\r
\r
- pack = *(unsigned int *)(Pico.vram + addr);\r
+ pack = *(unsigned int *)(PicoMem.vram + addr);\r
if (!pack) {\r
blank = code;\r
continue;\r
htab+=plane_sh&1; // A or B\r
\r
// Get horizontal scroll value, will be masked later\r
- ts.hscroll=Pico.vram[htab&0x7fff];\r
+ ts.hscroll = PicoMem.vram[htab & 0x7fff];\r
\r
if((pvid->reg[12]&6) == 6) {\r
// interlace mode 2\r
- vscroll=Pico.vsram[plane_sh&1]; // Get vertical scroll value\r
+ vscroll = PicoMem.vsram[plane_sh & 1]; // Get vertical scroll value\r
\r
// Find the line in the name table\r
ts.line=(vscroll+(est->DrawScanline<<1))&((ymask<<1)|1);\r
ts.line=ymask|(shift[width]<<24); // save some stuff instead of line\r
DrawStripVSRam(&ts, plane_sh, cellskip);\r
} else {\r
- vscroll=Pico.vsram[plane_sh&1]; // Get vertical scroll value\r
+ vscroll = PicoMem.vsram[plane_sh & 1]; // Get vertical scroll value\r
\r
// Find the line in the name table\r
ts.line=(vscroll+est->DrawScanline)&ymask;\r
\r
if (!(est->rendstatus & PDRAW_WND_DIFF_PRIO)) {\r
// check the first tile code\r
- code=Pico.vram[nametab+tilex];\r
+ code = PicoMem.vram[nametab + tilex];\r
// if the whole window uses same priority (what is often the case), we may be able to skip this field\r
if ((code>>15) != prio) return;\r
}\r
int dx, addr;\r
int pal;\r
\r
- code=Pico.vram[nametab+tilex];\r
+ code = PicoMem.vram[nametab + tilex];\r
if (code==blank) continue;\r
if ((code>>15) != prio) {\r
est->rendstatus |= PDRAW_WND_DIFF_PRIO;\r
addr=(code&0x7ff)<<4;\r
if (code&0x1000) addr+=14-ty; else addr+=ty; // Y-flip\r
\r
- pack = *(unsigned int *)(Pico.vram + addr);\r
+ pack = *(unsigned int *)(PicoMem.vram + addr);\r
if (!pack) {\r
blank = code;\r
continue;\r
int dx, addr;\r
int pal;\r
\r
- code=Pico.vram[nametab+tilex];\r
+ code = PicoMem.vram[nametab + tilex];\r
if(code==blank) continue;\r
if((code>>15) != prio) {\r
est->rendstatus |= PDRAW_WND_DIFF_PRIO;\r
addr=(code&0x7ff)<<4;\r
if (code&0x1000) addr+=14-ty; else addr+=ty; // Y-flip\r
\r
- pack = *(unsigned int *)(Pico.vram + addr);\r
+ pack = *(unsigned int *)(PicoMem.vram + addr);\r
if (!pack) {\r
blank = code;\r
continue;\r
addr = (code & 0x7ff) << 4;\r
addr += code >> 25; // y offset into tile\r
\r
- pack = *(unsigned int *)(Pico.vram + addr);\r
+ pack = *(unsigned int *)(PicoMem.vram + addr);\r
if (!pack) {\r
blank = (short)code;\r
continue;\r
*zb++ &= 0xbf; *zb++ &= 0xbf; *zb++ &= 0xbf; *zb++ &= 0xbf;\r
*zb++ &= 0xbf; *zb++ &= 0xbf; *zb++ &= 0xbf; *zb++ &= 0xbf;\r
\r
- pack = *(unsigned int *)(Pico.vram + addr);\r
+ pack = *(unsigned int *)(PicoMem.vram + addr);\r
if (!pack)\r
continue;\r
\r
if(sx<=0) continue;\r
if(sx>=328) break; // Offscreen\r
\r
- pack = *(unsigned int *)(Pico.vram + (tile & 0x7fff));\r
+ pack = *(unsigned int *)(PicoMem.vram + (tile & 0x7fff));\r
fTileFunc(sx, pack, pal);\r
}\r
}\r
\r
dx = (code >> 16) & 0x1ff;\r
pal = ((code >> 9) & 0x30);\r
- pack = *(unsigned int *)(Pico.vram + addr);\r
+ pack = *(unsigned int *)(PicoMem.vram + addr);\r
\r
if (code & 0x0800) TileFlip_and(dx, pack, pal);\r
else TileNorm_and(dx, pack, pal);\r
if(sx<=0) continue;\r
if(sx>=328) break; // Offscreen\r
\r
- pack = *(unsigned int *)(Pico.vram + (tile & 0x7fff));\r
+ pack = *(unsigned int *)(PicoMem.vram + (tile & 0x7fff));\r
if (code & 0x0800) TileFlip(sx, pack, pal);\r
else TileNorm(sx, pack, pal);\r
}\r
unsigned int *sprite;\r
int code, sx, sy, height;\r
\r
- sprite=(unsigned int *)(Pico.vram+((table+(link<<2))&0x7ffc)); // Find sprite\r
+ sprite=(unsigned int *)(PicoMem.vram+((table+(link<<2))&0x7ffc)); // Find sprite\r
\r
// get sprite info\r
code = sprite[0];\r
if(sx<=0) continue;\r
if(sx>=328) break; // Offscreen\r
\r
- pack = *(unsigned int *)(Pico.vram + (tile & 0x7fff));\r
+ pack = *(unsigned int *)(PicoMem.vram + (tile & 0x7fff));\r
fTileFunc(sx, pack, pal);\r
}\r
}\r
if(sx<=0) continue;\r
if(sx>=328) break; // Offscreen\r
\r
- pack = *(unsigned int *)(Pico.vram + (tile & 0x7fff));\r
+ pack = *(unsigned int *)(PicoMem.vram + (tile & 0x7fff));\r
fTileFunc(sx, pack, pal);\r
}\r
}\r
unsigned int *sprite;\r
int code2, sx, sy, height;\r
\r
- sprite=(unsigned int *)(Pico.vram+((table+(link<<2))&0x7ffc)); // Find sprite\r
+ sprite=(unsigned int *)(PicoMem.vram+((table+(link<<2))&0x7ffc)); // Find sprite\r
\r
// parse sprite info\r
code2 = sprite[1];\r
unsigned int *sprite;\r
int code, code2, sx, sy, hv, height, width;\r
\r
- sprite=(unsigned int *)(Pico.vram+((table+(link<<2))&0x7ffc)); // Find sprite\r
+ sprite=(unsigned int *)(PicoMem.vram+((table+(link<<2))&0x7ffc)); // Find sprite\r
\r
// parse sprite info\r
code = sprite[0];\r
\r
Pico.m.dirtyPal = 0;\r
\r
- spal = (void *)Pico.cram;\r
+ spal = (void *)PicoMem.cram;\r
dpal = (void *)est->HighPal;\r
\r
for (i = 0; i < 0x40 / 2; i++) {\r
rs |= PDRAW_SONIC_MODE;\r
est->rendstatus = rs;\r
if (dirty_count == 3) {\r
- blockcpy(est->HighPal, Pico.cram, 0x40*2);\r
+ blockcpy(est->HighPal, PicoMem.cram, 0x40*2);\r
} else if (dirty_count == 11) {\r
- blockcpy(est->HighPal+0x40, Pico.cram, 0x40*2);\r
+ blockcpy(est->HighPal+0x40, PicoMem.cram, 0x40*2);\r
}\r
}\r
\r
static int HighCache2A[41*(TILE_ROWS+1)+1+1]; // caches for high layers\r
static int HighCache2B[41*(TILE_ROWS+1)+1+1];\r
\r
-unsigned short *PicoCramHigh=Pico.cram; // pointer to CRAM buff (0x40 shorts), converted to native device color (works only with 16bit for now)\r
+unsigned short *PicoCramHigh=PicoMem.cram; // pointer to CRAM buff (0x40 shorts), converted to native device color (works only with 16bit for now)\r
void (*PicoPrepareCram)()=0; // prepares PicoCramHigh for renderer to use\r
\r
\r
int i;\r
\r
for(i=8; i; i--, addr+=2, pd += LINE_WIDTH) {\r
- pack=*(unsigned int *)(Pico.vram+addr); // Get 8 pixels\r
+ pack=*(unsigned int *)(PicoMem.vram+addr); // Get 8 pixels\r
if(!pack) continue;\r
\r
t=pack&0x0000f000; if (t) pd[0]=(unsigned char)((t>>12)|pal);\r
int i;\r
\r
for(i=8; i; i--, addr+=2, pd += LINE_WIDTH) {\r
- pack=*(unsigned int *)(Pico.vram+addr); // Get 8 pixels\r
+ pack=*(unsigned int *)(PicoMem.vram+addr); // Get 8 pixels\r
if(!pack) continue;\r
\r
t=pack&0x000f0000; if (t) pd[0]=(unsigned char)((t>>16)|pal);\r
\r
addr+=14;\r
for(i=8; i; i--, addr-=2, pd += LINE_WIDTH) {\r
- pack=*(unsigned int *)(Pico.vram+addr); // Get 8 pixels\r
+ pack=*(unsigned int *)(PicoMem.vram+addr); // Get 8 pixels\r
if(!pack) continue;\r
\r
t=pack&0x0000f000; if (t) pd[0]=(unsigned char)((t>>12)|pal);\r
\r
addr+=14;\r
for(i=8; i; i--, addr-=2, pd += LINE_WIDTH) {\r
- pack=*(unsigned int *)(Pico.vram+addr); // Get 8 pixels\r
+ pack=*(unsigned int *)(PicoMem.vram+addr); // Get 8 pixels\r
if(!pack) continue;\r
\r
t=pack&0x000f0000; if (t) pd[0]=(unsigned char)((t>>16)|pal);\r
nametab += nametab_step*start;\r
\r
// check priority\r
- code=Pico.vram[nametab+tile_start];\r
+ code=PicoMem.vram[nametab+tile_start];\r
if ((code>>15) != prio) return; // hack: just assume that whole window uses same priority\r
\r
scrpos+=8*LINE_WIDTH+8;\r
// unsigned short *pal=NULL;\r
unsigned char pal;\r
\r
- code=Pico.vram[nametab+tilex];\r
+ code=PicoMem.vram[nametab+tilex];\r
if (code==blank) continue;\r
\r
// Get tile address/2:\r
\r
if(!(pvid->reg[11]&3)) { // full screen scroll\r
// Get horizontal scroll value\r
- hscroll=Pico.vram[htab&0x7fff];\r
+ hscroll=PicoMem.vram[htab&0x7fff];\r
htab = 0; // this marks that we don't have to update scroll value\r
}\r
\r
scrpos+=8*LINE_WIDTH*(planestart-START_ROW);\r
\r
// Get vertical scroll value:\r
- vscroll=Pico.vsram[plane]&0x1ff;\r
+ vscroll=PicoMem.vsram[plane]&0x1ff;\r
scrpos+=(8-(vscroll&7))*LINE_WIDTH;\r
if(vscroll&7) planeend++; // we have vertically clipped tiles due to vscroll, so we need 1 more row\r
\r
if(htab) {\r
int htaddr=htab+(trow<<4);\r
if(trow) htaddr-=(vscroll&7)<<1;\r
- hscroll=Pico.vram[htaddr&0x7fff];\r
+ hscroll=PicoMem.vram[htaddr&0x7fff];\r
}\r
\r
// Draw tiles across screen:\r
// unsigned short *pal=NULL;\r
unsigned char pal;\r
\r
- code=Pico.vram[nametab_row+(tilex&xmask)];\r
+ code=PicoMem.vram[nametab_row+(tilex&xmask)];\r
if (code==blank) continue;\r
\r
if (code>>15) { // high priority tile\r
unsigned int *sprite=NULL;\r
int code, code2, sx, sy, height;\r
\r
- sprite=(unsigned int *)(Pico.vram+((table+(link<<2))&0x7ffc)); // Find sprite\r
+ sprite=(unsigned int *)(PicoMem.vram+((table+(link<<2))&0x7ffc)); // Find sprite\r
\r
// get sprite info\r
code = sprite[0];\r
\r
mov r6, r1 @ hcache\r
\r
- ldr r11, [r12, #OFS_Pico_video]\r
- ldr r10, [r12, #OFS_Pico_vram]\r
- ldrb r5, [r11, #13] @ pvid->reg[13]\r
- ldrb r7, [r11, #11]\r
+ ldr r11, [r12, #OFS_EST_Pico]\r
+ ldr r10, [r12, #OFS_EST_PicoMem_vram]\r
+ ldrb r5, [r11, #OFS_Pico_video_reg+13] @ pvid->reg[13]\r
+ ldrb r7, [r11, #OFS_Pico_video_reg+11]\r
\r
sub lr, r3, r2\r
and lr, lr, #0x00ff0000 @ lr=cells\r
bic r5, r5, #0x00ff0000 @ just in case\r
\r
tst r7, #3 @ full screen scroll? (if ==0)\r
- ldrb r7, [r11, #16] @ ??hh??ww\r
+ ldrb r7, [r11, #OFS_Pico_video_reg+16] @ ??hh??ww\r
ldreqh r5, [r10, r5]\r
biceq r5, r5, #0x0000fc00 @ r5=hscroll (0-0x3ff)\r
movne r5, r5, lsr #1\r
\r
@ Find name table:\r
tst r0, r0\r
- ldreqb r4, [r11, #2]\r
+ ldreqb r4, [r11, #OFS_Pico_video_reg+2]\r
moveq r4, r4, lsr #3\r
- ldrneb r4, [r11, #4]\r
+ ldrneb r4, [r11, #OFS_Pico_video_reg+4]\r
and r4, r4, #7\r
orr lr, lr, r4, lsl #13 @ lr|=nametab_bits{3}<<13\r
\r
ldr r11,[sp, #9*4] @ est\r
sub r4, r9, #(START_ROW<<24)\r
- ldr r11, [r11, #OFS_Draw2FB]\r
+ ldr r11, [r11, #OFS_EST_Draw2FB]\r
mov r4, r4, asr #24\r
mov r7, #328*8\r
mla r11, r4, r7, r11 @ scrpos+=8*328*(planestart-START_ROW);\r
mov r9, #0xff000000 @ r9=prevcode=-1\r
mvn r6, #0 @ r6=prevy=-1\r
\r
- ldr r4, [r1, #OFS_Draw2FB]\r
+ ldr r4, [r1, #OFS_EST_Draw2FB]\r
ldr r2, [r0], #4 @ read y offset\r
mov r7, #328\r
mla r2, r7, r2, r4\r
sub r12, r2, #(328*8*START_ROW) @ r12=scrpos\r
\r
- ldr r10, [r1, #OFS_Pico_vram]\r
+ ldr r10, [r1, #OFS_EST_PicoMem_vram]\r
mov r8, r0 @ hc\r
mov r0, #0xf\r
\r
DrawWindowFull:\r
stmfd sp!, {r4-r11,lr}\r
\r
- ldr r11, [r3, #OFS_Pico_video]\r
- ldrb r12, [r11, #3] @ pvid->reg[3]\r
+ ldr r11, [r3, #OFS_EST_Pico]\r
+ ldrb r12, [r11, #OFS_Pico_video_reg+3] @ pvid->reg[3]\r
mov r12, r12, lsl #10\r
\r
- ldr r4, [r11, #12]\r
+ ldr r4, [r11, #OFS_Pico_video_reg+12]\r
mov r5, #1 @ nametab_step\r
tst r4, #1 @ 40 cell mode?\r
andne r12, r12, #0xf000 @ 0x3c<<10\r
and r4, r0, #0xff\r
mla r12, r5, r4, r12 @ nametab += nametab_step*start;\r
\r
- ldr r10, [r3, #OFS_Pico_vram]\r
+ ldr r10, [r3, #OFS_EST_PicoMem_vram]\r
mov r4, r0, lsr #16 @ r4=start_cell_h\r
add r7, r12, r4, lsl #1\r
\r
\r
mov r9, #0xff000000 @ r9=prevcode=-1\r
\r
- ldr r11, [r3, #OFS_Draw2FB]\r
+ ldr r11, [r3, #OFS_EST_Draw2FB]\r
and r4, r0, #0xff\r
add r11, r11, #328*8\r
sub r4, r4, #START_ROW\r
tst r9, #0x080000 @ hflip?\r
bne .dwf_hflip\r
\r
- @ Tile (r1=pdest, r3=pal, r9=prevcode, r10=Pico.vram) r2,r4,r7: scratch, r0=0xf\r
+ @ Tile (r1=pdest, r3=pal, r9=prevcode, r10=PicoMem.vram)\r
+ @ r2,r4,r7: scratch, r0=0xf\r
Tile 0, 0\r
b .dwfloop\r
\r
cmp r6, #(END_ROW*8+8)\r
bge 52b\r
\r
- @ Tile (r1=pdest, r3=pal, r9=prevcode, r10=Pico.vram) r2,r4,r7: scratch, r0=0xf\r
+ @ Tile (r1=pdest, r3=pal, r9=prevcode, r10=PicoMem.vram)\r
+ @ r2,r4,r7: scratch, r0=0xf\r
Tile \hflip, \vflip\r
b 52b\r
.endm\r
and r3, lr, #0x6000\r
mov r3, r3, lsr #9 @ r3=pal=((code>>9)&0x30);\r
\r
- ldr r11, [r1, #OFS_Draw2FB]\r
- ldr r10, [r1, #OFS_Pico_vram]\r
+ ldr r11, [r1, #OFS_EST_Draw2FB]\r
+ ldr r10, [r1, #OFS_EST_PicoMem_vram]\r
sub r1, r12, #(START_ROW*8)\r
mov r0, #328\r
mla r11, r1, r0, r11 @ scrpos+=(sy-START_ROW*8)*328;\r
ldr r12, [sp] @ est\r
stmfd sp!, {r4-r11,lr}\r
\r
- ldr r11, [r12, #OFS_Pico_video]\r
+ ldr r11, [r12, #OFS_EST_Pico]\r
mov r8, #1\r
\r
- ldrb r7, [r11, #16] @ ??vv??hh\r
+ ldrb r7, [r11, #OFS_Pico_video_reg+16] @ ??vv??hh\r
\r
mov r6, r1 @ hcache\r
orr r9, r3, r0, lsl #29 @ r9=force[31]|sh[30]|plane[29]\r
cmp r10, #7\r
subge r10, r10, #1 @ r10=shift[width] (5,6,6,7)\r
\r
- ldr r2, [r12, #OFS_DrawScanline]\r
- ldr lr, [r12, #OFS_Pico_vram]\r
+ ldr r2, [r12, #OFS_EST_DrawScanline]\r
+ ldr lr, [r12, #OFS_EST_PicoMem_vram]\r
\r
@ Find name table:\r
ands r0, r0, #1\r
- ldreqb r12, [r11, #2]\r
- ldrneb r12, [r11, #4]\r
+ ldreqb r12, [r11, #OFS_Pico_video_reg+2]\r
+ ldrneb r12, [r11, #OFS_Pico_video_reg+4]\r
\r
@ calculate xmask:\r
mov r5, r8, lsl r10\r
movne r12, r12, lsl #13\r
and r12, r12, #(7<<13) @ r12=(ts->nametab<<1) (halfword compliant)\r
\r
- ldrh r8, [r11, #12]\r
- ldrb r7, [r11, #11]\r
+ ldrh r8, [r11, #OFS_Pico_video_reg+12]\r
+ ldrb r7, [r11, #OFS_Pico_video_reg+11]\r
\r
mov r4, r8, lsr #8 @ pvid->reg[13]\r
mov r4, r4, lsl #10 @ htab=pvid->reg[13]<<9; (halfwords)\r
\r
@ Get vertical scroll value:\r
add r7, lr, #0x012000\r
- add r7, r7, #0x000180 @ r7=Pico.vsram (Pico+0x22180)\r
+ add r7, r7, #0x000180 @ r7=PicoMem.vsram (PicoMem+0x22180)\r
ldr r7, [r7]\r
\r
tst r8, #2\r
@ cache some stuff to avoid mem access\r
ldr r11,[sp, #9*4] @ est\r
mov r0, #0xf\r
- ldr r11,[r11, #OFS_HighCol]\r
+ ldr r11,[r11, #OFS_EST_HighCol]\r
\r
mvn r9, #0 @ r9=prevcode=-1\r
add r1, r11, r7 @ r1=pdest\r
tst r10, #1<<21 @ seen non hi-prio tile\r
ldr r1, [sp, #9*4] @ est\r
mov r0, #0\r
- ldreq r2, [r1, #OFS_rendstatus]\r
+ ldreq r2, [r1, #OFS_EST_rendstatus]\r
str r0, [r6] @ terminate the cache list\r
orreq r2, r2, #PDRAW_PLANE_HI_PRIO @ had a layer with all hi-prio tiles\r
- streq r2, [r1, #OFS_rendstatus]\r
+ streq r2, [r1, #OFS_EST_rendstatus]\r
\r
ldmfd sp!, {r4-r11,lr}\r
bx lr\r
\r
ldr r11, [sp, #9*4] @ est\r
orr r5, r1, r10, lsl #24\r
- ldr r4, [r11, #OFS_DrawScanline]\r
+ ldr r4, [r11, #OFS_EST_DrawScanline]\r
sub r1, r3, #1\r
orr r5, r5, r4, lsl #16 @ r5=(shift_width[31:24]|scanline[23:16]|ymask[15:0])\r
and r1, r1, #7\r
@ cache some stuff to avoid mem access\r
ldr r11,[sp, #9*4] @ est\r
mov r0, #0xf\r
- ldr r11,[r11, #OFS_HighCol]\r
+ ldr r11,[r11, #OFS_EST_HighCol]\r
\r
mvn r9, #0 @ r9=prevcode=-1\r
add r1, r11, r7 @ r1=pdest\r
\r
@ calc offset and read tileline code to r7, also calc ty\r
add r7, lr, #0x012000\r
- add r7, r7, #0x000180 @ r7=Pico.vsram (Pico+0x22180)\r
+ add r7, r7, #0x000180 @ r7=PicoMem.vsram (PicoMem+0x22180)\r
add r7, r7, r10,asr #23 @ vsram + ((cell&~1)<<1)\r
bic r7, r7, #3\r
tst r10,#0x8000 @ plane1?\r
mov r4, r4, lsl r7 @ nametabadd\r
\r
and r7, r8, r8, lsr #25\r
- add r7, lr, r7, lsl #1 @ Pico.vram+((tilex&ts->xmask) as halfwords)\r
+ add r7, lr, r7, lsl #1 @ PicoMem.vram+((tilex&ts->xmask) as halfwords)\r
add r7, r7, r4, lsl #1\r
ldrh r7, [r7, r12] @ r7=code (int, but from unsigned, no sign extend)\r
\r
mov r2, r2, lsr #17\r
eorcs r2, r2, #0x0e @ if (code&0x1000) addr^=0xe;\r
\r
- ldr r2, [lr, r2, lsl #1] @ pack=*(unsigned int *)(Pico.vram+addr); // Get 8 pixels\r
+ ldr r2, [lr, r2, lsl #1] @ pack=*(unsigned int *)(PicoMem.vram+addr); // Get 8 pixels\r
\r
bic r7, r3, #0x3f\r
and r3, r9, #0x6000\r
add r2, r2, r10, lsl #17\r
mov r2, r2, lsr #17\r
eorcs r2, r2, #0x0e @ if (code&0x1000) addr^=0xe;\r
- ldr r2, [lr, r2, lsl #1] @ pack=*(unsigned int *)(Pico.vram+addr); // Get 8 pixels\r
+ ldr r2, [lr, r2, lsl #1] @ pack=*(unsigned int *)(PicoMem.vram+addr); // Get 8 pixels\r
mov r9, r7 @ remember code\r
tst r2, r2\r
orrne r10, r10, #1<<22\r
tst r8, #(1<<24) @ seen non hi-prio tile\r
ldr r1, [sp, #9*4] @ est\r
mov r0, #0\r
- ldreq r2, [r1, #OFS_rendstatus]\r
+ ldreq r2, [r1, #OFS_EST_rendstatus]\r
str r0, [r6] @ terminate the cache list\r
orreq r2, r2, #PDRAW_PLANE_HI_PRIO @ had a layer with all hi-prio tiles\r
- streq r2, [r1, #OFS_rendstatus]\r
+ streq r2, [r1, #OFS_EST_rendstatus]\r
\r
ldmfd sp!, {r4-r11,lr}\r
bx lr\r
stmfd sp!, {r4-r9,lr}\r
\r
mov r0, r0, lsl #26\r
- ldr lr, [r2, #OFS_HighCol]\r
+ ldr lr, [r2, #OFS_EST_HighCol]\r
mov r0, r0, lsr #26\r
add lr, lr, #8\r
\r
stmfd sp!, {r4-r9,r11,lr}\r
\r
@ cache some stuff to avoid mem access\r
- ldr r11,[r3, #OFS_HighCol]\r
+ ldr r11,[r3, #OFS_EST_HighCol]\r
mov r12,#0xf\r
- ldr lr, [r3, #OFS_Pico_vram]\r
+ ldr lr, [r3, #OFS_EST_PicoMem_vram]\r
mov r9, r3 @ est\r
\r
mvn r5, #0 @ r5=prevcode=-1\r
\r
@ check if we have detected layer covered with hi-prio tiles:\r
.dtfc_check_rendflags:\r
- ldr r2, [r9, #OFS_rendstatus]\r
+ ldr r2, [r9, #OFS_EST_rendstatus]\r
tst r2, #(PDRAW_PLANE_HI_PRIO|PDRAW_SHHI_DONE)\r
beq .dtfc_loop\r
bic r8, r8, #1 @ sh/hi mode off\r
tst r2, #PDRAW_SHHI_DONE\r
bne .dtfc_loop @ already processed\r
orr r2, r2, #PDRAW_SHHI_DONE\r
- str r2, [r9, #OFS_rendstatus]\r
+ str r2, [r9, #OFS_EST_rendstatus]\r
\r
add r1, r11,#8\r
mov r3, #320/4/4\r
add r10,r0, #3 @ r10=HighLnSpr end\r
add r10,r10,r3 @ r10=HighLnSpr end\r
\r
- ldr r11,[r1, #OFS_HighCol]\r
+ ldr r11,[r1, #OFS_EST_HighCol]\r
mov r12,#0xf\r
- ldr lr, [r1, #OFS_Pico_vram]\r
+ ldr lr, [r1, #OFS_EST_PicoMem_vram]\r
\r
\r
DrawSpriteSHi:\r
@ draw next sprite\r
ldrb r0, [r10,#-1]!\r
ldr r7, [sp] @ est\r
- ldr r1, [r7, #OFS_HighPreSpr]\r
+ ldr r1, [r7, #OFS_EST_HighPreSpr]\r
cmp r0, #0xff\r
ldmeqfd sp!, {r1,r4-r11,pc} @ end of list\r
and r0, r0, #0x7f\r
mov r5, r3, lsr #24\r
and r5, r5, #7 @ r5=height\r
\r
- ldr r7, [r7, #OFS_DrawScanline]\r
+ ldr r7, [r7, #OFS_EST_DrawScanline]\r
mov r0, r3, lsl #16 @ r4=sy<<16 (tmp)\r
\r
sub r7, r7, r0, asr #16 @ r7=row=DrawScanline-sy\r
mov r8, r8, lsl #17\r
mov r8, r8, lsr #17 @ tile&=0x7fff; // Clip tile address\r
\r
- ldr r2, [lr, r8, lsl #1] @ pack=*(unsigned int *)(Pico.vram+addr); // Get 8 pixels\r
+ ldr r2, [lr, r8, lsl #1] @ pack=*(unsigned int *)(PicoMem.vram+addr); // Get 8 pixels\r
add r1, r11, r0 @ r1=pdest\r
tst r2, r2\r
beq .dsprShi_loop\r
add r10,r0, #3\r
add r10,r10,r2 @ r10=HighLnSpr end\r
\r
- ldr r11,[r3, #OFS_HighCol]\r
+ ldr r11,[r3, #OFS_EST_HighCol]\r
mov r12,#0xf\r
- ldr lr, [r3, #OFS_Pico_vram]\r
+ ldr lr, [r3, #OFS_EST_PicoMem_vram]\r
\r
@ + 0 : hhhhvvvv ----hhvv yyyyyyyy yyyyyyyy // v, h: horiz. size\r
@ + 4 : xxxxxxxx xxxxxxxx pccvhnnn nnnnnnnn // x: x coord + 8\r
ldmeqfd sp!, {r1,r3-r11,pc} @ end of list\r
cmp r2, r8, lsr #1\r
bne DrawSprite @ wrong priority\r
- ldr r1, [r7, #OFS_HighPreSpr]\r
+ ldr r1, [r7, #OFS_EST_HighPreSpr]\r
and r0, r0, #0x7f\r
add r0, r1, r0, lsl #3\r
\r
ldr r3, [r0] @ sprite[0]\r
- ldr r7, [r7, #OFS_DrawScanline]\r
+ ldr r7, [r7, #OFS_EST_DrawScanline]\r
mov r6, r3, lsr #28\r
sub r6, r6, #1 @ r6=width-1 (inc later)\r
mov r5, r3, lsr #24\r
mov r8, r8, lsl #17\r
mov r8, r8, lsr #17 @ tile&=0x7fff; // Clip tile address\r
\r
- ldr r2, [lr, r8, lsl #1] @ pack=*(unsigned int *)(Pico.vram+addr); // Get 8 pixels\r
+ ldr r2, [lr, r8, lsl #1] @ pack=*(unsigned int *)(PicoMem.vram+addr); // Get 8 pixels\r
add r1, r11, r0 @ r1=pdest\r
tst r2, r2\r
beq .dspr_loop\r
ldr r12, [sp] @ est\r
stmfd sp!, {r4-r11,lr}\r
\r
- ldr r6, [r12, #OFS_Pico_video]\r
- ldr r10, [r12, #OFS_DrawScanline]\r
+ ldr r6, [r12, #OFS_EST_Pico]\r
+ ldr r10, [r12, #OFS_EST_DrawScanline]\r
mov r11, r12 @ est\r
- ldrb r12, [r6, #3] @ pvid->reg[3]\r
+ ldrb r12, [r6, #OFS_Pico_video_reg+3] @ pvid->reg[3]\r
\r
- ldr r4, [r6, #12]\r
+ ldr r4, [r6, #OFS_Pico_video_reg+12]\r
mov r5, r10, lsr #3\r
and r10, r10, #7\r
mov r10, r10, lsl #1 @ r10=ty\r
addeq r12, r12, r5, lsl #6 @ nametab\r
add r12, r12, r0, lsl #2 @ +starttile\r
\r
- ldr lr, [r11, #OFS_Pico_vram]\r
- ldr r6, [r11, #OFS_rendstatus]\r
+ ldr lr, [r11, #OFS_EST_PicoMem_vram]\r
+ ldr r6, [r11, #OFS_EST_rendstatus]\r
\r
@ fetch the first code now\r
ldrh r7, [lr, r12]\r
sub r8, r1, r0\r
\r
@ cache some stuff to avoid mem access\r
- ldr r11, [r11, #OFS_HighCol]\r
+ ldr r11, [r11, #OFS_EST_HighCol]\r
mov r8, r8, lsl #1 @ cells\r
add r11,r11,#8\r
mvn r9, #0 @ r9=prevcode=-1\r
and r2, r6, #PDRAW_WND_DIFF_PRIO\r
ldmfd sp!, {r4-r11,lr}\r
ldr r0, [sp]\r
- ldr r1, [r0, #OFS_rendstatus]\r
+ ldr r1, [r0, #OFS_EST_rendstatus]\r
orr r1, r1, r2\r
- str r1, [r0, #OFS_rendstatus]\r
+ str r1, [r0, #OFS_EST_rendstatus]\r
\r
bx lr\r
\r
stmfd sp!, {r4-r10,lr}\r
mov r10,r2 @ est\r
mov r1, #0\r
- ldr r8, [r10, #OFS_Pico_video]\r
+ ldr r8, [r10, #OFS_EST_Pico]\r
\r
PicoDoHighPal555_nopush:\r
orr r9, r1, r0, lsl #31 @ 0:called from FinalizeLine555, 31: s/h\r
\r
- add r0, r10, #OFS_HighPal\r
+ add r0, r10, #OFS_EST_HighPal\r
\r
mov r1, #0\r
- strb r1, [r8, #-0x1a] @ 0x2220e ~ dirtyPal\r
+ strb r1, [r8, #OFS_Pico_m_dirtyPal]\r
\r
- sub r1, r8, #0x128 @ r1=Pico.cram\r
+ ldr r1, [r10, #OFS_EST_PicoMem_cram]\r
mov r2, #0x40\r
mov r8, #0x0061\r
orr r8, r8, #0x0800\r
tst r9, #(1<<31)\r
beq PicoDoHighPal555_end\r
\r
- add r3, r10, #OFS_HighPal\r
+ add r3, r10, #OFS_EST_HighPal\r
\r
@ shadowed pixels:\r
mov r12, #0x008e\r
tst r9, #1\r
ldmeqfd sp!, {r4-r10,pc}\r
\r
- ldr r8, [r10, #OFS_Pico_video]\r
+ ldr r8, [r10, #OFS_EST_Pico]\r
b FinalizeLineRGB555_pal_done\r
\r
\r
FinalizeLine555:\r
stmfd sp!, {r4-r10,lr}\r
mov r10,r2 @ est\r
- ldr r8, [r10, #OFS_Pico_video]\r
+ ldr r8, [r10, #OFS_EST_Pico]\r
\r
- ldrb r2, [r8, #-0x1a] @ 0x2220e ~ dirtyPal\r
+ ldrb r2, [r8, #OFS_Pico_m_dirtyPal]\r
mov r1, #1\r
tst r2, r2\r
bne PicoDoHighPal555_nopush\r
\r
FinalizeLineRGB555_pal_done:\r
- add r3, r10, #OFS_HighPal\r
+ add r3, r10, #OFS_EST_HighPal\r
\r
- ldr r12, [r10, #OFS_rendstatus]\r
+ ldr r12, [r10, #OFS_EST_rendstatus]\r
eors r0, r0, #1 @ sh is 0\r
mov lr, #0xff\r
tstne r12,#PDRAW_ACC_SPRITES\r
movne lr, #0x3f\r
\r
- ldr r1, [r10, #OFS_HighCol]\r
- ldr r0, [r10, #OFS_DrawLineDest]\r
+ ldr r1, [r10, #OFS_EST_HighCol]\r
+ ldr r0, [r10, #OFS_EST_DrawLineDest]\r
add r1, r1, #8\r
\r
- ldrb r12, [r8, #12]\r
+ ldrb r12, [r8, #OFS_Pico_video_reg+12]\r
mov lr, lr, lsl #1\r
\r
tst r12, #1\r
movne r2, #320/8 @ len\r
bne .fl_no32colRGB555\r
- ldr r4, [r10, #OFS_PicoOpt]\r
+ ldr r4, [r10, #OFS_EST_PicoOpt]\r
mov r2, #256/8\r
ldr r4, [r4]\r
tst r4, #0x4000\r
{\r
// we are started and SCL went high - next cycle\r
scyc++; // pre-increment\r
- if(SRam.eeprom_type) {\r
+ if(Pico.sv.eeprom_type) {\r
// X24C02+\r
if((ssa&1) && scyc == 18) {\r
scyc = 9;\r
saddr++; // next address in read mode\r
- /*if(SRam.eeprom_type==2) saddr&=0xff; else*/ saddr&=0x1fff; // mask\r
+ /*if(Pico.sv.eeprom_type==2) saddr&=0xff; else*/ saddr&=0x1fff; // mask\r
}\r
- else if(SRam.eeprom_type == 2 && scyc == 27) scyc = 18;\r
+ else if(Pico.sv.eeprom_type == 2 && scyc == 27) scyc = 18;\r
else if(scyc == 36) scyc = 27;\r
} else {\r
// X24C01\r
else if((sreg & 8) && (sreg & 2) && !(d&2))\r
{\r
// we are started and SCL went low (falling edge)\r
- if(SRam.eeprom_type) {\r
+ if(Pico.sv.eeprom_type) {\r
// X24C02+\r
if(scyc == 9 || scyc == 18 || scyc == 27); // ACK cycles\r
- else if( (SRam.eeprom_type == 3 && scyc > 27) || (SRam.eeprom_type == 2 && scyc > 18) ) {\r
+ else if( (Pico.sv.eeprom_type == 3 && scyc > 27) || (Pico.sv.eeprom_type == 2 && scyc > 18) ) {\r
if(!(ssa&1)) {\r
// data write\r
- unsigned char *pm=SRam.data+saddr;\r
+ unsigned char *pm=Pico.sv.data+saddr;\r
*pm <<= 1; *pm |= d&1;\r
if(scyc == 26 || scyc == 35) {\r
saddr=(saddr&~0xf)|((saddr+1)&0xf); // only 4 (?) lowest bits are incremented\r
elprintf(EL_EEPROM, "eeprom: write done, addr inc to: %x, last byte=%02x", saddr, *pm);\r
}\r
- SRam.changed = 1;\r
+ Pico.sv.changed = 1;\r
}\r
} else if(scyc > 9) {\r
if(!(ssa&1)) {\r
// we latch another addr bit\r
saddr<<=1;\r
- if(SRam.eeprom_type == 2) saddr&=0xff; else saddr&=0x1fff; // mask\r
+ if(Pico.sv.eeprom_type == 2) saddr&=0xff; else saddr&=0x1fff; // mask\r
saddr|=d&1;\r
if(scyc==17||scyc==26) {\r
elprintf(EL_EEPROM, "eeprom: addr reg done: %x", saddr);\r
- if(scyc==17&&SRam.eeprom_type==2) { saddr&=0xff; saddr|=(ssa<<7)&0x700; } // add device bits too\r
+ if(scyc==17&&Pico.sv.eeprom_type==2) { saddr&=0xff; saddr|=(ssa<<7)&0x700; } // add device bits too\r
}\r
}\r
} else {\r
else if(scyc > 9) {\r
if(!(saddr&1)) {\r
// data write\r
- unsigned char *pm=SRam.data+(saddr>>1);\r
+ unsigned char *pm=Pico.sv.data+(saddr>>1);\r
*pm <<= 1; *pm |= d&1;\r
if(scyc == 17) {\r
saddr=(saddr&0xf9)|((saddr+2)&6); // only 2 lowest bits are incremented\r
elprintf(EL_EEPROM, "eeprom: write done, addr inc to: %x, last byte=%02x", saddr>>1, *pm);\r
}\r
- SRam.changed = 1;\r
+ Pico.sv.changed = 1;\r
}\r
} else {\r
// we latch another addr bit\r
sreg &= ~0xc0;\r
\r
// SCL\r
- d1 = (d >> SRam.eeprom_bit_cl) & 1;\r
+ d1 = (d >> Pico.sv.eeprom_bit_cl) & 1;\r
sreg |= d1 << 7;\r
\r
// SDA in\r
- d1 = (d >> SRam.eeprom_bit_in) & 1;\r
+ d1 = (d >> Pico.sv.eeprom_bit_in) & 1;\r
sreg |= d1 << 6;\r
\r
Pico.m.eeprom_status = (unsigned char) sreg;\r
} else if (scyc > 9 && scyc < 18) {\r
// started and first command word received\r
shift = 17-scyc;\r
- if (SRam.eeprom_type) {\r
+ if (Pico.sv.eeprom_type) {\r
// X24C02+\r
if (ssa&1) {\r
elprintf(EL_EEPROM, "eeprom: read: addr %02x, cycle %i, reg %02x", saddr, scyc, sreg);\r
- if (shift==0) elprintf(EL_EEPROM, "eeprom: read done, byte %02x", SRam.data[saddr]);\r
- d = (SRam.data[saddr]>>shift)&1;\r
+ if (shift==0) elprintf(EL_EEPROM, "eeprom: read done, byte %02x", Pico.sv.data[saddr]);\r
+ d = (Pico.sv.data[saddr]>>shift)&1;\r
}\r
} else {\r
// X24C01\r
if (saddr&1) {\r
elprintf(EL_EEPROM, "eeprom: read: addr %02x, cycle %i, reg %02x", saddr>>1, scyc, sreg);\r
- if (shift==0) elprintf(EL_EEPROM, "eeprom: read done, byte %02x", SRam.data[saddr>>1]);\r
- d = (SRam.data[saddr>>1]>>shift)&1;\r
+ if (shift==0) elprintf(EL_EEPROM, "eeprom: read done, byte %02x", Pico.sv.data[saddr>>1]);\r
+ d = (Pico.sv.data[saddr>>1]>>shift)&1;\r
}\r
}\r
}\r
\r
- return (d << SRam.eeprom_bit_out);\r
+ return (d << Pico.sv.eeprom_bit_out);\r
}\r
\r
\r
static NOINLINE u32 port_read(int i)\r
{\r
- u32 data_reg = Pico.ioports[i + 1];\r
- u32 ctrl_reg = Pico.ioports[i + 4] | 0x80;\r
+ u32 data_reg = PicoMem.ioports[i + 1];\r
+ u32 ctrl_reg = PicoMem.ioports[i + 4] | 0x80;\r
u32 in, out;\r
\r
out = data_reg & ctrl_reg;\r
case 1: d = port_read(0); break;\r
case 2: d = port_read(1); break;\r
case 3: d = port_read(2); break;\r
- default: d = Pico.ioports[a]; break; // IO ports can be used as RAM\r
+ default: d = PicoMem.ioports[a]; break; // IO ports can be used as RAM\r
}\r
return d;\r
}\r
if (1 <= a && a <= 2)\r
{\r
Pico.m.padDelay[a - 1] = 0;\r
- if (!(Pico.ioports[a] & 0x40) && (d & 0x40))\r
+ if (!(PicoMem.ioports[a] & 0x40) && (d & 0x40))\r
Pico.m.padTHPhase[a - 1]++;\r
}\r
\r
// certain IO ports can be used as RAM\r
- Pico.ioports[a] = d;\r
+ PicoMem.ioports[a] = d;\r
}\r
\r
static int z80_cycles_from_68k(void)\r
{\r
- int m68k_cnt = SekCyclesDone() - timing.m68c_frame_start;\r
+ int m68k_cnt = SekCyclesDone() - Pico.t.m68c_frame_start;\r
return cycles_68k_to_z80(m68k_cnt);\r
}\r
\r
{\r
if (d)\r
{\r
- timing.z80c_cnt = z80_cycles_from_68k() + 2;\r
+ Pico.t.z80c_cnt = z80_cycles_from_68k() + 2;\r
}\r
else\r
{\r
}\r
else\r
{\r
- timing.z80c_cnt = z80_cycles_from_68k() + 2;\r
+ Pico.t.z80c_cnt = z80_cycles_from_68k() + 2;\r
z80_reset();\r
}\r
Pico.m.z80_reset = d;\r
static u32 PicoRead8_sram(u32 a)\r
{\r
u32 d;\r
- if (SRam.start <= a && a <= SRam.end && (Pico.m.sram_reg & SRR_MAPPED))\r
+ if (Pico.sv.start <= a && a <= Pico.sv.end && (Pico.m.sram_reg & SRR_MAPPED))\r
{\r
- if (SRam.flags & SRF_EEPROM) {\r
+ if (Pico.sv.flags & SRF_EEPROM) {\r
d = EEPROM_read();\r
if (!(a & 1))\r
d >>= 8;\r
} else\r
- d = *(u8 *)(SRam.data - SRam.start + a);\r
+ d = *(u8 *)(Pico.sv.data - Pico.sv.start + a);\r
elprintf(EL_SRAMIO, "sram r8 [%06x] %02x @ %06x", a, d, SekPc);\r
return d;\r
}\r
static u32 PicoRead16_sram(u32 a)\r
{\r
u32 d;\r
- if (SRam.start <= a && a <= SRam.end && (Pico.m.sram_reg & SRR_MAPPED))\r
+ if (Pico.sv.start <= a && a <= Pico.sv.end && (Pico.m.sram_reg & SRR_MAPPED))\r
{\r
- if (SRam.flags & SRF_EEPROM)\r
+ if (Pico.sv.flags & SRF_EEPROM)\r
d = EEPROM_read();\r
else {\r
- u8 *pm = (u8 *)(SRam.data - SRam.start + a);\r
+ u8 *pm = (u8 *)(Pico.sv.data - Pico.sv.start + a);\r
d = pm[0] << 8;\r
d |= pm[1];\r
}\r
\r
static void PicoWrite8_sram(u32 a, u32 d)\r
{\r
- if (a > SRam.end || a < SRam.start || !(Pico.m.sram_reg & SRR_MAPPED)) {\r
+ if (a > Pico.sv.end || a < Pico.sv.start || !(Pico.m.sram_reg & SRR_MAPPED)) {\r
m68k_unmapped_write8(a, d);\r
return;\r
}\r
\r
elprintf(EL_SRAMIO, "sram w8 [%06x] %02x @ %06x", a, d & 0xff, SekPc);\r
- if (SRam.flags & SRF_EEPROM)\r
+ if (Pico.sv.flags & SRF_EEPROM)\r
{\r
EEPROM_write8(a, d);\r
}\r
else {\r
- u8 *pm = (u8 *)(SRam.data - SRam.start + a);\r
+ u8 *pm = (u8 *)(Pico.sv.data - Pico.sv.start + a);\r
if (*pm != (u8)d) {\r
- SRam.changed = 1;\r
+ Pico.sv.changed = 1;\r
*pm = (u8)d;\r
}\r
}\r
\r
static void PicoWrite16_sram(u32 a, u32 d)\r
{\r
- if (a > SRam.end || a < SRam.start || !(Pico.m.sram_reg & SRR_MAPPED)) {\r
+ if (a > Pico.sv.end || a < Pico.sv.start || !(Pico.m.sram_reg & SRR_MAPPED)) {\r
m68k_unmapped_write16(a, d);\r
return;\r
}\r
\r
elprintf(EL_SRAMIO, "sram w16 [%06x] %04x @ %06x", a, d & 0xffff, SekPc);\r
- if (SRam.flags & SRF_EEPROM)\r
+ if (Pico.sv.flags & SRF_EEPROM)\r
{\r
EEPROM_write16(d);\r
}\r
else {\r
- u8 *pm = (u8 *)(SRam.data - SRam.start + a);\r
+ u8 *pm = (u8 *)(Pico.sv.data - Pico.sv.start + a);\r
if (pm[0] != (u8)(d >> 8)) {\r
- SRam.changed = 1;\r
+ Pico.sv.changed = 1;\r
pm[0] = (u8)(d >> 8);\r
}\r
if (pm[1] != (u8)d) {\r
- SRam.changed = 1;\r
+ Pico.sv.changed = 1;\r
pm[1] = (u8)d;\r
}\r
}\r
}\r
\r
if ((a & 0x4000) == 0x0000)\r
- d = Pico.zram[a & 0x1fff];\r
+ d = PicoMem.zram[a & 0x1fff];\r
else if ((a & 0x6000) == 0x4000) // 0x4000-0x5fff\r
d = ym2612_read_local_68k(); \r
else\r
}\r
\r
if ((a & 0x4000) == 0x0000) { // z80 RAM\r
- Pico.zram[a & 0x1fff] = (u8)d;\r
+ PicoMem.zram[a & 0x1fff] = (u8)d;\r
return;\r
}\r
if ((a & 0x6000) == 0x4000) { // FM Sound\r
\r
PICO_INTERNAL void PicoMemSetup(void)\r
{\r
- int mask, rs, a;\r
+ int mask, rs, sstart, a;\r
\r
// setup the memory map\r
cpu68k_map_set(m68k_read8_map, 0x000000, 0xffffff, m68k_unmapped_read8, 1);\r
cpu68k_map_set(m68k_read16_map, 0x000000, rs - 1, Pico.rom, 0);\r
\r
// Common case of on-cart (save) RAM, usually at 0x200000-...\r
- if ((SRam.flags & SRF_ENABLED) && SRam.data != NULL) {\r
- rs = SRam.end - SRam.start;\r
+ if ((Pico.sv.flags & SRF_ENABLED) && Pico.sv.data != NULL) {\r
+ sstart = Pico.sv.start;\r
+ rs = Pico.sv.end - sstart;\r
rs = (rs + mask) & ~mask;\r
- if (SRam.start + rs >= 0x1000000)\r
- rs = 0x1000000 - SRam.start;\r
- cpu68k_map_set(m68k_read8_map, SRam.start, SRam.start + rs - 1, PicoRead8_sram, 1);\r
- cpu68k_map_set(m68k_read16_map, SRam.start, SRam.start + rs - 1, PicoRead16_sram, 1);\r
- cpu68k_map_set(m68k_write8_map, SRam.start, SRam.start + rs - 1, PicoWrite8_sram, 1);\r
- cpu68k_map_set(m68k_write16_map, SRam.start, SRam.start + rs - 1, PicoWrite16_sram, 1);\r
+ if (sstart + rs >= 0x1000000)\r
+ rs = 0x1000000 - sstart;\r
+ cpu68k_map_set(m68k_read8_map, sstart, sstart + rs - 1, PicoRead8_sram, 1);\r
+ cpu68k_map_set(m68k_read16_map, sstart, sstart + rs - 1, PicoRead16_sram, 1);\r
+ cpu68k_map_set(m68k_write8_map, sstart, sstart + rs - 1, PicoWrite8_sram, 1);\r
+ cpu68k_map_set(m68k_write16_map, sstart, sstart + rs - 1, PicoWrite16_sram, 1);\r
}\r
\r
// Z80 region\r
\r
// RAM and it's mirrors\r
for (a = 0xe00000; a < 0x1000000; a += 0x010000) {\r
- cpu68k_map_set(m68k_read8_map, a, a + 0xffff, Pico.ram, 0);\r
- cpu68k_map_set(m68k_read16_map, a, a + 0xffff, Pico.ram, 0);\r
- cpu68k_map_set(m68k_write8_map, a, a + 0xffff, Pico.ram, 0);\r
- cpu68k_map_set(m68k_write16_map, a, a + 0xffff, Pico.ram, 0);\r
+ cpu68k_map_set(m68k_read8_map, a, a + 0xffff, PicoMem.ram, 0);\r
+ cpu68k_map_set(m68k_read16_map, a, a + 0xffff, PicoMem.ram, 0);\r
+ cpu68k_map_set(m68k_write8_map, a, a + 0xffff, PicoMem.ram, 0);\r
+ cpu68k_map_set(m68k_write16_map, a, a + 0xffff, PicoMem.ram, 0);\r
}\r
\r
// Setup memory callbacks:\r
{\r
if (is_from_z80) {\r
int mclk_z80 = z80_cyclesDone() * 15;\r
- int mclk_line = timing.z80_scanline * 488 * 7;\r
+ int mclk_line = Pico.t.z80_scanline * 488 * 7;\r
while (mclk_z80 - mclk_line >= 488 * 7)\r
- timing.z80_scanline++, mclk_line += 488 * 7;\r
- return timing.z80_scanline;\r
+ Pico.t.z80_scanline++, mclk_line += 488 * 7;\r
+ return Pico.t.z80_scanline;\r
}\r
\r
return Pico.m.scanline;\r
\r
static void z80_mem_setup(void)\r
{\r
- z80_map_set(z80_read_map, 0x0000, 0x1fff, Pico.zram, 0);\r
- z80_map_set(z80_read_map, 0x2000, 0x3fff, Pico.zram, 0);\r
+ z80_map_set(z80_read_map, 0x0000, 0x1fff, PicoMem.zram, 0);\r
+ z80_map_set(z80_read_map, 0x2000, 0x3fff, PicoMem.zram, 0);\r
z80_map_set(z80_read_map, 0x4000, 0x5fff, ym2612_read_local_z80, 1);\r
z80_map_set(z80_read_map, 0x6000, 0x7fff, z80_md_vdp_read, 1);\r
z80_map_set(z80_read_map, 0x8000, 0xffff, z80_md_bank_read, 1);\r
\r
- z80_map_set(z80_write_map, 0x0000, 0x1fff, Pico.zram, 0);\r
- z80_map_set(z80_write_map, 0x2000, 0x3fff, Pico.zram, 0);\r
+ z80_map_set(z80_write_map, 0x0000, 0x1fff, PicoMem.zram, 0);\r
+ z80_map_set(z80_write_map, 0x2000, 0x3fff, PicoMem.zram, 0);\r
z80_map_set(z80_write_map, 0x4000, 0x5fff, z80_md_ym2612_write, 1);\r
z80_map_set(z80_write_map, 0x6000, 0x7fff, z80_md_vdp_br_write, 1);\r
z80_map_set(z80_write_map, 0x8000, 0xffff, z80_md_bank_write, 1);\r
drZ80.z80_out = z80_md_out;\r
#endif\r
#ifdef _USE_CZ80\r
- Cz80_Set_Fetch(&CZ80, 0x0000, 0x1fff, (FPTR)Pico.zram); // main RAM\r
- Cz80_Set_Fetch(&CZ80, 0x2000, 0x3fff, (FPTR)Pico.zram); // mirror\r
+ Cz80_Set_Fetch(&CZ80, 0x0000, 0x1fff, (FPTR)PicoMem.zram); // main RAM\r
+ Cz80_Set_Fetch(&CZ80, 0x2000, 0x3fff, (FPTR)PicoMem.zram); // mirror\r
Cz80_Set_INPort(&CZ80, z80_md_in);\r
Cz80_Set_OUTPort(&CZ80, z80_md_out);\r
#endif\r
# OUT OF DATE
+#include "pico_int_o32.h"
+
.set noreorder
.set noat
PicoMemReset:
- lui $v1, %hi(Pico+0x22204)
- lw $v1, %lo(Pico+0x22204)($v1) # romsize
+ lui $v1, %hi(Pico+OFS_Pico_romsize)
+ lw $v1, %lo(Pico+OFS_Pico_romsize)($v1) # romsize
lui $t0, 8
addu $v1, $t0
addiu $v1, -1
jr $ra
addiu $v0, $0, 0xffff
-# loads &Pico.rom to $t3
+# loads &Pico to $t3
.macro m_read_rom_try_sram is200000 size
- lui $t2, %hi(SRam)
- addiu $t2, %lo(SRam)
- lui $t3, %hi(Pico+0x22200)
- lw $t1, 8($t2) # SRam.end
+ lui $t2, %hi(Pico)
+ addiu $t2, %lo(Pico)
+ lw $t1, OFS_Pico_sv_end($t2)
.if \is200000
ins $a0, $0, 19, 13
lui $t4, 0x20
.endif
subu $t4, $a0, $t1
bgtz $t4, 1f
- addiu $t3, %lo(Pico+0x22200)
- lw $t1, 4($t2) # SRam.start
+ lw $t1, OFS_Pico_sv_start($t2)
subu $t4, $t1, $a0
bgtz $t4, 1f
nop
- lb $t1, 0x11($t3) # Pico.m.sram_reg
+ lb $t1, OFS_Pico_m_sram_reg($t2)
andi $t4, $t1, 5
beqz $t4, 1f
nop
.endm
.macro m_read8_rom sect
- lui $t0, %hi(Pico+0x22200)
- lw $t0, %lo(Pico+0x22200)($t0) # rom
+ lui $t0, %hi(Pico+OFS_Pico_rom)
+ lw $t0, %lo(Pico+OFS_Pico_rom)($t0) # rom
xori $a0, 1
ins $a0, $0, 19, 13
.if \sect
nop
m_read8_misc_hwreg:
- lui $v0, %hi(Pico+0x2220f)
+ lui $v0, %hi(Pico+OFS_Pico_m_hardware)
jr $ra
- lb $v0, %lo(Pico+0x2220f)($v0)
+ lb $v0, %lo(Pico+OFS_Pico_m_hardware)($v0)
m_read8_misc_ioports:
- lui $v0, %hi(Pico+0x22000)
+ lui $v0, %hi(PicoMem+0x22000)
ins $v0, $t0, 0, 5
jr $ra
- lb $v0, %lo(Pico+0x22000)($v0)
+ lb $v0, %lo(PicoMem+0x22000)($v0)
m_read8_misc2:
lui $t0, 0xa1
nop
m_read8_fake_ym2612:
- lb $v0, %lo(Pico+0x22208)($t0) # Pico.m.rotate
+ lb $v0, %lo(Pico+OFS_Pico_m_rotate)($t0)
addiu $t1, $v0, 1
jr $ra
- sb $t1, %lo(Pico+0x22208)($t0)
+ sb $t1, %lo(Pico+OFS_Pico_m_rotate)($t0)
# delay slot friendly
.macro m_read8_call16 funcname is_func_ptr=0
nop
m_read8_ram:
- lui $t0, %hi(Pico)
+ lui $t0, %hi(PicoMem)
ins $t0, $a0, 0, 16
xori $t0, 1
jr $ra
- lb $v0, %lo(Pico)($t0)
+ lb $v0, %lo(PicoMem)($t0)
m_read8_above_rom:
# might still be SRam (Micro Machines, HardBall '95)
# #############################################################################
.macro m_read16_rom sect
- lui $t0, %hi(Pico+0x22200)
- lw $t0, %lo(Pico+0x22200)($t0) # rom
+ lui $t0, %hi(Pico+OFS_Pico_rom)
+ lw $t0, %lo(Pico+OFS_Pico_rom)($t0) # rom
ins $a0, $0, 0, 1
ins $a0, $0, 19, 13
.if \sect
nop
m_read16_ram:
- lui $t0, %hi(Pico)
+ lui $t0, %hi(PicoMem)
ins $a0, $0, 0, 1
ins $t0, $a0, 0, 16
jr $ra
- lh $v0, %lo(Pico)($t0)
+ lh $v0, %lo(PicoMem)($t0)
m_read16_above_rom:
# might still be SRam
# #############################################################################
.macro m_read32_rom sect
- lui $t0, %hi(Pico+0x22200)
- lw $t0, %lo(Pico+0x22200)($t0) # rom
+ lui $t0, %hi(Pico+OFS_Pico_rom)
+ lw $t0, %lo(Pico+OFS_Pico_rom)($t0) # rom
ins $a0, $0, 0, 1
ins $a0, $0, 19, 13
.if \sect
m_read32_call16 PicoVideoRead
m_read32_ram:
- lui $t0, %hi(Pico)
+ lui $t0, %hi(PicoMem)
ins $a0, $0, 0, 1
ins $t0, $a0, 0, 16
- lh $v1, %lo(Pico)($t0)
- lh $v0, %lo(Pico+2)($t0)
+ lh $v1, %lo(PicoMem)($t0)
+ lh $v0, %lo(PicoMem+2)($t0)
jr $ra
ins $v0, $v1, 16, 16
bnez $a0, pwr_banking
# sram register
- lui $t0, %hi(Pico+0x22211)
- lb $t1, %lo(Pico+0x22211)($t0) # Pico.m.sram_reg
+ lui $t0, %hi(Pico+OFS_Pico_m_sram_reg)
+ lb $t1, %lo(Pico+OFS_Pico_m_sram_reg)($t0) # Pico.m.sram_reg
ins $t1, $a1, 0, 2
jr $ra
- sb $t1, %lo(Pico+0x22211)($t0)
+ sb $t1, %lo(Pico+OFS_Pico_m_sram_reg)($t0)
pwr_banking:
andi $a1, 0x1f
* See COPYING file in the top-level directory.\r
*/\r
\r
+#include "pico_int_o32.h"\r
+\r
.equ SRR_MAPPED, (1 << 0)\r
.equ SRR_READONLY, (1 << 1)\r
.equ SRF_EEPROM, (1 << 1)\r
.global PicoWrite8_io\r
.global PicoWrite16_io\r
\r
-PicoRead8_sram: @ u32 a, u32 d\r
- ldr r2, =(SRam)\r
- ldr r3, =(Pico+0x22200)\r
- ldr r1, [r2, #8] @ SRam.end\r
+PicoRead8_sram: @ u32 a\r
+ ldr r3, =Pico\r
+ ldr r1, [r3, #OFS_Pico_sv_end]\r
cmp r0, r1\r
bgt m_read8_nosram\r
- ldr r1, [r2, #4] @ SRam.start\r
- cmp r0, r1\r
+ ldr r2, [r3, #OFS_Pico_sv_start]\r
+ cmp r0, r2\r
blt m_read8_nosram\r
- ldrb r1, [r3, #0x11] @ Pico.m.sram_reg\r
+ ldrb r1, [r3, #OFS_Pico_m_sram_reg]\r
tst r1, #SRR_MAPPED\r
beq m_read8_nosram\r
- ldr r1, [r2, #0x0c]\r
+ ldr r1, [r3, #OFS_Pico_sv_flags]\r
tst r1, #SRF_EEPROM\r
bne m_read8_eeprom\r
- ldr r1, [r2, #4] @ SRam.start\r
- ldr r2, [r2] @ SRam.data\r
- sub r0, r0, r1\r
- add r0, r0, r2\r
- ldrb r0, [r0]\r
+ ldr r1, [r3, #OFS_Pico_sv_data]\r
+ sub r0, r0, r2\r
+ ldrb r0, [r0, r1]\r
bx lr\r
\r
m_read8_nosram:\r
- ldr r1, [r3, #4] @ romsize\r
+ ldr r1, [r3, #OFS_Pico_romsize]\r
cmp r0, r1\r
movgt r0, #0\r
bxgt lr @ bad location\r
@ XXX: banking unfriendly\r
- ldr r1, [r3]\r
+ ldr r1, [r3, #OFS_Pico_rom]\r
eor r0, r0, #1\r
ldrb r0, [r1, r0]\r
bx lr\r
bx lr\r
\r
\r
-PicoRead8_io: @ u32 a, u32 d\r
+PicoRead8_io: @ u32 a\r
bic r2, r0, #0x001f @ most commonly we get i/o port read,\r
cmp r2, #0xa10000 @ so check for it first\r
beq io_ports_read\r
cmp r2, #0x1000\r
bne m_read8_not_brq\r
\r
- ldr r3, =(Pico+0x22200)\r
+ ldr r3, =Pico\r
mov r1, r0\r
- ldr r0, [r3, #8] @ Pico.m.rotate\r
+ ldr r0, [r3, #OFS_Pico_m_rotate]\r
add r0, r0, #1\r
- strb r0, [r3, #8]\r
+ strb r0, [r3, #OFS_Pico_m_rotate]\r
eor r0, r0, r0, lsl #6\r
\r
tst r1, #1\r
cmp r2, #0x1100\r
bxne lr @ not busreq\r
\r
- ldrb r1, [r3, #(8+0x01)] @ Pico.m.z80Run\r
- ldrb r2, [r3, #(8+0x0f)] @ Pico.m.z80_reset\r
+ ldrb r1, [r3, #OFS_Pico_m_z80Run]\r
+ ldrb r2, [r3, #OFS_Pico_m_z80_reset]\r
orr r0, r0, r1\r
orr r0, r0, r2\r
bx lr\r
@ @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@\r
\r
PicoRead16_sram: @ u32 a, u32 d\r
- ldr r2, =(SRam)\r
- ldr r3, =(Pico+0x22200)\r
- ldr r1, [r2, #8] @ SRam.end\r
+ ldr r3, =Pico\r
+ ldr r1, [r3, #OFS_Pico_sv_end]\r
cmp r0, r1\r
bgt m_read16_nosram\r
- ldr r1, [r2, #4] @ SRam.start\r
- cmp r0, r1\r
+ ldr r2, [r3, #OFS_Pico_sv_start]\r
+ cmp r0, r2\r
blt m_read16_nosram\r
- ldrb r1, [r3, #0x11] @ Pico.m.sram_reg\r
+ ldrb r1, [r3, #OFS_Pico_m_sram_reg]\r
tst r1, #SRR_MAPPED\r
beq m_read16_nosram\r
- ldr r1, [r2, #0x0c]\r
+ ldr r1, [r3, #OFS_Pico_sv_flags]\r
tst r1, #SRF_EEPROM\r
bne EEPROM_read\r
- ldr r1, [r2, #4] @ SRam.start\r
- ldr r2, [r2] @ SRam.data\r
- sub r0, r0, r1\r
- add r0, r0, r2\r
- ldrb r1, [r0], #1\r
- ldrb r0, [r0]\r
+ ldr r1, [r3, #OFS_Pico_sv_data]\r
+ sub r0, r0, r2\r
+ ldrb r1, [r0, r1]!\r
+ ldrb r0, [r0, #1]\r
orr r0, r0, r1, lsl #8\r
bx lr\r
\r
m_read16_nosram:\r
- ldr r1, [r3, #4] @ romsize\r
+ ldr r1, [r3, #OFS_Pico_romsize]\r
cmp r0, r1\r
movgt r0, #0\r
bxgt lr @ bad location\r
@ XXX: banking unfriendly\r
- ldr r1, [r3]\r
+ ldr r1, [r3, #OFS_Pico_rom]\r
ldrh r0, [r1, r0]\r
bx lr\r
\r
cmp r2, #0x1000\r
bne m_read16_not_brq\r
\r
- ldr r3, =(Pico+0x22200)\r
+ ldr r3, =Pico\r
and r2, r0, #0xff00\r
- ldr r0, [r3, #8] @ Pico.m.rotate\r
+ ldr r0, [r3, #OFS_Pico_m_rotate]\r
add r0, r0, #1\r
- strb r0, [r3, #8]\r
+ strb r0, [r3, #OFS_Pico_m_rotate]\r
eor r0, r0, r0, lsl #5\r
eor r0, r0, r0, lsl #8\r
bic r0, r0, #0x100 @ bit8 defined in this area\r
cmp r2, #0x1100\r
bxne lr @ not busreq\r
\r
- ldrb r1, [r3, #(8+0x01)] @ Pico.m.z80Run\r
- ldrb r2, [r3, #(8+0x0f)] @ Pico.m.z80_reset\r
+ ldrb r1, [r3, #OFS_Pico_m_z80Run]\r
+ ldrb r2, [r3, #OFS_Pico_m_z80_reset]\r
orr r0, r0, r1, lsl #8\r
orr r0, r0, r2, lsl #8\r
bx lr\r
eor r2, r2, #0x003000\r
eors r2, r2, #0x0000f1\r
bne m_write8_not_sreg\r
- ldr r3, =(Pico+0x22200)\r
- ldrb r2, [r3, #(8+9)] @ Pico.m.sram_reg\r
+ ldr r3, =Pico\r
+ ldrb r2, [r3, #OFS_Pico_m_sram_reg]\r
and r1, r1, #(SRR_MAPPED|SRR_READONLY)\r
bic r2, r2, #(SRR_MAPPED|SRR_READONLY)\r
orr r2, r2, r1\r
- strb r2, [r3, #(8+9)]\r
+ strb r2, [r3, #OFS_Pico_m_sram_reg]\r
bx lr\r
\r
m_write8_not_sreg:\r
eor r2, r2, #0x003000\r
eors r2, r2, #0x0000f0\r
bne m_write16_not_sreg\r
- ldr r3, =(Pico+0x22200)\r
- ldrb r2, [r3, #(8+9)] @ Pico.m.sram_reg\r
+ ldr r3, =Pico\r
+ ldrb r2, [r3, #OFS_Pico_m_sram_reg]\r
and r1, r1, #(SRR_MAPPED|SRR_READONLY)\r
bic r2, r2, #(SRR_MAPPED|SRR_READONLY)\r
orr r2, r2, r1\r
- strb r2, [r3, #(8+9)]\r
+ strb r2, [r3, #OFS_Pico_m_sram_reg]\r
bx lr\r
\r
m_write16_not_sreg:\r
unsigned char *pd = Pico.est.HighCol + sx;
unsigned int pack, t;
- pack = *(unsigned int *)(Pico.vram + addr); /* Get 4 bitplanes / 8 pixels */
+ pack = *(unsigned int *)(PicoMem.vram + addr); /* Get 4 bitplanes / 8 pixels */
if (pack)
{
PLANAR_PIXEL(0, 0)
unsigned char *pd = Pico.est.HighCol + sx;
unsigned int pack, t;
- pack = *(unsigned int *)(Pico.vram + addr); /* Get 4 bitplanes / 8 pixels */
+ pack = *(unsigned int *)(PicoMem.vram + addr); /* Get 4 bitplanes / 8 pixels */
if (pack)
{
PLANAR_PIXEL(0, 7)
if (pv->reg[0] & 8)
xoff = 0;
- sat = (unsigned char *)Pico.vram + ((pv->reg[5] & 0x7e) << 7);
+ sat = (unsigned char *)PicoMem.vram + ((pv->reg[5] & 0x7e) << 7);
if (pv->reg[1] & 2) {
addr_mask = 0xfe; h = 16;
} else {
line -= 224;
// Find name table:
- nametab = Pico.vram;
+ nametab = PicoMem.vram;
nametab += (pv->reg[2] & 0x0e) << (10-1);
nametab += (line>>3) << (6-1);
void PicoDoHighPal555M4(void)
{
- unsigned int *spal=(void *)Pico.cram;
+ unsigned int *spal=(void *)PicoMem.cram;
unsigned int *dpal=(void *)Pico.est.HighPal;
unsigned int t;
int i;
#include "sound/ym2612.h"\r
\r
struct Pico Pico;\r
+struct PicoMem PicoMem;\r
int PicoOpt; \r
int PicoSkipFrame; // skip rendering frame?\r
int PicoPad[2]; // Joypads, format is MXYZ SACB RLDU\r
int PicoRegionOverride; // override the region detection 0: Auto, 1: Japan NTSC, 2: Japan PAL, 4: US, 8: Europe\r
int PicoAutoRgnOrder;\r
\r
-struct PicoSRAM SRam;\r
int emustatus; // rapid_ym2612, multi_ym_updates\r
\r
-struct PicoTiming timing;\r
-\r
void (*PicoWriteSound)(int len) = NULL; // called at the best time to send sound buffer (PsndOut) to hardware\r
void (*PicoResetHook)(void) = NULL;\r
void (*PicoLineHook)(void) = NULL;\r
{\r
// Blank space for state:\r
memset(&Pico,0,sizeof(Pico));\r
+ memset(&PicoMem,0,sizeof(PicoMem));\r
memset(&PicoPad,0,sizeof(PicoPad));\r
memset(&PicoPadInt,0,sizeof(PicoPadInt));\r
\r
- Pico.est.Pico_video = &Pico.video;\r
- Pico.est.Pico_vram = Pico.vram;\r
+ Pico.est.Pico = &Pico;\r
+ Pico.est.PicoMem_vram = PicoMem.vram;\r
+ Pico.est.PicoMem_cram = PicoMem.cram;\r
Pico.est.PicoOpt = &PicoOpt;\r
\r
// Init CPUs:\r
PicoCartUnload();\r
z80_exit();\r
\r
- if (SRam.data)\r
- free(SRam.data);\r
+ if (Pico.sv.data)\r
+ free(Pico.sv.data);\r
pevt_dump();\r
}\r
\r
void PicoPower(void)\r
{\r
Pico.m.frame_count = 0;\r
- SekCycleCnt = SekCycleAim = 0;\r
+ Pico.t.m68c_cnt = Pico.t.m68c_aim = 0;\r
\r
// clear all memory of the emulated machine\r
- memset(&Pico.ram,0,(unsigned char *)&Pico.rom - Pico.ram);\r
+ memset(&PicoMem,0,sizeof(PicoMem));\r
\r
memset(&Pico.video,0,sizeof(Pico.video));\r
memset(&Pico.m,0,sizeof(Pico.m));\r
z80_reset();\r
\r
// my MD1 VA6 console has this in IO\r
- Pico.ioports[1] = Pico.ioports[2] = Pico.ioports[3] = 0xff;\r
+ PicoMem.ioports[1] = PicoMem.ioports[2] = PicoMem.ioports[3] = 0xff;\r
\r
// default VDP register values (based on Fusion)\r
Pico.video.reg[0] = Pico.video.reg[1] = 0x04;\r
\r
// reset sram state; enable sram access by default if it doesn't overlap with ROM\r
Pico.m.sram_reg = 0;\r
- if ((SRam.flags & SRF_EEPROM) || Pico.romsize <= SRam.start)\r
+ if ((Pico.sv.flags & SRF_EEPROM) || Pico.romsize <= Pico.sv.start)\r
Pico.m.sram_reg |= SRR_MAPPED;\r
\r
- if (SRam.flags & SRF_ENABLED)\r
- elprintf(EL_STATUS, "sram: %06x - %06x; eeprom: %i", SRam.start, SRam.end,\r
- !!(SRam.flags & SRF_EEPROM));\r
+ if (Pico.sv.flags & SRF_ENABLED)\r
+ elprintf(EL_STATUS, "sram: %06x - %06x; eeprom: %i", Pico.sv.start, Pico.sv.end,\r
+ !!(Pico.sv.flags & SRF_EEPROM));\r
\r
return 0;\r
}\r
\r
elprintf(EL_VDPDMA, "~Dma %i op=%i can=%i burn=%i [%u]",\r
Pico.m.dma_xfers, dma_op1, xfers_can, burn, SekCyclesDone());\r
- //dprintf("~aim: %i, cnt: %i", SekCycleAim, SekCycleCnt);\r
+ //dprintf("~aim: %i, cnt: %i", Pico.t.m68c_aim, Pico.t.m68c_cnt);\r
return burn;\r
}\r
\r
int m68k_cnt;\r
int cnt;\r
\r
- m68k_cnt = m68k_cycles_done - timing.m68c_frame_start;\r
- timing.z80c_aim = cycles_68k_to_z80(m68k_cnt);\r
- cnt = timing.z80c_aim - timing.z80c_cnt;\r
+ m68k_cnt = m68k_cycles_done - Pico.t.m68c_frame_start;\r
+ Pico.t.z80c_aim = cycles_68k_to_z80(m68k_cnt);\r
+ cnt = Pico.t.z80c_aim - Pico.t.z80c_cnt;\r
\r
pprof_start(z80);\r
\r
elprintf(EL_BUSREQ, "z80 sync %i (%u|%u -> %u|%u)", cnt,\r
- timing.z80c_cnt, timing.z80c_cnt * 15 / 7 / 488,\r
- timing.z80c_aim, timing.z80c_aim * 15 / 7 / 488);\r
+ Pico.t.z80c_cnt, Pico.t.z80c_cnt * 15 / 7 / 488,\r
+ Pico.t.z80c_aim, Pico.t.z80c_aim * 15 / 7 / 488);\r
\r
if (cnt > 0)\r
- timing.z80c_cnt += z80_run(cnt);\r
+ Pico.t.z80c_cnt += z80_run(cnt);\r
\r
pprof_end(z80);\r
}\r
SekRunM68k(m68k_cycles)
#endif
-// sync m68k to SekCycleAim
+// sync m68k to Pico.t.m68c_aim
static void SekSyncM68k(void)
{
int cyc_do;
pprof_start(m68k);
pevt_log_m68k_o(EVT_RUN_START);
- while ((cyc_do = SekCycleAim - SekCycleCnt) > 0) {
- SekCycleCnt += cyc_do;
+ while ((cyc_do = Pico.t.m68c_aim - Pico.t.m68c_cnt) > 0) {
+ Pico.t.m68c_cnt += cyc_do;
#if defined(EMU_C68K)
PicoCpuCM68k.cycles = cyc_do;
CycloneRun(&PicoCpuCM68k);
- SekCycleCnt -= PicoCpuCM68k.cycles;
+ Pico.t.m68c_cnt -= PicoCpuCM68k.cycles;
#elif defined(EMU_M68K)
- SekCycleCnt += m68k_execute(cyc_do) - cyc_do;
+ Pico.t.m68c_cnt += m68k_execute(cyc_do) - cyc_do;
#elif defined(EMU_F68K)
- SekCycleCnt += fm68k_emulate(cyc_do, 0) - cyc_do;
+ Pico.t.m68c_cnt += fm68k_emulate(cyc_do, 0) - cyc_do;
#endif
}
static inline void SekRunM68k(int cyc)
{
- SekCycleAim += cyc;
- cyc = SekCycleAim - SekCycleCnt;
+ Pico.t.m68c_aim += cyc;
+ cyc = Pico.t.m68c_aim - Pico.t.m68c_cnt;
if (cyc <= 0)
return;
- SekCycleCnt += cyc >> 6; // refresh slowdowns
+ Pico.t.m68c_cnt += cyc >> 6; // refresh slowdowns
SekSyncM68k();
}
}
else skip=PicoSkipFrame;
- timing.m68c_frame_start = SekCyclesDone();
+ Pico.t.m68c_frame_start = SekCyclesDone();
pv->v_counter = Pico.m.scanline = 0;
z80_resetCycles();
PsndStartFrame();
}
// Run scanline:
- line_base_cycles = SekCyclesDone();
+ Pico.t.m68c_line_start = SekCyclesDone();
do_timing_hacks_as(pv, vdp_slots);
CPUS_RUN(CYCLES_M68K_LINE);
// there must be a delay after vblank bit is set and irq is asserted (Mazin Saga)
// also delay between F bit (bit 7) is set in SR and IRQ happens (Ex-Mutants)
// also delay between last H-int and V-int (Golden Axe 3)
- line_base_cycles = SekCyclesDone();
+ Pico.t.m68c_line_start = SekCyclesDone();
do_timing_hacks_vb();
CPUS_RUN(CYCLES_M68K_VINT_LAG);
}
// Run scanline:
- line_base_cycles = SekCyclesDone();
+ Pico.t.m68c_line_start = SekCyclesDone();
do_timing_hacks_vb();
CPUS_RUN(CYCLES_M68K_LINE);
}
// Run scanline:
- line_base_cycles = SekCyclesDone();
+ Pico.t.m68c_line_start = SekCyclesDone();
do_timing_hacks_as(pv, vdp_slots);
CPUS_RUN(CYCLES_M68K_LINE);
#endif\r
#endif // EMU_M68K\r
\r
-// while running, cnt represents target of current timeslice\r
-// while not in SekRun(), it's actual cycles done\r
-// (but always use SekCyclesDone() if you need current position)\r
-// cnt may change if timeslice is ended prematurely or extended,\r
-// so we use SekCycleAim for the actual target\r
-extern unsigned int SekCycleCnt;\r
-extern unsigned int SekCycleAim;\r
-\r
// number of cycles done (can be checked anywhere)\r
-#define SekCyclesDone() (SekCycleCnt - SekCyclesLeft)\r
+#define SekCyclesDone() (Pico.t.m68c_cnt - SekCyclesLeft)\r
\r
// burn cycles while not in SekRun() and while in\r
-#define SekCyclesBurn(c) SekCycleCnt += c\r
+#define SekCyclesBurn(c) Pico.t.m68c_cnt += c\r
#define SekCyclesBurnRun(c) { \\r
SekCyclesLeft -= c; \\r
}\r
\r
// note: sometimes may extend timeslice to delay an irq\r
#define SekEndRun(after) { \\r
- SekCycleCnt -= SekCyclesLeft - (after); \\r
+ Pico.t.m68c_cnt -= SekCyclesLeft - (after); \\r
SekCyclesLeft = after; \\r
}\r
\r
#define Z80_STATE_SIZE 0x60\r
\r
#define z80_resetCycles() \\r
- timing.z80c_cnt = timing.z80c_aim = timing.z80_scanline = 0\r
+ Pico.t.z80c_cnt = Pico.t.z80c_aim = Pico.t.z80_scanline = 0\r
\r
#define z80_cyclesDone() \\r
- (timing.z80c_aim - z80_cyclesLeft)\r
+ (Pico.t.z80c_aim - z80_cyclesLeft)\r
\r
#define cycles_68k_to_z80(x) ((x) * 3823 >> 13)\r
\r
void *DrawLineDest; // draw destination\r
unsigned char *HighCol;\r
int *HighPreSpr;\r
- void *Pico_video;\r
- void *Pico_vram;\r
+ struct Pico *Pico;\r
+ void *PicoMem_vram;\r
+ void *PicoMem_cram;\r
int *PicoOpt;\r
unsigned char *Draw2FB;\r
unsigned short HighPal[0x100];\r
};\r
\r
-// some assembly stuff depend on these, do not touch!\r
-struct Pico\r
+// some assembly stuff still depends on these, do not touch!\r
+struct PicoMem\r
{\r
unsigned char ram[0x10000]; // 0x00000 scratch ram\r
union { // vram is byteswapped for easier reads when drawing\r
unsigned char pad[0xf0]; // unused\r
unsigned short cram[0x40]; // 0x22100\r
unsigned short vsram[0x40]; // 0x22180\r
-\r
- unsigned char *rom; // 0x22200\r
- unsigned int romsize; // 0x22204 (on 32bits)\r
-\r
- struct PicoMisc m;\r
- struct PicoVideo video;\r
- struct PicoMS ms;\r
- struct PicoEState est;\r
};\r
\r
// sram\r
#define SRF_ENABLED (1 << 0)\r
#define SRF_EEPROM (1 << 1)\r
\r
-struct PicoSRAM\r
+struct PicoCartSave\r
{\r
unsigned char *data; // actual data\r
unsigned int start; // start address in 68k address space\r
unsigned int size;\r
};\r
\r
+struct PicoTiming\r
+{\r
+ // while running, cnt represents target of current timeslice\r
+ // while not in SekRun(), it's actual cycles done\r
+ // (but always use SekCyclesDone() if you need current position)\r
+ // _cnt may change if timeslice is ended prematurely or extended,\r
+ // so we use _aim for the actual target\r
+ unsigned int m68c_cnt;\r
+ unsigned int m68c_aim;\r
+ unsigned int m68c_frame_start; // m68k cycles\r
+ unsigned int m68c_line_start;\r
+\r
+ unsigned int z80c_cnt; // z80 cycles done (this frame)\r
+ unsigned int z80c_aim;\r
+ int z80_scanline;\r
+};\r
+\r
+// run tools/mkoffsets pico/pico_int_o32.h if you change these\r
+// careful with savestate compat\r
+struct Pico\r
+{\r
+ struct PicoVideo video;\r
+ struct PicoMisc m;\r
+ struct PicoTiming t;\r
+ struct PicoCartSave sv;\r
+ struct PicoEState est;\r
+ struct PicoMS ms;\r
+\r
+ unsigned char *rom;\r
+ unsigned int romsize;\r
+};\r
+\r
// MCD\r
#define PCM_MIXBUF_LEN ((12500000 / 384) / 50 + 1)\r
\r
unsigned short pwm_fifo[2][4]; // [0] - current raw, others - fifo entries\r
};\r
\r
-struct PicoTiming\r
-{\r
- unsigned int m68c_frame_start; // m68k cycles\r
- unsigned int z80c_cnt; // z80 cycles done (this frame)\r
- unsigned int z80c_aim;\r
- int z80_scanline;\r
-};\r
-extern struct PicoTiming timing;\r
-\r
// area.c\r
extern void (*PicoLoadStateHook)(void);\r
\r
\r
// pico.c\r
extern struct Pico Pico;\r
-extern struct PicoSRAM SRam;\r
+extern struct PicoMem PicoMem;\r
extern int PicoPadInt[2];\r
extern int emustatus;\r
extern void (*PicoResetHook)(void);\r
\r
\r
// videoport.c\r
-extern int line_base_cycles;\r
PICO_INTERNAL_ASM void PicoVideoWrite(unsigned int a,unsigned short d);\r
PICO_INTERNAL_ASM unsigned int PicoVideoRead(unsigned int a);\r
unsigned char PicoVideoRead8DataH(void);\r
void p32x_schedule_hint(SH2 *sh2, int m68k_cycles);\r
\r
// 32x/memory.c\r
-struct Pico32xMem *Pico32xMem;\r
+extern struct Pico32xMem *Pico32xMem;\r
unsigned int PicoRead8_32x(unsigned int a);\r
unsigned int PicoRead16_32x(unsigned int a);\r
void PicoWrite8_32x(unsigned int a, unsigned int d);\r
-/* autogenerated by ./tools/mkoffsets, do not edit */
-#define OFS_DrawScanline 0x00
-#define OFS_rendstatus 0x04
-#define OFS_DrawLineDest 0x08
-#define OFS_HighCol 0x0c
-#define OFS_HighPreSpr 0x10
-#define OFS_Pico_video 0x14
-#define OFS_Pico_vram 0x18
-#define OFS_PicoOpt 0x1c
-#define OFS_Draw2FB 0x20
-#define OFS_HighPal 0x24
+/* autogenerated by tools/mkoffsets, do not edit */
+#define OFS_Pico_video_reg 0x0000
+#define OFS_Pico_m_rotate 0x0040
+#define OFS_Pico_m_z80Run 0x0041
+#define OFS_Pico_m_dirtyPal 0x0046
+#define OFS_Pico_m_hardware 0x0047
+#define OFS_Pico_m_z80_reset 0x004f
+#define OFS_Pico_m_sram_reg 0x0049
+#define OFS_Pico_sv 0x007c
+#define OFS_Pico_sv_data 0x007c
+#define OFS_Pico_sv_start 0x0080
+#define OFS_Pico_sv_end 0x0084
+#define OFS_Pico_sv_flags 0x0088
+#define OFS_Pico_rom 0x031c
+#define OFS_Pico_romsize 0x0320
+#define OFS_EST_DrawScanline 0x00
+#define OFS_EST_rendstatus 0x04
+#define OFS_EST_DrawLineDest 0x08
+#define OFS_EST_HighCol 0x0c
+#define OFS_EST_HighPreSpr 0x10
+#define OFS_EST_Pico 0x14
+#define OFS_EST_PicoMem_vram 0x18
+#define OFS_EST_PicoMem_cram 0x1c
+#define OFS_EST_PicoOpt 0x20
+#define OFS_EST_Draw2FB 0x24
+#define OFS_EST_HighPal 0x28
#include "pico_int.h"\r
#include "memory.h"\r
\r
-\r
-unsigned int SekCycleCnt;\r
-unsigned int SekCycleAim;\r
-\r
-\r
/* context */\r
// Cyclone 68000\r
#ifdef EMU_C68K\r
static int SekIntAck(int level)\r
{\r
// try to emulate VDP's reaction to 68000 int ack\r
- if (level == 4) { Pico.video.pending_ints = 0; elprintf(EL_INTS, "hack: @ %06x [%u]", SekPc, SekCycleCnt); }\r
- else if(level == 6) { Pico.video.pending_ints &= ~0x20; elprintf(EL_INTS, "vack: @ %06x [%u]", SekPc, SekCycleCnt); }\r
+ if (level == 4) { Pico.video.pending_ints = 0; elprintf(EL_INTS, "hack: @ %06x [%u]", SekPc, Pico.t.m68c_cnt); }\r
+ else if(level == 6) { Pico.video.pending_ints &= ~0x20; elprintf(EL_INTS, "vack: @ %06x [%u]", SekPc, Pico.t.m68c_cnt); }\r
PicoCpuCM68k.irq = 0;\r
return CYCLONE_INT_ACK_AUTOVECTOR;\r
}\r
#ifdef EMU_M68K\r
static int SekIntAckM68K(int level)\r
{\r
- if (level == 4) { Pico.video.pending_ints = 0; elprintf(EL_INTS, "hack: @ %06x [%u]", SekPc, SekCycleCnt); }\r
- else if(level == 6) { Pico.video.pending_ints &= ~0x20; elprintf(EL_INTS, "vack: @ %06x [%u]", SekPc, SekCycleCnt); }\r
+ if (level == 4) { Pico.video.pending_ints = 0; elprintf(EL_INTS, "hack: @ %06x [%u]", SekPc, Pico.t.m68c_cnt); }\r
+ else if(level == 6) { Pico.video.pending_ints &= ~0x20; elprintf(EL_INTS, "vack: @ %06x [%u]", SekPc, Pico.t.m68c_cnt); }\r
CPU_INT_LEVEL = 0;\r
return M68K_INT_ACK_AUTOVECTOR;\r
}\r
\r
void SekStepM68k(void)\r
{\r
- SekCycleAim=SekCycleCnt+1;\r
+ Pico.t.m68c_aim = Pico.t.m68c_cnt + 1;\r
#if defined(EMU_CORE_DEBUG)\r
- SekCycleCnt+=CM_compareRun(1, 0);\r
+ Pico.t.m68c_cnt += CM_compareRun(1, 0);\r
#elif defined(EMU_C68K)\r
PicoCpuCM68k.cycles=1;\r
CycloneRun(&PicoCpuCM68k);\r
- SekCycleCnt+=1-PicoCpuCM68k.cycles;\r
+ Pico.t.m68c_cnt += 1 - PicoCpuCM68k.cycles;\r
#elif defined(EMU_M68K)\r
- SekCycleCnt+=m68k_execute(1);\r
+ Pico.t.m68c_cnt += m68k_execute(1);\r
#elif defined(EMU_F68K)\r
- SekCycleCnt+=fm68k_emulate(1, 0);\r
+ Pico.t.m68c_cnt += fm68k_emulate(1, 0);\r
#endif\r
}\r
\r
\r
*(unsigned int *)(cpu+0x40) = pc;\r
*(unsigned int *)(cpu+0x50) =\r
- is_sub ? SekCycleCntS68k : SekCycleCnt;\r
+ is_sub ? SekCycleCntS68k : Pico.t.m68c_cnt;\r
}\r
\r
PICO_INTERNAL void SekUnpackCpu(const unsigned char *cpu, int is_sub)\r
if (is_sub)\r
SekCycleCntS68k = *(unsigned int *)(cpu+0x50);\r
else\r
- SekCycleCnt = *(unsigned int *)(cpu+0x50);\r
+ Pico.t.m68c_cnt = *(unsigned int *)(cpu+0x50);\r
}\r
\r
\r
struct ref_68k *x68k = &ref_68ks[is_s68k];\r
u32 pc = is_s68k ? SekPcS68k : SekPc;\r
u32 sr = is_s68k ? SekSrS68k : SekSr;\r
- u32 cycles = is_s68k ? SekCycleCntS68k : SekCycleCnt;\r
+ u32 cycles = is_s68k ? SekCycleCntS68k : Pico.t.m68c_cnt;\r
u32 r;\r
u8 cmd;\r
#ifdef CPU_CMP_W\r
struct PicoVideo *pv = &Pico.video;
unsigned char d;
- d = Pico.vramb[pv->addr];
+ d = PicoMem.vramb[pv->addr];
pv->addr = (pv->addr + 1) & 0x3fff;
pv->pending = 0;
return d;
struct PicoVideo *pv = &Pico.video;
if (pv->type == 3) {
- Pico.cram[pv->addr & 0x1f] = d;
+ PicoMem.cram[pv->addr & 0x1f] = d;
Pico.m.dirtyPal = 1;
} else {
- Pico.vramb[pv->addr] = d;
+ PicoMem.vramb[pv->addr] = d;
}
pv->addr = (pv->addr + 1) & 0x3fff;
{
elprintf(EL_IO, "z80 write [%04x] %02x", a, d);
if (a >= 0xc000)
- Pico.zram[a & 0x1fff] = d;
+ PicoMem.zram[a & 0x1fff] = d;
if (a >= 0xfff8)
write_bank(a, d);
}
{
int s, tmp;
- memset(&Pico.ram,0,(unsigned char *)&Pico.rom - Pico.ram);
+ memset(&PicoMem,0,sizeof(PicoMem));
memset(&Pico.video,0,sizeof(Pico.video));
memset(&Pico.m,0,sizeof(Pico.m));
Pico.m.pal = 0;
void PicoMemSetupMS(void)
{
z80_map_set(z80_read_map, 0x0000, 0xbfff, Pico.rom, 0);
- z80_map_set(z80_read_map, 0xc000, 0xdfff, Pico.zram, 0);
- z80_map_set(z80_read_map, 0xe000, 0xffff, Pico.zram, 0);
+ z80_map_set(z80_read_map, 0xc000, 0xdfff, PicoMem.zram, 0);
+ z80_map_set(z80_read_map, 0xe000, 0xffff, PicoMem.zram, 0);
z80_map_set(z80_write_map, 0x0000, 0xbfff, xwrite, 1);
- z80_map_set(z80_write_map, 0xc000, 0xdfff, Pico.zram, 0);
+ z80_map_set(z80_write_map, 0xc000, 0xdfff, PicoMem.zram, 0);
z80_map_set(z80_write_map, 0xe000, 0xffff, xwrite, 1);
#ifdef _USE_DRZ80
#endif
#ifdef _USE_CZ80
Cz80_Set_Fetch(&CZ80, 0x0000, 0xbfff, (FPTR)Pico.rom);
- Cz80_Set_Fetch(&CZ80, 0xc000, 0xdfff, (FPTR)Pico.zram);
- Cz80_Set_Fetch(&CZ80, 0xe000, 0xffff, (FPTR)Pico.zram);
+ Cz80_Set_Fetch(&CZ80, 0xc000, 0xdfff, (FPTR)PicoMem.zram);
+ Cz80_Set_Fetch(&CZ80, 0xe000, 0xffff, (FPTR)PicoMem.zram);
Cz80_Set_INPort(&CZ80, z80_sms_in);
Cz80_Set_OUTPort(&CZ80, z80_sms_out);
#endif
memset(buff, 0, sizeof(buff));\r
SekPackCpu(buff, 0);\r
CHECKED_WRITE_BUFF(CHUNK_M68K, buff);\r
- CHECKED_WRITE_BUFF(CHUNK_RAM, Pico.ram);\r
- CHECKED_WRITE_BUFF(CHUNK_VSRAM, Pico.vsram);\r
- CHECKED_WRITE_BUFF(CHUNK_IOPORTS, Pico.ioports);\r
+ CHECKED_WRITE_BUFF(CHUNK_RAM, PicoMem.ram);\r
+ CHECKED_WRITE_BUFF(CHUNK_VSRAM, PicoMem.vsram);\r
+ CHECKED_WRITE_BUFF(CHUNK_IOPORTS, PicoMem.ioports);\r
ym2612_pack_state();\r
CHECKED_WRITE(CHUNK_FM, 0x200+4, ym2612_regs);\r
}\r
CHECKED_WRITE_BUFF(CHUNK_SMS, Pico.ms);\r
}\r
\r
- CHECKED_WRITE_BUFF(CHUNK_VRAM, Pico.vram);\r
- CHECKED_WRITE_BUFF(CHUNK_ZRAM, Pico.zram);\r
- CHECKED_WRITE_BUFF(CHUNK_CRAM, Pico.cram);\r
+ CHECKED_WRITE_BUFF(CHUNK_VRAM, PicoMem.vram);\r
+ CHECKED_WRITE_BUFF(CHUNK_ZRAM, PicoMem.zram);\r
+ CHECKED_WRITE_BUFF(CHUNK_CRAM, PicoMem.cram);\r
CHECKED_WRITE_BUFF(CHUNK_MISC, Pico.m);\r
CHECKED_WRITE_BUFF(CHUNK_VIDEO, Pico.video);\r
\r
CHECKED_READ_BUFF(buff_z80);\r
break;\r
\r
- case CHUNK_RAM: CHECKED_READ_BUFF(Pico.ram); break;\r
- case CHUNK_VRAM: CHECKED_READ_BUFF(Pico.vram); break;\r
- case CHUNK_ZRAM: CHECKED_READ_BUFF(Pico.zram); break;\r
- case CHUNK_CRAM: CHECKED_READ_BUFF(Pico.cram); break;\r
- case CHUNK_VSRAM: CHECKED_READ_BUFF(Pico.vsram); break;\r
+ case CHUNK_RAM: CHECKED_READ_BUFF(PicoMem.ram); break;\r
+ case CHUNK_VRAM: CHECKED_READ_BUFF(PicoMem.vram); break;\r
+ case CHUNK_ZRAM: CHECKED_READ_BUFF(PicoMem.zram); break;\r
+ case CHUNK_CRAM: CHECKED_READ_BUFF(PicoMem.cram); break;\r
+ case CHUNK_VSRAM: CHECKED_READ_BUFF(PicoMem.vsram); break;\r
case CHUNK_MISC: CHECKED_READ_BUFF(Pico.m); break;\r
case CHUNK_VIDEO: CHECKED_READ_BUFF(Pico.video); break;\r
- case CHUNK_IOPORTS: CHECKED_READ_BUFF(Pico.ioports); break;\r
+ case CHUNK_IOPORTS: CHECKED_READ_BUFF(PicoMem.ioports); break;\r
case CHUNK_PSG: CHECKED_READ2(28*4, sn76496_regs); break;\r
case CHUNK_FM:\r
ym2612_regs = YM2612GetRegs();\r
z80_unpack(buff_z80);\r
\r
// due to dep from 68k cycles..\r
- SekCycleAim = SekCycleCnt;\r
+ Pico.t.m68c_aim = Pico.t.m68c_cnt;\r
if (PicoAHW & PAHW_32X)\r
Pico32xStateLoaded(0);\r
if (PicoAHW & PAHW_MCD)\r
\r
switch (buff[0])\r
{\r
- case CHUNK_VRAM: CHECKED_READ_BUFF(Pico.vram); found++; break;\r
- case CHUNK_CRAM: CHECKED_READ_BUFF(Pico.cram); found++; break;\r
- case CHUNK_VSRAM: CHECKED_READ_BUFF(Pico.vsram); found++; break;\r
+ case CHUNK_VRAM: CHECKED_READ_BUFF(PicoMem.vram); found++; break;\r
+ case CHUNK_CRAM: CHECKED_READ_BUFF(PicoMem.cram); found++; break;\r
+ case CHUNK_VSRAM: CHECKED_READ_BUFF(PicoMem.vsram); found++; break;\r
case CHUNK_VIDEO: CHECKED_READ_BUFF(Pico.video); found++; break;\r
\r
#ifndef NO_32X\r
if (ret != 0) {\r
// assume legacy\r
areaSeek(afile, 0x10020, SEEK_SET); // skip header and RAM\r
- areaRead(Pico.vram, 1, sizeof(Pico.vram), afile);\r
+ areaRead(PicoMem.vram, 1, sizeof(PicoMem.vram), afile);\r
areaSeek(afile, 0x2000, SEEK_CUR);\r
- areaRead(Pico.cram, 1, sizeof(Pico.cram), afile);\r
- areaRead(Pico.vsram, 1, sizeof(Pico.vsram), afile);\r
+ areaRead(PicoMem.cram, 1, sizeof(PicoMem.cram), afile);\r
+ areaRead(PicoMem.vsram, 1, sizeof(PicoMem.vsram), afile);\r
areaSeek(afile, 0x221a0, SEEK_SET);\r
areaRead(&Pico.video, 1, sizeof(Pico.video), afile);\r
}\r
if (t == NULL)\r
return NULL;\r
\r
- memcpy(t->vram, Pico.vram, sizeof(Pico.vram));\r
- memcpy(t->cram, Pico.cram, sizeof(Pico.cram));\r
- memcpy(t->vsram, Pico.vsram, sizeof(Pico.vsram));\r
+ memcpy(t->vram, PicoMem.vram, sizeof(PicoMem.vram));\r
+ memcpy(t->cram, PicoMem.cram, sizeof(PicoMem.cram));\r
+ memcpy(t->vsram, PicoMem.vsram, sizeof(PicoMem.vsram));\r
memcpy(&t->video, &Pico.video, sizeof(Pico.video));\r
\r
#ifndef NO_32X\r
if (t == NULL)\r
return;\r
\r
- memcpy(Pico.vram, t->vram, sizeof(Pico.vram));\r
- memcpy(Pico.cram, t->cram, sizeof(Pico.cram));\r
- memcpy(Pico.vsram, t->vsram, sizeof(Pico.vsram));\r
+ memcpy(PicoMem.vram, t->vram, sizeof(PicoMem.vram));\r
+ memcpy(PicoMem.cram, t->cram, sizeof(PicoMem.cram));\r
+ memcpy(PicoMem.vsram, t->vsram, sizeof(PicoMem.vsram));\r
memcpy(&Pico.video, &t->video, sizeof(Pico.video));\r
Pico.m.dirtyPal = 1;\r
\r
#define NEED_DMA_SOURCE\r
#include "memory.h"\r
\r
-int line_base_cycles;\r
extern const unsigned char hcounts_32[];\r
extern const unsigned char hcounts_40[];\r
\r
{\r
// nasty\r
a = ((a & 2) >> 1) | ((a & 0x400) >> 9) | (a & 0x3FC) | ((a & 0x1F800) >> 1);\r
- ((u8 *)Pico.vram)[a] = d;\r
+ ((u8 *)PicoMem.vram)[a] = d;\r
}\r
\r
static void VideoWrite(u16 d)\r
{\r
- unsigned int a=Pico.video.addr;\r
+ unsigned int a = Pico.video.addr;\r
\r
switch (Pico.video.type)\r
{\r
- case 1: if(a&1) d=(u16)((d<<8)|(d>>8)); // If address is odd, bytes are swapped (which game needs this?)\r
- Pico.vram [(a>>1)&0x7fff]=d;\r
+ case 1: if (a & 1)\r
+ d = (u16)((d << 8) | (d >> 8));\r
+ PicoMem.vram [(a >> 1) & 0x7fff] = d;\r
if (a - ((unsigned)(Pico.video.reg[5]&0x7f) << 9) < 0x400)\r
Pico.est.rendstatus |= PDRAW_DIRTY_SPRITES;\r
break;\r
case 3: Pico.m.dirtyPal = 1;\r
- Pico.cram [(a>>1)&0x003f]=d; break; // wraps (Desert Strike)\r
- case 5: Pico.vsram[(a>>1)&0x003f]=d; break;\r
+ PicoMem.cram [(a >> 1) & 0x3f] = d; break;\r
+ case 5: PicoMem.vsram[(a >> 1) & 0x3f] = d; break;\r
case 0x81:\r
a |= Pico.video.addr_u << 16;\r
VideoWrite128(a, d);\r
\r
switch (Pico.video.type)\r
{\r
- case 0: d=Pico.vram [a&0x7fff]; break;\r
- case 8: d=Pico.cram [a&0x003f]; break;\r
- case 4: d=Pico.vsram[a&0x003f]; break;\r
+ case 0: d=PicoMem.vram [a & 0x7fff]; break;\r
+ case 8: d=PicoMem.cram [a & 0x003f]; break;\r
+ case 4: d=PicoMem.vsram[a & 0x003f]; break;\r
default:elprintf(EL_ANOMALY, "VDP read with bad type %i", Pico.video.type); break;\r
}\r
\r
SekCyclesBurnRun(CheckDMA());\r
\r
if ((source & 0xe00000) == 0xe00000) { // Ram\r
- base = (u16 *)Pico.ram;\r
+ base = (u16 *)PicoMem.ram;\r
mask = 0xffff;\r
}\r
else if (PicoAHW & PAHW_MCD)\r
switch (Pico.video.type)\r
{\r
case 1: // vram\r
- r = Pico.vram;\r
+ r = PicoMem.vram;\r
if (inc == 2 && !(a & 1) && a + len * 2 < 0x10000\r
&& !(((source + len - 1) ^ source) & ~mask))\r
{\r
\r
case 3: // cram\r
Pico.m.dirtyPal = 1;\r
- r = Pico.cram;\r
+ r = PicoMem.cram;\r
for (; len; len--)\r
{\r
r[(a / 2) & 0x3f] = base[source++ & mask];\r
break;\r
\r
case 5: // vsram\r
- r = Pico.vsram;\r
+ r = PicoMem.vsram;\r
for (; len; len--)\r
{\r
r[(a / 2) & 0x3f] = base[source++ & mask];\r
\r
static void DmaCopy(int len)\r
{\r
- u16 a=Pico.video.addr;\r
- unsigned char *vr = (unsigned char *) Pico.vram;\r
- unsigned char inc=Pico.video.reg[0xf];\r
+ u16 a = Pico.video.addr;\r
+ u8 *vr = (u8 *)PicoMem.vram;\r
+ u8 inc = Pico.video.reg[0xf];\r
int source;\r
elprintf(EL_VDPDMA, "DmaCopy len %i [%u]", len, SekCyclesDone());\r
\r
\r
static NOINLINE void DmaFill(int data)\r
{\r
- unsigned short a=Pico.video.addr;\r
- unsigned char *vr=(unsigned char *) Pico.vram;\r
- unsigned char high = (unsigned char) (data >> 8);\r
- unsigned char inc=Pico.video.reg[0xf];\r
+ u16 a = Pico.video.addr;\r
+ u8 *vr = (u8 *)PicoMem.vram;\r
+ u8 high = (u8)(data >> 8);\r
+ u8 inc = Pico.video.reg[0xf];\r
int source;\r
int len, l;\r
\r
// try avoiding the sync..\r
if (Pico.m.scanline < 224 && (pvid->reg[1]&0x40) &&\r
!(!pvid->pending &&\r
- ((pvid->command & 0xc00000f0) == 0x40000010 && Pico.vsram[pvid->addr>>1] == d))\r
+ ((pvid->command & 0xc00000f0) == 0x40000010 && PicoMem.vsram[pvid->addr>>1] == d))\r
)\r
DrawSync(0);\r
\r
return;\r
}\r
\r
- if (num == 1 && !(d&0x40) && SekCyclesDone() - line_base_cycles <= 488-390)\r
+ if (num == 1 && !(d&0x40) && SekCyclesDone() - Pico.t.m68c_line_start <= 488-390)\r
blank_on = 1;\r
DrawSync(blank_on);\r
pvid->reg[num]=(unsigned char)d;\r
unsigned int d;\r
d=pv->status;\r
//if (PicoOpt&POPT_ALT_RENDERER) d|=0x0020; // sprite collision (Shadow of the Beast)\r
- if (SekCyclesDone() - line_base_cycles >= 488-88)\r
+ if (SekCyclesDone() - Pico.t.m68c_line_start >= 488-88)\r
d|=0x0004; // H-Blank (Sonic3 vs)\r
\r
d |= ((pv->reg[1]&0x40)^0x40) >> 3; // set V-Blank if display is disabled\r
{\r
unsigned int d;\r
\r
- d = (SekCyclesDone() - line_base_cycles) & 0x1ff; // FIXME\r
+ d = (SekCyclesDone() - Pico.t.m68c_line_start) & 0x1ff; // FIXME\r
if (Pico.video.reg[12]&1)\r
d = hcounts_40[d];\r
else d = hcounts_32[d];\r
//if (PicoOpt&POPT_ALT_RENDERER) d|=0x0020; // sprite collision (Shadow of the Beast)\r
d |= ((Pico.video.reg[1]&0x40)^0x40) >> 3; // set V-Blank if display is disabled\r
d |= (Pico.video.pending_ints&0x20)<<2; // V-int pending?\r
- if (SekCyclesDone() - line_base_cycles >= 488-88) d |= 4; // H-Blank\r
+ if (SekCyclesDone() - Pico.t.m68c_line_start >= 488-88) d |= 4; // H-Blank\r
Pico.video.pending = 0;\r
elprintf(EL_SR, "SR read (l): %02x @ %06x", d, SekPc);\r
return d;\r
// FIXME: broken\r
unsigned char PicoVideoRead8HV_L(void)\r
{\r
- u32 d = (SekCyclesDone() - line_base_cycles) & 0x1ff; // FIXME\r
+ u32 d = (SekCyclesDone() - Pico.t.m68c_line_start) & 0x1ff; // FIXME\r
if (Pico.video.reg[12]&1)\r
d = hcounts_40[d];\r
else d = hcounts_32[d];\r
endif
ifeq "$(asm_memory)" "1"
DEFINES += _ASM_MEMORY_C
-SRCS_COMMON += $(R)pico/memory_arm.s
+SRCS_COMMON += $(R)pico/memory_arm.S
endif
ifeq "$(asm_ym2612)" "1"
DEFINES += _ASM_YM2612_C
endif
ifeq "$(asm_cdmemory)" "1"
DEFINES += _ASM_CD_MEMORY_C
-SRCS_COMMON += $(R)pico/cd/memory_arm.s
+SRCS_COMMON += $(R)pico/cd/memory_arm.S
endif
ifeq "$(asm_32xdraw)" "1"
DEFINES += _ASM_32X_DRAW
{\r
if (PicoOpt & POPT_EN_MCD_RAMCART) {\r
sram_size = 0x12000;\r
- sram_data = SRam.data;\r
+ sram_data = Pico.sv.data;\r
if (sram_data)\r
memcpy32((int *)sram_data, (int *)Pico_mcd->bram, 0x2000/4);\r
} else {\r
truncate = 0; // the .brm may contain RAM cart data after normal brm\r
}\r
} else {\r
- sram_size = SRam.size;\r
- sram_data = SRam.data;\r
+ sram_size = Pico.sv.size;\r
+ sram_data = Pico.sv.data;\r
}\r
if (sram_data == NULL)\r
- return 0; // SRam forcefully disabled for this game\r
+ return 0; // cart saves forcefully disabled for this game\r
\r
if (load)\r
{\r
void emu_finish(void)\r
{\r
// save SRAM\r
- if ((currentConfig.EmuOpt & EOPT_EN_SRAM) && SRam.changed) {\r
+ if ((currentConfig.EmuOpt & EOPT_EN_SRAM) && Pico.sv.changed) {\r
emu_save_load_game(0, 1);\r
- SRam.changed = 0;\r
+ Pico.sv.changed = 0;\r
}\r
\r
if (!(currentConfig.EmuOpt & EOPT_NO_AUTOSVCFG)) {\r
emu_set_fastforward(0);\r
\r
// save SRAM\r
- if ((currentConfig.EmuOpt & EOPT_EN_SRAM) && SRam.changed) {\r
+ if ((currentConfig.EmuOpt & EOPT_EN_SRAM) && Pico.sv.changed) {\r
plat_status_msg_busy_first("Writing SRAM/BRAM...");\r
emu_save_load_game(0, 1);\r
- SRam.changed = 0;\r
+ Pico.sv.changed = 0;\r
}\r
\r
pemu_loop_end();\r
#include "../pico/pico_int.h"
-#define DUMP(f, field) \
+#define DUMP(f, prefix, type, field) \
fprintf(f, "#define %-20s 0x%02x\n", \
- "OFS_" #field, \
- (int)offsetof(struct PicoEState, field))
+ prefix #field, (int)offsetof(type, field))
+
+#define DUMP_P(f, field) \
+ fprintf(f, "#define %-20s 0x%04x\n", \
+ "OFS_Pico_" #field, (char *)&p.field - (char *)&p)
+
+#define DUMP_PS(f, s1, field) \
+ fprintf(f, "#define %-20s 0x%04x\n", \
+ "OFS_Pico_" #s1 "_" #field, (char *)&p.s1.field - (char *)&p)
+
+#define DUMP_EST(f, field) \
+ DUMP(f, "OFS_EST_", struct PicoEState, field)
+
+extern struct Pico p;
int main(int argc, char *argv[])
{
}
fprintf(f, "/* autogenerated by %s, do not edit */\n", argv[0]);
- DUMP(f, DrawScanline);
- DUMP(f, rendstatus);
- DUMP(f, DrawLineDest);
- DUMP(f, HighCol);
- DUMP(f, HighPreSpr);
- DUMP(f, Pico_video);
- DUMP(f, Pico_vram);
- DUMP(f, PicoOpt);
- DUMP(f, Draw2FB);
- DUMP(f, HighPal);
+ DUMP_PS(f, video, reg);
+ DUMP_PS(f, m, rotate);
+ DUMP_PS(f, m, z80Run);
+ DUMP_PS(f, m, dirtyPal);
+ DUMP_PS(f, m, hardware);
+ DUMP_PS(f, m, z80_reset);
+ DUMP_PS(f, m, sram_reg);
+ DUMP_P (f, sv);
+ DUMP_PS(f, sv, data);
+ DUMP_PS(f, sv, start);
+ DUMP_PS(f, sv, end);
+ DUMP_PS(f, sv, flags);
+ DUMP_P (f, rom);
+ DUMP_P (f, romsize);
+ DUMP_EST(f, DrawScanline);
+ DUMP_EST(f, rendstatus);
+ DUMP_EST(f, DrawLineDest);
+ DUMP_EST(f, HighCol);
+ DUMP_EST(f, HighPreSpr);
+ DUMP_EST(f, Pico);
+ DUMP_EST(f, PicoMem_vram);
+ DUMP_EST(f, PicoMem_cram);
+ DUMP_EST(f, PicoOpt);
+ DUMP_EST(f, Draw2FB);
+ DUMP_EST(f, HighPal);
fclose(f);
return 0;
notaz.gp2x.de / picodrive.git / commitdiff