pico/carthw/svp/compiler.o : cpu/drc/emit_$(ARCH).c
cpu/sh2/compiler.o : cpu/drc/emit_$(ARCH).c
cpu/sh2/mame/sh2pico.o : cpu/sh2/mame/sh2.c
-pico/pico.o pico/cd/pico.o : pico/pico_cmn.c pico/pico_int.h
+pico/pico.o pico/cd/pico.o pico/32x/32x.o : pico/pico_cmn.c pico/pico_int.h
pico/memory.o pico/cd/memory.o : pico/pico_int.h pico/memory.h
cpu/fame/famec.o: cpu/fame/famec.c cpu/fame/famec_opcodes.h
// sh2->icount -= 13;
}
-void sh2_irl_irq(SH2 *sh2, int level, int nested_call)
+int sh2_irl_irq(SH2 *sh2, int level, int nested_call)
{
+ int taken;
+
sh2->pending_irl = level;
if (level < sh2->pending_int_irq)
level = sh2->pending_int_irq;
sh2->pending_level = level;
- if (!nested_call) {
- // not in memhandler, so handle this now (recompiler friendly)
- // do this to avoid missing irqs that other SH2 might clear
- if (level > ((sh2->sr >> 4) & 0x0f)) {
+ taken = (level > ((sh2->sr >> 4) & 0x0f));
+ if (taken) {
+ if (!nested_call) {
+ // not in memhandler, so handle this now (recompiler friendly)
+ // do this to avoid missing irqs that other SH2 might clear
int vector = sh2->irq_callback(sh2, level);
sh2_do_irq(sh2, level, vector);
}
+ else
+ sh2->test_irq = 1;
}
- else
- sh2->test_irq = 1;
+ return taken;
}
void sh2_internal_irq(SH2 *sh2, int level, int vector)
int sh2_init(SH2 *sh2, int is_slave);\r
void sh2_finish(SH2 *sh2);\r
void sh2_reset(SH2 *sh2);\r
-void sh2_irl_irq(SH2 *sh2, int level, int nested_call);\r
+int sh2_irl_irq(SH2 *sh2, int level, int nested_call);\r
void sh2_internal_irq(SH2 *sh2, int level, int vector);\r
void sh2_do_irq(SH2 *sh2, int level, int vector);\r
void sh2_pack(const SH2 *sh2, unsigned char *buff);\r
}
}
+// if !nested_call, must sync CPUs before calling this
void p32x_update_irls(int nested_call)
{
int irqs, mlvl = 0, slvl = 0;
+ int mrun, srun;
// msh2
irqs = (Pico32x.sh2irqs | Pico32x.sh2irqi[0]) & ((Pico32x.sh2irq_mask[0] << 3) | P32XI_VRES);
slvl++;
slvl *= 2;
- elprintf(EL_32X, "update_irls: m %d, s %d", mlvl, slvl);
- sh2_irl_irq(&msh2, mlvl, nested_call);
- sh2_irl_irq(&ssh2, slvl, nested_call);
- mlvl = mlvl ? 1 : 0;
- slvl = slvl ? 1 : 0;
- p32x_poll_event(mlvl | (slvl << 1), 0);
+ mrun = sh2_irl_irq(&msh2, mlvl, nested_call);
+ srun = sh2_irl_irq(&ssh2, slvl, nested_call);
+ p32x_poll_event(mrun | (srun << 1), 0);
+ elprintf(EL_32X, "update_irls: m %d/%d, s %d/%d", mlvl, mrun, slvl, srun);
}
void Pico32xStartup(void)
ssh2.irq_callback = sh2_irq_cb;
PicoMemSetup32x();
+ p32x_timers_recalc();
if (!Pico.m.pal)
Pico32x.vdp_regs[0] |= P32XV_nPAL;
Pico32x.sh2irqs |= P32XI_VRES;
p32x_update_irls(0);
p32x_poll_event(3, 0);
+ p32x_timers_recalc();
}
}
p32x_poll_event(3, 1);
}
+/* events */
+static void pwm_irq_event(unsigned int now)
+{
+ Pico32x.emu_flags &= ~P32XF_PWM_PEND;
+ p32x_pwm_schedule(now);
+
+ Pico32x.sh2irqs |= P32XI_PWM;
+ p32x_update_irls(0);
+}
+
+static void fillend_event(unsigned int now)
+{
+ Pico32x.vdp_regs[0x0a/2] &= ~P32XV_nFEN;
+ p32x_poll_event(3, 1);
+}
+
+typedef void (event_cb)(unsigned int now);
+
+static unsigned int event_times[P32X_EVENT_COUNT];
+static unsigned int event_time_next;
+static event_cb *event_cbs[] = {
+ [P32X_EVENT_PWM] = pwm_irq_event,
+ [P32X_EVENT_FILLEND] = fillend_event,
+};
+
+// schedule event at some time (in m68k clocks)
+void p32x_event_schedule(enum p32x_event event, unsigned int now, int after)
+{
+ unsigned int when = (now + after) | 1;
+
+ elprintf(EL_32X, "new event #%u %u->%u", event, now, when);
+ event_times[event] = when;
+
+ if (event_time_next == 0 || (int)(event_time_next - now) > after)
+ event_time_next = when;
+}
+
+static void run_events(unsigned int until)
+{
+ int oldest, oldest_diff, time;
+ int i, diff;
+
+ while (1) {
+ oldest = -1, oldest_diff = 0x7fffffff;
+
+ for (i = 0; i < P32X_EVENT_COUNT; i++) {
+ if (event_times[i]) {
+ diff = event_times[i] - until;
+ if (diff < oldest_diff) {
+ oldest_diff = diff;
+ oldest = i;
+ }
+ }
+ }
+
+ if (oldest_diff <= 0) {
+ time = event_times[oldest];
+ event_times[oldest] = 0;
+ elprintf(EL_32X, "run event #%d %u", oldest, time);
+ event_cbs[oldest](time);
+ }
+ else if (oldest_diff < 0x7fffffff) {
+ event_time_next = event_times[oldest];
+ break;
+ }
+ else {
+ event_time_next = 0;
+ break;
+ }
+ }
+
+ if (oldest != -1)
+ elprintf(EL_32X, "next event #%d at %u", oldest, event_time_next);
+}
+
+// compare cycles, handling overflows
+// check if a > b
+#define CYCLES_GT(a, b) \
+ ((int)((a) - (b)) > 0)
+// check if a >= b
+#define CYCLES_GE(a, b) \
+ ((int)((a) - (b)) >= 0)
+
#define sync_sh2s_normal p32x_sync_sh2s
//#define sync_sh2s_lockstep p32x_sync_sh2s
+/* most timing is in 68k clock */
void sync_sh2s_normal(unsigned int m68k_target)
{
- unsigned int target = m68k_target;
- int msh2_cycles, ssh2_cycles;
- int done;
+ unsigned int now, target, timer_cycles;
+ int cycles, done;
- elprintf(EL_32X, "sh2 sync to %u (%u)", m68k_target, SekCycleCnt);
+ elprintf(EL_32X, "sh2 sync to %u", m68k_target);
if (!(Pico32x.regs[0] & P32XS_nRES))
return; // rare
+ now = msh2.m68krcycles_done;
+ if (CYCLES_GT(now, ssh2.m68krcycles_done))
+ now = ssh2.m68krcycles_done;
+ timer_cycles = now;
+
+ while (CYCLES_GT(m68k_target, now))
{
- msh2_cycles = C_M68K_TO_SH2(msh2, target - msh2.m68krcycles_done);
- ssh2_cycles = C_M68K_TO_SH2(ssh2, target - ssh2.m68krcycles_done);
+ if (event_time_next && CYCLES_GE(now, event_time_next))
+ run_events(now);
- while (msh2_cycles > 0 || ssh2_cycles > 0) {
- elprintf(EL_32X, "sh2 exec %u,%u->%u",
- msh2.m68krcycles_done, ssh2.m68krcycles_done, target);
+ target = m68k_target;
+ if (event_time_next && CYCLES_GT(target, event_time_next))
+ target = event_time_next;
+
+ while (CYCLES_GT(target, now))
+ {
+ elprintf(EL_32X, "sh2 exec to %u %d,%d/%d, flags %x", target,
+ target - msh2.m68krcycles_done, target - ssh2.m68krcycles_done,
+ m68k_target - now, Pico32x.emu_flags);
if (Pico32x.emu_flags & (P32XF_SSH2POLL|P32XF_SSH2VPOLL)) {
ssh2.m68krcycles_done = target;
- ssh2_cycles = 0;
}
- else if (ssh2_cycles > 0) {
- done = sh2_execute(&ssh2, ssh2_cycles);
- ssh2.m68krcycles_done += C_SH2_TO_M68K(ssh2, done);
-
- ssh2_cycles = C_M68K_TO_SH2(ssh2, target - ssh2.m68krcycles_done);
+ else {
+ cycles = target - ssh2.m68krcycles_done;
+ if (cycles > 0) {
+ done = sh2_execute(&ssh2, C_M68K_TO_SH2(ssh2, cycles));
+ ssh2.m68krcycles_done += C_SH2_TO_M68K(ssh2, done);
+
+ if (event_time_next && CYCLES_GT(target, event_time_next))
+ target = event_time_next;
+ }
}
if (Pico32x.emu_flags & (P32XF_MSH2POLL|P32XF_MSH2VPOLL)) {
msh2.m68krcycles_done = target;
- msh2_cycles = 0;
}
- else if (msh2_cycles > 0) {
- done = sh2_execute(&msh2, msh2_cycles);
- msh2.m68krcycles_done += C_SH2_TO_M68K(msh2, done);
-
- msh2_cycles = C_M68K_TO_SH2(msh2, target - msh2.m68krcycles_done);
+ else {
+ cycles = target - msh2.m68krcycles_done;
+ if (cycles > 0) {
+ done = sh2_execute(&msh2, C_M68K_TO_SH2(msh2, cycles));
+ msh2.m68krcycles_done += C_SH2_TO_M68K(msh2, done);
+
+ if (event_time_next && CYCLES_GT(target, event_time_next))
+ target = event_time_next;
+ }
}
+
+ now = msh2.m68krcycles_done;
+ if (CYCLES_GT(now, ssh2.m68krcycles_done))
+ now = ssh2.m68krcycles_done;
}
+
+ p32x_timers_do(now - timer_cycles);
+ timer_cycles = now;
}
}
#define CPUS_RUN(m68k_cycles,s68k_cycles) do { \
SekRunM68k(m68k_cycles); \
- if (SekIsStoppedM68k()) \
+ if (Pico32x.emu_flags & P32XF_68KPOLL) \
p32x_sync_sh2s(SekCycleCntT + SekCycleCnt); \
} while (0)
void PicoFrame32x(void)
{
- pwm_frame_smp_cnt = 0;
-
Pico32x.vdp_regs[0x0a/2] &= ~P32XV_VBLK; // get out of vblank
if ((Pico32x.vdp_regs[0] & P32XV_Mx) != 0) // no forced blanking
Pico32x.vdp_regs[0x0a/2] &= ~P32XV_PEN; // no palette access
{
a &= 0x3e;
- if (a == 2) // INTM, INTS
- return ((Pico32x.sh2irqi[0] & P32XI_CMD) >> 4) | ((Pico32x.sh2irqi[1] & P32XI_CMD) >> 3);
#if 0
if ((a & 0x30) == 0x20)
return sh2_comm_faker(a);
#else
if ((a & 0x30) == 0x20) {
- // evil X-Men proto polls in a dbra loop and expects it to expire..
static u32 dr2 = 0;
+ unsigned int cycles = SekCyclesDoneT();
+ int comreg = 1 << (a & 0x0f) / 2;
+
+ // evil X-Men proto polls in a dbra loop and expects it to expire..
if (SekDar(2) != dr2)
m68k_poll.cnt = 0;
dr2 = SekDar(2);
- if (p32x_poll_detect(&m68k_poll, a, SekCyclesDoneT(), 0)) {
+ if (cycles - msh2.m68krcycles_done > 500)
+ p32x_sync_sh2s(cycles);
+ if (Pico32x.comm_dirty_sh2 & comreg)
+ Pico32x.comm_dirty_sh2 &= ~comreg;
+ else if (p32x_poll_detect(&m68k_poll, a, cycles, 0)) {
SekSetStop(1);
SekEndTimeslice(16);
}
dr2 = SekDar(2);
+ goto out;
}
#endif
+ if (a == 2) { // INTM, INTS
+ unsigned int cycles = SekCyclesDoneT();
+ if (cycles - msh2.m68krcycles_done > 64)
+ p32x_sync_sh2s(cycles);
+ return ((Pico32x.sh2irqi[0] & P32XI_CMD) >> 4) | ((Pico32x.sh2irqi[1] & P32XI_CMD) >> 3);
+ }
+
if ((a & 0x30) == 0x30)
return p32x_pwm_read16(a);
+out:
return Pico32x.regs[a / 2];
}
return;
case 3: // irq ctl
if ((d & 1) && !(Pico32x.sh2irqi[0] & P32XI_CMD)) {
+ p32x_sync_sh2s(SekCyclesDoneT());
Pico32x.sh2irqi[0] |= P32XI_CMD;
p32x_update_irls(0);
- SekEndRun(16);
}
if ((d & 2) && !(Pico32x.sh2irqi[1] & P32XI_CMD)) {
+ p32x_sync_sh2s(SekCyclesDoneT());
Pico32x.sh2irqi[1] |= P32XI_CMD;
p32x_update_irls(0);
- SekEndRun(16);
}
return;
case 5: // bank
if ((a & 0x30) == 0x20) {
u8 *r8 = (u8 *)r;
+ int cycles = SekCyclesDoneT();
+ int comreg;
+
+ if (r8[a ^ 1] == d)
+ return;
+
+ comreg = 1 << (a & 0x0f) / 2;
+ if (Pico32x.comm_dirty_68k & comreg)
+ p32x_sync_sh2s(cycles);
+
r8[a ^ 1] = d;
p32x_poll_undetect(&sh2_poll[0], 0);
p32x_poll_undetect(&sh2_poll[1], 0);
- // if some SH2 is busy waiting, it needs to see the result ASAP
- if (SekCyclesLeftNoMCD > 32)
- SekEndRun(32);
+ Pico32x.comm_dirty_68k |= comreg;
+
+ if (cycles - (int)msh2.m68krcycles_done > 120)
+ p32x_sync_sh2s(cycles);
return;
}
}
return;
}
// comm port
- else if ((a & 0x30) == 0x20 && r[a / 2] != d) {
+ else if ((a & 0x30) == 0x20) {
+ int cycles = SekCyclesDoneT();
+ int comreg;
+
+ if (r[a / 2] == d)
+ return;
+
+ comreg = 1 << (a & 0x0f) / 2;
+ if (Pico32x.comm_dirty_68k & comreg)
+ p32x_sync_sh2s(cycles);
+
r[a / 2] = d;
p32x_poll_undetect(&sh2_poll[0], 0);
p32x_poll_undetect(&sh2_poll[1], 0);
- // same as for w8
- if (SekCyclesLeftNoMCD > 32)
- SekEndRun(32);
+ Pico32x.comm_dirty_68k |= comreg;
+
+ if (cycles - (int)msh2.m68krcycles_done > 120)
+ p32x_sync_sh2s(cycles);
return;
}
// PWM
}
}
-static void p32x_vdp_write16(u32 a, u32 d)
+static void p32x_vdp_write16(u32 a, u32 d, u32 cycles)
{
a &= 0x0e;
if (a == 6) { // fill start
if (a == 8) { // fill data
u16 *dram = Pico32xMem->dram[(Pico32x.vdp_regs[0x0a/2] & P32XV_FS) ^ 1];
int len = Pico32x.vdp_regs[4 / 2] + 1;
+ int len1 = len;
a = Pico32x.vdp_regs[6 / 2];
- while (len--) {
+ while (len1--) {
dram[a] = d;
a = (a & 0xff00) | ((a + 1) & 0xff);
}
- Pico32x.vdp_regs[6 / 2] = a;
- Pico32x.vdp_regs[8 / 2] = d;
+ Pico32x.vdp_regs[0x06 / 2] = a;
+ Pico32x.vdp_regs[0x08 / 2] = d;
+ if (cycles > 0) {
+ Pico32x.vdp_regs[0x0a / 2] |= P32XV_nFEN;
+ p32x_event_schedule(P32X_EVENT_FILLEND, cycles, len);
+ }
return;
}
return r[a / 2];
// comm port
if ((a & 0x30) == 0x20) {
- if (p32x_poll_detect(&sh2_poll[cpuid], a, ash2_cycles_done(), 0))
+ int comreg = 1 << (a & 0x0f) / 2;
+ if (Pico32x.comm_dirty_68k & comreg)
+ Pico32x.comm_dirty_68k &= ~comreg;
+ else if (p32x_poll_detect(&sh2_poll[cpuid], a, ash2_cycles_done(), 0))
ash2_end_run(8);
return r[a / 2];
}
Pico32x.sh2irq_mask[cpuid] = d & 0x8f;
Pico32x.sh2_regs[0] &= ~0x80;
Pico32x.sh2_regs[0] |= d & 0x80;
+ if (d & 1)
+ p32x_pwm_schedule(sh2s[cpuid].m68krcycles_done); // XXX: timing?
p32x_update_irls(1);
return;
case 5: // H count
if ((a & 0x30) == 0x20) {
u8 *r8 = (u8 *)Pico32x.regs;
+ int comreg;
+ if (r8[a ^ 1] == d)
+ return;
+
r8[a ^ 1] = d;
if (p32x_poll_undetect(&m68k_poll, 0))
SekSetStop(0);
p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0);
+ comreg = 1 << (a & 0x0f) / 2;
+ Pico32x.comm_dirty_sh2 |= comreg;
return;
}
}
a &= 0xfe;
// comm
- if ((a & 0x30) == 0x20 && Pico32x.regs[a/2] != d) {
+ if ((a & 0x30) == 0x20) {
+ int comreg;
+ if (Pico32x.regs[a / 2] == d)
+ return;
+
Pico32x.regs[a / 2] = d;
if (p32x_poll_undetect(&m68k_poll, 0))
SekSetStop(0);
p32x_poll_undetect(&sh2_poll[cpuid ^ 1], 0);
+ comreg = 1 << (a & 0x0f) / 2;
+ Pico32x.comm_dirty_sh2 |= comreg;
return;
}
// PWM
case 0x1a: Pico32x.sh2irqi[cpuid] &= ~P32XI_CMD; goto irls;
case 0x1c:
Pico32x.sh2irqs &= ~P32XI_PWM;
- p32x_timers_do(0);
+ if (!(Pico32x.emu_flags & P32XF_PWM_PEND))
+ p32x_pwm_schedule(sh2s[cpuid].m68krcycles_done); // timing?
goto irls;
}
}
if ((a & 0xfff0) == 0x5180) { // a15180
- p32x_vdp_write16(a, d);
+ p32x_vdp_write16(a, d, 0); // FIXME?
return;
}
if ((a & 0x3ff00) == 0x4100) {
sh2_poll[id].cnt = 0; // for poll before VDP accesses
- p32x_vdp_write16(a, d);
+ p32x_vdp_write16(a, d, sh2s[id].m68krcycles_done);
return 0;
}
p32x_poll_event(3, 0);
Pico32x.dirty_pal = 1;
memset(Pico32xMem->pwm, 0, sizeof(Pico32xMem->pwm));
+ p32x_timers_recalc();
#ifdef DRC_SH2
sh2_drc_flush_all();
#endif
*/
#include "../pico_int.h"
-static int pwm_line_samples;
+static int pwm_cycle_counter;
static int pwm_cycles;
static int pwm_mult;
static int pwm_ptr;
-int pwm_frame_smp_cnt;
-static int timer_line_ticks[2];
+static int pwm_smp_cnt;
+static int pwm_smp_expect;
+
+static int timer_cycles[2];
+static int timer_tick_cycles[2];
// timers. This includes PWM timer in 32x and internal SH2 timers
void p32x_timers_recalc(void)
{
int cycles = Pico32x.regs[0x32 / 2];
- int frame_samples;
int tmp, i;
cycles = (cycles - 1) & 0x0fff;
}
pwm_cycles = cycles;
pwm_mult = 0x10000 / cycles;
- if (Pico.m.pal)
- frame_samples = OSC_PAL / 7 * 3 / 50 / cycles;
- else
- frame_samples = OSC_NTSC / 7 * 3 / 60 / cycles;
-
- pwm_line_samples = (frame_samples << 16) / scanlines_total;
// SH2 timer step
for (i = 0; i < 2; i++) {
cycles = 0x20 << tmp;
else
cycles = 2;
- if (Pico.m.pal)
- tmp = OSC_PAL / 7 * 3 / 50 / scanlines_total;
- else
- tmp = OSC_NTSC / 7 * 3 / 60 / scanlines_total;
- timer_line_ticks[i] = (tmp << 16) / cycles;
- elprintf(EL_32X, "timer_line_ticks[%d] = %.3f", i, (double)timer_line_ticks[i] / 0x10000);
+ timer_tick_cycles[i] = cycles;
+ elprintf(EL_32X, "WDT cycles[%d] = %d", i, cycles);
}
}
// PWM irq for every tm samples
-void p32x_timers_do(int line_call)
+void p32x_timers_do(unsigned int cycles)
{
- int tm, cnt, i;
+ int cnt, i;
- if (PicoOpt & POPT_EN_PWM)
- {
- tm = (Pico32x.regs[0x30 / 2] & 0x0f00) >> 8;
- if (tm != 0) {
- if (line_call)
- Pico32x.pwm_irq_sample_cnt += pwm_line_samples;
- if (Pico32x.pwm_irq_sample_cnt >= (tm << 16)) {
- Pico32x.pwm_irq_sample_cnt -= tm << 16;
- Pico32x.sh2irqs |= P32XI_PWM;
- p32x_update_irls(!line_call);
- }
- }
- }
+ cycles *= 3;
- if (!line_call)
- return;
+ pwm_cycle_counter += cycles;
+ while (pwm_cycle_counter > pwm_cycles) {
+ pwm_cycle_counter -= pwm_cycles;
+ pwm_smp_expect++;
+ }
+ // WDT timers
for (i = 0; i < 2; i++) {
void *pregs = Pico32xMem->sh2_peri_regs[i];
if (PREG8(pregs, 0x80) & 0x20) { // TME
+ timer_cycles[i] += cycles;
cnt = PREG8(pregs, 0x81);
- cnt += timer_line_ticks[i];
+ while (timer_cycles[i] >= timer_tick_cycles[i]) {
+ timer_cycles[i] -= timer_tick_cycles[i];
+ cnt++;
+ }
if (cnt >= 0x100) {
int level = PREG8(pregs, 0xe3) >> 4;
int vector = PREG8(pregs, 0xe4) & 0x7f;
- elprintf(EL_32X, "%csh2 WDT irq (%d, %d)", i ? 's' : 'm', level, vector);
+ elprintf(EL_32X, "%csh2 WDT irq (%d, %d)",
+ i ? 's' : 'm', level, vector);
sh2_internal_irq(&sh2s[i], level, vector);
+ cnt &= 0xff;
}
- cnt &= 0xff;
PREG8(pregs, 0x81) = cnt;
}
}
}
+void p32x_pwm_schedule(unsigned int now)
+{
+ int tm;
+
+ if (Pico32x.emu_flags & P32XF_PWM_PEND)
+ return; // already scheduled
+ if (Pico32x.sh2irqs & P32XI_PWM)
+ return; // previous not acked
+ if (!((Pico32x.sh2irq_mask[0] | Pico32x.sh2irq_mask[1]) & 1))
+ return; // masked by everyone
+
+ tm = (Pico32x.regs[0x30 / 2] & 0x0f00) >> 8;
+ tm = ((tm - 1) & 0x0f) + 1;
+ p32x_event_schedule(P32X_EVENT_PWM, now, pwm_cycles * tm / 3);
+ Pico32x.emu_flags |= P32XF_PWM_PEND;
+}
+
unsigned int p32x_pwm_read16(unsigned int a)
{
unsigned int d = 0;
- int predict;
+ int diff;
a &= 0x0e;
switch (a) {
case 4: // L ch
case 6: // R ch
case 8: // MONO
- predict = (pwm_line_samples * Pico.m.scanline) >> 16;
- elprintf(EL_PWM, "pwm: read status: ptr %d/%d, predict %d",
- pwm_frame_smp_cnt, (pwm_line_samples * scanlines_total) >> 16, predict);
- if (pwm_frame_smp_cnt > predict + 3)
+ diff = pwm_smp_cnt - pwm_smp_expect;
+ elprintf(EL_PWM, "pwm: read status: ptr %d/%d %d",
+ pwm_smp_cnt, pwm_smp_expect, diff);
+ if (diff > 3)
d |= P32XP_FULL;
- else if (pwm_frame_smp_cnt == 0 || pwm_frame_smp_cnt < predict - 1)
+ else if (diff < 0)
d |= P32XP_EMPTY;
break;
}
Pico32xMem->pwm[pwm_ptr * 2] = Pico32xMem->pwm[pwm_ptr * 2 + 1] = d;
if (a >= 6) { // R or MONO
- pwm_frame_smp_cnt++;
+ pwm_smp_cnt++;
pwm_ptr = (pwm_ptr + 1) & (PWM_BUFF_LEN - 1);
- elprintf(EL_PWM, "pwm: smp_cnt %d, ptr %d, smp %x", pwm_frame_smp_cnt, pwm_ptr, d);
+ elprintf(EL_PWM, "pwm: smp_cnt %d, ptr %d, smp %x",
+ pwm_smp_cnt, pwm_ptr, d);
}
}
}
pwm_ptr = 0;
}
+// vim:shiftwidth=2:ts=2:expandtab
\r
Pico.m.dirtyPal = 1;\r
rendstatus_old = -1;\r
-\r
- if (PicoAHW & PAHW_32X)\r
- p32x_timers_recalc();\r
}\r
\r
\r
#ifdef PICO_CD
check_cd_dma();
#endif
-#ifdef PICO_32X
- p32x_timers_do(1);
-#endif
// H-Interrupts:
if (--hint < 0) // y <= lines_vis: Comix Zone, Golden Axe
PicoSyncZ80(SekCycleCnt);
if (ym2612.dacen && PsndDacLine <= y)
PsndDoDAC(y);
+#ifdef PICO_32X
+ p32x_sync_sh2s(SekCycleCntT + SekCycleCnt);
+#endif
PsndGetSamples(y);
}
#ifdef PICO_CD
check_cd_dma();
#endif
-#ifdef PICO_32X
- p32x_timers_do(1);
-#endif
// Last H-Int:
if (--hint < 0)
pv->status|=0x08; // go into vblank
pv->pending_ints|=0x20;
-#ifdef PICO_32X
- p32x_start_blank();
-#endif
-
// the following SekRun is there for several reasons:
// there must be a delay after vblank bit is set and irq is asserted (Mazin Saga)
// also delay between F bit (bit 7) is set in SR and IRQ happens (Ex-Mutants)
z80_int();
}
+#ifdef PICO_32X
+ p32x_sync_sh2s(SekCycleCntT + SekCycleCnt);
+ p32x_start_blank();
+#endif
+
// get samples from sound chips
if (y == 224 && PsndOut)
{
#ifdef PICO_CD
check_cd_dma();
#endif
-#ifdef PICO_32X
- p32x_timers_do(1);
-#endif
// Run scanline:
if (Pico.m.dma_xfers) SekCyclesBurn(CheckDMA());
if (PsndOut && ym2612.dacen && PsndDacLine <= lines-1)
PsndDoDAC(lines-1);
+#ifdef PICO_32X
+ p32x_sync_sh2s(SekCycleCntT + SekCycleCnt);
+#endif
timers_cycle();
return 0;
#define ssh2 sh2s[1]\r
\r
#ifndef DRC_SH2\r
-# define ash2_end_run(after) if (sh2->icount > (after)) sh2->icount = after\r
+# define ash2_end_run(after) do { \\r
+ if (sh2->icount > (after)) { \\r
+ sh2->cycles_timeslice -= sh2->icount; \\r
+ sh2->icount = after; \\r
+ } \\r
+} while (0)\r
# define ash2_cycles_done() (sh2->cycles_timeslice - sh2->icount)\r
#else\r
-# define ash2_end_run(after) { \\r
- if ((sh2->sr >> 12) > (after)) \\r
- { sh2->sr &= 0xfff; sh2->sr |= (after) << 12; } \\r
-}\r
+# define ash2_end_run(after) do { \\r
+ int left = sh2->sr >> 12; \\r
+ if (left > (after)) { \\r
+ sh2->cycles_timeslice -= left; \\r
+ sh2->sr &= 0xfff; \\r
+ sh2->sr |= (after) << 12; \\r
+ } \\r
+} while (0)\r
# define ash2_cycles_done() (sh2->cycles_timeslice - (sh2->sr >> 12))\r
#endif\r
\r
#define P32XF_68KVPOLL (1 << 3)\r
#define P32XF_MSH2VPOLL (1 << 4)\r
#define P32XF_SSH2VPOLL (1 << 5)\r
+#define P32XF_PWM_PEND (1 << 6)\r
\r
#define P32XI_VRES (1 << 14/2) // IRL/2\r
#define P32XI_VINT (1 << 12/2)\r
unsigned short dmac_fifo[DMAC_FIFO_LEN];\r
unsigned int dmac_ptr;\r
unsigned int pwm_irq_sample_cnt;\r
- unsigned int reserved[9];\r
+ unsigned char comm_dirty_68k;\r
+ unsigned char comm_dirty_sh2;\r
+ unsigned short pad;\r
+ unsigned int reserved[8];\r
};\r
\r
struct Pico32xMem\r
void p32x_update_irls(int nested_call);\r
void p32x_reset_sh2s(void);\r
\r
+enum p32x_event {\r
+ P32X_EVENT_PWM,\r
+ P32X_EVENT_FILLEND,\r
+ P32X_EVENT_COUNT,\r
+};\r
+void p32x_event_schedule(enum p32x_event event, unsigned int now, int after);\r
+\r
// 32x/memory.c\r
struct Pico32xMem *Pico32xMem;\r
unsigned int PicoRead8_32x(unsigned int a);\r
unsigned int p32x_pwm_read16(unsigned int a);\r
void p32x_pwm_write16(unsigned int a, unsigned int d);\r
void p32x_pwm_update(int *buf32, int length, int stereo);\r
-void p32x_timers_do(int line_call);\r
+void p32x_timers_do(unsigned int cycles);\r
void p32x_timers_recalc(void);\r
-extern int pwm_frame_smp_cnt;\r
+void p32x_pwm_schedule(unsigned int now);\r
#else\r
#define Pico32xInit()\r
#define PicoPower32x()\r
\r
#if EL_LOGMASK\r
#define elprintf(w,f,...) \\r
-{ \\r
+do { \\r
if ((w) & EL_LOGMASK) \\r
lprintf("%05i:%03i: " f "\n",Pico.m.frame_count,Pico.m.scanline,##__VA_ARGS__); \\r
-}\r
+} while (0)\r
#elif defined(_MSC_VER)\r
#define elprintf\r
#else\r
notaz.gp2x.de / picodrive.git / commitdiff