it's wrong, but I need it to be consistent with other cores now
{
SET_PC(execute_exception(M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR));
#ifdef USE_CYCLONE_TIMING_DIV
{
SET_PC(execute_exception(M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR));
#ifdef USE_CYCLONE_TIMING_DIV
{
flag_V = M68K_SR_V;
#ifdef USE_CYCLONE_TIMING_DIV
{
flag_V = M68K_SR_V;
#ifdef USE_CYCLONE_TIMING_DIV
DREGu32((Opcode >> 9) & 7) = res;
}
#ifdef USE_CYCLONE_TIMING_DIV
DREGu32((Opcode >> 9) & 7) = res;
}
#ifdef USE_CYCLONE_TIMING_DIV
{
SET_PC(execute_exception(M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR));
#ifdef USE_CYCLONE_TIMING_DIV
{
SET_PC(execute_exception(M68K_ZERO_DIVIDE_EX, GET_PC, GET_SR));
#ifdef USE_CYCLONE_TIMING_DIV
{
flag_V = M68K_SR_V;
#ifdef USE_CYCLONE_TIMING_DIV
{
flag_V = M68K_SR_V;
#ifdef USE_CYCLONE_TIMING_DIV
DREGu32((Opcode >> 9) & 7) = res;
}
#ifdef USE_CYCLONE_TIMING_DIV
DREGu32((Opcode >> 9) & 7) = res;
}
#ifdef USE_CYCLONE_TIMING_DIV