- use consistent read tables (with write)
- use sh2 ptr instead of id
- place data_array/peri_regs in sh2 struct
#define emith_sh2_wcall(a, tab) { \
emith_lsr(12, a, SH2_WRITE_SHIFT); \
EOP_LDR_REG_LSL(A_COND_AL,12,tab,12,2); \
#define emith_sh2_wcall(a, tab) { \
emith_lsr(12, a, SH2_WRITE_SHIFT); \
EOP_LDR_REG_LSL(A_COND_AL,12,tab,12,2); \
- emith_ctx_read(2, offsetof(SH2, is_slave)); \
+ emith_move_r_r(2, CONTEXT_REG); \
emith_lsr(xBX, a, SH2_WRITE_SHIFT); \
EMIT_OP_MODRM(0x8b, 0, xBX, 4); \
EMIT_SIB(2, xBX, tab); /* mov ebx, [tab + ebx * 4] */ \
emith_lsr(xBX, a, SH2_WRITE_SHIFT); \
EMIT_OP_MODRM(0x8b, 0, xBX, 4); \
EMIT_SIB(2, xBX, tab); /* mov ebx, [tab + ebx * 4] */ \
- emith_ctx_read(arg2_, offsetof(SH2, is_slave)); \
+ emith_move_r_r(arg2_, CONTEXT_REG); \
static u32 REGPARM(2) (*sh2_drc_read32)(u32 a, SH2 *sh2);
static void REGPARM(2) (*sh2_drc_write8)(u32 a, u32 d);
static void REGPARM(2) (*sh2_drc_write16)(u32 a, u32 d);
static u32 REGPARM(2) (*sh2_drc_read32)(u32 a, SH2 *sh2);
static void REGPARM(2) (*sh2_drc_write8)(u32 a, u32 d);
static void REGPARM(2) (*sh2_drc_write16)(u32 a, u32 d);
-static int REGPARM(3) (*sh2_drc_write32)(u32 a, u32 d, SH2 *sh2);
+static void REGPARM(3) (*sh2_drc_write32)(u32 a, u32 d, SH2 *sh2);
// address space stuff
static int dr_ctx_get_mem_ptr(u32 a, u32 *mask)
// address space stuff
static int dr_ctx_get_mem_ptr(u32 a, u32 *mask)
}
else if ((a & 0xfffff000) == 0xc0000000) {
// data array
}
else if ((a & 0xfffff000) == 0xc0000000) {
// data array
+ // FIXME: access sh2->data_array instead
poffs = offsetof(SH2, p_da);
*mask = 0xfff;
}
poffs = offsetof(SH2, p_da);
*mask = 0xfff;
}
{
// fill the convenience pointers
sh2->p_bios = sh2->is_slave ? Pico32xMem->sh2_rom_s : Pico32xMem->sh2_rom_m;
{
// fill the convenience pointers
sh2->p_bios = sh2->is_slave ? Pico32xMem->sh2_rom_s : Pico32xMem->sh2_rom_m;
- sh2->p_da = Pico32xMem->data_array[sh2->is_slave];
+ sh2->p_da = sh2->data_array;
sh2->p_sdram = Pico32xMem->sdram;
sh2->p_rom = Pico.rom;
}
sh2->p_sdram = Pico32xMem->sdram;
sh2->p_rom = Pico.rom;
}
}
else if ((pc & 0xfffff000) == 0xc0000000) {
// data array
}
else if ((pc & 0xfffff000) == 0xc0000000) {
// data array
- ret = Pico32xMem->data_array[is_slave];
+ ret = sh2s[is_slave].data_array;
mask = 0xfff;
}
else if ((pc & 0xc6000000) == 0x06000000) {
mask = 0xfff;
}
else if ((pc & 0xc6000000) == 0x06000000) {
-int sh2_init(SH2 *sh2, int is_slave)
+int sh2_init(SH2 *sh2, int is_slave, SH2 *other_sh2)
{
int ret = 0;
memset(sh2, 0, offsetof(SH2, mult_m68k_to_sh2));
sh2->is_slave = is_slave;
{
int ret = 0;
memset(sh2, 0, offsetof(SH2, mult_m68k_to_sh2));
sh2->is_slave = is_slave;
+ sh2->other_sh2 = other_sh2;
pdb_register_cpu(sh2, PDBCT_SH2, is_slave ? "ssh2" : "msh2");
#ifdef DRC_SH2
ret = sh2_drc_init(sh2);
pdb_register_cpu(sh2, PDBCT_SH2, is_slave ? "ssh2" : "msh2");
#ifdef DRC_SH2
ret = sh2_drc_init(sh2);
-#define SH2MAP_ADDR2OFFS_R(a) \
- ((((a) >> 25) & 3) | (((a) >> 27) & 0x1c))
-
static unsigned int local_read32(SH2 *sh2, u32 a)
{
const sh2_memmap *sh2_map = sh2->read16_map;
u16 *pd;
uptr p;
static unsigned int local_read32(SH2 *sh2, u32 a)
{
const sh2_memmap *sh2_map = sh2->read16_map;
u16 *pd;
uptr p;
- sh2_map += SH2MAP_ADDR2OFFS_R(a);
p = sh2_map->addr;
if (!map_flag_set(p)) {
pd = (u16 *)((p << 1) + ((a & sh2_map->mask) & ~1));
p = sh2_map->addr;
if (!map_flag_set(p)) {
pd = (u16 *)((p << 1) + ((a & sh2_map->mask) & ~1));
if ((a & 0xfffff000) == 0xc0000000) {
// data array
if ((a & 0xfffff000) == 0xc0000000) {
// data array
- pd = (u16 *)Pico32xMem->data_array[sh2->is_slave]
- + (a & 0xfff) / 2;
+ pd = (u16 *)sh2->data_array + (a & 0xfff) / 2;
return (pd[0] << 16) | pd[1];
}
if ((a & 0xdfffffc0) == 0x4000) {
return (pd[0] << 16) | pd[1];
}
if ((a & 0xdfffffc0) == 0x4000) {
\r
unsigned int cycles_timeslice;\r
\r
\r
unsigned int cycles_timeslice;\r
\r
+ struct SH2_ *other_sh2;\r
+\r
// we use 68k reference cycles for easier sync\r
unsigned int m68krcycles_done;\r
unsigned int mult_m68k_to_sh2;\r
unsigned int mult_sh2_to_m68k;\r
// we use 68k reference cycles for easier sync\r
unsigned int m68krcycles_done;\r
unsigned int mult_m68k_to_sh2;\r
unsigned int mult_sh2_to_m68k;\r
+\r
+ unsigned char data_array[0x1000]; // cache (can be used as RAM)\r
+ unsigned int peri_regs[0x200/4]; // periphereal regs\r
} SH2;\r
\r
#define CYCLE_MULT_SHIFT 10\r
} SH2;\r
\r
#define CYCLE_MULT_SHIFT 10\r
#define C_SH2_TO_M68K(xsh2, c) \\r
((int)((c + 3) * (xsh2).mult_sh2_to_m68k) >> CYCLE_MULT_SHIFT)\r
\r
#define C_SH2_TO_M68K(xsh2, c) \\r
((int)((c + 3) * (xsh2).mult_sh2_to_m68k) >> CYCLE_MULT_SHIFT)\r
\r
-int sh2_init(SH2 *sh2, int is_slave);\r
+int sh2_init(SH2 *sh2, int is_slave, SH2 *other_sh2);\r
void sh2_finish(SH2 *sh2);\r
void sh2_reset(SH2 *sh2);\r
int sh2_irl_irq(SH2 *sh2, int level, int nested_call);\r
void sh2_finish(SH2 *sh2);\r
void sh2_reset(SH2 *sh2);\r
int sh2_irl_irq(SH2 *sh2, int level, int nested_call);\r
unsigned int REGPARM(2) p32x_sh2_read8(unsigned int a, SH2 *sh2);\r
unsigned int REGPARM(2) p32x_sh2_read16(unsigned int a, SH2 *sh2);\r
unsigned int REGPARM(2) p32x_sh2_read32(unsigned int a, SH2 *sh2);\r
unsigned int REGPARM(2) p32x_sh2_read8(unsigned int a, SH2 *sh2);\r
unsigned int REGPARM(2) p32x_sh2_read16(unsigned int a, SH2 *sh2);\r
unsigned int REGPARM(2) p32x_sh2_read32(unsigned int a, SH2 *sh2);\r
-int REGPARM(3) p32x_sh2_write8 (unsigned int a, unsigned int d, SH2 *sh2);\r
-int REGPARM(3) p32x_sh2_write16(unsigned int a, unsigned int d, SH2 *sh2);\r
-int REGPARM(3) p32x_sh2_write32(unsigned int a, unsigned int d, SH2 *sh2);\r
+void REGPARM(3) p32x_sh2_write8 (unsigned int a, unsigned int d, SH2 *sh2);\r
+void REGPARM(3) p32x_sh2_write16(unsigned int a, unsigned int d, SH2 *sh2);\r
+void REGPARM(3) p32x_sh2_write32(unsigned int a, unsigned int d, SH2 *sh2);\r
\r
// debug\r
#ifdef DRC_CMP\r
\r
// debug\r
#ifdef DRC_CMP\r
// TODO: OOM handling
PicoAHW |= PAHW_32X;
// TODO: OOM handling
PicoAHW |= PAHW_32X;
+ sh2_init(&msh2, 0, &ssh2);
msh2.irq_callback = sh2_irq_cb;
msh2.irq_callback = sh2_irq_cb;
+ sh2_init(&ssh2, 1, &msh2);
ssh2.irq_callback = sh2_irq_cb;
PicoMemSetup32x();
ssh2.irq_callback = sh2_irq_cb;
PicoMemSetup32x();
if (!Pico.m.pal)
Pico32x.vdp_regs[0] |= P32XV_nPAL;
if (!Pico.m.pal)
Pico32x.vdp_regs[0] |= P32XV_nPAL;
- PREG8(Pico32xMem->sh2_peri_regs[0], 4) =
- PREG8(Pico32xMem->sh2_peri_regs[1], 4) = 0x84; // SCI SSR
+ PREG8(msh2.peri_regs, 4) =
+ PREG8(ssh2.peri_regs, 4) = 0x84; // SCI SSR
// note: recursive call
void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target)
{
// note: recursive call
void p32x_sync_other_sh2(SH2 *sh2, unsigned int m68k_target)
{
- SH2 *osh2 = &sh2s[sh2->is_slave ^ 1];
+ SH2 *osh2 = sh2->other_sh2;
int left_to_event;
int m68k_cycles;
int left_to_event;
int m68k_cycles;
// ------------------------------------------------------------------
// SH2 regs
// ------------------------------------------------------------------
// SH2 regs
-static u32 p32x_sh2reg_read16(u32 a, int cpuid)
+static u32 p32x_sh2reg_read16(u32 a, SH2 *sh2)
{
u16 *r = Pico32x.regs;
a &= 0xfe; // ?
switch (a) {
case 0x00: // adapter/irq ctl
{
u16 *r = Pico32x.regs;
a &= 0xfe; // ?
switch (a) {
case 0x00: // adapter/irq ctl
- return (r[0] & P32XS_FM) | Pico32x.sh2_regs[0] | Pico32x.sh2irq_mask[cpuid];
+ return (r[0] & P32XS_FM) | Pico32x.sh2_regs[0]
+ | Pico32x.sh2irq_mask[sh2->is_slave];
case 0x04: // H count (often as comm too)
case 0x04: // H count (often as comm too)
- sh2_poll_detect(&sh2s[cpuid], a, SH2_STATE_CPOLL);
- sh2s_sync_on_read(&sh2s[cpuid]);
+ sh2_poll_detect(sh2, a, SH2_STATE_CPOLL);
+ sh2s_sync_on_read(sh2);
return Pico32x.sh2_regs[4 / 2];
case 0x10: // DREQ len
return r[a / 2];
return Pico32x.sh2_regs[4 / 2];
case 0x10: // DREQ len
return r[a / 2];
if (Pico32x.comm_dirty_68k & comreg)
Pico32x.comm_dirty_68k &= ~comreg;
else
if (Pico32x.comm_dirty_68k & comreg)
Pico32x.comm_dirty_68k &= ~comreg;
else
- sh2_poll_detect(&sh2s[cpuid], a, SH2_STATE_CPOLL);
- sh2s_sync_on_read(&sh2s[cpuid]);
+ sh2_poll_detect(sh2, a, SH2_STATE_CPOLL);
+ sh2s_sync_on_read(sh2);
return r[a / 2];
}
if ((a & 0x30) == 0x30) {
return r[a / 2];
}
if ((a & 0x30) == 0x30) {
- return p32x_pwm_read16(a, &sh2s[cpuid], sh2_cycles_done_m68k(&sh2s[cpuid]));
+ return p32x_pwm_read16(a, sh2, sh2_cycles_done_m68k(sh2));
-static void p32x_sh2reg_write8(u32 a, u32 d, int cpuid)
+static void p32x_sh2reg_write8(u32 a, u32 d, SH2 *sh2)
- sh2s[cpuid].poll_addr = 0;
switch (a) {
case 0: // FM
switch (a) {
case 0: // FM
case 1: // HEN/irq masks
if ((d ^ Pico32x.sh2_regs[0]) & 0x80)
elprintf(EL_ANOMALY|EL_32X, "HEN");
case 1: // HEN/irq masks
if ((d ^ Pico32x.sh2_regs[0]) & 0x80)
elprintf(EL_ANOMALY|EL_32X, "HEN");
- Pico32x.sh2irq_mask[cpuid] = d & 0x8f;
+ Pico32x.sh2irq_mask[sh2->is_slave] = d & 0x8f;
Pico32x.sh2_regs[0] &= ~0x80;
Pico32x.sh2_regs[0] |= d & 0x80;
if (d & 1)
Pico32x.sh2_regs[0] &= ~0x80;
Pico32x.sh2_regs[0] |= d & 0x80;
if (d & 1)
- p32x_pwm_schedule_sh2(&sh2s[cpuid]);
- p32x_update_irls(&sh2s[cpuid], 0);
+ p32x_pwm_schedule_sh2(sh2);
+ p32x_update_irls(sh2, 0);
return;
case 5: // H count
d &= 0xff;
if (Pico32x.sh2_regs[4 / 2] != d) {
Pico32x.sh2_regs[4 / 2] = d;
return;
case 5: // H count
d &= 0xff;
if (Pico32x.sh2_regs[4 / 2] != d) {
Pico32x.sh2_regs[4 / 2] = d;
- p32x_sh2_poll_event(&sh2s[cpuid ^ 1], SH2_STATE_CPOLL,
- sh2_cycles_done_m68k(&sh2s[cpuid]));
- sh2_end_run(&sh2s[cpuid], 4);
+ p32x_sh2_poll_event(sh2->other_sh2, SH2_STATE_CPOLL,
+ sh2_cycles_done_m68k(sh2));
+ sh2_end_run(sh2, 4);
r8[a ^ 1] = d;
p32x_m68k_poll_event(P32XF_68KCPOLL);
r8[a ^ 1] = d;
p32x_m68k_poll_event(P32XF_68KCPOLL);
- p32x_sh2_poll_event(&sh2s[cpuid ^ 1], SH2_STATE_CPOLL,
- sh2_cycles_done_m68k(&sh2s[cpuid]));
+ p32x_sh2_poll_event(sh2->other_sh2, SH2_STATE_CPOLL,
+ sh2_cycles_done_m68k(sh2));
comreg = 1 << (a & 0x0f) / 2;
Pico32x.comm_dirty_sh2 |= comreg;
return;
}
}
comreg = 1 << (a & 0x0f) / 2;
Pico32x.comm_dirty_sh2 |= comreg;
return;
}
}
-static void p32x_sh2reg_write16(u32 a, u32 d, int cpuid)
+static void p32x_sh2reg_write16(u32 a, u32 d, SH2 *sh2)
- sh2s[cpuid].poll_addr = 0;
// comm
if ((a & 0x30) == 0x20) {
// comm
if ((a & 0x30) == 0x20) {
Pico32x.regs[a / 2] = d;
p32x_m68k_poll_event(P32XF_68KCPOLL);
Pico32x.regs[a / 2] = d;
p32x_m68k_poll_event(P32XF_68KCPOLL);
- p32x_sh2_poll_event(&sh2s[cpuid ^ 1], SH2_STATE_CPOLL,
- sh2_cycles_done_m68k(&sh2s[cpuid]));
+ p32x_sh2_poll_event(sh2->other_sh2, SH2_STATE_CPOLL,
+ sh2_cycles_done_m68k(sh2));
comreg = 1 << (a & 0x0f) / 2;
Pico32x.comm_dirty_sh2 |= comreg;
return;
}
// PWM
else if ((a & 0x30) == 0x30) {
comreg = 1 << (a & 0x0f) / 2;
Pico32x.comm_dirty_sh2 |= comreg;
return;
}
// PWM
else if ((a & 0x30) == 0x30) {
- p32x_pwm_write16(a, d, &sh2s[cpuid], sh2_cycles_done_m68k(&sh2s[cpuid]));
+ p32x_pwm_write16(a, d, sh2, sh2_cycles_done_m68k(sh2));
case 0x14: Pico32x.sh2irqs &= ~P32XI_VRES; goto irls;
case 0x16: Pico32x.sh2irqs &= ~P32XI_VINT; goto irls;
case 0x18: Pico32x.sh2irqs &= ~P32XI_HINT; goto irls;
case 0x14: Pico32x.sh2irqs &= ~P32XI_VRES; goto irls;
case 0x16: Pico32x.sh2irqs &= ~P32XI_VINT; goto irls;
case 0x18: Pico32x.sh2irqs &= ~P32XI_HINT; goto irls;
- case 0x1a: Pico32x.sh2irqi[cpuid] &= ~P32XI_CMD; goto irls;
+ case 0x1a: Pico32x.sh2irqi[sh2->is_slave] &= ~P32XI_CMD; goto irls;
case 0x1c:
Pico32x.sh2irqs &= ~P32XI_PWM;
case 0x1c:
Pico32x.sh2irqs &= ~P32XI_PWM;
- p32x_pwm_schedule_sh2(&sh2s[cpuid]);
+ p32x_pwm_schedule_sh2(sh2);
- p32x_sh2reg_write8(a | 1, d, cpuid);
+ p32x_sh2reg_write8(a | 1, d, sh2);
- p32x_update_irls(&sh2s[cpuid], 0);
+ p32x_update_irls(sh2, 0);
}
// ------------------------------------------------------------------
}
// ------------------------------------------------------------------
-#define sh2_write16_dramN(n, ret) \
+#define sh2_write16_dramN(n) \
u16 *pd = &Pico32xMem->dram[n][(a & 0x1ffff) / 2]; \
if (!(a & 0x20000)) { \
*pd = d; \
u16 *pd = &Pico32xMem->dram[n][(a & 0x1ffff) / 2]; \
if (!(a & 0x20000)) { \
*pd = d; \
} \
/* overwrite */ \
if (!(d & 0xff00)) d |= *pd & 0xff00; \
if (!(d & 0x00ff)) d |= *pd & 0x00ff; \
} \
/* overwrite */ \
if (!(d & 0xff00)) d |= *pd & 0xff00; \
if (!(d & 0x00ff)) d |= *pd & 0x00ff; \
- *pd = d; \
- return ret
static void m68k_write16_dram0_ow(u32 a, u32 d)
{
static void m68k_write16_dram0_ow(u32 a, u32 d)
{
}
static void m68k_write16_dram1_ow(u32 a, u32 d)
{
}
static void m68k_write16_dram1_ow(u32 a, u32 d)
{
}
// -----------------------------------------------------------------
}
// -----------------------------------------------------------------
// -----------------------------------------------------------------
// read8
// -----------------------------------------------------------------
// read8
-static u32 sh2_read8_unmapped(u32 a, int id)
+static u32 sh2_read8_unmapped(u32 a, SH2 *sh2)
{
elprintf(EL_UIO, "%csh2 unmapped r8 [%08x] %02x @%06x",
{
elprintf(EL_UIO, "%csh2 unmapped r8 [%08x] %02x @%06x",
- id ? 's' : 'm', a, 0, sh2_pc(id));
+ sh2->is_slave ? 's' : 'm', a, 0, sh2_pc(sh2));
-static u32 sh2_read8_cs0(u32 a, int id)
+static u32 sh2_read8_cs0(u32 a, SH2 *sh2)
{
u32 d = 0;
// 0x3ff00 is veridied
if ((a & 0x3ff00) == 0x4000) {
{
u32 d = 0;
// 0x3ff00 is veridied
if ((a & 0x3ff00) == 0x4000) {
- d = p32x_sh2reg_read16(a, id);
+ d = p32x_sh2reg_read16(a, sh2);
goto out_16to8;
}
if ((a & 0x3ff00) == 0x4100) {
d = p32x_vdp_read16(a);
goto out_16to8;
}
if ((a & 0x3ff00) == 0x4100) {
d = p32x_vdp_read16(a);
- sh2_poll_detect(&sh2s[id], a, SH2_STATE_VPOLL);
+ sh2_poll_detect(sh2, a, SH2_STATE_VPOLL);
goto out_16to8;
}
// TODO: mirroring?
goto out_16to8;
}
// TODO: mirroring?
- if (id == 0 && a < sizeof(Pico32xMem->sh2_rom_m))
+ if (!sh2->is_slave && a < sizeof(Pico32xMem->sh2_rom_m))
return Pico32xMem->sh2_rom_m[a ^ 1];
return Pico32xMem->sh2_rom_m[a ^ 1];
- if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s))
+ if (sh2->is_slave && a < sizeof(Pico32xMem->sh2_rom_s))
return Pico32xMem->sh2_rom_s[a ^ 1];
if ((a & 0x3fe00) == 0x4200) {
return Pico32xMem->sh2_rom_s[a ^ 1];
if ((a & 0x3fe00) == 0x4200) {
- return sh2_read8_unmapped(a, id);
+ return sh2_read8_unmapped(a, sh2);
d >>= 8;
elprintf(EL_32X, "%csh2 r8 [%08x] %02x @%06x",
d >>= 8;
elprintf(EL_32X, "%csh2 r8 [%08x] %02x @%06x",
- id ? 's' : 'm', a, d, sh2_pc(id));
+ sh2->is_slave ? 's' : 'm', a, d, sh2_pc(sh2));
-static u32 sh2_read8_da(u32 a, int id)
+static u32 sh2_read8_da(u32 a, SH2 *sh2)
- return Pico32xMem->data_array[id][(a & 0xfff) ^ 1];
+ return sh2->data_array[(a & 0xfff) ^ 1];
-static u32 sh2_read16_unmapped(u32 a, int id)
+static u32 sh2_read16_unmapped(u32 a, SH2 *sh2)
{
elprintf(EL_UIO, "%csh2 unmapped r16 [%08x] %04x @%06x",
{
elprintf(EL_UIO, "%csh2 unmapped r16 [%08x] %04x @%06x",
- id ? 's' : 'm', a, 0, sh2_pc(id));
+ sh2->is_slave ? 's' : 'm', a, 0, sh2_pc(sh2));
-static u32 sh2_read16_cs0(u32 a, int id)
+static u32 sh2_read16_cs0(u32 a, SH2 *sh2)
{
u32 d = 0;
if ((a & 0x3ff00) == 0x4000) {
{
u32 d = 0;
if ((a & 0x3ff00) == 0x4000) {
- d = p32x_sh2reg_read16(a, id);
+ d = p32x_sh2reg_read16(a, sh2);
if (!(EL_LOGMASK & EL_PWM) && (a & 0x30) == 0x30) // hide PWM
return d;
goto out;
if (!(EL_LOGMASK & EL_PWM) && (a & 0x30) == 0x30) // hide PWM
return d;
goto out;
if ((a & 0x3ff00) == 0x4100) {
d = p32x_vdp_read16(a);
if ((a & 0x3ff00) == 0x4100) {
d = p32x_vdp_read16(a);
- sh2_poll_detect(&sh2s[id], a, SH2_STATE_VPOLL);
+ sh2_poll_detect(sh2, a, SH2_STATE_VPOLL);
- if (id == 0 && a < sizeof(Pico32xMem->sh2_rom_m))
+ if (!sh2->is_slave && a < sizeof(Pico32xMem->sh2_rom_m))
return *(u16 *)(Pico32xMem->sh2_rom_m + a);
return *(u16 *)(Pico32xMem->sh2_rom_m + a);
- if (id == 1 && a < sizeof(Pico32xMem->sh2_rom_s))
+ if (sh2->is_slave && a < sizeof(Pico32xMem->sh2_rom_s))
return *(u16 *)(Pico32xMem->sh2_rom_s + a);
if ((a & 0x3fe00) == 0x4200) {
return *(u16 *)(Pico32xMem->sh2_rom_s + a);
if ((a & 0x3fe00) == 0x4200) {
- return sh2_read16_unmapped(a, id);
+ return sh2_read16_unmapped(a, sh2);
out:
elprintf(EL_32X, "%csh2 r16 [%08x] %04x @%06x",
out:
elprintf(EL_32X, "%csh2 r16 [%08x] %04x @%06x",
- id ? 's' : 'm', a, d, sh2_pc(id));
+ sh2->is_slave ? 's' : 'm', a, d, sh2_pc(sh2));
-static u32 sh2_read16_da(u32 a, int id)
+static u32 sh2_read16_da(u32 a, SH2 *sh2)
- return ((u16 *)Pico32xMem->data_array[id])[(a & 0xfff) / 2];
+ return ((u16 *)sh2->data_array)[(a & 0xfff) / 2];
-static int REGPARM(3) sh2_write_ignore(u32 a, u32 d, int id)
+// writes
+static void REGPARM(3) sh2_write_ignore(u32 a, u32 d, SH2 *sh2)
-static int REGPARM(3) sh2_write8_unmapped(u32 a, u32 d, int id)
+static void REGPARM(3) sh2_write8_unmapped(u32 a, u32 d, SH2 *sh2)
{
elprintf(EL_UIO, "%csh2 unmapped w8 [%08x] %02x @%06x",
{
elprintf(EL_UIO, "%csh2 unmapped w8 [%08x] %02x @%06x",
- id ? 's' : 'm', a, d & 0xff, sh2_pc(id));
- return 0;
+ sh2->is_slave ? 's' : 'm', a, d & 0xff, sh2_pc(sh2));
-static int REGPARM(3) sh2_write8_cs0(u32 a, u32 d, int id)
+static void REGPARM(3) sh2_write8_cs0(u32 a, u32 d, SH2 *sh2)
{
elprintf(EL_32X, "%csh2 w8 [%08x] %02x @%06x",
{
elprintf(EL_32X, "%csh2 w8 [%08x] %02x @%06x",
- id ? 's' : 'm', a, d & 0xff, sh2_pc(id));
+ sh2->is_slave ? 's' : 'm', a, d & 0xff, sh2_pc(sh2));
if (Pico32x.regs[0] & P32XS_FM) {
if ((a & 0x3ff00) == 0x4100) {
if (Pico32x.regs[0] & P32XS_FM) {
if ((a & 0x3ff00) == 0x4100) {
- sh2s[id].poll_addr = 0;
}
}
if ((a & 0x3ff00) == 0x4000) {
}
}
if ((a & 0x3ff00) == 0x4000) {
- p32x_sh2reg_write8(a, d, id);
- return 1;
+ p32x_sh2reg_write8(a, d, sh2);
+ return;
- return sh2_write8_unmapped(a, d, id);
+ sh2_write8_unmapped(a, d, sh2);
-static int REGPARM(3) sh2_write8_dram0(u32 a, u32 d, int id)
+static void REGPARM(3) sh2_write8_dram0(u32 a, u32 d, SH2 *sh2)
-static int REGPARM(3) sh2_write8_dram1(u32 a, u32 d, int id)
+static void REGPARM(3) sh2_write8_dram1(u32 a, u32 d, SH2 *sh2)
-static int REGPARM(3) sh2_write8_sdram(u32 a, u32 d, int id)
+static void REGPARM(3) sh2_write8_sdram(u32 a, u32 d, SH2 *sh2)
{
u32 a1 = a & 0x3ffff;
#ifdef DRC_SH2
int t = Pico32xMem->drcblk_ram[a1 >> SH2_DRCBLK_RAM_SHIFT];
if (t)
{
u32 a1 = a & 0x3ffff;
#ifdef DRC_SH2
int t = Pico32xMem->drcblk_ram[a1 >> SH2_DRCBLK_RAM_SHIFT];
if (t)
- sh2_drc_wcheck_ram(a, t, id);
+ sh2_drc_wcheck_ram(a, t, sh2->is_slave);
#endif
Pico32xMem->sdram[a1 ^ 1] = d;
#endif
Pico32xMem->sdram[a1 ^ 1] = d;
-static int REGPARM(3) sh2_write8_da(u32 a, u32 d, int id)
+static void REGPARM(3) sh2_write8_da(u32 a, u32 d, SH2 *sh2)
{
u32 a1 = a & 0xfff;
#ifdef DRC_SH2
{
u32 a1 = a & 0xfff;
#ifdef DRC_SH2
+ int id = sh2->is_slave;
int t = Pico32xMem->drcblk_da[id][a1 >> SH2_DRCBLK_DA_SHIFT];
if (t)
sh2_drc_wcheck_da(a, t, id);
#endif
int t = Pico32xMem->drcblk_da[id][a1 >> SH2_DRCBLK_DA_SHIFT];
if (t)
sh2_drc_wcheck_da(a, t, id);
#endif
- Pico32xMem->data_array[id][a1 ^ 1] = d;
- return 0;
+ sh2->data_array[a1 ^ 1] = d;
-static int REGPARM(3) sh2_write16_unmapped(u32 a, u32 d, int id)
+static void REGPARM(3) sh2_write16_unmapped(u32 a, u32 d, SH2 *sh2)
{
elprintf(EL_UIO, "%csh2 unmapped w16 [%08x] %04x @%06x",
{
elprintf(EL_UIO, "%csh2 unmapped w16 [%08x] %04x @%06x",
- id ? 's' : 'm', a, d & 0xffff, sh2_pc(id));
- return 0;
+ sh2->is_slave ? 's' : 'm', a, d & 0xffff, sh2_pc(sh2));
-static int REGPARM(3) sh2_write16_cs0(u32 a, u32 d, int id)
+static void REGPARM(3) sh2_write16_cs0(u32 a, u32 d, SH2 *sh2)
{
if (((EL_LOGMASK & EL_PWM) || (a & 0x30) != 0x30)) // hide PWM
elprintf(EL_32X, "%csh2 w16 [%08x] %04x @%06x",
{
if (((EL_LOGMASK & EL_PWM) || (a & 0x30) != 0x30)) // hide PWM
elprintf(EL_32X, "%csh2 w16 [%08x] %04x @%06x",
- id ? 's' : 'm', a, d & 0xffff, sh2_pc(id));
+ sh2->is_slave ? 's' : 'm', a, d & 0xffff, sh2_pc(sh2));
if (Pico32x.regs[0] & P32XS_FM) {
if ((a & 0x3ff00) == 0x4100) {
if (Pico32x.regs[0] & P32XS_FM) {
if ((a & 0x3ff00) == 0x4100) {
- sh2s[id].poll_addr = 0;
- p32x_vdp_write16(a, d, &sh2s[id]);
- return 0;
+ sh2->poll_addr = 0;
+ p32x_vdp_write16(a, d, sh2);
+ return;
}
if ((a & 0x3fe00) == 0x4200) {
Pico32xMem->pal[(a & 0x1ff) / 2] = d;
Pico32x.dirty_pal = 1;
}
if ((a & 0x3fe00) == 0x4200) {
Pico32xMem->pal[(a & 0x1ff) / 2] = d;
Pico32x.dirty_pal = 1;
}
}
if ((a & 0x3ff00) == 0x4000) {
}
}
if ((a & 0x3ff00) == 0x4000) {
- p32x_sh2reg_write16(a, d, id);
- return 1;
+ p32x_sh2reg_write16(a, d, sh2);
+ return;
- return sh2_write16_unmapped(a, d, id);
+ sh2_write16_unmapped(a, d, sh2);
-static int REGPARM(3) sh2_write16_dram0(u32 a, u32 d, int id)
+static void REGPARM(3) sh2_write16_dram0(u32 a, u32 d, SH2 *sh2)
- sh2_write16_dramN(0, 0);
-static int REGPARM(3) sh2_write16_dram1(u32 a, u32 d, int id)
+static void REGPARM(3) sh2_write16_dram1(u32 a, u32 d, SH2 *sh2)
- sh2_write16_dramN(1, 0);
-static int REGPARM(3) sh2_write16_sdram(u32 a, u32 d, int id)
+static void REGPARM(3) sh2_write16_sdram(u32 a, u32 d, SH2 *sh2)
{
u32 a1 = a & 0x3ffff;
#ifdef DRC_SH2
int t = Pico32xMem->drcblk_ram[a1 >> SH2_DRCBLK_RAM_SHIFT];
if (t)
{
u32 a1 = a & 0x3ffff;
#ifdef DRC_SH2
int t = Pico32xMem->drcblk_ram[a1 >> SH2_DRCBLK_RAM_SHIFT];
if (t)
- sh2_drc_wcheck_ram(a, t, id);
+ sh2_drc_wcheck_ram(a, t, sh2->is_slave);
#endif
((u16 *)Pico32xMem->sdram)[a1 / 2] = d;
#endif
((u16 *)Pico32xMem->sdram)[a1 / 2] = d;
-static int REGPARM(3) sh2_write16_da(u32 a, u32 d, int id)
+static void REGPARM(3) sh2_write16_da(u32 a, u32 d, SH2 *sh2)
{
u32 a1 = a & 0xfff;
#ifdef DRC_SH2
{
u32 a1 = a & 0xfff;
#ifdef DRC_SH2
+ int id = sh2->is_slave;
int t = Pico32xMem->drcblk_da[id][a1 >> SH2_DRCBLK_DA_SHIFT];
if (t)
sh2_drc_wcheck_da(a, t, id);
#endif
int t = Pico32xMem->drcblk_da[id][a1 >> SH2_DRCBLK_DA_SHIFT];
if (t)
sh2_drc_wcheck_da(a, t, id);
#endif
- ((u16 *)Pico32xMem->data_array[id])[a1 / 2] = d;
- return 0;
+ ((u16 *)sh2->data_array)[a1 / 2] = d;
-typedef u32 (sh2_read_handler)(u32 a, int id);
-typedef int REGPARM(3) (sh2_write_handler)(u32 a, u32 d, int id);
+typedef u32 (sh2_read_handler)(u32 a, SH2 *sh2);
+typedef void REGPARM(3) (sh2_write_handler)(u32 a, u32 d, SH2 *sh2);
#define SH2MAP_ADDR2OFFS_R(a) \
#define SH2MAP_ADDR2OFFS_R(a) \
- ((((a) >> 25) & 3) | (((a) >> 27) & 0x1c))
+ ((u32)(a) >> SH2_READ_SHIFT)
#define SH2MAP_ADDR2OFFS_W(a) \
((u32)(a) >> SH2_WRITE_SHIFT)
#define SH2MAP_ADDR2OFFS_W(a) \
((u32)(a) >> SH2_WRITE_SHIFT)
sh2_map += SH2MAP_ADDR2OFFS_R(a);
p = sh2_map->addr;
if (map_flag_set(p))
sh2_map += SH2MAP_ADDR2OFFS_R(a);
p = sh2_map->addr;
if (map_flag_set(p))
- return ((sh2_read_handler *)(p << 1))(a, sh2->is_slave);
+ return ((sh2_read_handler *)(p << 1))(a, sh2);
else
return *(u8 *)((p << 1) + ((a & sh2_map->mask) ^ 1));
}
else
return *(u8 *)((p << 1) + ((a & sh2_map->mask) ^ 1));
}
sh2_map += SH2MAP_ADDR2OFFS_R(a);
p = sh2_map->addr;
if (map_flag_set(p))
sh2_map += SH2MAP_ADDR2OFFS_R(a);
p = sh2_map->addr;
if (map_flag_set(p))
- return ((sh2_read_handler *)(p << 1))(a, sh2->is_slave);
+ return ((sh2_read_handler *)(p << 1))(a, sh2);
else
return *(u16 *)((p << 1) + ((a & sh2_map->mask) & ~1));
}
else
return *(u16 *)((p << 1) + ((a & sh2_map->mask) & ~1));
}
- return sh2_peripheral_read32(a, sh2->is_slave);
+ return sh2_peripheral_read32(a, sh2);
handler = (sh2_read_handler *)(p << 1);
handler = (sh2_read_handler *)(p << 1);
- return (handler(a, sh2->is_slave) << 16) | handler(a + 2, sh2->is_slave);
+ return (handler(a, sh2) << 16) | handler(a + 2, sh2);
-// return nonzero if write potentially causes an interrupt (used by drc)
-int REGPARM(3) p32x_sh2_write8(u32 a, u32 d, SH2 *sh2)
+void REGPARM(3) p32x_sh2_write8(u32 a, u32 d, SH2 *sh2)
{
const void **sh2_wmap = sh2->write8_tab;
sh2_write_handler *wh;
wh = sh2_wmap[SH2MAP_ADDR2OFFS_W(a)];
{
const void **sh2_wmap = sh2->write8_tab;
sh2_write_handler *wh;
wh = sh2_wmap[SH2MAP_ADDR2OFFS_W(a)];
- return wh(a, d, sh2->is_slave);
-int REGPARM(3) p32x_sh2_write16(u32 a, u32 d, SH2 *sh2)
+void REGPARM(3) p32x_sh2_write16(u32 a, u32 d, SH2 *sh2)
{
const void **sh2_wmap = sh2->write16_tab;
sh2_write_handler *wh;
wh = sh2_wmap[SH2MAP_ADDR2OFFS_W(a)];
{
const void **sh2_wmap = sh2->write16_tab;
sh2_write_handler *wh;
wh = sh2_wmap[SH2MAP_ADDR2OFFS_W(a)];
- return wh(a, d, sh2->is_slave);
-int REGPARM(3) p32x_sh2_write32(u32 a, u32 d, SH2 *sh2)
+void REGPARM(3) p32x_sh2_write32(u32 a, u32 d, SH2 *sh2)
{
const void **sh2_wmap = sh2->write16_tab;
{
const void **sh2_wmap = sh2->write16_tab;
- sh2_write_handler *handler;
u32 offs;
offs = SH2MAP_ADDR2OFFS_W(a);
if (offs == SH2MAP_ADDR2OFFS_W(0xffffc000)) {
u32 offs;
offs = SH2MAP_ADDR2OFFS_W(a);
if (offs == SH2MAP_ADDR2OFFS_W(0xffffc000)) {
- sh2_peripheral_write32(a, d, sh2->is_slave);
- return 0;
+ sh2_peripheral_write32(a, d, sh2);
+ return;
- handler = sh2_wmap[offs];
- handler(a, d >> 16, sh2->is_slave);
- handler(a + 2, d, sh2->is_slave);
- return 0;
+ wh = sh2_wmap[offs];
+ wh(a, d >> 16, sh2);
+ wh(a + 2, d, sh2);
}
// -----------------------------------------------------------------
}
// -----------------------------------------------------------------
#define MAP_MEMORY(m) ((uptr)(m) >> 1)
#define MAP_HANDLER(h) ( ((uptr)(h) >> 1) | ((uptr)1 << (sizeof(uptr) * 8 - 1)) )
#define MAP_MEMORY(m) ((uptr)(m) >> 1)
#define MAP_HANDLER(h) ( ((uptr)(h) >> 1) | ((uptr)1 << (sizeof(uptr) * 8 - 1)) )
-static sh2_memmap sh2_read8_map[0x20], sh2_read16_map[0x20];
+static sh2_memmap sh2_read8_map[0x80], sh2_read16_map[0x80];
// for writes we are using handlers only
static sh2_write_handler *sh2_write8_map[0x80], *sh2_write16_map[0x80];
// for writes we are using handlers only
static sh2_write_handler *sh2_write8_map[0x80], *sh2_write16_map[0x80];
b ? m68k_write16_dram1_ow : m68k_write16_dram0_ow, 1);
// SH2
b ? m68k_write16_dram1_ow : m68k_write16_dram0_ow, 1);
// SH2
- sh2_read8_map[2].addr = sh2_read8_map[6].addr =
- sh2_read16_map[2].addr = sh2_read16_map[6].addr = MAP_MEMORY(Pico32xMem->dram[b]);
+ sh2_read8_map[0x04/2].addr = sh2_read8_map[0x24/2].addr =
+ sh2_read16_map[0x04/2].addr = sh2_read16_map[0x24/2].addr = MAP_MEMORY(Pico32xMem->dram[b]);
sh2_write8_map[0x04/2] = sh2_write8_map[0x24/2] = b ? sh2_write8_dram1 : sh2_write8_dram0;
sh2_write16_map[0x04/2] = sh2_write16_map[0x24/2] = b ? sh2_write16_dram1 : sh2_write16_dram0;
sh2_write8_map[0x04/2] = sh2_write8_map[0x24/2] = b ? sh2_write8_dram1 : sh2_write8_dram0;
sh2_write16_map[0x04/2] = sh2_write16_map[0x24/2] = b ? sh2_write16_dram1 : sh2_write16_dram0;
- sh2_read8_map[0].addr = sh2_read8_map[4].addr = MAP_HANDLER(sh2_read8_cs0);
- sh2_read16_map[0].addr = sh2_read16_map[4].addr = MAP_HANDLER(sh2_read16_cs0);
+ sh2_read8_map[0x00/2].addr = sh2_read8_map[0x20/2].addr = MAP_HANDLER(sh2_read8_cs0);
+ sh2_read16_map[0x00/2].addr = sh2_read16_map[0x20/2].addr = MAP_HANDLER(sh2_read16_cs0);
sh2_write8_map[0x00/2] = sh2_write8_map[0x20/2] = sh2_write8_cs0;
sh2_write16_map[0x00/2] = sh2_write16_map[0x20/2] = sh2_write16_cs0;
// CS1 - ROM
sh2_write8_map[0x00/2] = sh2_write8_map[0x20/2] = sh2_write8_cs0;
sh2_write16_map[0x00/2] = sh2_write16_map[0x20/2] = sh2_write16_cs0;
// CS1 - ROM
- sh2_read8_map[1].addr = sh2_read8_map[5].addr =
- sh2_read16_map[1].addr = sh2_read16_map[5].addr = MAP_MEMORY(Pico.rom);
- sh2_read8_map[1].mask = sh2_read8_map[5].mask =
- sh2_read16_map[1].mask = sh2_read16_map[5].mask = 0x3fffff; // FIXME
+ sh2_read8_map[0x02/2].addr = sh2_read8_map[0x22/2].addr =
+ sh2_read16_map[0x02/2].addr = sh2_read16_map[0x22/2].addr = MAP_MEMORY(Pico.rom);
+ sh2_read8_map[0x02/2].mask = sh2_read8_map[0x22/2].mask =
+ sh2_read16_map[0x02/2].mask = sh2_read16_map[0x22/2].mask = 0x3fffff; // FIXME
// CS2 - DRAM - done by Pico32xSwapDRAM()
// CS2 - DRAM - done by Pico32xSwapDRAM()
- sh2_read8_map[2].mask = sh2_read8_map[6].mask =
- sh2_read16_map[2].mask = sh2_read16_map[6].mask = 0x01ffff;
+ sh2_read8_map[0x04/2].mask = sh2_read8_map[0x24/2].mask =
+ sh2_read16_map[0x04/2].mask = sh2_read16_map[0x24/2].mask = 0x01ffff;
- sh2_read8_map[3].addr = sh2_read8_map[7].addr =
- sh2_read16_map[3].addr = sh2_read16_map[7].addr = MAP_MEMORY(Pico32xMem->sdram);
- sh2_write8_map[0x06/2] = sh2_write8_map[0x26/2] = sh2_write8_sdram;
- sh2_write16_map[0x06/2] = sh2_write16_map[0x26/2] = sh2_write16_sdram;
- sh2_read8_map[3].mask = sh2_read8_map[7].mask =
- sh2_read16_map[3].mask = sh2_read16_map[7].mask = 0x03ffff;
+ sh2_read8_map[0x06/2].addr = sh2_read8_map[0x26/2].addr =
+ sh2_read16_map[0x06/2].addr = sh2_read16_map[0x26/2].addr = MAP_MEMORY(Pico32xMem->sdram);
+ sh2_write8_map[0x06/2] = sh2_write8_map[0x26/2] = sh2_write8_sdram;
+ sh2_write16_map[0x06/2] = sh2_write16_map[0x26/2] = sh2_write16_sdram;
+ sh2_read8_map[0x06/2].mask = sh2_read8_map[0x26/2].mask =
+ sh2_read16_map[0x06/2].mask = sh2_read16_map[0x26/2].mask = 0x03ffff;
- sh2_read8_map[0x18].addr = MAP_HANDLER(sh2_read8_da);
- sh2_read16_map[0x18].addr = MAP_HANDLER(sh2_read16_da);
- sh2_write8_map[0xc0/2] = sh2_write8_da;
- sh2_write16_map[0xc0/2] = sh2_write16_da;
+ sh2_read8_map[0xc0/2].addr = MAP_HANDLER(sh2_read8_da);
+ sh2_read16_map[0xc0/2].addr = MAP_HANDLER(sh2_read16_da);
+ sh2_write8_map[0xc0/2] = sh2_write8_da;
+ sh2_write16_map[0xc0/2] = sh2_write16_da;
- sh2_read8_map[0x1f].addr = MAP_HANDLER(sh2_peripheral_read8);
- sh2_read16_map[0x1f].addr = MAP_HANDLER(sh2_peripheral_read16);
- sh2_write8_map[0xff/2] = sh2_peripheral_write8;
- sh2_write16_map[0xff/2] = sh2_peripheral_write16;
+ sh2_read8_map[0xff/2].addr = MAP_HANDLER(sh2_peripheral_read8);
+ sh2_read16_map[0xff/2].addr = MAP_HANDLER(sh2_peripheral_read16);
+ sh2_write8_map[0xff/2] = sh2_peripheral_write8;
+ sh2_write16_map[0xff/2] = sh2_peripheral_write16;
// map DRAM area, both 68k and SH2
Pico32xSwapDRAM(1);
// map DRAM area, both 68k and SH2
Pico32xSwapDRAM(1);
static void dmac_te_irq(SH2 *sh2, struct dma_chan *chan)
{
static void dmac_te_irq(SH2 *sh2, struct dma_chan *chan)
{
- char *regs = (void *)Pico32xMem->sh2_peri_regs[sh2->is_slave];
+ char *regs = (void *)sh2->peri_regs;
struct dmac *dmac = (void *)(regs + 0x180);
int level = PREG8(regs, 0xe2) & 0x0f; // IPRA
int vector = (chan == &dmac->chan[0]) ?
struct dmac *dmac = (void *)(regs + 0x180);
int level = PREG8(regs, 0xe2) & 0x0f; // IPRA
int vector = (chan == &dmac->chan[0]) ?
// SH2 timer step
for (i = 0; i < 2; i++) {
// SH2 timer step
for (i = 0; i < 2; i++) {
- tmp = PREG8(Pico32xMem->sh2_peri_regs[i], 0x80) & 7;
+ tmp = PREG8(sh2s[i].peri_regs, 0x80) & 7;
// Sclk cycles per timer tick
if (tmp)
cycles = 0x20 << tmp;
// Sclk cycles per timer tick
if (tmp)
cycles = 0x20 << tmp;
// WDT timers
for (i = 0; i < 2; i++) {
// WDT timers
for (i = 0; i < 2; i++) {
- void *pregs = Pico32xMem->sh2_peri_regs[i];
+ void *pregs = sh2s[i].peri_regs;
if (PREG8(pregs, 0x80) & 0x20) { // TME
timer_cycles[i] += cycles;
cnt = PREG8(pregs, 0x81);
if (PREG8(pregs, 0x80) & 0x20) { // TME
timer_cycles[i] += cycles;
cnt = PREG8(pregs, 0x81);
// SH2 internal peripheral memhandlers
// we keep them in little endian format
// SH2 internal peripheral memhandlers
// we keep them in little endian format
-u32 sh2_peripheral_read8(u32 a, int id)
+u32 sh2_peripheral_read8(u32 a, SH2 *sh2)
- u8 *r = (void *)Pico32xMem->sh2_peri_regs[id];
+ u8 *r = (void *)sh2->peri_regs;
u32 d;
a &= 0x1ff;
d = PREG8(r, a);
u32 d;
a &= 0x1ff;
d = PREG8(r, a);
- elprintf(EL_32XP, "%csh2 peri r8 [%08x] %02x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id));
+ elprintf(EL_32XP, "%csh2 peri r8 [%08x] %02x @%06x",
+ sh2->is_slave ? 's' : 'm', a | ~0x1ff, d, sh2_pc(sh2));
-u32 sh2_peripheral_read16(u32 a, int id)
+u32 sh2_peripheral_read16(u32 a, SH2 *sh2)
- u16 *r = (void *)Pico32xMem->sh2_peri_regs[id];
+ u16 *r = (void *)sh2->peri_regs;
u32 d;
a &= 0x1ff;
d = r[(a / 2) ^ 1];
u32 d;
a &= 0x1ff;
d = r[(a / 2) ^ 1];
- elprintf(EL_32XP, "%csh2 peri r16 [%08x] %04x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id));
+ elprintf(EL_32XP, "%csh2 peri r16 [%08x] %04x @%06x",
+ sh2->is_slave ? 's' : 'm', a | ~0x1ff, d, sh2_pc(sh2));
-u32 sh2_peripheral_read32(u32 a, int id)
+u32 sh2_peripheral_read32(u32 a, SH2 *sh2)
- d = Pico32xMem->sh2_peri_regs[id][a / 4];
+ d = sh2->peri_regs[a / 4];
- elprintf(EL_32XP, "%csh2 peri r32 [%08x] %08x @%06x", id ? 's' : 'm', a | ~0x1ff, d, sh2_pc(id));
+ elprintf(EL_32XP, "%csh2 peri r32 [%08x] %08x @%06x",
+ sh2->is_slave ? 's' : 'm', a | ~0x1ff, d, sh2_pc(sh2));
-int REGPARM(3) sh2_peripheral_write8(u32 a, u32 d, int id)
+void REGPARM(3) sh2_peripheral_write8(u32 a, u32 d, SH2 *sh2)
- u8 *r = (void *)Pico32xMem->sh2_peri_regs[id];
- elprintf(EL_32XP, "%csh2 peri w8 [%08x] %02x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
+ u8 *r = (void *)sh2->peri_regs;
+ elprintf(EL_32XP, "%csh2 peri w8 [%08x] %02x @%06x",
+ sh2->is_slave ? 's' : 'm', a, d, sh2_pc(sh2));
a &= 0x1ff;
PREG8(r, a) = d;
a &= 0x1ff;
PREG8(r, a) = d;
// X-men SCI hack
if ((a == 2 && (d & 0x20)) || // transmiter enabled
(a == 4 && !(d & 0x80))) { // valid data in TDR
// X-men SCI hack
if ((a == 2 && (d & 0x20)) || // transmiter enabled
(a == 4 && !(d & 0x80))) { // valid data in TDR
- void *oregs = Pico32xMem->sh2_peri_regs[id ^ 1];
+ void *oregs = sh2->other_sh2->peri_regs;
if ((PREG8(oregs, 2) & 0x50) == 0x50) { // receiver + irq enabled
int level = PREG8(oregs, 0x60) >> 4;
int vector = PREG8(oregs, 0x63) & 0x7f;
if ((PREG8(oregs, 2) & 0x50) == 0x50) { // receiver + irq enabled
int level = PREG8(oregs, 0x60) >> 4;
int vector = PREG8(oregs, 0x63) & 0x7f;
- elprintf(EL_32XP, "%csh2 SCI recv irq (%d, %d)", (id ^ 1) ? 's' : 'm', level, vector);
- sh2_internal_irq(&sh2s[id ^ 1], level, vector);
- return 1;
+ elprintf(EL_32XP, "%csh2 SCI recv irq (%d, %d)",
+ (sh2->is_slave ^ 1) ? 's' : 'm', level, vector);
+ sh2_internal_irq(sh2->other_sh2, level, vector);
+ return;
-int REGPARM(3) sh2_peripheral_write16(u32 a, u32 d, int id)
+void REGPARM(3) sh2_peripheral_write16(u32 a, u32 d, SH2 *sh2)
- u16 *r = (void *)Pico32xMem->sh2_peri_regs[id];
- elprintf(EL_32XP, "%csh2 peri w16 [%08x] %04x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
+ u16 *r = (void *)sh2->peri_regs;
+ elprintf(EL_32XP, "%csh2 peri w16 [%08x] %04x @%06x",
+ sh2->is_slave ? 's' : 'm', a, d, sh2_pc(sh2));
}
if ((d & 0xff00) == 0x5a00) // WTCNT
PREG8(r, 0x81) = d;
}
if ((d & 0xff00) == 0x5a00) // WTCNT
PREG8(r, 0x81) = d;
-void sh2_peripheral_write32(u32 a, u32 d, int id)
+void sh2_peripheral_write32(u32 a, u32 d, SH2 *sh2)
- u32 *r = Pico32xMem->sh2_peri_regs[id];
- elprintf(EL_32XP, "%csh2 peri w32 [%08x] %08x @%06x", id ? 's' : 'm', a, d, sh2_pc(id));
+ u32 *r = sh2->peri_regs;
+ elprintf(EL_32XP, "%csh2 peri w32 [%08x] %08x @%06x",
+ sh2->is_slave ? 's' : 'm', a, d, sh2_pc(sh2));
a &= 0x1fc;
r[a / 4] = d;
a &= 0x1fc;
r[a / 4] = d;
switch (a) {
// division unit (TODO: verify):
case 0x104: // DVDNT: divident L, starts divide
switch (a) {
// division unit (TODO: verify):
case 0x104: // DVDNT: divident L, starts divide
- elprintf(EL_32XP, "%csh2 divide %08x / %08x", id ? 's' : 'm', d, r[0x100 / 4]);
+ elprintf(EL_32XP, "%csh2 divide %08x / %08x",
+ sh2->is_slave ? 's' : 'm', d, r[0x100 / 4]);
if (r[0x100 / 4]) {
signed int divisor = r[0x100 / 4];
r[0x118 / 4] = r[0x110 / 4] = (signed int)d % divisor;
if (r[0x100 / 4]) {
signed int divisor = r[0x100 / 4];
r[0x118 / 4] = r[0x110 / 4] = (signed int)d % divisor;
break;
case 0x114:
elprintf(EL_32XP, "%csh2 divide %08x%08x / %08x @%08x",
break;
case 0x114:
elprintf(EL_32XP, "%csh2 divide %08x%08x / %08x @%08x",
- id ? 's' : 'm', r[0x110 / 4], d, r[0x100 / 4], sh2_pc(id));
+ sh2->is_slave ? 's' : 'm', r[0x110 / 4], d, r[0x100 / 4], sh2_pc(sh2));
if (r[0x100 / 4]) {
signed long long divident = (signed long long)r[0x110 / 4] << 32 | d;
signed int divisor = r[0x100 / 4];
if (r[0x100 / 4]) {
signed long long divident = (signed long long)r[0x110 / 4] << 32 | d;
signed int divisor = r[0x100 / 4];
r[0x11c / 4] = r[0x114 / 4] = divident;
divident >>= 31;
if ((unsigned long long)divident + 1 > 1) {
r[0x11c / 4] = r[0x114 / 4] = divident;
divident >>= 31;
if ((unsigned long long)divident + 1 > 1) {
- //elprintf(EL_32XP, "%csh2 divide overflow! @%08x", id ? 's' : 'm', sh2_pc(id));
+ //elprintf(EL_32XP, "%csh2 divide overflow! @%08x",
+ // sh2->is_slave ? 's' : 'm', sh2_pc(sh2));
r[0x11c / 4] = r[0x114 / 4] = divident > 0 ? 0x7fffffff : 0x80000000; // overflow
}
}
r[0x11c / 4] = r[0x114 / 4] = divident > 0 ? 0x7fffffff : 0x80000000; // overflow
}
}
// perhaps starting a DMA?
if (a == 0x1b0 || a == 0x18c || a == 0x19c) {
// perhaps starting a DMA?
if (a == 0x1b0 || a == 0x18c || a == 0x19c) {
- struct dmac *dmac = (void *)&Pico32xMem->sh2_peri_regs[id][0x180 / 4];
+ struct dmac *dmac = (void *)&sh2->peri_regs[0x180 / 4];
if (!(dmac->dmaor & DMA_DME))
return;
if ((dmac->chan[0].chcr & (DMA_TE|DMA_DE)) == DMA_DE)
if (!(dmac->dmaor & DMA_DME))
return;
if ((dmac->chan[0].chcr & (DMA_TE|DMA_DE)) == DMA_DE)
- dmac_trigger(&sh2s[id], &dmac->chan[0]);
+ dmac_trigger(sh2, &dmac->chan[0]);
if ((dmac->chan[1].chcr & (DMA_TE|DMA_DE)) == DMA_DE)
if ((dmac->chan[1].chcr & (DMA_TE|DMA_DE)) == DMA_DE)
- dmac_trigger(&sh2s[id], &dmac->chan[1]);
+ dmac_trigger(sh2, &dmac->chan[1]);
void p32x_dreq0_trigger(void)
{
void p32x_dreq0_trigger(void)
{
- struct dmac *mdmac = (void *)&Pico32xMem->sh2_peri_regs[0][0x180 / 4];
- struct dmac *sdmac = (void *)&Pico32xMem->sh2_peri_regs[1][0x180 / 4];
+ struct dmac *mdmac = (void *)&msh2.peri_regs[0x180 / 4];
+ struct dmac *sdmac = (void *)&ssh2.peri_regs[0x180 / 4];
elprintf(EL_32XP, "dreq0_trigger");
if ((mdmac->dmaor & DMA_DME) && (mdmac->chan[0].chcr & 3) == DMA_DE) {
elprintf(EL_32XP, "dreq0_trigger");
if ((mdmac->dmaor & DMA_DME) && (mdmac->chan[0].chcr & 3) == DMA_DE) {
void p32x_dreq1_trigger(void)
{
void p32x_dreq1_trigger(void)
{
- struct dmac *mdmac = (void *)&Pico32xMem->sh2_peri_regs[0][0x180 / 4];
- struct dmac *sdmac = (void *)&Pico32xMem->sh2_peri_regs[1][0x180 / 4];
+ struct dmac *mdmac = (void *)&msh2.peri_regs[0x180 / 4];
+ struct dmac *sdmac = (void *)&ssh2.peri_regs[0x180 / 4];
int hit = 0;
elprintf(EL_32XP, "dreq1_trigger");
int hit = 0;
elprintf(EL_32XP, "dreq1_trigger");
i*2, r[i+0], r[i+1], r[i+2], r[i+3], r[i+4], r[i+5], r[i+6], r[i+7]); MVP;
sprintf(dstrp, " mSH2 sSH2\n"); MVP;
i*2, r[i+0], r[i+1], r[i+2], r[i+3], r[i+4], r[i+5], r[i+6], r[i+7]); MVP;
sprintf(dstrp, " mSH2 sSH2\n"); MVP;
- sprintf(dstrp, "PC,SR %08x, %03x %08x, %03x\n", sh2_pc(0), sh2_sr(0), sh2_pc(1), sh2_sr(1)); MVP;
+ sprintf(dstrp, "PC,SR %08x, %03x %08x, %03x\n", sh2_pc(&msh2), sh2_sr(0), sh2_pc(&ssh2), sh2_sr(1)); MVP;
for (i = 0; i < 16/2; i++) {
sprintf(dstrp, "R%d,%2d %08x,%08x %08x,%08x\n", i, i + 8,
sh2_reg(0,i), sh2_reg(0,i+8), sh2_reg(1,i), sh2_reg(1,i+8)); MVP;
for (i = 0; i < 16/2; i++) {
sprintf(dstrp, "R%d,%2d %08x,%08x %08x,%08x\n", i, i + 8,
sh2_reg(0,i), sh2_reg(0,i+8), sh2_reg(1,i), sh2_reg(1,i+8)); MVP;
dump_ram(Pico32xMem->dram[0], "dumps/dram0.bin");
dump_ram(Pico32xMem->dram[1], "dumps/dram1.bin");
dump_ram(Pico32xMem->pal, "dumps/pal32x.bin");
dump_ram(Pico32xMem->dram[0], "dumps/dram0.bin");
dump_ram(Pico32xMem->dram[1], "dumps/dram1.bin");
dump_ram(Pico32xMem->pal, "dumps/pal32x.bin");
- dump_ram(Pico32xMem->data_array[0], "dumps/data_array0.bin");
- dump_ram(Pico32xMem->data_array[1], "dumps/data_array1.bin");
+ dump_ram(msh2.data_array, "dumps/data_array0.bin");
+ dump_ram(ssh2.data_array, "dumps/data_array1.bin");
} \\r
} while (0)\r
# define sh2_cycles_left(sh2) (sh2)->icount\r
} \\r
} while (0)\r
# define sh2_cycles_left(sh2) (sh2)->icount\r
-# define sh2_pc(c) (c) ? ssh2.ppc : msh2.ppc\r
+# define sh2_pc(sh2) (sh2)->ppc\r
#else\r
# define sh2_end_run(sh2, after_) do { \\r
int left_ = (signed int)(sh2)->sr >> 12; \\r
#else\r
# define sh2_end_run(sh2, after_) do { \\r
int left_ = (signed int)(sh2)->sr >> 12; \\r
} \\r
} while (0)\r
# define sh2_cycles_left(sh2) ((signed int)(sh2)->sr >> 12)\r
} \\r
} while (0)\r
# define sh2_cycles_left(sh2) ((signed int)(sh2)->sr >> 12)\r
-# define sh2_pc(c) (c) ? ssh2.pc : msh2.pc\r
+# define sh2_pc(sh2) (sh2)->pc\r
#endif\r
\r
#define sh2_cycles_done(sh2) ((int)(sh2)->cycles_timeslice - sh2_cycles_left(sh2))\r
#endif\r
\r
#define sh2_cycles_done(sh2) ((int)(sh2)->cycles_timeslice - sh2_cycles_left(sh2))\r
#define SH2_DRCBLK_RAM_SHIFT 1\r
#define SH2_DRCBLK_DA_SHIFT 1\r
\r
#define SH2_DRCBLK_RAM_SHIFT 1\r
#define SH2_DRCBLK_DA_SHIFT 1\r
\r
+#define SH2_READ_SHIFT 25\r
#define SH2_WRITE_SHIFT 25\r
\r
struct Pico32x\r
#define SH2_WRITE_SHIFT 25\r
\r
struct Pico32x\r
unsigned char m68k_rom[0x100];\r
unsigned char m68k_rom_bank[0x10000]; // M68K_BANK_SIZE\r
};\r
unsigned char m68k_rom[0x100];\r
unsigned char m68k_rom_bank[0x10000]; // M68K_BANK_SIZE\r
};\r
- unsigned char data_array[2][0x1000]; // cache in SH2s (can be used as RAM)\r
#ifdef DRC_SH2\r
unsigned short drcblk_da[2][1 << (12 - SH2_DRCBLK_DA_SHIFT)];\r
#endif\r
#ifdef DRC_SH2\r
unsigned short drcblk_da[2][1 << (12 - SH2_DRCBLK_DA_SHIFT)];\r
#endif\r
unsigned char sh2_rom_s[0x400];\r
unsigned short pal[0x100];\r
unsigned short pal_native[0x100]; // converted to native (for renderer)\r
unsigned char sh2_rom_s[0x400];\r
unsigned short pal[0x100];\r
unsigned short pal_native[0x100]; // converted to native (for renderer)\r
- unsigned int sh2_peri_regs[2][0x200/4]; // periphereal regs of SH2s\r
signed short pwm[2*PWM_BUFF_LEN]; // PWM buffer for current frame\r
signed short pwm_fifo[2][4]; // [0] - current, others - fifo entries\r
};\r
signed short pwm[2*PWM_BUFF_LEN]; // PWM buffer for current frame\r
signed short pwm_fifo[2][4]; // [0] - current, others - fifo entries\r
};\r
void p32x_dreq1_trigger(void);\r
void p32x_timers_recalc(void);\r
void p32x_timers_do(unsigned int m68k_slice);\r
void p32x_dreq1_trigger(void);\r
void p32x_timers_recalc(void);\r
void p32x_timers_do(unsigned int m68k_slice);\r
-unsigned int sh2_peripheral_read8(unsigned int a, int id);\r
-unsigned int sh2_peripheral_read16(unsigned int a, int id);\r
-unsigned int sh2_peripheral_read32(unsigned int a, int id);\r
-int sh2_peripheral_write8(unsigned int a, unsigned int d, int id);\r
-int sh2_peripheral_write16(unsigned int a, unsigned int d, int id);\r
-void sh2_peripheral_write32(unsigned int a, unsigned int d, int id);\r
+unsigned int sh2_peripheral_read8(unsigned int a, SH2 *sh2);\r
+unsigned int sh2_peripheral_read16(unsigned int a, SH2 *sh2);\r
+unsigned int sh2_peripheral_read32(unsigned int a, SH2 *sh2);\r
+void sh2_peripheral_write8(unsigned int a, unsigned int d, SH2 *sh2);\r
+void sh2_peripheral_write16(unsigned int a, unsigned int d, SH2 *sh2);\r
+void sh2_peripheral_write32(unsigned int a, unsigned int d, SH2 *sh2);\r
\r
#else\r
#define Pico32xInit()\r
\r
#else\r
#define Pico32xInit()\r
\r
sh2_pack(&sh2s[0], cpubuff);\r
CHECKED_WRITE_BUFF(CHUNK_MSH2, cpubuff);\r
\r
sh2_pack(&sh2s[0], cpubuff);\r
CHECKED_WRITE_BUFF(CHUNK_MSH2, cpubuff);\r
- CHECKED_WRITE_BUFF(CHUNK_MSH2_DATA, Pico32xMem->data_array[0]);\r
- CHECKED_WRITE_BUFF(CHUNK_MSH2_PERI, Pico32xMem->sh2_peri_regs[0]);\r
+ CHECKED_WRITE_BUFF(CHUNK_MSH2_DATA, sh2s[0].data_array);\r
+ CHECKED_WRITE_BUFF(CHUNK_MSH2_PERI, sh2s[0].peri_regs);\r
\r
sh2_pack(&sh2s[1], cpubuff);\r
CHECKED_WRITE_BUFF(CHUNK_SSH2, cpubuff);\r
\r
sh2_pack(&sh2s[1], cpubuff);\r
CHECKED_WRITE_BUFF(CHUNK_SSH2, cpubuff);\r
- CHECKED_WRITE_BUFF(CHUNK_SSH2_DATA, Pico32xMem->data_array[1]);\r
- CHECKED_WRITE_BUFF(CHUNK_SSH2_PERI, Pico32xMem->sh2_peri_regs[1]);\r
+ CHECKED_WRITE_BUFF(CHUNK_SSH2_DATA, sh2s[1].data_array);\r
+ CHECKED_WRITE_BUFF(CHUNK_SSH2_PERI, sh2s[1].peri_regs);\r
\r
CHECKED_WRITE_BUFF(CHUNK_32XSYS, Pico32x);\r
CHECKED_WRITE_BUFF(CHUNK_M68K_BIOS, Pico32xMem->m68k_rom);\r
\r
CHECKED_WRITE_BUFF(CHUNK_32XSYS, Pico32x);\r
CHECKED_WRITE_BUFF(CHUNK_M68K_BIOS, Pico32xMem->m68k_rom);\r
sh2_unpack(&sh2s[1], buff_sh2);\r
break;\r
\r
sh2_unpack(&sh2s[1], buff_sh2);\r
break;\r
\r
- case CHUNK_MSH2_DATA: CHECKED_READ_BUFF(Pico32xMem->data_array[0]); break;\r
- case CHUNK_MSH2_PERI: CHECKED_READ_BUFF(Pico32xMem->sh2_peri_regs[0]); break;\r
- case CHUNK_SSH2_DATA: CHECKED_READ_BUFF(Pico32xMem->data_array[1]); break;\r
- case CHUNK_SSH2_PERI: CHECKED_READ_BUFF(Pico32xMem->sh2_peri_regs[1]); break;\r
+ case CHUNK_MSH2_DATA: CHECKED_READ_BUFF(sh2s[0].data_array); break;\r
+ case CHUNK_MSH2_PERI: CHECKED_READ_BUFF(sh2s[0].peri_regs); break;\r
+ case CHUNK_SSH2_DATA: CHECKED_READ_BUFF(sh2s[1].data_array); break;\r
+ case CHUNK_SSH2_PERI: CHECKED_READ_BUFF(sh2s[1].peri_regs); break;\r
case CHUNK_32XSYS: CHECKED_READ_BUFF(Pico32x); break;\r
case CHUNK_M68K_BIOS: CHECKED_READ_BUFF(Pico32xMem->m68k_rom); break;\r
case CHUNK_MSH2_BIOS: CHECKED_READ_BUFF(Pico32xMem->sh2_rom_m); break;\r
case CHUNK_32XSYS: CHECKED_READ_BUFF(Pico32x); break;\r
case CHUNK_M68K_BIOS: CHECKED_READ_BUFF(Pico32xMem->m68k_rom); break;\r
case CHUNK_MSH2_BIOS: CHECKED_READ_BUFF(Pico32xMem->sh2_rom_m); break;\r