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1 | // common code for Memory.c and cd/Memory.c |
2 | // (c) Copyright 2006-2007, Grazvydas "notaz" Ignotas |
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3 | |
eff55556 |
4 | #ifndef UTYPES_DEFINED |
5 | typedef unsigned char u8; |
6 | typedef unsigned short u16; |
7 | typedef unsigned int u32; |
8 | #define UTYPES_DEFINED |
9 | #endif |
10 | |
11 | #ifdef _ASM_MEMORY_C |
12 | u32 OtherRead16End(u32 a, int realsize); |
13 | #endif |
14 | #ifdef _ASM_CD_MEMORY_C |
15 | static void OtherWrite8End(u32 a,u32 d,int realsize); |
16 | #endif |
17 | |
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18 | |
19 | #ifndef _ASM_MEMORY_C |
20 | static |
21 | #endif |
22 | u8 z80Read8(u32 a) |
23 | { |
24 | if(Pico.m.z80Run&1) return 0; |
25 | |
26 | a&=0x1fff; |
27 | |
28 | if(!(PicoOpt&4)) { |
29 | // Z80 disabled, do some faking |
30 | static u8 zerosent = 0; |
31 | if(a == Pico.m.z80_lastaddr) { // probably polling something |
32 | u8 d = Pico.m.z80_fakeval; |
33 | if((d & 0xf) == 0xf && !zerosent) { |
34 | d = 0; zerosent = 1; |
35 | } else { |
36 | Pico.m.z80_fakeval++; |
37 | zerosent = 0; |
38 | } |
39 | return d; |
40 | } else { |
41 | Pico.m.z80_fakeval = 0; |
42 | } |
43 | } |
44 | |
45 | Pico.m.z80_lastaddr = (u16) a; |
46 | return Pico.zram[a]; |
47 | } |
48 | |
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49 | #ifndef _ASM_MEMORY_C |
50 | static |
51 | #endif |
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52 | u32 z80ReadBusReq(void) |
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53 | { |
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54 | u32 d=Pico.m.z80Run&1; |
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55 | if (!d && Pico.m.scanline != -1) { |
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56 | // needed by buggy Terminator (Sega CD) |
57 | int stop_before = SekCyclesDone() - z80stopCycle; |
58 | dprintf("stop before: %i", stop_before); |
59 | if (stop_before > 0 && stop_before <= 32) // Gens uses 16 here |
60 | d = 1; // bus not yet available |
61 | } |
62 | // |=0x80 for Shadow of the Beast & Super Offroad |
63 | return d|0x80; |
64 | } |
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65 | |
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66 | #ifndef _ASM_MEMORY_C |
67 | static |
68 | #endif |
69 | void z80WriteBusReq(u32 d) |
70 | { |
71 | d&=1; d^=1; |
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72 | if(Pico.m.scanline != -1) |
73 | { |
74 | if(!d) { |
75 | // this is for a nasty situation where Z80 was enabled and disabled in the same 68k timeslice (Golden Axe III) |
76 | if (Pico.m.z80Run) { |
77 | int lineCycles; |
78 | z80stopCycle = SekCyclesDone(); |
79 | if (Pico.m.z80Run&2) |
80 | lineCycles=(488-SekCyclesLeft)&0x1ff; |
81 | else lineCycles=z80stopCycle-z80startCycle; // z80 was started at current line |
82 | if (lineCycles > 0 && lineCycles <= 488) { |
83 | dprintf("zrun: %i/%i cycles", lineCycles, (lineCycles>>1)-(lineCycles>>5)); |
84 | lineCycles=(lineCycles>>1)-(lineCycles>>5); |
85 | z80_run(lineCycles); |
86 | } |
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87 | } |
f58f05d2 |
88 | } else { |
89 | z80startCycle = SekCyclesDone(); |
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90 | } |
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91 | } |
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92 | dprintf("set_zrun: %02x [%i|%i] @%06x", d, Pico.m.scanline, SekCyclesDone(), /*mz80GetRegisterValue(NULL, 0),*/ SekPc); |
93 | Pico.m.z80Run=(u8)d; |
94 | } |
95 | |
96 | #ifndef _ASM_MEMORY_C |
97 | static |
98 | #endif |
99 | u32 OtherRead16(u32 a, int realsize) |
100 | { |
101 | u32 d=0; |
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102 | |
103 | if ((a&0xffffe0)==0xa10000) { // I/O ports |
104 | a=(a>>1)&0xf; |
105 | switch(a) { |
106 | case 0: d=Pico.m.hardware; break; // Hardware value (Version register) |
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107 | case 1: d=PadRead(0); break; |
108 | case 2: d=PadRead(1); break; |
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109 | default: d=Pico.ioports[a]; break; // IO ports can be used as RAM |
110 | } |
111 | d|=d<<8; |
112 | goto end; |
113 | } |
114 | |
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115 | // rotate fakes next fetched instruction for Time Killers |
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116 | if (a==0xa11100) { // z80 busreq |
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117 | d=(z80ReadBusReq()<<8)|Pico.m.rotate++; |
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118 | dprintf("get_zrun: %04x [%i|%i] @%06x", d, Pico.m.scanline, SekCyclesDone(), SekPc); |
119 | goto end; |
120 | } |
121 | |
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122 | if ((a&0xff0000)==0xa00000) { |
123 | if ((a&0x4000)==0x0000) { d=z80Read8(a); d|=d<<8; goto end; } // Z80 ram (not byteswaped) |
124 | if ((a&0x6000)==0x4000) { // 0x4000-0x5fff, Fudge if disabled |
125 | if(PicoOpt&1) d=YM2612Read(); |
126 | else d=Pico.m.rotate++&3; |
127 | dprintf("read ym2612: %04x", d); |
128 | goto end; |
129 | } |
130 | d=0xffff; |
131 | goto end; |
132 | } |
133 | |
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134 | #ifndef _ASM_MEMORY_C |
135 | if ((a&0xe700e0)==0xc00000) { d=PicoVideoRead(a); goto end; } |
136 | #endif |
137 | |
138 | d = OtherRead16End(a, realsize); |
139 | |
140 | end: |
141 | return d; |
142 | } |
143 | |
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144 | static void IoWrite8(u32 a, u32 d) |
145 | { |
146 | a=(a>>1)&0xf; |
147 | // 6 button gamepad: if TH went from 0 to 1, gamepad changes state |
148 | if(PicoOpt&0x20) { |
149 | if(a==1) { |
150 | Pico.m.padDelay[0] = 0; |
151 | if(!(Pico.ioports[1]&0x40) && (d&0x40)) Pico.m.padTHPhase[0]++; |
152 | } |
153 | else if(a==2) { |
154 | Pico.m.padDelay[1] = 0; |
155 | if(!(Pico.ioports[2]&0x40) && (d&0x40)) Pico.m.padTHPhase[1]++; |
156 | } |
157 | } |
158 | Pico.ioports[a]=(u8)d; // IO ports can be used as RAM |
159 | } |
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160 | |
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161 | #ifndef _ASM_CD_MEMORY_C |
162 | static |
163 | #endif |
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164 | void OtherWrite8(u32 a,u32 d) |
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165 | { |
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166 | #ifndef _ASM_MEMORY_C |
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167 | if ((a&0xe700f9)==0xc00011||(a&0xff7ff9)==0xa07f11) { if(PicoOpt&2) SN76496Write(d); return; } // PSG Sound |
168 | if ((a&0xff4000)==0xa00000) { if(!(Pico.m.z80Run&1)) Pico.zram[a&0x1fff]=(u8)d; return; } // Z80 ram |
169 | if ((a&0xff6000)==0xa04000) { if(PicoOpt&1) emustatus|=YM2612Write(a&3, d); return; } // FM Sound |
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170 | if ((a&0xffffe0)==0xa10000) { IoWrite8(a, d); return; } // I/O ports |
171 | #endif |
172 | if (a==0xa11100) { z80WriteBusReq(d); return; } |
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173 | if (a==0xa11200) { |
174 | dprintf("write z80Reset: %02x", d); |
175 | if(!(d&1)) z80_reset(); |
176 | return; |
177 | } |
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178 | #ifndef _ASM_MEMORY_C |
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179 | if ((a&0xff7f00)==0xa06000) // Z80 BANK register |
180 | { |
181 | Pico.m.z80_bank68k>>=1; |
182 | Pico.m.z80_bank68k|=(d&1)<<8; |
183 | Pico.m.z80_bank68k&=0x1ff; // 9 bits and filled in the new top one |
184 | return; |
185 | } |
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186 | #endif |
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187 | if ((a&0xe700e0)==0xc00000) { |
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188 | d&=0xff; |
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189 | PicoVideoWrite(a,(u16)(d|(d<<8))); // Byte access gets mirrored |
190 | return; |
191 | } |
192 | |
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193 | OtherWrite8End(a, d, 8); |
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194 | } |
195 | |
196 | |
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197 | #ifndef _ASM_CD_MEMORY_C |
198 | static |
199 | #endif |
200 | void OtherWrite16(u32 a,u32 d) |
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201 | { |
202 | if ((a&0xe700e0)==0xc00000) { PicoVideoWrite(a,(u16)d); return; } |
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203 | if (a==0xa11100) { z80WriteBusReq(d>>8); return; } |
204 | if (a==0xa11200) { dprintf("write z80reset: %04x", d); if(!(d&0x100)) z80_reset(); return; } |
205 | if ((a&0xffffe0)==0xa10000) { IoWrite8(a, d); return; } // I/O ports |
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206 | if ((a&0xff4000)==0xa00000) { if(!(Pico.m.z80Run&1)) Pico.zram[a&0x1fff]=(u8)(d>>8); return; } // Z80 ram (MSB only) |
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207 | if ((a&0xe700f8)==0xc00010||(a&0xff7ff8)==0xa07f10) { if(PicoOpt&2) SN76496Write(d); return; } // PSG Sound |
208 | if ((a&0xff6000)==0xa04000) { if(PicoOpt&1) emustatus|=YM2612Write(a&3, d); return; } // FM Sound (??) |
209 | if ((a&0xff7f00)==0xa06000) // Z80 BANK register |
210 | { |
211 | Pico.m.z80_bank68k>>=1; |
212 | Pico.m.z80_bank68k|=(d&1)<<8; |
213 | Pico.m.z80_bank68k&=0x1ff; // 9 bits and filled in the new top one |
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214 | return; |
215 | } |
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216 | |
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217 | if (a >= SRam.start && a <= SRam.end) { |
218 | if ((a&0x16)==0x10) { // detected, not EEPROM, write not disabled |
219 | u8 *pm=(u8 *)(SRam.data-SRam.start+a); |
220 | *pm++=d>>8; |
221 | *pm++=d; |
222 | SRam.changed = 1; |
223 | } |
224 | else |
225 | SRAMWrite(a, d); // ?? |
226 | return; |
227 | } |
228 | //OtherWrite8End(a, d>>8, 16); |
229 | //OtherWrite8End(a+1,d&0xff, 16); |
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230 | } |
231 | |
232 | |