FAMEC idle loops, PSP port sync, minor adjustments
[picodrive.git] / Pico / MemoryCmn.c
CommitLineData
6cadc2da 1// common code for Memory.c and cd/Memory.c
2// (c) Copyright 2006-2007, Grazvydas "notaz" Ignotas
fa1e5e29 3
eff55556 4#ifndef UTYPES_DEFINED
5typedef unsigned char u8;
6typedef unsigned short u16;
7typedef unsigned int u32;
8#define UTYPES_DEFINED
9#endif
10
fa1e5e29 11
12#ifndef _ASM_MEMORY_C
13static
14#endif
15u8 z80Read8(u32 a)
16{
17 if(Pico.m.z80Run&1) return 0;
18
19 a&=0x1fff;
20
602133e1 21 if (!(PicoOpt&POPT_EN_Z80))
22 {
fa1e5e29 23 // Z80 disabled, do some faking
24 static u8 zerosent = 0;
25 if(a == Pico.m.z80_lastaddr) { // probably polling something
26 u8 d = Pico.m.z80_fakeval;
27 if((d & 0xf) == 0xf && !zerosent) {
28 d = 0; zerosent = 1;
29 } else {
30 Pico.m.z80_fakeval++;
31 zerosent = 0;
32 }
33 return d;
34 } else {
35 Pico.m.z80_fakeval = 0;
36 }
37 }
38
39 Pico.m.z80_lastaddr = (u16) a;
40 return Pico.zram[a];
41}
42
fa1e5e29 43#ifndef _ASM_MEMORY_C
44static
45#endif
e5503e2f 46u32 z80ReadBusReq(void)
fa1e5e29 47{
e5503e2f 48 u32 d=Pico.m.z80Run&1;
2aa27095 49 if (!d) {
e5503e2f 50 // needed by buggy Terminator (Sega CD)
51 int stop_before = SekCyclesDone() - z80stopCycle;
69996cb7 52 //elprintf(EL_BUSREQ, "get_zrun: stop before: %i", stop_before);
53 // note: if we use 20 or more here, Barkley Shut Up and Jam! will purposedly crash itself.
5f20bb80 54 // but CD Terminator needs at least 32, so it only works because next frame cycle wrap.
69996cb7 55 if (stop_before > 0 && stop_before < 20) // Gens uses 16 here
e5503e2f 56 d = 1; // bus not yet available
57 }
2aa27095 58
69996cb7 59 elprintf(EL_BUSREQ, "get_zrun: %02x [%i] @%06x", d|0x80, SekCyclesDone(), SekPc);
e5503e2f 60 return d|0x80;
61}
fa1e5e29 62
e5503e2f 63#ifndef _ASM_MEMORY_C
64static
65#endif
66void z80WriteBusReq(u32 d)
67{
68 d&=1; d^=1;
f58f05d2 69 {
b542be46 70 if (!d)
71 {
bd613473 72 if ((PicoOpt&POPT_EN_Z80) && Pico.m.z80Run)
73 {
f58f05d2 74 z80stopCycle = SekCyclesDone();
4b9c5888 75 PicoSyncZ80(z80stopCycle);
e5503e2f 76 }
f58f05d2 77 } else {
69996cb7 78 if (!Pico.m.z80Run)
4b9c5888 79 z80_cycle_cnt = cycles_68k_to_z80(SekCyclesDone());
fa1e5e29 80 }
fa1e5e29 81 }
69996cb7 82 elprintf(EL_BUSREQ, "set_zrun: %i->%i [%i] @%06x", Pico.m.z80Run, d, SekCyclesDone(), SekPc);
e5503e2f 83 Pico.m.z80Run=(u8)d;
84}
85
86#ifndef _ASM_MEMORY_C
87static
88#endif
89u32 OtherRead16(u32 a, int realsize)
90{
91 u32 d=0;
fa1e5e29 92
93 if ((a&0xffffe0)==0xa10000) { // I/O ports
94 a=(a>>1)&0xf;
95 switch(a) {
96 case 0: d=Pico.m.hardware; break; // Hardware value (Version register)
e5503e2f 97 case 1: d=PadRead(0); break;
98 case 2: d=PadRead(1); break;
fa1e5e29 99 default: d=Pico.ioports[a]; break; // IO ports can be used as RAM
100 }
101 d|=d<<8;
102 goto end;
103 }
104
f58f05d2 105 // rotate fakes next fetched instruction for Time Killers
fa1e5e29 106 if (a==0xa11100) { // z80 busreq
e5503e2f 107 d=(z80ReadBusReq()<<8)|Pico.m.rotate++;
fa1e5e29 108 goto end;
109 }
110
bd613473 111 if ((a&0xff0000)==0xa00000)
112 {
113 if (Pico.m.z80Run&1)
583ab72c 114 elprintf(EL_ANOMALY, "68k z80 read with no bus! [%06x] @ %06x", a, SekPc);
e5503e2f 115 if ((a&0x4000)==0x0000) { d=z80Read8(a); d|=d<<8; goto end; } // Z80 ram (not byteswaped)
c060a9ab 116 if ((a&0x6000)==0x4000) { d=ym2612_read_local_68k(); goto end; } // 0x4000-0x5fff
117
bd613473 118 elprintf(EL_ANOMALY, "68k bad read [%06x]", a);
e5503e2f 119 d=0xffff;
120 goto end;
121 }
122
f53f286a 123 d = PicoRead16Hook(a, realsize);
fa1e5e29 124
125end:
126 return d;
127}
128
e5503e2f 129static void IoWrite8(u32 a, u32 d)
130{
131 a=(a>>1)&0xf;
132 // 6 button gamepad: if TH went from 0 to 1, gamepad changes state
583ab72c 133 if (PicoOpt&POPT_6BTN_PAD)
602133e1 134 {
135 if (a==1) {
e5503e2f 136 Pico.m.padDelay[0] = 0;
137 if(!(Pico.ioports[1]&0x40) && (d&0x40)) Pico.m.padTHPhase[0]++;
138 }
602133e1 139 else if (a==2) {
e5503e2f 140 Pico.m.padDelay[1] = 0;
141 if(!(Pico.ioports[2]&0x40) && (d&0x40)) Pico.m.padTHPhase[1]++;
142 }
143 }
144 Pico.ioports[a]=(u8)d; // IO ports can be used as RAM
145}
fa1e5e29 146
4ff2d527 147#ifndef _ASM_CD_MEMORY_C
148static
149#endif
e5503e2f 150void OtherWrite8(u32 a,u32 d)
fa1e5e29 151{
3ec29f01 152#if !defined(_ASM_MEMORY_C) || defined(_ASM_MEMORY_C_AMIPS)
fa1e5e29 153 if ((a&0xe700f9)==0xc00011||(a&0xff7ff9)==0xa07f11) { if(PicoOpt&2) SN76496Write(d); return; } // PSG Sound
bd613473 154 if ((a&0xff4000)==0xa00000) { // z80 RAM
760e26c7 155 SekCyclesBurn(2); // hack
156 if (!(Pico.m.z80Run&1) && !Pico.m.z80_reset) Pico.zram[a&0x1fff]=(u8)d;
157 else elprintf(EL_ANOMALY, "68k z80 write with no bus or reset! [%06x] %02x @ %06x", a, d&0xff, SekPc);
bd613473 158 return;
159 }
4b9c5888 160 if ((a&0xff6000)==0xa04000) { if(PicoOpt&1) emustatus|=ym2612_write_local(a&3, d&0xff, 0)&1; return; } // FM Sound
e5503e2f 161 if ((a&0xffffe0)==0xa10000) { IoWrite8(a, d); return; } // I/O ports
162#endif
163 if (a==0xa11100) { z80WriteBusReq(d); return; }
fa1e5e29 164 if (a==0xa11200) {
5f20bb80 165 elprintf(EL_BUSREQ, "write z80Reset: %02x", d);
bd613473 166 if (!(d&0x1)) { Pico.m.z80_reset = 1; Pico.m.z80Run = 0; YM2612ResetChip(); }
167 else if (Pico.m.z80_reset) {
168 Pico.m.z80_reset = 0;
169 YM2612ResetChip();
170 z80_reset();
4b9c5888 171 timers_reset();
bd613473 172 }
fa1e5e29 173 return;
174 }
3ec29f01 175#if !defined(_ASM_MEMORY_C) || defined(_ASM_MEMORY_C_AMIPS)
fa1e5e29 176 if ((a&0xff7f00)==0xa06000) // Z80 BANK register
177 {
178 Pico.m.z80_bank68k>>=1;
179 Pico.m.z80_bank68k|=(d&1)<<8;
180 Pico.m.z80_bank68k&=0x1ff; // 9 bits and filled in the new top one
bd613473 181 elprintf(EL_Z80BNK, "z80 bank=%06x", Pico.m.z80_bank68k<<15);
fa1e5e29 182 return;
183 }
e5503e2f 184#endif
fa1e5e29 185 if ((a&0xe700e0)==0xc00000) {
f58f05d2 186 d&=0xff;
fa1e5e29 187 PicoVideoWrite(a,(u16)(d|(d<<8))); // Byte access gets mirrored
188 return;
189 }
190
4b9c5888 191 PicoWrite8Hook(a, d&0xff, 8);
fa1e5e29 192}
193
194
4ff2d527 195#ifndef _ASM_CD_MEMORY_C
196static
197#endif
198void OtherWrite16(u32 a,u32 d)
fa1e5e29 199{
e5503e2f 200 if (a==0xa11100) { z80WriteBusReq(d>>8); return; }
e5503e2f 201 if ((a&0xffffe0)==0xa10000) { IoWrite8(a, d); return; } // I/O ports
e5503e2f 202 if ((a&0xe700f8)==0xc00010||(a&0xff7ff8)==0xa07f10) { if(PicoOpt&2) SN76496Write(d); return; } // PSG Sound
4b9c5888 203 if ((a&0xff6000)==0xa04000) { if(PicoOpt&1) emustatus|=ym2612_write_local(a&3, d&0xff, 0)&1; return; } // FM Sound
bd613473 204 if ((a&0xff4000)==0xa00000) { // Z80 ram (MSB only)
760e26c7 205 if (!(Pico.m.z80Run&1) && !Pico.m.z80_reset) Pico.zram[a&0x1fff]=(u8)(d>>8);
206 else elprintf(EL_ANOMALY, "68k z80 write with no bus or reset! [%06x] %04x @ %06x", a, d&0xffff, SekPc);
bd613473 207 return;
208 }
209 if (a==0xa11200) {
210 elprintf(EL_BUSREQ, "write z80reset: %04x", d);
211 if (!(d&0x100)) { Pico.m.z80_reset = 1; Pico.m.z80Run = 0; YM2612ResetChip(); }
212 else if (Pico.m.z80_reset) {
213 Pico.m.z80_reset = 0;
214 YM2612ResetChip();
215 z80_reset();
4b9c5888 216 timers_reset();
bd613473 217 }
218 return;
219 }
e5503e2f 220 if ((a&0xff7f00)==0xa06000) // Z80 BANK register
221 {
222 Pico.m.z80_bank68k>>=1;
223 Pico.m.z80_bank68k|=(d&1)<<8;
224 Pico.m.z80_bank68k&=0x1ff; // 9 bits and filled in the new top one
bd613473 225 elprintf(EL_Z80BNK, "z80 bank=%06x", Pico.m.z80_bank68k<<15);
fa1e5e29 226 return;
227 }
fa1e5e29 228
69996cb7 229#ifndef _CD_MEMORY_C
7969166e 230 if (a >= SRam.start && a <= SRam.end) {
1dceadae 231 elprintf(EL_SRAMIO, "sram w16 [%06x] %04x @ %06x", a, d, SekPc);
9dc09829 232 if ((Pico.m.sram_reg&0x16)==0x10) { // detected, not EEPROM, write not disabled
7969166e 233 u8 *pm=(u8 *)(SRam.data-SRam.start+a);
234 *pm++=d>>8;
235 *pm++=d;
236 SRam.changed = 1;
237 }
238 else
1dceadae 239 SRAMWrite(a, d);
7969166e 240 return;
241 }
69996cb7 242#endif
f53f286a 243
4b9c5888 244 PicoWrite16Hook(a, d&0xffff, 16);
fa1e5e29 245}
246