minor adjustments for Cyclone
[picodrive.git] / Pico / MemoryCmn.c
CommitLineData
6cadc2da 1// common code for Memory.c and cd/Memory.c
2// (c) Copyright 2006-2007, Grazvydas "notaz" Ignotas
fa1e5e29 3
eff55556 4#ifndef UTYPES_DEFINED
5typedef unsigned char u8;
6typedef unsigned short u16;
7typedef unsigned int u32;
8#define UTYPES_DEFINED
9#endif
10
fa1e5e29 11
12#ifndef _ASM_MEMORY_C
13static
14#endif
15u8 z80Read8(u32 a)
16{
17 if(Pico.m.z80Run&1) return 0;
18
19 a&=0x1fff;
20
602133e1 21 if (!(PicoOpt&POPT_EN_Z80))
22 {
fa1e5e29 23 // Z80 disabled, do some faking
24 static u8 zerosent = 0;
25 if(a == Pico.m.z80_lastaddr) { // probably polling something
26 u8 d = Pico.m.z80_fakeval;
27 if((d & 0xf) == 0xf && !zerosent) {
28 d = 0; zerosent = 1;
29 } else {
30 Pico.m.z80_fakeval++;
31 zerosent = 0;
32 }
33 return d;
34 } else {
35 Pico.m.z80_fakeval = 0;
36 }
37 }
38
39 Pico.m.z80_lastaddr = (u16) a;
40 return Pico.zram[a];
41}
42
fa1e5e29 43#ifndef _ASM_MEMORY_C
44static
45#endif
e5503e2f 46u32 z80ReadBusReq(void)
fa1e5e29 47{
e5503e2f 48 u32 d=Pico.m.z80Run&1;
f58f05d2 49 if (!d && Pico.m.scanline != -1) {
e5503e2f 50 // needed by buggy Terminator (Sega CD)
51 int stop_before = SekCyclesDone() - z80stopCycle;
69996cb7 52 //elprintf(EL_BUSREQ, "get_zrun: stop before: %i", stop_before);
53 // note: if we use 20 or more here, Barkley Shut Up and Jam! will purposedly crash itself.
5f20bb80 54 // but CD Terminator needs at least 32, so it only works because next frame cycle wrap.
69996cb7 55 if (stop_before > 0 && stop_before < 20) // Gens uses 16 here
e5503e2f 56 d = 1; // bus not yet available
57 }
58 // |=0x80 for Shadow of the Beast & Super Offroad
69996cb7 59 elprintf(EL_BUSREQ, "get_zrun: %02x [%i] @%06x", d|0x80, SekCyclesDone(), SekPc);
e5503e2f 60 return d|0x80;
61}
fa1e5e29 62
e5503e2f 63#ifndef _ASM_MEMORY_C
64static
65#endif
66void z80WriteBusReq(u32 d)
67{
68 d&=1; d^=1;
f58f05d2 69 {
b542be46 70 if (!d)
71 {
f58f05d2 72 // this is for a nasty situation where Z80 was enabled and disabled in the same 68k timeslice (Golden Axe III)
73 if (Pico.m.z80Run) {
74 int lineCycles;
75 z80stopCycle = SekCyclesDone();
9a8ffeee 76 if ((Pico.m.z80Run&2) && Pico.m.scanline != -1)
f58f05d2 77 lineCycles=(488-SekCyclesLeft)&0x1ff;
78 else lineCycles=z80stopCycle-z80startCycle; // z80 was started at current line
9a8ffeee 79 if (lineCycles > 0) { // && lineCycles <= 488) {
69996cb7 80 //dprintf("zrun: %i/%i cycles", lineCycles, (lineCycles>>1)-(lineCycles>>5));
f58f05d2 81 lineCycles=(lineCycles>>1)-(lineCycles>>5);
b542be46 82 z80_run_nr(lineCycles);
f58f05d2 83 }
e5503e2f 84 }
f58f05d2 85 } else {
69996cb7 86 if (!Pico.m.z80Run)
87 z80startCycle = SekCyclesDone();
88 else
89 d|=Pico.m.z80Run;
fa1e5e29 90 }
fa1e5e29 91 }
69996cb7 92 elprintf(EL_BUSREQ, "set_zrun: %i->%i [%i] @%06x", Pico.m.z80Run, d, SekCyclesDone(), SekPc);
e5503e2f 93 Pico.m.z80Run=(u8)d;
94}
95
96#ifndef _ASM_MEMORY_C
97static
98#endif
99u32 OtherRead16(u32 a, int realsize)
100{
101 u32 d=0;
fa1e5e29 102
103 if ((a&0xffffe0)==0xa10000) { // I/O ports
104 a=(a>>1)&0xf;
105 switch(a) {
106 case 0: d=Pico.m.hardware; break; // Hardware value (Version register)
e5503e2f 107 case 1: d=PadRead(0); break;
108 case 2: d=PadRead(1); break;
fa1e5e29 109 default: d=Pico.ioports[a]; break; // IO ports can be used as RAM
110 }
111 d|=d<<8;
112 goto end;
113 }
114
f58f05d2 115 // rotate fakes next fetched instruction for Time Killers
fa1e5e29 116 if (a==0xa11100) { // z80 busreq
e5503e2f 117 d=(z80ReadBusReq()<<8)|Pico.m.rotate++;
fa1e5e29 118 goto end;
119 }
120
e5503e2f 121 if ((a&0xff0000)==0xa00000) {
122 if ((a&0x4000)==0x0000) { d=z80Read8(a); d|=d<<8; goto end; } // Z80 ram (not byteswaped)
123 if ((a&0x6000)==0x4000) { // 0x4000-0x5fff, Fudge if disabled
602133e1 124 if(PicoOpt&POPT_EN_FM) d=YM2612Read();
e5503e2f 125 else d=Pico.m.rotate++&3;
69996cb7 126 elprintf(EL_YM2612R, "read ym2612: %02x", d);
e5503e2f 127 goto end;
128 }
129 d=0xffff;
130 goto end;
131 }
132
f53f286a 133 d = PicoRead16Hook(a, realsize);
fa1e5e29 134
135end:
136 return d;
137}
138
e5503e2f 139static void IoWrite8(u32 a, u32 d)
140{
141 a=(a>>1)&0xf;
142 // 6 button gamepad: if TH went from 0 to 1, gamepad changes state
602133e1 143 if(PicoOpt&POPT_6BTN_PAD)
144 {
145 if (a==1) {
e5503e2f 146 Pico.m.padDelay[0] = 0;
147 if(!(Pico.ioports[1]&0x40) && (d&0x40)) Pico.m.padTHPhase[0]++;
148 }
602133e1 149 else if (a==2) {
e5503e2f 150 Pico.m.padDelay[1] = 0;
151 if(!(Pico.ioports[2]&0x40) && (d&0x40)) Pico.m.padTHPhase[1]++;
152 }
153 }
154 Pico.ioports[a]=(u8)d; // IO ports can be used as RAM
155}
fa1e5e29 156
4ff2d527 157#ifndef _ASM_CD_MEMORY_C
158static
159#endif
e5503e2f 160void OtherWrite8(u32 a,u32 d)
fa1e5e29 161{
3ec29f01 162#if !defined(_ASM_MEMORY_C) || defined(_ASM_MEMORY_C_AMIPS)
fa1e5e29 163 if ((a&0xe700f9)==0xc00011||(a&0xff7ff9)==0xa07f11) { if(PicoOpt&2) SN76496Write(d); return; } // PSG Sound
164 if ((a&0xff4000)==0xa00000) { if(!(Pico.m.z80Run&1)) Pico.zram[a&0x1fff]=(u8)d; return; } // Z80 ram
fa283c9a 165 if ((a&0xff6000)==0xa04000) { if(PicoOpt&1) emustatus|=YM2612Write(a&3, d)&1; return; } // FM Sound
e5503e2f 166 if ((a&0xffffe0)==0xa10000) { IoWrite8(a, d); return; } // I/O ports
167#endif
168 if (a==0xa11100) { z80WriteBusReq(d); return; }
fa1e5e29 169 if (a==0xa11200) {
5f20bb80 170 elprintf(EL_BUSREQ, "write z80Reset: %02x", d);
fa1e5e29 171 if(!(d&1)) z80_reset();
172 return;
173 }
3ec29f01 174#if !defined(_ASM_MEMORY_C) || defined(_ASM_MEMORY_C_AMIPS)
fa1e5e29 175 if ((a&0xff7f00)==0xa06000) // Z80 BANK register
176 {
177 Pico.m.z80_bank68k>>=1;
178 Pico.m.z80_bank68k|=(d&1)<<8;
179 Pico.m.z80_bank68k&=0x1ff; // 9 bits and filled in the new top one
180 return;
181 }
e5503e2f 182#endif
fa1e5e29 183 if ((a&0xe700e0)==0xc00000) {
f58f05d2 184 d&=0xff;
fa1e5e29 185 PicoVideoWrite(a,(u16)(d|(d<<8))); // Byte access gets mirrored
186 return;
187 }
188
f53f286a 189 PicoWrite8Hook(a, d, 8);
fa1e5e29 190}
191
192
4ff2d527 193#ifndef _ASM_CD_MEMORY_C
194static
195#endif
196void OtherWrite16(u32 a,u32 d)
fa1e5e29 197{
e5503e2f 198 if (a==0xa11100) { z80WriteBusReq(d>>8); return; }
ca61ee42 199 if (a==0xa11200) { elprintf(EL_BUSREQ, "write z80reset: %04x", d); if(!(d&0x100)) z80_reset(); return; }
e5503e2f 200 if ((a&0xffffe0)==0xa10000) { IoWrite8(a, d); return; } // I/O ports
fa1e5e29 201 if ((a&0xff4000)==0xa00000) { if(!(Pico.m.z80Run&1)) Pico.zram[a&0x1fff]=(u8)(d>>8); return; } // Z80 ram (MSB only)
e5503e2f 202 if ((a&0xe700f8)==0xc00010||(a&0xff7ff8)==0xa07f10) { if(PicoOpt&2) SN76496Write(d); return; } // PSG Sound
fa283c9a 203 if ((a&0xff6000)==0xa04000) { if(PicoOpt&1) emustatus|=YM2612Write(a&3, d)&1; return; } // FM Sound (??)
e5503e2f 204 if ((a&0xff7f00)==0xa06000) // Z80 BANK register
205 {
206 Pico.m.z80_bank68k>>=1;
207 Pico.m.z80_bank68k|=(d&1)<<8;
208 Pico.m.z80_bank68k&=0x1ff; // 9 bits and filled in the new top one
fa1e5e29 209 return;
210 }
fa1e5e29 211
69996cb7 212#ifndef _CD_MEMORY_C
7969166e 213 if (a >= SRam.start && a <= SRam.end) {
1dceadae 214 elprintf(EL_SRAMIO, "sram w16 [%06x] %04x @ %06x", a, d, SekPc);
9dc09829 215 if ((Pico.m.sram_reg&0x16)==0x10) { // detected, not EEPROM, write not disabled
7969166e 216 u8 *pm=(u8 *)(SRam.data-SRam.start+a);
217 *pm++=d>>8;
218 *pm++=d;
219 SRam.changed = 1;
220 }
221 else
1dceadae 222 SRAMWrite(a, d);
7969166e 223 return;
224 }
69996cb7 225#endif
f53f286a 226
f8ef8ff7 227 PicoWrite16Hook(a, d, 16);
fa1e5e29 228}
229