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bugfixes, new config system and messed code for it
[picodrive.git] / Pico / carthw / svp / compiler.c
CommitLineData
726bbb3e 1
2#include "../../PicoInt.h"
e807ac75 3#include "compiler.h"
726bbb3e 4
71bb1b7b 5#define u32 unsigned int
6
71bb1b7b 7static u32 *tcache_ptr = NULL;
726bbb3e 8
726bbb3e 9static int nblocks = 0;
71bb1b7b 10static int n_in_ops = 0;
11
12extern ssp1601_t *ssp;
13
14#define rPC ssp->gr[SSP_PC].h
15#define rPMC ssp->gr[SSP_PMC]
16
17#define SSP_FLAG_Z (1<<0xd)
18#define SSP_FLAG_N (1<<0xf)
726bbb3e 19
5d817c91 20#ifndef ARM
0b5e8296 21#define DUMP_BLOCK 0x0c9a
1ca2ea4f 22u32 *ssp_block_table[0x5090/2];
23u32 *ssp_block_table_iram[15][0x800/2];
24u32 tcache[SSP_TCACHE_SIZE/4];
45883918 25void ssp_drc_next(void){}
26void ssp_drc_next_patch(void){}
27void ssp_drc_end(void){}
5d817c91 28#endif
29
5c129565 30#include "gen_arm.c"
726bbb3e 31
32// -----------------------------------------------------
33
71bb1b7b 34static int get_inc(int mode)
892b1dd2 35{
71bb1b7b 36 int inc = (mode >> 11) & 7;
37 if (inc != 0) {
38 if (inc != 7) inc--;
39 inc = 1 << inc; // 0 1 2 4 8 16 32 128
40 if (mode & 0x8000) inc = -inc; // decrement mode
892b1dd2 41 }
71bb1b7b 42 return inc;
892b1dd2 43}
44
ee9ee9fd 45u32 ssp_pm_read(int reg)
d5276282 46{
47 u32 d = 0, mode;
48
49 if (ssp->emu_status & SSP_PMC_SET)
50 {
51 ssp->pmac_read[reg] = rPMC.v;
52 ssp->emu_status &= ~SSP_PMC_SET;
d5276282 53 return 0;
54 }
55
d5276282 56 // just in case
57 ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
58
59 mode = ssp->pmac_read[reg]>>16;
60 if ((mode & 0xfff0) == 0x0800) // ROM
61 {
62 d = ((unsigned short *)Pico.rom)[ssp->pmac_read[reg]&0xfffff];
63 ssp->pmac_read[reg] += 1;
64 }
65 else if ((mode & 0x47ff) == 0x0018) // DRAM
66 {
67 unsigned short *dram = (unsigned short *)svp->dram;
68 int inc = get_inc(mode);
69 d = dram[ssp->pmac_read[reg]&0xffff];
70 ssp->pmac_read[reg] += inc;
71 }
72
73 // PMC value corresponds to last PMR accessed
74 rPMC.v = ssp->pmac_read[reg];
75
76 return d;
77}
78
71bb1b7b 79#define overwrite_write(dst, d) \
80{ \
81 if (d & 0xf000) { dst &= ~0xf000; dst |= d & 0xf000; } \
82 if (d & 0x0f00) { dst &= ~0x0f00; dst |= d & 0x0f00; } \
83 if (d & 0x00f0) { dst &= ~0x00f0; dst |= d & 0x00f0; } \
84 if (d & 0x000f) { dst &= ~0x000f; dst |= d & 0x000f; } \
85}
86
ee9ee9fd 87void ssp_pm_write(u32 d, int reg)
d5276282 88{
89 unsigned short *dram;
90 int mode, addr;
91
92 if (ssp->emu_status & SSP_PMC_SET)
93 {
94 ssp->pmac_write[reg] = rPMC.v;
95 ssp->emu_status &= ~SSP_PMC_SET;
96 return;
97 }
98
99 // just in case
100 ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
101
102 dram = (unsigned short *)svp->dram;
103 mode = ssp->pmac_write[reg]>>16;
104 addr = ssp->pmac_write[reg]&0xffff;
105 if ((mode & 0x43ff) == 0x0018) // DRAM
106 {
107 int inc = get_inc(mode);
108 if (mode & 0x0400) {
109 overwrite_write(dram[addr], d);
110 } else dram[addr] = d;
111 ssp->pmac_write[reg] += inc;
112 }
113 else if ((mode & 0xfbff) == 0x4018) // DRAM, cell inc
114 {
115 if (mode & 0x0400) {
116 overwrite_write(dram[addr], d);
117 } else dram[addr] = d;
34e243f1 118 ssp->pmac_write[reg] += (addr&1) ? 0x1f : 1;
d5276282 119 }
120 else if ((mode & 0x47ff) == 0x001c) // IRAM
121 {
122 int inc = get_inc(mode);
123 ((unsigned short *)svp->iram_rom)[addr&0x3ff] = d;
124 ssp->pmac_write[reg] += inc;
e122fae6 125 ssp->drc.iram_dirty = 1;
d5276282 126 }
127
128 rPMC.v = ssp->pmac_write[reg];
129}
130
131
892b1dd2 132// -----------------------------------------------------
133
0b5e8296 134// 14 IRAM blocks
df143b36 135static unsigned char iram_context_map[] =
136{
137 0, 0, 0, 0, 1, 0, 0, 0, // 04
138 0, 0, 0, 0, 0, 0, 2, 0, // 0e
139 0, 0, 0, 0, 0, 3, 0, 4, // 15 17
140 5, 0, 0, 6, 0, 7, 0, 0, // 18 1b 1d
141 8, 9, 0, 0, 0,10, 0, 0, // 20 21 25
142 0, 0, 0, 0, 0, 0, 0, 0,
143 0, 0,11, 0, 0,12, 0, 0, // 32 35
144 13,14, 0, 0, 0, 0, 0, 0 // 38 39
145};
146
71bb1b7b 147int ssp_get_iram_context(void)
df143b36 148{
149 unsigned char *ir = (unsigned char *)svp->iram_rom;
150 int val1, val = ir[0x083^1] + ir[0x4FA^1] + ir[0x5F7^1] + ir[0x47B^1];
df143b36 151 val1 = iram_context_map[(val>>1)&0x3f];
152
5c129565 153 if (val1 == 0) {
df143b36 154 printf("val: %02x PC=%04x\n", (val>>1)&0x3f, rPC);
df143b36 155 //debug_dump2file(name, svp->iram_rom, 0x800);
156 exit(1);
157 }
5c129565 158// elprintf(EL_ANOMALY, "iram_context: %02i", val1);
df143b36 159 return val1;
160}
161
5d817c91 162// -----------------------------------------------------
0b5e8296 163
5d817c91 164/* regs with known values */
165static struct
166{
167 ssp_reg_t gr[8];
168 unsigned char r[8];
ede7220f 169 unsigned int pmac_read[5];
170 unsigned int pmac_write[5];
d5276282 171 ssp_reg_t pmc;
ede7220f 172 unsigned int emu_status;
bad5731d 173} known_regs;
174
175#define KRREG_X (1 << SSP_X)
176#define KRREG_Y (1 << SSP_Y)
177#define KRREG_A (1 << SSP_A) /* AH only */
178#define KRREG_ST (1 << SSP_ST)
179#define KRREG_STACK (1 << SSP_STACK)
180#define KRREG_PC (1 << SSP_PC)
181#define KRREG_P (1 << SSP_P)
182#define KRREG_PR0 (1 << 8)
183#define KRREG_PR4 (1 << 12)
184#define KRREG_AL (1 << 16)
d5276282 185#define KRREG_PMCM (1 << 18) /* only mode word of PMC */
186#define KRREG_PMC (1 << 19)
ede7220f 187#define KRREG_PM0R (1 << 20)
188#define KRREG_PM1R (1 << 21)
189#define KRREG_PM2R (1 << 22)
190#define KRREG_PM3R (1 << 23)
191#define KRREG_PM4R (1 << 24)
192#define KRREG_PM0W (1 << 25)
193#define KRREG_PM1W (1 << 26)
194#define KRREG_PM2W (1 << 27)
195#define KRREG_PM3W (1 << 28)
196#define KRREG_PM4W (1 << 29)
bad5731d 197
198/* bitfield of known register values */
199static u32 known_regb = 0;
200
201/* known vals, which need to be flushed
d5276282 202 * (only ST, P, r0-r7, PMCx, PMxR, PMxW)
bad5731d 203 * ST means flags are being held in ARM PSR
89fea1e9 204 * P means that it needs to be recalculated
bad5731d 205 */
206static u32 dirty_regb = 0;
5d817c91 207
208/* known values of host regs.
d274c33b 209 * -1 - unknown
210 * 000000-00ffff - 16bit value
211 * 100000-10ffff - base reg (r7) + 16bit val
6e39239f 212 * 0r0000 - means reg (low) eq gr[r].h, r != AL
5d817c91 213 */
214static int hostreg_r[4];
215
216static void hostreg_clear(void)
217{
218 int i;
219 for (i = 0; i < 4; i++)
220 hostreg_r[i] = -1;
221}
222
6e39239f 223static void hostreg_sspreg_changed(int sspreg)
5d817c91 224{
225 int i;
226 for (i = 0; i < 4; i++)
6e39239f 227 if (hostreg_r[i] == (sspreg<<16)) hostreg_r[i] = -1;
5d817c91 228}
229
726bbb3e 230
ede7220f 231#define PROGRAM(x) ((unsigned short *)svp->iram_rom)[x]
232#define PROGRAM_P(x) ((unsigned short *)svp->iram_rom + (x))
726bbb3e 233
ee9ee9fd 234void tr_unhandled(void)
6e39239f 235{
236 FILE *f = fopen("tcache.bin", "wb");
237 fwrite(tcache, 1, (tcache_ptr - tcache)*4, f);
238 fclose(f);
239 printf("unhandled @ %04x\n", known_regs.gr[SSP_PC].h<<1);
240 exit(1);
241}
242
0e4d7ba5 243/* update P, if needed. Trashes r0 */
d274c33b 244static void tr_flush_dirty_P(void)
245{
246 // TODO: const regs
bad5731d 247 if (!(dirty_regb & KRREG_P)) return;
d274c33b 248 EOP_MOV_REG_ASR(10, 4, 16); // mov r10, r4, asr #16
0e4d7ba5 249 EOP_MOV_REG_LSL( 0, 4, 16); // mov r0, r4, lsl #16
250 EOP_MOV_REG_ASR( 0, 0, 15); // mov r0, r0, asr #15
251 EOP_MUL(10, 0, 10); // mul r10, r0, r10
bad5731d 252 dirty_regb &= ~KRREG_P;
0e4d7ba5 253 hostreg_r[0] = -1;
d274c33b 254}
255
89fea1e9 256/* write dirty pr to host reg. Nothing is trashed */
257static void tr_flush_dirty_pr(int r)
258{
259 int ror = 0, reg;
6e39239f 260
89fea1e9 261 if (!(dirty_regb & (1 << (r+8)))) return;
262
263 switch (r&3) {
264 case 0: ror = 0; break;
265 case 1: ror = 24/2; break;
266 case 2: ror = 16/2; break;
267 }
268 reg = (r < 4) ? 8 : 9;
269 EOP_BIC_IMM(reg,reg,ror,0xff);
270 if (known_regs.r[r] != 0)
271 EOP_ORR_IMM(reg,reg,ror,known_regs.r[r]);
272 dirty_regb &= ~(1 << (r+8));
273}
274
275/* write all dirty pr0-pr7 to host regs. Nothing is trashed */
276static void tr_flush_dirty_prs(void)
5d817c91 277{
278 int i, ror = 0, reg;
bad5731d 279 int dirty = dirty_regb >> 8;
2385f273 280 if ((dirty&7) == 7) {
281 emit_mov_const(A_COND_AL, 8, known_regs.r[0]|(known_regs.r[1]<<8)|(known_regs.r[2]<<16));
282 dirty &= ~7;
283 }
284 if ((dirty&0x70) == 0x70) {
285 emit_mov_const(A_COND_AL, 9, known_regs.r[4]|(known_regs.r[5]<<8)|(known_regs.r[6]<<16));
286 dirty &= ~0x70;
287 }
5d817c91 288 /* r0-r7 */
bad5731d 289 for (i = 0; dirty && i < 8; i++, dirty >>= 1)
5d817c91 290 {
bad5731d 291 if (!(dirty&1)) continue;
5d817c91 292 switch (i&3) {
293 case 0: ror = 0; break;
294 case 1: ror = 24/2; break;
295 case 2: ror = 16/2; break;
296 }
297 reg = (i < 4) ? 8 : 9;
298 EOP_BIC_IMM(reg,reg,ror,0xff);
bad5731d 299 if (known_regs.r[i] != 0)
300 EOP_ORR_IMM(reg,reg,ror,known_regs.r[i]);
5d817c91 301 }
bad5731d 302 dirty_regb &= ~0xff00;
303}
304
89fea1e9 305/* write dirty pr and "forget" it. Nothing is trashed. */
306static void tr_release_pr(int r)
307{
308 tr_flush_dirty_pr(r);
309 known_regb &= ~(1 << (r+8));
310}
311
6e39239f 312/* fush ARM PSR to r6. Trashes r1 */
bad5731d 313static void tr_flush_dirty_ST(void)
314{
315 if (!(dirty_regb & KRREG_ST)) return;
316 EOP_BIC_IMM(6,6,0,0x0f);
6e39239f 317 EOP_MRS(1);
318 EOP_ORR_REG_LSR(6,6,1,28);
bad5731d 319 dirty_regb &= ~KRREG_ST;
6e39239f 320 hostreg_r[1] = -1;
321}
322
323/* inverse of above. Trashes r1 */
324static void tr_make_dirty_ST(void)
325{
326 if (dirty_regb & KRREG_ST) return;
327 if (known_regb & KRREG_ST) {
328 int flags = 0;
329 if (known_regs.gr[SSP_ST].h & SSP_FLAG_N) flags |= 8;
330 if (known_regs.gr[SSP_ST].h & SSP_FLAG_Z) flags |= 4;
331 EOP_MSR_IMM(4/2, flags);
332 } else {
333 EOP_MOV_REG_LSL(1, 6, 28);
334 EOP_MSR_REG(1);
335 hostreg_r[1] = -1;
336 }
337 dirty_regb |= KRREG_ST;
bad5731d 338}
339
340/* load 16bit val into host reg r0-r3. Nothing is trashed */
341static void tr_mov16(int r, int val)
342{
343 if (hostreg_r[r] != val) {
344 emit_mov_const(A_COND_AL, r, val);
345 hostreg_r[r] = val;
346 }
347}
348
349static void tr_mov16_cond(int cond, int r, int val)
350{
351 emit_mov_const(cond, r, val);
a6fb500b 352 hostreg_r[r] = -1;
5d817c91 353}
354
45883918 355/* trashes r1 */
ede7220f 356static void tr_flush_dirty_pmcrs(void)
357{
358 u32 i, val = (u32)-1;
d5276282 359 if (!(dirty_regb & 0x3ff80000)) return;
ede7220f 360
d5276282 361 if (dirty_regb & KRREG_PMC) {
362 val = known_regs.pmc.v;
e122fae6 363 emit_mov_const(A_COND_AL, 1, val);
364 EOP_STR_IMM(1,7,0x400+SSP_PMC*4);
ede7220f 365
d5276282 366 if (known_regs.emu_status & (SSP_PMC_SET|SSP_PMC_HAVE_ADDR)) {
367 printf("!! SSP_PMC_SET|SSP_PMC_HAVE_ADDR set on flush\n");
368 tr_unhandled();
369 }
ede7220f 370 }
371 for (i = 0; i < 5; i++)
372 {
d5276282 373 if (dirty_regb & (1 << (20+i))) {
ede7220f 374 if (val != known_regs.pmac_read[i]) {
375 val = known_regs.pmac_read[i];
e122fae6 376 emit_mov_const(A_COND_AL, 1, val);
ede7220f 377 }
e122fae6 378 EOP_STR_IMM(1,7,0x454+i*4); // pmac_read
ede7220f 379 }
d5276282 380 if (dirty_regb & (1 << (25+i))) {
ede7220f 381 if (val != known_regs.pmac_write[i]) {
382 val = known_regs.pmac_write[i];
e122fae6 383 emit_mov_const(A_COND_AL, 1, val);
ede7220f 384 }
e122fae6 385 EOP_STR_IMM(1,7,0x46c+i*4); // pmac_write
ede7220f 386 }
387 }
d5276282 388 dirty_regb &= ~0x3ff80000;
e122fae6 389 hostreg_r[1] = -1;
ede7220f 390}
391
0e4d7ba5 392/* read bank word to r0 (upper bits zero). Thrashes r1. */
5d817c91 393static void tr_bank_read(int addr) /* word addr 0-0x1ff */
394{
bad5731d 395 int breg = 7;
396 if (addr > 0x7f) {
397 if (hostreg_r[1] != (0x100000|((addr&0x180)<<1))) {
398 EOP_ADD_IMM(1,7,30/2,(addr&0x180)>>1); // add r1, r7, ((op&0x180)<<1)
399 hostreg_r[1] = 0x100000|((addr&0x180)<<1);
5d817c91 400 }
bad5731d 401 breg = 1;
5d817c91 402 }
bad5731d 403 EOP_LDRH_IMM(0,breg,(addr&0x7f)<<1); // ldrh r0, [r1, (op&0x7f)<<1]
5d817c91 404 hostreg_r[0] = -1;
405}
406
407/* write r0 to bank. Trashes r1. */
408static void tr_bank_write(int addr)
409{
410 int breg = 7;
411 if (addr > 0x7f) {
d274c33b 412 if (hostreg_r[1] != (0x100000|((addr&0x180)<<1))) {
5d817c91 413 EOP_ADD_IMM(1,7,30/2,(addr&0x180)>>1); // add r1, r7, ((op&0x180)<<1)
d274c33b 414 hostreg_r[1] = 0x100000|((addr&0x180)<<1);
5d817c91 415 }
416 breg = 1;
417 }
b9c1d012 418 EOP_STRH_IMM(0,breg,(addr&0x7f)<<1); // strh r0, [r1, (op&0x7f)<<1]
5d817c91 419}
420
89fea1e9 421/* handle RAM bank pointer modifiers. if need_modulo, trash r1-r3, else nothing */
422static void tr_ptrr_mod(int r, int mod, int need_modulo, int count)
5d817c91 423{
a6fb500b 424 int modulo_shift = -1; /* unknown */
5d817c91 425
426 if (mod == 0) return;
427
428 if (!need_modulo || mod == 1) // +!
429 modulo_shift = 8;
bad5731d 430 else if (need_modulo && (known_regb & KRREG_ST)) {
431 modulo_shift = known_regs.gr[SSP_ST].h & 7;
5d817c91 432 if (modulo_shift == 0) modulo_shift = 8;
433 }
434
89fea1e9 435 if (modulo_shift == -1)
436 {
a6fb500b 437 int reg = (r < 4) ? 8 : 9;
89fea1e9 438 tr_release_pr(r);
0e4d7ba5 439 if (dirty_regb & KRREG_ST) {
440 // avoid flushing ARM flags
441 EOP_AND_IMM(1, 6, 0, 0x70);
442 EOP_SUB_IMM(1, 1, 0, 0x10);
443 EOP_AND_IMM(1, 1, 0, 0x70);
444 EOP_ADD_IMM(1, 1, 0, 0x10);
445 } else {
446 EOP_C_DOP_IMM(A_COND_AL,A_OP_AND,1,6,1,0,0x70); // ands r1, r6, #0x70
447 EOP_C_DOP_IMM(A_COND_EQ,A_OP_MOV,0,0,1,0,0x80); // moveq r1, #0x80
448 }
89fea1e9 449 EOP_MOV_REG_LSR(1, 1, 4); // mov r1, r1, lsr #4
450 EOP_RSB_IMM(2, 1, 0, 8); // rsb r1, r1, #8
451 EOP_MOV_IMM(3, 8/2, count); // mov r3, #0x01000000
452 if (r&3)
453 EOP_ADD_IMM(1, 1, 0, (r&3)*8); // add r1, r1, #(r&3)*8
454 EOP_MOV_REG2_ROR(reg,reg,1); // mov reg, reg, ror r1
455 if (mod == 2)
456 EOP_SUB_REG2_LSL(reg,reg,3,2); // sub reg, reg, #0x01000000 << r2
457 else EOP_ADD_REG2_LSL(reg,reg,3,2);
458 EOP_RSB_IMM(1, 1, 0, 32); // rsb r1, r1, #32
459 EOP_MOV_REG2_ROR(reg,reg,1); // mov reg, reg, ror r1
460 hostreg_r[1] = hostreg_r[2] = hostreg_r[3] = -1;
a6fb500b 461 }
462 else if (known_regb & (1 << (r + 8)))
463 {
464 int modulo = (1 << modulo_shift) - 1;
5d817c91 465 if (mod == 2)
89fea1e9 466 known_regs.r[r] = (known_regs.r[r] & ~modulo) | ((known_regs.r[r] - count) & modulo);
467 else known_regs.r[r] = (known_regs.r[r] & ~modulo) | ((known_regs.r[r] + count) & modulo);
a6fb500b 468 }
469 else
470 {
5d817c91 471 int reg = (r < 4) ? 8 : 9;
472 int ror = ((r&3) + 1)*8 - (8 - modulo_shift);
473 EOP_MOV_REG_ROR(reg,reg,ror);
474 // {add|sub} reg, reg, #1<<shift
89fea1e9 475 EOP_C_DOP_IMM(A_COND_AL,(mod==2)?A_OP_SUB:A_OP_ADD,0,reg,reg, 8/2, count << (8 - modulo_shift));
5d817c91 476 EOP_MOV_REG_ROR(reg,reg,32-ror);
477 }
478}
479
bad5731d 480/* handle writes r0 to (rX). Trashes r1.
481 * fortunately we can ignore modulo increment modes for writes. */
0e4d7ba5 482static void tr_rX_write(int op)
bad5731d 483{
484 if ((op&3) == 3)
485 {
486 int mod = (op>>2) & 3; // direct addressing
487 tr_bank_write((op & 0x100) + mod);
488 }
489 else
490 {
491 int r = (op&3) | ((op>>6)&4);
492 if (known_regb & (1 << (r + 8))) {
493 tr_bank_write((op&0x100) | known_regs.r[r]);
494 } else {
495 int reg = (r < 4) ? 8 : 9;
496 int ror = ((4 - (r&3))*8) & 0x1f;
497 EOP_AND_IMM(1,reg,ror/2,0xff); // and r1, r{7,8}, <mask>
498 if (r >= 4)
499 EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1); // orr r1, r1, 1<<shift
500 if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1); // add r1, r7, r1, lsr #lsr
501 else EOP_ADD_REG_LSL(1,7,1,1);
502 EOP_STRH_SIMPLE(0,1); // strh r0, [r1]
503 hostreg_r[1] = -1;
504 }
89fea1e9 505 tr_ptrr_mod(r, (op>>2) & 3, 0, 1);
506 }
507}
508
509/* read (rX) to r0. Trashes r1-r3. */
510static void tr_rX_read(int r, int mod)
511{
512 if ((r&3) == 3)
513 {
514 tr_bank_read(((r << 6) & 0x100) + mod); // direct addressing
515 }
516 else
517 {
518 if (known_regb & (1 << (r + 8))) {
6e39239f 519 tr_bank_read(((r << 6) & 0x100) | known_regs.r[r]);
89fea1e9 520 } else {
521 int reg = (r < 4) ? 8 : 9;
522 int ror = ((4 - (r&3))*8) & 0x1f;
523 EOP_AND_IMM(1,reg,ror/2,0xff); // and r1, r{7,8}, <mask>
524 if (r >= 4)
525 EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1); // orr r1, r1, 1<<shift
526 if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1); // add r1, r7, r1, lsr #lsr
527 else EOP_ADD_REG_LSL(1,7,1,1);
528 EOP_LDRH_SIMPLE(0,1); // ldrh r0, [r1]
0e4d7ba5 529 hostreg_r[0] = hostreg_r[1] = -1;
89fea1e9 530 }
531 tr_ptrr_mod(r, mod, 1, 1);
bad5731d 532 }
533}
534
0e4d7ba5 535/* read ((rX)) to r0. Trashes r1,r2. */
536static void tr_rX_read2(int op)
537{
538 int r = (op&3) | ((op>>6)&4); // src
539
540 if ((r&3) == 3) {
541 tr_bank_read((op&0x100) | ((op>>2)&3));
542 } else if (known_regb & (1 << (r+8))) {
543 tr_bank_read((op&0x100) | known_regs.r[r]);
544 } else {
545 int reg = (r < 4) ? 8 : 9;
546 int ror = ((4 - (r&3))*8) & 0x1f;
547 EOP_AND_IMM(1,reg,ror/2,0xff); // and r1, r{7,8}, <mask>
548 if (r >= 4)
549 EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1); // orr r1, r1, 1<<shift
550 if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1); // add r1, r7, r1, lsr #lsr
551 else EOP_ADD_REG_LSL(1,7,1,1);
552 EOP_LDRH_SIMPLE(0,1); // ldrh r0, [r1]
553 }
554 EOP_LDR_IMM(2,7,0x48c); // ptr_iram_rom
555 EOP_ADD_REG_LSL(2,2,0,1); // add r2, r2, r0, lsl #1
556 EOP_ADD_IMM(0,0,0,1); // add r0, r0, #1
557 if ((r&3) == 3) {
558 tr_bank_write((op&0x100) | ((op>>2)&3));
559 } else if (known_regb & (1 << (r+8))) {
560 tr_bank_write((op&0x100) | known_regs.r[r]);
561 } else {
562 EOP_STRH_SIMPLE(0,1); // strh r0, [r1]
563 hostreg_r[1] = -1;
564 }
565 EOP_LDRH_SIMPLE(0,2); // ldrh r0, [r2]
566 hostreg_r[0] = hostreg_r[2] = -1;
567}
89fea1e9 568
2385f273 569// check if AL is going to be used later in block
570static int tr_predict_al_need(void)
571{
572 int tmpv, tmpv2, op, pc = known_regs.gr[SSP_PC].h;
573
574 while (1)
575 {
576 op = PROGRAM(pc);
577 switch (op >> 9)
578 {
579 // ld d, s
580 case 0x00:
581 tmpv2 = (op >> 4) & 0xf; // dst
582 tmpv = op & 0xf; // src
583 if ((tmpv2 == SSP_A && tmpv == SSP_P) || tmpv2 == SSP_AL) // ld A, P; ld AL, *
584 return 0;
585 break;
586
587 // ld (ri), s
588 case 0x02:
589 // ld ri, s
590 case 0x0a:
591 // OP a, s
592 case 0x10: case 0x30: case 0x40: case 0x60: case 0x70:
593 tmpv = op & 0xf; // src
594 if (tmpv == SSP_AL) // OP *, AL
595 return 1;
596 break;
597
598 case 0x04:
599 case 0x06:
600 case 0x14:
601 case 0x34:
602 case 0x44:
603 case 0x64:
604 case 0x74: pc++; break;
605
606 // call cond, addr
607 case 0x24:
608 // bra cond, addr
609 case 0x26:
610 // mod cond, op
611 case 0x48:
612 // mpys?
613 case 0x1b:
614 // mpya (rj), (ri), b
615 case 0x4b: return 1;
616
617 // mld (rj), (ri), b
618 case 0x5b: return 0; // cleared anyway
619
620 // and A, *
621 case 0x50:
622 tmpv = op & 0xf; // src
623 if (tmpv == SSP_AL) return 1;
624 case 0x51: case 0x53: case 0x54: case 0x55: case 0x59: case 0x5c:
625 return 0;
626 }
627 pc++;
628 }
629}
630
631
bad5731d 632/* get ARM cond which would mean that SSP cond is satisfied. No trash. */
633static int tr_cond_check(int op)
634{
6e39239f 635 int f = (op & 0x100) >> 8;
bad5731d 636 switch (op&0xf0) {
637 case 0x00: return A_COND_AL; /* always true */
638 case 0x50: /* Z matches f(?) bit */
639 if (dirty_regb & KRREG_ST) return f ? A_COND_EQ : A_COND_NE;
640 EOP_TST_IMM(6, 0, 4);
641 return f ? A_COND_NE : A_COND_EQ;
642 case 0x70: /* N matches f(?) bit */
643 if (dirty_regb & KRREG_ST) return f ? A_COND_MI : A_COND_PL;
644 EOP_TST_IMM(6, 0, 8);
645 return f ? A_COND_NE : A_COND_EQ;
646 default:
647 printf("unimplemented cond?\n");
6e39239f 648 tr_unhandled();
bad5731d 649 return 0;
650 }
651}
652
653static int tr_neg_cond(int cond)
654{
655 switch (cond) {
656 case A_COND_AL: printf("neg for AL?\n"); exit(1);
657 case A_COND_EQ: return A_COND_NE;
658 case A_COND_NE: return A_COND_EQ;
659 case A_COND_MI: return A_COND_PL;
660 case A_COND_PL: return A_COND_MI;
661 default: printf("bad cond for neg\n"); exit(1);
662 }
663 return 0;
664}
665
ede7220f 666static int tr_aop_ssp2arm(int op)
667{
668 switch (op) {
669 case 1: return A_OP_SUB;
670 case 3: return A_OP_CMP;
671 case 4: return A_OP_ADD;
672 case 5: return A_OP_AND;
673 case 6: return A_OP_ORR;
674 case 7: return A_OP_EOR;
675 }
676
677 tr_unhandled();
678 return 0;
679}
680
681// -----------------------------------------------------
682
b9c1d012 683//@ r4: XXYY
684//@ r5: A
685//@ r6: STACK and emu flags
686//@ r7: SSP context
687//@ r10: P
688
bad5731d 689// read general reg to r0. Trashes r1
d5276282 690static void tr_GR0_to_r0(int op)
d274c33b 691{
692 tr_mov16(0, 0xffff);
693}
694
d5276282 695static void tr_X_to_r0(int op)
d274c33b 696{
697 if (hostreg_r[0] != (SSP_X<<16)) {
698 EOP_MOV_REG_LSR(0, 4, 16); // mov r0, r4, lsr #16
699 hostreg_r[0] = SSP_X<<16;
700 }
701}
702
d5276282 703static void tr_Y_to_r0(int op)
d274c33b 704{
d274c33b 705 if (hostreg_r[0] != (SSP_Y<<16)) {
706 EOP_MOV_REG_SIMPLE(0, 4); // mov r0, r4
707 hostreg_r[0] = SSP_Y<<16;
708 }
709}
710
d5276282 711static void tr_A_to_r0(int op)
d274c33b 712{
713 if (hostreg_r[0] != (SSP_A<<16)) {
714 EOP_MOV_REG_LSR(0, 5, 16); // mov r0, r5, lsr #16 @ AH
715 hostreg_r[0] = SSP_A<<16;
716 }
717}
718
d5276282 719static void tr_ST_to_r0(int op)
d274c33b 720{
721 // VR doesn't need much accuracy here..
722 EOP_MOV_REG_LSR(0, 6, 4); // mov r0, r6, lsr #4
723 EOP_AND_IMM(0, 0, 0, 0x67); // and r0, r0, #0x67
724 hostreg_r[0] = -1;
725}
726
d5276282 727static void tr_STACK_to_r0(int op)
d274c33b 728{
729 // 448
730 EOP_SUB_IMM(6, 6, 8/2, 0x20); // sub r6, r6, #1<<29
731 EOP_ADD_IMM(1, 7, 24/2, 0x04); // add r1, r7, 0x400
732 EOP_ADD_IMM(1, 1, 0, 0x48); // add r1, r1, 0x048
733 EOP_ADD_REG_LSR(1, 1, 6, 28); // add r1, r1, r6, lsr #28
734 EOP_LDRH_SIMPLE(0, 1); // ldrh r0, [r1]
735 hostreg_r[0] = hostreg_r[1] = -1;
736}
737
d5276282 738static void tr_PC_to_r0(int op)
d274c33b 739{
bad5731d 740 tr_mov16(0, known_regs.gr[SSP_PC].h);
d274c33b 741}
742
d5276282 743static void tr_P_to_r0(int op)
d274c33b 744{
745 tr_flush_dirty_P();
746 EOP_MOV_REG_LSR(0, 10, 16); // mov r0, r10, lsr #16
747 hostreg_r[0] = -1;
748}
d5276282 749
750static void tr_AL_to_r0(int op)
ede7220f 751{
d5276282 752 if (op == 0x000f) {
753 if (known_regb & KRREG_PMC) {
754 known_regs.emu_status &= ~(SSP_PMC_SET|SSP_PMC_HAVE_ADDR);
755 } else {
756 EOP_LDR_IMM(0,7,0x484); // ldr r1, [r7, #0x484] // emu_status
757 EOP_BIC_IMM(0,0,0,SSP_PMC_SET|SSP_PMC_HAVE_ADDR);
758 EOP_STR_IMM(0,7,0x484);
759 }
760 }
761
762 if (hostreg_r[0] != (SSP_AL<<16)) {
763 EOP_MOV_REG_SIMPLE(0, 5); // mov r0, r5
764 hostreg_r[0] = SSP_AL<<16;
765 }
ede7220f 766}
ede7220f 767
d5276282 768static void tr_PMX_to_r0(int reg)
ede7220f 769{
ede7220f 770 if ((known_regb & KRREG_PMC) && (known_regs.emu_status & SSP_PMC_SET))
771 {
d5276282 772 known_regs.pmac_read[reg] = known_regs.pmc.v;
ede7220f 773 known_regs.emu_status &= ~SSP_PMC_SET;
0336d643 774 known_regb |= 1 << (20+reg);
d5276282 775 dirty_regb |= 1 << (20+reg);
776 return;
ede7220f 777 }
778
d5276282 779 if ((known_regb & KRREG_PMC) && (known_regb & (1 << (20+reg))))
ede7220f 780 {
d5276282 781 u32 pmcv = known_regs.pmac_read[reg];
782 int mode = pmcv>>16;
783 known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR;
784
ede7220f 785 if ((mode & 0xfff0) == 0x0800)
786 {
ede7220f 787 EOP_LDR_IMM(1,7,0x488); // rom_ptr
788 emit_mov_const(A_COND_AL, 0, (pmcv&0xfffff)<<1);
789 EOP_LDRH_REG(0,1,0); // ldrh r0, [r1, r0]
d5276282 790 known_regs.pmac_read[reg] += 1;
ede7220f 791 }
792 else if ((mode & 0x47ff) == 0x0018) // DRAM
793 {
794 int inc = get_inc(mode);
ede7220f 795 EOP_LDR_IMM(1,7,0x490); // dram_ptr
796 emit_mov_const(A_COND_AL, 0, (pmcv&0xffff)<<1);
797 EOP_LDRH_REG(0,1,0); // ldrh r0, [r1, r0]
d5276282 798 if (reg == 4 && (pmcv == 0x187f03 || pmcv == 0x187f04)) // wait loop detection
ede7220f 799 {
800 int flag = (pmcv == 0x187f03) ? SSP_WAIT_30FE06 : SSP_WAIT_30FE08;
801 tr_flush_dirty_ST();
802 EOP_LDR_IMM(1,7,0x484); // ldr r1, [r7, #0x484] // emu_status
803 EOP_TST_REG_SIMPLE(0,0);
71bb1b7b 804 EOP_C_DOP_IMM(A_COND_EQ,A_OP_SUB,0,11,11,22/2,1); // subeq r11, r11, #1024
d5276282 805 EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1,24/2,flag>>8); // orreq r1, r1, #SSP_WAIT_30FE08
ede7220f 806 EOP_STR_IMM(1,7,0x484); // str r1, [r7, #0x484] // emu_status
807 }
d5276282 808 known_regs.pmac_read[reg] += inc;
ede7220f 809 }
810 else
811 {
812 tr_unhandled();
813 }
d5276282 814 known_regs.pmc.v = known_regs.pmac_read[reg];
815 //known_regb |= KRREG_PMC;
816 dirty_regb |= KRREG_PMC;
817 dirty_regb |= 1 << (20+reg);
818 hostreg_r[0] = hostreg_r[1] = -1;
819 return;
820 }
ede7220f 821
d5276282 822 known_regb &= ~KRREG_PMC;
823 dirty_regb &= ~KRREG_PMC;
824 known_regb &= ~(1 << (20+reg));
825 dirty_regb &= ~(1 << (20+reg));
826
827 // call the C code to handle this
828 tr_flush_dirty_ST();
829 //tr_flush_dirty_pmcrs();
830 tr_mov16(0, reg);
45883918 831 emit_call(A_COND_AL, ssp_pm_read);
d5276282 832 hostreg_clear();
833}
834
835static void tr_PM0_to_r0(int op)
836{
837 tr_PMX_to_r0(0);
838}
839
840static void tr_PM1_to_r0(int op)
841{
842 tr_PMX_to_r0(1);
843}
844
845static void tr_PM2_to_r0(int op)
846{
847 tr_PMX_to_r0(2);
848}
849
850static void tr_XST_to_r0(int op)
851{
852 EOP_ADD_IMM(0, 7, 24/2, 4); // add r0, r7, #0x400
853 EOP_LDRH_IMM(0, 0, SSP_XST*4+2);
854}
855
856static void tr_PM4_to_r0(int op)
857{
858 tr_PMX_to_r0(4);
859}
860
861static void tr_PMC_to_r0(int op)
862{
863 if (known_regb & KRREG_PMC)
864 {
865 if (known_regs.emu_status & SSP_PMC_HAVE_ADDR) {
866 known_regs.emu_status |= SSP_PMC_SET;
867 known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR;
868 // do nothing - this is handled elsewhere
869 } else {
870 tr_mov16(0, known_regs.pmc.l);
871 known_regs.emu_status |= SSP_PMC_HAVE_ADDR;
872 }
873 }
874 else
875 {
876 EOP_LDR_IMM(1,7,0x484); // ldr r1, [r7, #0x484] // emu_status
877 tr_flush_dirty_ST();
878 if (op != 0x000e)
879 EOP_LDR_IMM(0, 7, 0x400+SSP_PMC*4);
880 EOP_TST_IMM(1, 0, SSP_PMC_HAVE_ADDR);
881 EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // orreq r1, r1, #..
882 EOP_C_DOP_IMM(A_COND_NE,A_OP_BIC,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // bicne r1, r1, #..
883 EOP_C_DOP_IMM(A_COND_NE,A_OP_ORR,0, 1, 1, 0, SSP_PMC_SET); // orrne r1, r1, #..
884 EOP_STR_IMM(1,7,0x484);
885 hostreg_r[0] = hostreg_r[1] = -1;
ede7220f 886 }
ede7220f 887}
888
d274c33b 889
d5276282 890typedef void (tr_read_func)(int op);
d274c33b 891
d5276282 892static tr_read_func *tr_read_funcs[16] =
d274c33b 893{
894 tr_GR0_to_r0,
895 tr_X_to_r0,
896 tr_Y_to_r0,
897 tr_A_to_r0,
898 tr_ST_to_r0,
899 tr_STACK_to_r0,
900 tr_PC_to_r0,
d5276282 901 tr_P_to_r0,
902 tr_PM0_to_r0,
903 tr_PM1_to_r0,
904 tr_PM2_to_r0,
905 tr_XST_to_r0,
906 tr_PM4_to_r0,
907 (tr_read_func *)tr_unhandled,
908 tr_PMC_to_r0,
909 tr_AL_to_r0
d274c33b 910};
911
912
b9c1d012 913// write r0 to general reg handlers. Trashes r1
6e39239f 914#define TR_WRITE_R0_TO_REG(reg) \
915{ \
916 hostreg_sspreg_changed(reg); \
917 hostreg_r[0] = (reg)<<16; \
918 if (const_val != -1) { \
919 known_regs.gr[reg].h = const_val; \
920 known_regb |= 1 << (reg); \
921 } else { \
922 known_regb &= ~(1 << (reg)); \
923 } \
b9c1d012 924}
925
6e39239f 926static void tr_r0_to_GR0(int const_val)
b9c1d012 927{
928 // do nothing
929}
930
6e39239f 931static void tr_r0_to_X(int const_val)
b9c1d012 932{
933 EOP_MOV_REG_LSL(4, 4, 16); // mov r4, r4, lsl #16
934 EOP_MOV_REG_LSR(4, 4, 16); // mov r4, r4, lsr #16
935 EOP_ORR_REG_LSL(4, 4, 0, 16); // orr r4, r4, r0, lsl #16
6e39239f 936 dirty_regb |= KRREG_P; // touching X or Y makes P dirty.
937 TR_WRITE_R0_TO_REG(SSP_X);
b9c1d012 938}
939
6e39239f 940static void tr_r0_to_Y(int const_val)
b9c1d012 941{
942 EOP_MOV_REG_LSR(4, 4, 16); // mov r4, r4, lsr #16
943 EOP_ORR_REG_LSL(4, 4, 0, 16); // orr r4, r4, r0, lsl #16
944 EOP_MOV_REG_ROR(4, 4, 16); // mov r4, r4, ror #16
bad5731d 945 dirty_regb |= KRREG_P;
6e39239f 946 TR_WRITE_R0_TO_REG(SSP_Y);
b9c1d012 947}
948
6e39239f 949static void tr_r0_to_A(int const_val)
b9c1d012 950{
2385f273 951 if (tr_predict_al_need()) {
952 EOP_MOV_REG_LSL(5, 5, 16); // mov r5, r5, lsl #16
953 EOP_MOV_REG_LSR(5, 5, 16); // mov r5, r5, lsr #16 @ AL
954 EOP_ORR_REG_LSL(5, 5, 0, 16); // orr r5, r5, r0, lsl #16
955 }
956 else
957 EOP_MOV_REG_LSL(5, 0, 16);
6e39239f 958 TR_WRITE_R0_TO_REG(SSP_A);
b9c1d012 959}
960
6e39239f 961static void tr_r0_to_ST(int const_val)
b9c1d012 962{
963 // VR doesn't need much accuracy here..
964 EOP_AND_IMM(1, 0, 0, 0x67); // and r1, r0, #0x67
965 EOP_AND_IMM(6, 6, 8/2, 0xe0); // and r6, r6, #7<<29 @ preserve STACK
966 EOP_ORR_REG_LSL(6, 6, 1, 4); // orr r6, r6, r1, lsl #4
6e39239f 967 TR_WRITE_R0_TO_REG(SSP_ST);
b9c1d012 968 hostreg_r[1] = -1;
6e39239f 969 dirty_regb &= ~KRREG_ST;
b9c1d012 970}
971
6e39239f 972static void tr_r0_to_STACK(int const_val)
b9c1d012 973{
974 // 448
975 EOP_ADD_IMM(1, 7, 24/2, 0x04); // add r1, r7, 0x400
976 EOP_ADD_IMM(1, 1, 0, 0x48); // add r1, r1, 0x048
d274c33b 977 EOP_ADD_REG_LSR(1, 1, 6, 28); // add r1, r1, r6, lsr #28
b9c1d012 978 EOP_STRH_SIMPLE(0, 1); // strh r0, [r1]
d274c33b 979 EOP_ADD_IMM(6, 6, 8/2, 0x20); // add r6, r6, #1<<29
b9c1d012 980 hostreg_r[1] = -1;
981}
982
6e39239f 983static void tr_r0_to_PC(int const_val)
b9c1d012 984{
45883918 985/*
986 * do nothing - dispatcher will take care of this
b9c1d012 987 EOP_MOV_REG_LSL(1, 0, 16); // mov r1, r0, lsl #16
d274c33b 988 EOP_STR_IMM(1,7,0x400+6*4); // str r1, [r7, #(0x400+6*8)]
b9c1d012 989 hostreg_r[1] = -1;
45883918 990*/
b9c1d012 991}
992
d5276282 993static void tr_r0_to_AL(int const_val)
994{
995 EOP_MOV_REG_LSR(5, 5, 16); // mov r5, r5, lsr #16
996 EOP_ORR_REG_LSL(5, 5, 0, 16); // orr r5, r5, r0, lsl #16
997 EOP_MOV_REG_ROR(5, 5, 16); // mov r5, r5, ror #16
998 hostreg_sspreg_changed(SSP_AL);
999 if (const_val != -1) {
1000 known_regs.gr[SSP_A].l = const_val;
1001 known_regb |= 1 << SSP_AL;
1002 } else
1003 known_regb &= ~(1 << SSP_AL);
1004}
1005
1006static void tr_r0_to_PMX(int reg)
1007{
d5276282 1008 if ((known_regb & KRREG_PMC) && (known_regs.emu_status & SSP_PMC_SET))
1009 {
1010 known_regs.pmac_write[reg] = known_regs.pmc.v;
1011 known_regs.emu_status &= ~SSP_PMC_SET;
1012 known_regb |= 1 << (25+reg);
1013 dirty_regb |= 1 << (25+reg);
1014 return;
1015 }
0b5e8296 1016
d5276282 1017 if ((known_regb & KRREG_PMC) && (known_regb & (1 << (25+reg))))
1018 {
1019 int mode, addr;
1020
1021 known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR;
1022
1023 mode = known_regs.pmac_write[reg]>>16;
1024 addr = known_regs.pmac_write[reg]&0xffff;
1025 if ((mode & 0x43ff) == 0x0018) // DRAM
1026 {
1027 int inc = get_inc(mode);
1028 if (mode & 0x0400) tr_unhandled();
1029 EOP_LDR_IMM(1,7,0x490); // dram_ptr
1030 emit_mov_const(A_COND_AL, 2, addr<<1);
1031 EOP_STRH_REG(0,1,2); // strh r0, [r1, r2]
1032 known_regs.pmac_write[reg] += inc;
1033 }
1034 else if ((mode & 0xfbff) == 0x4018) // DRAM, cell inc
1035 {
1036 if (mode & 0x0400) tr_unhandled();
1037 EOP_LDR_IMM(1,7,0x490); // dram_ptr
1038 emit_mov_const(A_COND_AL, 2, addr<<1);
1039 EOP_STRH_REG(0,1,2); // strh r0, [r1, r2]
1040 known_regs.pmac_write[reg] += (addr&1) ? 31 : 1;
1041 }
1042 else if ((mode & 0x47ff) == 0x001c) // IRAM
1043 {
1044 int inc = get_inc(mode);
1045 EOP_LDR_IMM(1,7,0x48c); // iram_ptr
1046 emit_mov_const(A_COND_AL, 2, (addr&0x3ff)<<1);
1047 EOP_STRH_REG(0,1,2); // strh r0, [r1, r2]
e122fae6 1048 EOP_MOV_IMM(1,0,1);
1049 EOP_STR_IMM(1,7,0x494); // iram_dirty
d5276282 1050 known_regs.pmac_write[reg] += inc;
1051 }
1052 else
1053 tr_unhandled();
1054
1055 known_regs.pmc.v = known_regs.pmac_write[reg];
1056 //known_regb |= KRREG_PMC;
1057 dirty_regb |= KRREG_PMC;
1058 dirty_regb |= 1 << (25+reg);
1059 hostreg_r[1] = hostreg_r[2] = -1;
e122fae6 1060 return;
d5276282 1061 }
1062
1063 known_regb &= ~KRREG_PMC;
1064 dirty_regb &= ~KRREG_PMC;
1065 known_regb &= ~(1 << (25+reg));
1066 dirty_regb &= ~(1 << (25+reg));
d5276282 1067
1068 // call the C code to handle this
1069 tr_flush_dirty_ST();
1070 //tr_flush_dirty_pmcrs();
1071 tr_mov16(1, reg);
45883918 1072 emit_call(A_COND_AL, ssp_pm_write);
d5276282 1073 hostreg_clear();
1074}
1075
1076static void tr_r0_to_PM0(int const_val)
1077{
1078 tr_r0_to_PMX(0);
1079}
1080
1081static void tr_r0_to_PM1(int const_val)
1082{
1083 tr_r0_to_PMX(1);
1084}
1085
1086static void tr_r0_to_PM2(int const_val)
1087{
1088 tr_r0_to_PMX(2);
1089}
1090
1091static void tr_r0_to_PM4(int const_val)
1092{
1093 tr_r0_to_PMX(4);
1094}
1095
1096static void tr_r0_to_PMC(int const_val)
1097{
1098 if ((known_regb & KRREG_PMC) && const_val != -1)
1099 {
1100 if (known_regs.emu_status & SSP_PMC_HAVE_ADDR) {
1101 known_regs.emu_status |= SSP_PMC_SET;
1102 known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR;
1103 known_regs.pmc.h = const_val;
1104 } else {
1105 known_regs.emu_status |= SSP_PMC_HAVE_ADDR;
1106 known_regs.pmc.l = const_val;
1107 }
1108 }
1109 else
1110 {
1111 tr_flush_dirty_ST();
1112 if (known_regb & KRREG_PMC) {
1113 emit_mov_const(A_COND_AL, 1, known_regs.pmc.v);
1114 EOP_STR_IMM(1,7,0x400+SSP_PMC*4);
1115 known_regb &= ~KRREG_PMC;
1116 dirty_regb &= ~KRREG_PMC;
1117 }
1118 EOP_LDR_IMM(1,7,0x484); // ldr r1, [r7, #0x484] // emu_status
1119 EOP_ADD_IMM(2,7,24/2,4); // add r2, r7, #0x400
1120 EOP_TST_IMM(1, 0, SSP_PMC_HAVE_ADDR);
1121 EOP_C_AM3_IMM(A_COND_EQ,1,0,2,0,0,1,SSP_PMC*4); // strxx r0, [r2, #SSP_PMC]
1122 EOP_C_AM3_IMM(A_COND_NE,1,0,2,0,0,1,SSP_PMC*4+2);
1123 EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // orreq r1, r1, #..
1124 EOP_C_DOP_IMM(A_COND_NE,A_OP_BIC,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // bicne r1, r1, #..
1125 EOP_C_DOP_IMM(A_COND_NE,A_OP_ORR,0, 1, 1, 0, SSP_PMC_SET); // orrne r1, r1, #..
1126 EOP_STR_IMM(1,7,0x484);
1127 hostreg_r[1] = hostreg_r[2] = -1;
1128 }
1129}
1130
6e39239f 1131typedef void (tr_write_func)(int const_val);
b9c1d012 1132
d5276282 1133static tr_write_func *tr_write_funcs[16] =
b9c1d012 1134{
1135 tr_r0_to_GR0,
1136 tr_r0_to_X,
1137 tr_r0_to_Y,
1138 tr_r0_to_A,
1139 tr_r0_to_ST,
1140 tr_r0_to_STACK,
1141 tr_r0_to_PC,
d5276282 1142 (tr_write_func *)tr_unhandled,
1143 tr_r0_to_PM0,
1144 tr_r0_to_PM1,
1145 tr_r0_to_PM2,
1146 (tr_write_func *)tr_unhandled,
1147 tr_r0_to_PM4,
1148 (tr_write_func *)tr_unhandled,
1149 tr_r0_to_PMC,
1150 tr_r0_to_AL
b9c1d012 1151};
1152
0e4d7ba5 1153static void tr_mac_load_XY(int op)
1154{
1155 tr_rX_read(op&3, (op>>2)&3); // X
1156 EOP_MOV_REG_LSL(4, 0, 16);
1157 tr_rX_read(((op>>4)&3)|4, (op>>6)&3); // Y
1158 EOP_ORR_REG_SIMPLE(4, 0);
1159 dirty_regb |= KRREG_P;
1160 hostreg_sspreg_changed(SSP_X);
1161 hostreg_sspreg_changed(SSP_Y);
1162 known_regb &= ~KRREG_X;
1163 known_regb &= ~KRREG_Y;
1164}
1165
ede7220f 1166// -----------------------------------------------------
1167
ede7220f 1168static int tr_detect_set_pm(unsigned int op, int *pc, int imm)
0e4d7ba5 1169{
ede7220f 1170 u32 pmcv, tmpv;
1171 if (!((op&0xfef0) == 0x08e0 && (PROGRAM(*pc)&0xfef0) == 0x08e0)) return 0;
1172
1173 // programming PMC:
1174 // ldi PMC, imm1
1175 // ldi PMC, imm2
1176 (*pc)++;
1177 pmcv = imm | (PROGRAM((*pc)++) << 16);
d5276282 1178 known_regs.pmc.v = pmcv;
ede7220f 1179 known_regb |= KRREG_PMC;
d5276282 1180 dirty_regb |= KRREG_PMC;
ede7220f 1181 known_regs.emu_status |= SSP_PMC_SET;
71bb1b7b 1182 n_in_ops++;
ede7220f 1183
1184 // check for possible reg programming
1185 tmpv = PROGRAM(*pc);
1186 if ((tmpv & 0xfff8) == 0x08 || (tmpv & 0xff8f) == 0x80)
1187 {
1188 int is_write = (tmpv & 0xff8f) == 0x80;
1189 int reg = is_write ? ((tmpv>>4)&0x7) : (tmpv&0x7);
1190 if (reg > 4) tr_unhandled();
d5276282 1191 if ((tmpv & 0x0f) != 0 && (tmpv & 0xf0) != 0) tr_unhandled();
ede7220f 1192 known_regs.pmac_read[is_write ? reg + 5 : reg] = pmcv;
1193 known_regb |= is_write ? (1 << (reg+25)) : (1 << (reg+20));
d5276282 1194 dirty_regb |= is_write ? (1 << (reg+25)) : (1 << (reg+20));
ede7220f 1195 known_regs.emu_status &= ~SSP_PMC_SET;
1196 (*pc)++;
71bb1b7b 1197 n_in_ops++;
ede7220f 1198 return 5;
0e4d7ba5 1199 }
1200
d5276282 1201 tr_unhandled();
ede7220f 1202 return 4;
1203}
1204
1205static const short pm0_block_seq[] = { 0x0880, 0, 0x0880, 0, 0x0840, 0x60 };
1206
1207static int tr_detect_pm0_block(unsigned int op, int *pc, int imm)
1208{
1209 // ldi ST, 0
1210 // ldi PM0, 0
1211 // ldi PM0, 0
1212 // ldi ST, 60h
1213 unsigned short *pp;
1214 if (op != 0x0840 || imm != 0) return 0;
1215 pp = PROGRAM_P(*pc);
1216 if (memcmp(pp, pm0_block_seq, sizeof(pm0_block_seq)) != 0) return 0;
1217
1218 EOP_AND_IMM(6, 6, 8/2, 0xe0); // and r6, r6, #7<<29 @ preserve STACK
1219 EOP_ORR_IMM(6, 6, 24/2, 6); // orr r6, r6, 0x600
1220 hostreg_sspreg_changed(SSP_ST);
1221 known_regs.gr[SSP_ST].h = 0x60;
1222 known_regb |= 1 << SSP_ST;
1223 dirty_regb &= ~KRREG_ST;
1224 (*pc) += 3*2;
71bb1b7b 1225 n_in_ops += 3;
ede7220f 1226 return 4*2;
0e4d7ba5 1227}
5d817c91 1228
d5276282 1229static int tr_detect_rotate(unsigned int op, int *pc, int imm)
1230{
1231 // @ 3DA2 and 426A
1232 // ld PMC, (r3|00)
1233 // ld (r3|00), PMC
1234 // ld -, AL
1235 if (op != 0x02e3 || PROGRAM(*pc) != 0x04e3 || PROGRAM(*pc + 1) != 0x000f) return 0;
1236
1237 tr_bank_read(0);
1238 EOP_MOV_REG_LSL(0, 0, 4);
1239 EOP_ORR_REG_LSR(0, 0, 0, 16);
1240 tr_bank_write(0);
1241 (*pc) += 2;
71bb1b7b 1242 n_in_ops += 2;
d5276282 1243 return 3;
1244}
1245
ede7220f 1246// -----------------------------------------------------
1247
45883918 1248static int translate_op(unsigned int op, int *pc, int imm, int *end_cond, int *jump_pc)
5d817c91 1249{
0e4d7ba5 1250 u32 tmpv, tmpv2, tmpv3;
5d817c91 1251 int ret = 0;
bad5731d 1252 known_regs.gr[SSP_PC].h = *pc;
5d817c91 1253
e807ac75 1254 switch (op >> 9)
1255 {
1256 // ld d, s
f48f5e3b 1257 case 0x00:
5d817c91 1258 if (op == 0) { ret++; break; } // nop
d274c33b 1259 tmpv = op & 0xf; // src
1260 tmpv2 = (op >> 4) & 0xf; // dst
d274c33b 1261 if (tmpv2 == SSP_A && tmpv == SSP_P) { // ld A, P
1262 tr_flush_dirty_P();
1263 EOP_MOV_REG_SIMPLE(5, 10);
d5276282 1264 hostreg_sspreg_changed(SSP_A);
bad5731d 1265 known_regb &= ~(KRREG_A|KRREG_AL);
d274c33b 1266 ret++; break;
1267 }
d5276282 1268 tr_read_funcs[tmpv](op);
6e39239f 1269 tr_write_funcs[tmpv2]((known_regb & (1 << tmpv)) ? known_regs.gr[tmpv].h : -1);
45883918 1270 if (tmpv2 == SSP_PC) {
1271 ret |= 0x10000;
1272 *end_cond = -A_COND_AL;
1273 }
bad5731d 1274 ret++; break;
1275
1276 // ld d, (ri)
89fea1e9 1277 case 0x01: {
89fea1e9 1278 int r = (op&3) | ((op>>6)&4);
1279 int mod = (op>>2)&3;
1280 tmpv = (op >> 4) & 0xf; // dst
d5276282 1281 ret = tr_detect_rotate(op, pc, imm);
1282 if (ret > 0) break;
89fea1e9 1283 if (tmpv != 0)
2385f273 1284 tr_rX_read(r, mod);
1285 else {
1286 int cnt = 1;
1287 while (PROGRAM(*pc) == op) {
1288 (*pc)++; cnt++; ret++;
1289 n_in_ops++;
1290 }
1291 tr_ptrr_mod(r, mod, 1, cnt); // skip
1292 }
6e39239f 1293 tr_write_funcs[tmpv](-1);
45883918 1294 if (tmpv == SSP_PC) {
1295 ret |= 0x10000;
1296 *end_cond = -A_COND_AL;
1297 }
89fea1e9 1298 ret++; break;
1299 }
bad5731d 1300
1301 // ld (ri), s
1302 case 0x02:
1303 tmpv = (op >> 4) & 0xf; // src
d5276282 1304 tr_read_funcs[tmpv](op);
0e4d7ba5 1305 tr_rX_write(op);
d274c33b 1306 ret++; break;
f48f5e3b 1307
1308 // ld a, adr
1309 case 0x03:
5d817c91 1310 tr_bank_read(op&0x1ff);
6e39239f 1311 tr_r0_to_A(-1);
5d817c91 1312 ret++; break;
1313
b9c1d012 1314 // ldi d, imm
1315 case 0x04:
ede7220f 1316 tmpv = (op & 0xf0) >> 4; // dst
1317 ret = tr_detect_pm0_block(op, pc, imm);
1318 if (ret > 0) break;
ede7220f 1319 ret = tr_detect_set_pm(op, pc, imm);
1320 if (ret > 0) break;
0b5e8296 1321 tr_mov16(0, imm);
1322 tr_write_funcs[tmpv](imm);
45883918 1323 if (tmpv == SSP_PC) {
1324 ret |= 0x10000;
1325 *jump_pc = imm;
1326 }
0b5e8296 1327 ret += 2; break;
b9c1d012 1328
bad5731d 1329 // ld d, ((ri))
0e4d7ba5 1330 case 0x05:
bad5731d 1331 tmpv2 = (op >> 4) & 0xf; // dst
0e4d7ba5 1332 tr_rX_read2(op);
6e39239f 1333 tr_write_funcs[tmpv2](-1);
45883918 1334 if (tmpv2 == SSP_PC) {
1335 ret |= 0x10000;
1336 *end_cond = -A_COND_AL;
1337 }
0e4d7ba5 1338 ret += 3; break;
b9c1d012 1339
5d817c91 1340 // ldi (ri), imm
1341 case 0x06:
5d817c91 1342 tr_mov16(0, imm);
0e4d7ba5 1343 tr_rX_write(op);
a6fb500b 1344 ret += 2; break;
f48f5e3b 1345
1346 // ld adr, a
1347 case 0x07:
d5276282 1348 tr_A_to_r0(op);
5d817c91 1349 tr_bank_write(op&0x1ff);
1350 ret++; break;
1351
d274c33b 1352 // ld d, ri
1353 case 0x09: {
bad5731d 1354 int r;
d274c33b 1355 r = (op&3) | ((op>>6)&4); // src
bad5731d 1356 tmpv2 = (op >> 4) & 0xf; // dst
bad5731d 1357 if ((r&3) == 3) tr_unhandled();
d274c33b 1358
bad5731d 1359 if (known_regb & (1 << (r+8))) {
1360 tr_mov16(0, known_regs.r[r]);
6e39239f 1361 tr_write_funcs[tmpv2](known_regs.r[r]);
d274c33b 1362 } else {
bad5731d 1363 int reg = (r < 4) ? 8 : 9;
d274c33b 1364 if (r&3) EOP_MOV_REG_LSR(0, reg, (r&3)*8); // mov r0, r{7,8}, lsr #lsr
1365 EOP_AND_IMM(0, (r&3)?0:reg, 0, 0xff); // and r0, r{7,8}, <mask>
1366 hostreg_r[0] = -1;
6e39239f 1367 tr_write_funcs[tmpv2](-1);
d274c33b 1368 }
d274c33b 1369 ret++; break;
1370 }
1371
bad5731d 1372 // ld ri, s
1373 case 0x0a: {
1374 int r;
1375 r = (op&3) | ((op>>6)&4); // dst
1376 tmpv = (op >> 4) & 0xf; // src
bad5731d 1377 if ((r&3) == 3) tr_unhandled();
1378
1379 if (known_regb & (1 << tmpv)) {
1380 known_regs.r[r] = known_regs.gr[tmpv].h;
1381 known_regb |= 1 << (r + 8);
1382 dirty_regb |= 1 << (r + 8);
1383 } else {
1384 int reg = (r < 4) ? 8 : 9;
1385 int ror = ((4 - (r&3))*8) & 0x1f;
d5276282 1386 tr_read_funcs[tmpv](op);
bad5731d 1387 EOP_BIC_IMM(reg, reg, ror/2, 0xff); // bic r{7,8}, r{7,8}, <mask>
1388 EOP_AND_IMM(0, 0, 0, 0xff); // and r0, r0, 0xff
1389 EOP_ORR_REG_LSL(reg, reg, 0, (r&3)*8); // orr r{7,8}, r{7,8}, r0, lsl #lsl
1390 hostreg_r[0] = -1;
1391 known_regb &= ~(1 << (r+8));
1392 dirty_regb &= ~(1 << (r+8));
1393 }
1394 ret++; break;
1395 }
1396
5d817c91 1397 // ldi ri, simm
1398 case 0x0c ... 0x0f:
1399 tmpv = (op>>8)&7;
bad5731d 1400 known_regs.r[tmpv] = op;
1401 known_regb |= 1 << (tmpv + 8);
5d817c91 1402 dirty_regb |= 1 << (tmpv + 8);
1403 ret++; break;
bad5731d 1404
a6fb500b 1405 // call cond, addr
6e39239f 1406 case 0x24: {
1407 u32 *jump_op = NULL;
a6fb500b 1408 tmpv = tr_cond_check(op);
6e39239f 1409 if (tmpv != A_COND_AL) {
1410 jump_op = tcache_ptr;
1411 EOP_MOV_IMM(0, 0, 0); // placeholder for branch
1412 }
1413 tr_mov16(0, *pc);
1414 tr_r0_to_STACK(*pc);
1415 if (tmpv != A_COND_AL) {
1416 u32 *real_ptr = tcache_ptr;
1417 tcache_ptr = jump_op;
1418 EOP_C_B(tr_neg_cond(tmpv),0,real_ptr - jump_op - 2);
1419 tcache_ptr = real_ptr;
1420 }
a6fb500b 1421 tr_mov16_cond(tmpv, 0, imm);
45883918 1422 if (tmpv != A_COND_AL)
a6fb500b 1423 tr_mov16_cond(tr_neg_cond(tmpv), 0, *pc);
6e39239f 1424 tr_r0_to_PC(tmpv == A_COND_AL ? imm : -1);
ede7220f 1425 ret |= 0x10000;
45883918 1426 *end_cond = tmpv;
1427 *jump_pc = imm;
a6fb500b 1428 ret += 2; break;
6e39239f 1429 }
a6fb500b 1430
bad5731d 1431 // ld d, (a)
1432 case 0x25:
bad5731d 1433 tmpv2 = (op >> 4) & 0xf; // dst
d5276282 1434 tr_A_to_r0(op);
bad5731d 1435 EOP_LDR_IMM(1,7,0x48c); // ptr_iram_rom
1436 EOP_ADD_REG_LSL(0,1,0,1); // add r0, r1, r0, lsl #1
1437 EOP_LDRH_SIMPLE(0,0); // ldrh r0, [r0]
1438 hostreg_r[0] = hostreg_r[1] = -1;
6e39239f 1439 tr_write_funcs[tmpv2](-1);
45883918 1440 if (tmpv2 == SSP_PC) {
1441 ret |= 0x10000;
1442 *end_cond = -A_COND_AL;
1443 }
a6fb500b 1444 ret += 3; break;
bad5731d 1445
1446 // bra cond, addr
a6fb500b 1447 case 0x26:
bad5731d 1448 tmpv = tr_cond_check(op);
1449 tr_mov16_cond(tmpv, 0, imm);
45883918 1450 if (tmpv != A_COND_AL)
bad5731d 1451 tr_mov16_cond(tr_neg_cond(tmpv), 0, *pc);
6e39239f 1452 tr_r0_to_PC(tmpv == A_COND_AL ? imm : -1);
ede7220f 1453 ret |= 0x10000;
45883918 1454 *end_cond = tmpv;
1455 *jump_pc = imm;
a6fb500b 1456 ret += 2; break;
bad5731d 1457
89fea1e9 1458 // mod cond, op
89fea1e9 1459 case 0x48: {
1460 // check for repeats of this op
1461 tmpv = 1; // count
1462 while (PROGRAM(*pc) == op && (op & 7) != 6) {
1463 (*pc)++; tmpv++;
71bb1b7b 1464 n_in_ops++;
89fea1e9 1465 }
6e39239f 1466 if ((op&0xf0) != 0) // !always
1467 tr_make_dirty_ST();
1468
89fea1e9 1469 tmpv2 = tr_cond_check(op);
1470 switch (op & 7) {
1471 case 2: EOP_C_DOP_REG_XIMM(tmpv2,A_OP_MOV,1,0,5,tmpv,A_AM1_ASR,5); break; // shr (arithmetic)
1472 case 3: EOP_C_DOP_REG_XIMM(tmpv2,A_OP_MOV,1,0,5,tmpv,A_AM1_LSL,5); break; // shl
1473 case 6: EOP_C_DOP_IMM(tmpv2,A_OP_RSB,1,5,5,0,0); break; // neg
6e39239f 1474 case 7: EOP_C_DOP_REG_XIMM(tmpv2,A_OP_EOR,0,5,1,31,A_AM1_ASR,5); // eor r1, r5, r5, asr #31
1475 EOP_C_DOP_REG_XIMM(tmpv2,A_OP_ADD,1,1,5,31,A_AM1_LSR,5); // adds r5, r1, r5, lsr #31
89fea1e9 1476 hostreg_r[1] = -1; break; // abs
1477 default: tr_unhandled();
1478 }
6e39239f 1479
1480 hostreg_sspreg_changed(SSP_A);
1481 dirty_regb |= KRREG_ST;
1482 known_regb &= ~KRREG_ST;
1483 known_regb &= ~(KRREG_A|KRREG_AL);
89fea1e9 1484 ret += tmpv; break;
1485 }
0e4d7ba5 1486
bad5731d 1487 // mpys?
1488 case 0x1b:
0e4d7ba5 1489 tr_flush_dirty_P();
1490 tr_mac_load_XY(op);
1491 tr_make_dirty_ST();
1492 EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_SUB,1,5,5,0,A_AM1_LSL,10); // subs r5, r5, r10
1493 hostreg_sspreg_changed(SSP_A);
1494 known_regb &= ~(KRREG_A|KRREG_AL);
1495 dirty_regb |= KRREG_ST;
1496 ret++; break;
bad5731d 1497
1498 // mpya (rj), (ri), b
1499 case 0x4b:
0e4d7ba5 1500 tr_flush_dirty_P();
1501 tr_mac_load_XY(op);
1502 tr_make_dirty_ST();
1503 EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_ADD,1,5,5,0,A_AM1_LSL,10); // adds r5, r5, r10
1504 hostreg_sspreg_changed(SSP_A);
1505 known_regb &= ~(KRREG_A|KRREG_AL);
1506 dirty_regb |= KRREG_ST;
1507 ret++; break;
bad5731d 1508
1509 // mld (rj), (ri), b
1510 case 0x5b:
0e4d7ba5 1511 EOP_C_DOP_IMM(A_COND_AL,A_OP_MOV,1,0,5,0,0); // movs r5, #0
1512 hostreg_sspreg_changed(SSP_A);
1513 known_regs.gr[SSP_A].v = 0;
bad5731d 1514 known_regb |= (KRREG_A|KRREG_AL);
0e4d7ba5 1515 dirty_regb |= KRREG_ST;
1516 tr_mac_load_XY(op);
1517 ret++; break;
1518
1519 // OP a, s
1520 case 0x10:
1521 case 0x30:
1522 case 0x40:
1523 case 0x50:
1524 case 0x60:
1525 case 0x70:
1526 tmpv = op & 0xf; // src
1527 tmpv2 = tr_aop_ssp2arm(op>>13); // op
1528 tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
0e4d7ba5 1529 if (tmpv == SSP_P) {
1530 tr_flush_dirty_P();
1531 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3, 0,A_AM1_LSL,10); // OPs r5, r5, r10
1532 } else if (tmpv == SSP_A) {
1533 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3, 0,A_AM1_LSL, 5); // OPs r5, r5, r5
1534 } else {
d5276282 1535 tr_read_funcs[tmpv](op);
0e4d7ba5 1536 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL, 0); // OPs r5, r5, r0, lsl #16
1537 }
1538 hostreg_sspreg_changed(SSP_A);
1539 known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1540 dirty_regb |= KRREG_ST;
1541 ret++; break;
1542
1543 // OP a, (ri)
1544 case 0x11:
1545 case 0x31:
1546 case 0x41:
1547 case 0x51:
1548 case 0x61:
1549 case 0x71:
1550 tmpv2 = tr_aop_ssp2arm(op>>13); // op
1551 tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1552 tr_rX_read((op&3)|((op>>6)&4), (op>>2)&3);
1553 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16
1554 hostreg_sspreg_changed(SSP_A);
1555 known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1556 dirty_regb |= KRREG_ST;
1557 ret++; break;
1558
1559 // OP a, adr
1560 case 0x13:
1561 case 0x33:
1562 case 0x43:
1563 case 0x53:
1564 case 0x63:
1565 case 0x73:
1566 tmpv2 = tr_aop_ssp2arm(op>>13); // op
1567 tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1568 tr_bank_read(op&0x1ff);
1569 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16
1570 hostreg_sspreg_changed(SSP_A);
1571 known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1572 dirty_regb |= KRREG_ST;
1573 ret++; break;
1574
1575 // OP a, imm
1576 case 0x14:
1577 case 0x34:
1578 case 0x44:
1579 case 0x54:
1580 case 0x64:
1581 case 0x74:
1582 tmpv = (op & 0xf0) >> 4;
1583 tmpv2 = tr_aop_ssp2arm(op>>13); // op
1584 tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1585 tr_mov16(0, imm);
1586 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16
1587 hostreg_sspreg_changed(SSP_A);
1588 known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1589 dirty_regb |= KRREG_ST;
1590 ret += 2; break;
1591
1592 // OP a, ((ri))
1593 case 0x15:
1594 case 0x35:
1595 case 0x45:
1596 case 0x55:
1597 case 0x65:
1598 case 0x75:
1599 tmpv2 = tr_aop_ssp2arm(op>>13); // op
1600 tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1601 tr_rX_read2(op);
1602 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16
1603 hostreg_sspreg_changed(SSP_A);
1604 known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1605 dirty_regb |= KRREG_ST;
1606 ret += 3; break;
1607
1608 // OP a, ri
1609 case 0x19:
1610 case 0x39:
1611 case 0x49:
1612 case 0x59:
1613 case 0x69:
1614 case 0x79: {
1615 int r;
1616 tmpv2 = tr_aop_ssp2arm(op>>13); // op
1617 tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1618 r = (op&3) | ((op>>6)&4); // src
1619 if ((r&3) == 3) tr_unhandled();
1620
1621 if (known_regb & (1 << (r+8))) {
1622 EOP_C_DOP_IMM(A_COND_AL,tmpv2,1,5,tmpv3,16/2,known_regs.r[r]); // OPs r5, r5, #val<<16
1623 } else {
1624 int reg = (r < 4) ? 8 : 9;
1625 if (r&3) EOP_MOV_REG_LSR(0, reg, (r&3)*8); // mov r0, r{7,8}, lsr #lsr
1626 EOP_AND_IMM(0, (r&3)?0:reg, 0, 0xff); // and r0, r{7,8}, <mask>
1627 EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16
1628 hostreg_r[0] = -1;
1629 }
1630 hostreg_sspreg_changed(SSP_A);
1631 known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1632 dirty_regb |= KRREG_ST;
1633 ret++; break;
1634 }
1635
1636 // OP simm
1637 case 0x1c:
1638 case 0x3c:
1639 case 0x4c:
1640 case 0x5c:
1641 case 0x6c:
1642 case 0x7c:
1643 tmpv2 = tr_aop_ssp2arm(op>>13); // op
1644 tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5;
1645 EOP_C_DOP_IMM(A_COND_AL,tmpv2,1,5,tmpv3,16/2,op & 0xff); // OPs r5, r5, #val<<16
1646 hostreg_sspreg_changed(SSP_A);
1647 known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST);
1648 dirty_regb |= KRREG_ST;
bad5731d 1649 ret++; break;
e807ac75 1650 }
1651
71bb1b7b 1652 n_in_ops++;
1653
5d817c91 1654 return ret;
e807ac75 1655}
1656
45883918 1657static void emit_block_prologue(void)
1658{
1659 // check if there are enough cycles..
1660 // note: r0 must contain PC of current block
1661 EOP_CMP_IMM(11,0,0); // cmp r11, #0
1662 emit_call(A_COND_LE, ssp_drc_end);
1663}
1664
1665/* cond:
1666 * >0: direct (un)conditional jump
1667 * <0: indirect jump
1668 */
1669static void emit_block_epilogue(int cycles, int cond, int pc, int end_pc)
1670{
1671 if (cycles > 0xff) { printf("large cycle count: %i\n", cycles); cycles = 0xff; }
1672 EOP_SUB_IMM(11,11,0,cycles); // sub r11, r11, #cycles
1673
1674 if (cond < 0 || (end_pc >= 0x400 && pc < 0x400)) {
1675 // indirect jump, or rom -> iram jump, must use dispatcher
1676 emit_jump(A_COND_AL, ssp_drc_next);
1677 }
1678 else if (cond == A_COND_AL) {
1ca2ea4f 1679 u32 *target = (pc < 0x400) ? ssp_block_table_iram[ssp->drc.iram_context][pc] : ssp_block_table[pc];
45883918 1680 if (target != NULL)
1681 emit_jump(A_COND_AL, target);
1682 else {
1683 emit_jump(A_COND_AL, ssp_drc_next);
1684 // cause the next block to be emitted over jump instrction
1685 tcache_ptr--;
1686 }
1687 }
1688 else {
1ca2ea4f 1689 u32 *target1 = (pc < 0x400) ? ssp_block_table_iram[ssp->drc.iram_context][pc] : ssp_block_table[pc];
1690 u32 *target2 = (end_pc < 0x400) ? ssp_block_table_iram[ssp->drc.iram_context][end_pc] : ssp_block_table[end_pc];
45883918 1691 if (target1 != NULL)
1692 emit_jump(cond, target1);
1693 else emit_call(cond, ssp_drc_next_patch);
1694 if (target2 != NULL)
1695 emit_jump(tr_neg_cond(cond), target2); // neg_cond, to be able to swap jumps if needed
1696 else emit_call(tr_neg_cond(cond), ssp_drc_next_patch);
1697 }
1698}
1699
71bb1b7b 1700void *ssp_translate_block(int pc)
726bbb3e 1701{
e807ac75 1702 unsigned int op, op1, imm, ccount = 0;
5c129565 1703 unsigned int *block_start;
45883918 1704 int ret, end_cond = A_COND_AL, jump_pc = -1;
5c129565 1705
259ed0ea 1706 printf("translate %04x -> %04x\n", pc<<1, (tcache_ptr-tcache)<<2);
5c129565 1707 block_start = tcache_ptr;
bad5731d 1708 known_regb = 0;
1709 dirty_regb = KRREG_P;
d5276282 1710 known_regs.emu_status = 0;
5d817c91 1711 hostreg_clear();
5c129565 1712
1713 emit_block_prologue();
726bbb3e 1714
e807ac75 1715 for (; ccount < 100;)
726bbb3e 1716 {
1717 op = PROGRAM(pc++);
1718 op1 = op >> 9;
e807ac75 1719 imm = (u32)-1;
5c129565 1720
e807ac75 1721 if ((op1 & 0xf) == 4 || (op1 & 0xf) == 6)
1722 imm = PROGRAM(pc++); // immediate
5c129565 1723
45883918 1724 ret = translate_op(op, &pc, imm, &end_cond, &jump_pc);
e807ac75 1725 if (ret <= 0)
1726 {
71bb1b7b 1727 printf("NULL func! op=%08x (%02x)\n", op, op1);
1728 exit(1);
892b1dd2 1729 }
ede7220f 1730
45883918 1731 ccount += ret & 0xffff;
1732 if (ret & 0x10000) break;
726bbb3e 1733 }
5c129565 1734
45883918 1735 if (ccount >= 100) {
1736 end_cond = A_COND_AL;
1737 jump_pc = pc;
1738 emit_mov_const(A_COND_AL, 0, pc);
1739 }
0b5e8296 1740
89fea1e9 1741 tr_flush_dirty_prs();
1742 tr_flush_dirty_ST();
ede7220f 1743 tr_flush_dirty_pmcrs();
45883918 1744 emit_block_epilogue(ccount, end_cond, jump_pc, pc);
726bbb3e 1745
1ca2ea4f 1746 if (tcache_ptr - tcache > SSP_TCACHE_SIZE/4) {
726bbb3e 1747 printf("tcache overflow!\n");
1748 fflush(stdout);
1749 exit(1);
1750 }
1751
1752 // stats
1753 nblocks++;
71bb1b7b 1754 printf("%i blocks, %i bytes, k=%.3f\n", nblocks, (tcache_ptr - tcache)*4,
1755 (double)(tcache_ptr - tcache) / (double)n_in_ops);
df143b36 1756
5d817c91 1757#ifdef DUMP_BLOCK
5c129565 1758 {
1759 FILE *f = fopen("tcache.bin", "wb");
1760 fwrite(tcache, 1, (tcache_ptr - tcache)*4, f);
1761 fclose(f);
1762 }
1763 exit(0);
1764#endif
259ed0ea 1765
1766 handle_caches();
1767
5c129565 1768 return block_start;
726bbb3e 1769}
1770
1771
1772
1773// -----------------------------------------------------
1774
fad24893 1775static void ssp1601_state_load(void)
1776{
1777 ssp->drc.iram_dirty = 1;
1778 ssp->drc.iram_context = 0;
1779}
1780
e807ac75 1781int ssp1601_dyn_startup(void)
726bbb3e 1782{
1ca2ea4f 1783 memset(tcache, 0, SSP_TCACHE_SIZE);
1784 memset(ssp_block_table, 0, sizeof(ssp_block_table));
1785 memset(ssp_block_table_iram, 0, sizeof(ssp_block_table_iram));
e807ac75 1786 tcache_ptr = tcache;
726bbb3e 1787
fad24893 1788 PicoLoadStateHook = ssp1601_state_load;
1789
f5d1115f 1790 n_in_ops = 0;
d5276282 1791#ifdef ARM
1792 // hle'd blocks
1ca2ea4f 1793 ssp_block_table[0x800/2] = (void *) ssp_hle_800;
1794 ssp_block_table[0x902/2] = (void *) ssp_hle_902;
1795 ssp_block_table_iram[ 7][0x030/2] = (void *) ssp_hle_07_030;
1796 ssp_block_table_iram[ 7][0x036/2] = (void *) ssp_hle_07_036;
1797 ssp_block_table_iram[ 7][0x6d6/2] = (void *) ssp_hle_07_6d6;
1798 ssp_block_table_iram[11][0x12c/2] = (void *) ssp_hle_11_12c;
1799 ssp_block_table_iram[11][0x384/2] = (void *) ssp_hle_11_384;
1800 ssp_block_table_iram[11][0x38a/2] = (void *) ssp_hle_11_38a;
d5276282 1801#endif
1802
726bbb3e 1803 return 0;
1804}
1805
1806
1807void ssp1601_dyn_reset(ssp1601_t *ssp)
1808{
45883918 1809 // debug
1810 {
1811 int i, u;
1812 FILE *f = fopen("tcache.bin", "wb");
1813 fwrite(tcache, 1, (tcache_ptr - tcache)*4, f);
1814 fclose(f);
1815
1816 for (i = 0; i < 0x5090/2; i++)
1ca2ea4f 1817 if (ssp_block_table[i])
1818 printf("%06x -> __:%04x\n", (ssp_block_table[i] - tcache)*4, i<<1);
45883918 1819 for (u = 1; u < 15; u++)
1820 for (i = 0; i < 0x800/2; i++)
1ca2ea4f 1821 if (ssp_block_table_iram[u][i])
1822 printf("%06x -> %02i:%04x\n", (ssp_block_table_iram[u][i] - tcache)*4, u, i<<1);
45883918 1823 }
1824
71bb1b7b 1825 ssp1601_reset(ssp);
1826 ssp->drc.iram_dirty = 1;
1827 ssp->drc.iram_context = 0;
1828 // must do this here because ssp is not available @ startup()
1829 ssp->drc.ptr_rom = (u32) Pico.rom;
1830 ssp->drc.ptr_iram_rom = (u32) svp->iram_rom;
1831 ssp->drc.ptr_dram = (u32) svp->dram;
1ca2ea4f 1832 ssp->drc.ptr_btable = (u32) ssp_block_table;
1833 ssp->drc.ptr_btable_iram = (u32) ssp_block_table_iram;
45883918 1834
1835 // prevent new versions of IRAM from appearing
1836 memset(svp->iram_rom, 0, 0x800);
726bbb3e 1837}
1838
726bbb3e 1839void ssp1601_dyn_run(int cycles)
1840{
b9c1d012 1841 if (ssp->emu_status & SSP_WAIT_MASK) return;
b9c1d012 1842
fad24893 1843#ifdef DUMP_BLOCK
1844 ssp_translate_block(DUMP_BLOCK >> 1);
1845#endif
1846#ifdef ARM
71bb1b7b 1847 ssp_drc_entry(cycles);
fad24893 1848#endif
726bbb3e 1849}
1850
fast MegaDrive/MegaCD/32X emulator