726bbb3e |
1 | |
2 | #include "../../PicoInt.h" |
e807ac75 |
3 | #include "compiler.h" |
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4 | |
71bb1b7b |
5 | #define u32 unsigned int |
6 | |
7 | static u32 *block_table[0x5090/2]; |
8 | static u32 *block_table_iram[15][0x800/2]; |
9 | static u32 *tcache_ptr = NULL; |
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10 | |
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11 | static int nblocks = 0; |
71bb1b7b |
12 | static int n_in_ops = 0; |
13 | |
14 | extern ssp1601_t *ssp; |
15 | |
16 | #define rPC ssp->gr[SSP_PC].h |
17 | #define rPMC ssp->gr[SSP_PMC] |
18 | |
19 | #define SSP_FLAG_Z (1<<0xd) |
20 | #define SSP_FLAG_N (1<<0xf) |
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21 | |
5d817c91 |
22 | #ifndef ARM |
0b5e8296 |
23 | #define DUMP_BLOCK 0x0c9a |
5d817c91 |
24 | unsigned int tcache[512*1024]; |
25 | void regfile_load(void){} |
26 | void regfile_store(void){} |
27 | #endif |
28 | |
5c129565 |
29 | #include "gen_arm.c" |
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30 | |
31 | // ----------------------------------------------------- |
32 | |
71bb1b7b |
33 | static int get_inc(int mode) |
892b1dd2 |
34 | { |
71bb1b7b |
35 | int inc = (mode >> 11) & 7; |
36 | if (inc != 0) { |
37 | if (inc != 7) inc--; |
38 | inc = 1 << inc; // 0 1 2 4 8 16 32 128 |
39 | if (mode & 0x8000) inc = -inc; // decrement mode |
892b1dd2 |
40 | } |
71bb1b7b |
41 | return inc; |
892b1dd2 |
42 | } |
43 | |
d5276282 |
44 | static u32 ssp_pm_read(int reg) |
45 | { |
46 | u32 d = 0, mode; |
47 | |
48 | if (ssp->emu_status & SSP_PMC_SET) |
49 | { |
50 | ssp->pmac_read[reg] = rPMC.v; |
51 | ssp->emu_status &= ~SSP_PMC_SET; |
d5276282 |
52 | return 0; |
53 | } |
54 | |
d5276282 |
55 | // just in case |
56 | ssp->emu_status &= ~SSP_PMC_HAVE_ADDR; |
57 | |
58 | mode = ssp->pmac_read[reg]>>16; |
59 | if ((mode & 0xfff0) == 0x0800) // ROM |
60 | { |
61 | d = ((unsigned short *)Pico.rom)[ssp->pmac_read[reg]&0xfffff]; |
62 | ssp->pmac_read[reg] += 1; |
63 | } |
64 | else if ((mode & 0x47ff) == 0x0018) // DRAM |
65 | { |
66 | unsigned short *dram = (unsigned short *)svp->dram; |
67 | int inc = get_inc(mode); |
68 | d = dram[ssp->pmac_read[reg]&0xffff]; |
69 | ssp->pmac_read[reg] += inc; |
70 | } |
71 | |
72 | // PMC value corresponds to last PMR accessed |
73 | rPMC.v = ssp->pmac_read[reg]; |
74 | |
75 | return d; |
76 | } |
77 | |
71bb1b7b |
78 | #define overwrite_write(dst, d) \ |
79 | { \ |
80 | if (d & 0xf000) { dst &= ~0xf000; dst |= d & 0xf000; } \ |
81 | if (d & 0x0f00) { dst &= ~0x0f00; dst |= d & 0x0f00; } \ |
82 | if (d & 0x00f0) { dst &= ~0x00f0; dst |= d & 0x00f0; } \ |
83 | if (d & 0x000f) { dst &= ~0x000f; dst |= d & 0x000f; } \ |
84 | } |
85 | |
d5276282 |
86 | static void ssp_pm_write(u32 d, int reg) |
87 | { |
88 | unsigned short *dram; |
89 | int mode, addr; |
90 | |
91 | if (ssp->emu_status & SSP_PMC_SET) |
92 | { |
93 | ssp->pmac_write[reg] = rPMC.v; |
94 | ssp->emu_status &= ~SSP_PMC_SET; |
95 | return; |
96 | } |
97 | |
98 | // just in case |
99 | ssp->emu_status &= ~SSP_PMC_HAVE_ADDR; |
100 | |
101 | dram = (unsigned short *)svp->dram; |
102 | mode = ssp->pmac_write[reg]>>16; |
103 | addr = ssp->pmac_write[reg]&0xffff; |
104 | if ((mode & 0x43ff) == 0x0018) // DRAM |
105 | { |
106 | int inc = get_inc(mode); |
107 | if (mode & 0x0400) { |
108 | overwrite_write(dram[addr], d); |
109 | } else dram[addr] = d; |
110 | ssp->pmac_write[reg] += inc; |
111 | } |
112 | else if ((mode & 0xfbff) == 0x4018) // DRAM, cell inc |
113 | { |
114 | if (mode & 0x0400) { |
115 | overwrite_write(dram[addr], d); |
116 | } else dram[addr] = d; |
117 | ssp->pmac_write[reg] += (addr&1) ? 31 : 1; |
118 | } |
119 | else if ((mode & 0x47ff) == 0x001c) // IRAM |
120 | { |
121 | int inc = get_inc(mode); |
122 | ((unsigned short *)svp->iram_rom)[addr&0x3ff] = d; |
123 | ssp->pmac_write[reg] += inc; |
e122fae6 |
124 | ssp->drc.iram_dirty = 1; |
d5276282 |
125 | } |
126 | |
127 | rPMC.v = ssp->pmac_write[reg]; |
128 | } |
129 | |
130 | |
892b1dd2 |
131 | // ----------------------------------------------------- |
132 | |
0b5e8296 |
133 | // 14 IRAM blocks |
df143b36 |
134 | static unsigned char iram_context_map[] = |
135 | { |
136 | 0, 0, 0, 0, 1, 0, 0, 0, // 04 |
137 | 0, 0, 0, 0, 0, 0, 2, 0, // 0e |
138 | 0, 0, 0, 0, 0, 3, 0, 4, // 15 17 |
139 | 5, 0, 0, 6, 0, 7, 0, 0, // 18 1b 1d |
140 | 8, 9, 0, 0, 0,10, 0, 0, // 20 21 25 |
141 | 0, 0, 0, 0, 0, 0, 0, 0, |
142 | 0, 0,11, 0, 0,12, 0, 0, // 32 35 |
143 | 13,14, 0, 0, 0, 0, 0, 0 // 38 39 |
144 | }; |
145 | |
71bb1b7b |
146 | int ssp_get_iram_context(void) |
df143b36 |
147 | { |
148 | unsigned char *ir = (unsigned char *)svp->iram_rom; |
149 | int val1, val = ir[0x083^1] + ir[0x4FA^1] + ir[0x5F7^1] + ir[0x47B^1]; |
df143b36 |
150 | val1 = iram_context_map[(val>>1)&0x3f]; |
151 | |
5c129565 |
152 | if (val1 == 0) { |
df143b36 |
153 | printf("val: %02x PC=%04x\n", (val>>1)&0x3f, rPC); |
df143b36 |
154 | //debug_dump2file(name, svp->iram_rom, 0x800); |
155 | exit(1); |
156 | } |
5c129565 |
157 | // elprintf(EL_ANOMALY, "iram_context: %02i", val1); |
df143b36 |
158 | return val1; |
159 | } |
160 | |
5d817c91 |
161 | // ----------------------------------------------------- |
0b5e8296 |
162 | |
5d817c91 |
163 | /* regs with known values */ |
164 | static struct |
165 | { |
166 | ssp_reg_t gr[8]; |
167 | unsigned char r[8]; |
ede7220f |
168 | unsigned int pmac_read[5]; |
169 | unsigned int pmac_write[5]; |
d5276282 |
170 | ssp_reg_t pmc; |
ede7220f |
171 | unsigned int emu_status; |
bad5731d |
172 | } known_regs; |
173 | |
174 | #define KRREG_X (1 << SSP_X) |
175 | #define KRREG_Y (1 << SSP_Y) |
176 | #define KRREG_A (1 << SSP_A) /* AH only */ |
177 | #define KRREG_ST (1 << SSP_ST) |
178 | #define KRREG_STACK (1 << SSP_STACK) |
179 | #define KRREG_PC (1 << SSP_PC) |
180 | #define KRREG_P (1 << SSP_P) |
181 | #define KRREG_PR0 (1 << 8) |
182 | #define KRREG_PR4 (1 << 12) |
183 | #define KRREG_AL (1 << 16) |
d5276282 |
184 | #define KRREG_PMCM (1 << 18) /* only mode word of PMC */ |
185 | #define KRREG_PMC (1 << 19) |
ede7220f |
186 | #define KRREG_PM0R (1 << 20) |
187 | #define KRREG_PM1R (1 << 21) |
188 | #define KRREG_PM2R (1 << 22) |
189 | #define KRREG_PM3R (1 << 23) |
190 | #define KRREG_PM4R (1 << 24) |
191 | #define KRREG_PM0W (1 << 25) |
192 | #define KRREG_PM1W (1 << 26) |
193 | #define KRREG_PM2W (1 << 27) |
194 | #define KRREG_PM3W (1 << 28) |
195 | #define KRREG_PM4W (1 << 29) |
bad5731d |
196 | |
197 | /* bitfield of known register values */ |
198 | static u32 known_regb = 0; |
199 | |
200 | /* known vals, which need to be flushed |
d5276282 |
201 | * (only ST, P, r0-r7, PMCx, PMxR, PMxW) |
bad5731d |
202 | * ST means flags are being held in ARM PSR |
89fea1e9 |
203 | * P means that it needs to be recalculated |
bad5731d |
204 | */ |
205 | static u32 dirty_regb = 0; |
5d817c91 |
206 | |
207 | /* known values of host regs. |
d274c33b |
208 | * -1 - unknown |
209 | * 000000-00ffff - 16bit value |
210 | * 100000-10ffff - base reg (r7) + 16bit val |
6e39239f |
211 | * 0r0000 - means reg (low) eq gr[r].h, r != AL |
5d817c91 |
212 | */ |
213 | static int hostreg_r[4]; |
214 | |
215 | static void hostreg_clear(void) |
216 | { |
217 | int i; |
218 | for (i = 0; i < 4; i++) |
219 | hostreg_r[i] = -1; |
220 | } |
221 | |
6e39239f |
222 | static void hostreg_sspreg_changed(int sspreg) |
5d817c91 |
223 | { |
224 | int i; |
225 | for (i = 0; i < 4; i++) |
6e39239f |
226 | if (hostreg_r[i] == (sspreg<<16)) hostreg_r[i] = -1; |
5d817c91 |
227 | } |
228 | |
726bbb3e |
229 | |
ede7220f |
230 | #define PROGRAM(x) ((unsigned short *)svp->iram_rom)[x] |
231 | #define PROGRAM_P(x) ((unsigned short *)svp->iram_rom + (x)) |
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232 | |
6e39239f |
233 | static void tr_unhandled(void) |
234 | { |
235 | FILE *f = fopen("tcache.bin", "wb"); |
236 | fwrite(tcache, 1, (tcache_ptr - tcache)*4, f); |
237 | fclose(f); |
238 | printf("unhandled @ %04x\n", known_regs.gr[SSP_PC].h<<1); |
239 | exit(1); |
240 | } |
241 | |
0e4d7ba5 |
242 | /* update P, if needed. Trashes r0 */ |
d274c33b |
243 | static void tr_flush_dirty_P(void) |
244 | { |
245 | // TODO: const regs |
bad5731d |
246 | if (!(dirty_regb & KRREG_P)) return; |
d274c33b |
247 | EOP_MOV_REG_ASR(10, 4, 16); // mov r10, r4, asr #16 |
0e4d7ba5 |
248 | EOP_MOV_REG_LSL( 0, 4, 16); // mov r0, r4, lsl #16 |
249 | EOP_MOV_REG_ASR( 0, 0, 15); // mov r0, r0, asr #15 |
250 | EOP_MUL(10, 0, 10); // mul r10, r0, r10 |
bad5731d |
251 | dirty_regb &= ~KRREG_P; |
0e4d7ba5 |
252 | hostreg_r[0] = -1; |
d274c33b |
253 | } |
254 | |
89fea1e9 |
255 | /* write dirty pr to host reg. Nothing is trashed */ |
256 | static void tr_flush_dirty_pr(int r) |
257 | { |
258 | int ror = 0, reg; |
6e39239f |
259 | |
89fea1e9 |
260 | if (!(dirty_regb & (1 << (r+8)))) return; |
261 | |
262 | switch (r&3) { |
263 | case 0: ror = 0; break; |
264 | case 1: ror = 24/2; break; |
265 | case 2: ror = 16/2; break; |
266 | } |
267 | reg = (r < 4) ? 8 : 9; |
268 | EOP_BIC_IMM(reg,reg,ror,0xff); |
269 | if (known_regs.r[r] != 0) |
270 | EOP_ORR_IMM(reg,reg,ror,known_regs.r[r]); |
271 | dirty_regb &= ~(1 << (r+8)); |
272 | } |
273 | |
274 | /* write all dirty pr0-pr7 to host regs. Nothing is trashed */ |
275 | static void tr_flush_dirty_prs(void) |
5d817c91 |
276 | { |
277 | int i, ror = 0, reg; |
bad5731d |
278 | int dirty = dirty_regb >> 8; |
5d817c91 |
279 | /* r0-r7 */ |
bad5731d |
280 | for (i = 0; dirty && i < 8; i++, dirty >>= 1) |
5d817c91 |
281 | { |
bad5731d |
282 | if (!(dirty&1)) continue; |
5d817c91 |
283 | switch (i&3) { |
284 | case 0: ror = 0; break; |
285 | case 1: ror = 24/2; break; |
286 | case 2: ror = 16/2; break; |
287 | } |
288 | reg = (i < 4) ? 8 : 9; |
289 | EOP_BIC_IMM(reg,reg,ror,0xff); |
bad5731d |
290 | if (known_regs.r[i] != 0) |
291 | EOP_ORR_IMM(reg,reg,ror,known_regs.r[i]); |
5d817c91 |
292 | } |
bad5731d |
293 | dirty_regb &= ~0xff00; |
294 | } |
295 | |
89fea1e9 |
296 | /* write dirty pr and "forget" it. Nothing is trashed. */ |
297 | static void tr_release_pr(int r) |
298 | { |
299 | tr_flush_dirty_pr(r); |
300 | known_regb &= ~(1 << (r+8)); |
301 | } |
302 | |
6e39239f |
303 | /* fush ARM PSR to r6. Trashes r1 */ |
bad5731d |
304 | static void tr_flush_dirty_ST(void) |
305 | { |
306 | if (!(dirty_regb & KRREG_ST)) return; |
307 | EOP_BIC_IMM(6,6,0,0x0f); |
6e39239f |
308 | EOP_MRS(1); |
309 | EOP_ORR_REG_LSR(6,6,1,28); |
bad5731d |
310 | dirty_regb &= ~KRREG_ST; |
6e39239f |
311 | hostreg_r[1] = -1; |
312 | } |
313 | |
314 | /* inverse of above. Trashes r1 */ |
315 | static void tr_make_dirty_ST(void) |
316 | { |
317 | if (dirty_regb & KRREG_ST) return; |
318 | if (known_regb & KRREG_ST) { |
319 | int flags = 0; |
320 | if (known_regs.gr[SSP_ST].h & SSP_FLAG_N) flags |= 8; |
321 | if (known_regs.gr[SSP_ST].h & SSP_FLAG_Z) flags |= 4; |
322 | EOP_MSR_IMM(4/2, flags); |
323 | } else { |
324 | EOP_MOV_REG_LSL(1, 6, 28); |
325 | EOP_MSR_REG(1); |
326 | hostreg_r[1] = -1; |
327 | } |
328 | dirty_regb |= KRREG_ST; |
bad5731d |
329 | } |
330 | |
331 | /* load 16bit val into host reg r0-r3. Nothing is trashed */ |
332 | static void tr_mov16(int r, int val) |
333 | { |
334 | if (hostreg_r[r] != val) { |
335 | emit_mov_const(A_COND_AL, r, val); |
336 | hostreg_r[r] = val; |
337 | } |
338 | } |
339 | |
340 | static void tr_mov16_cond(int cond, int r, int val) |
341 | { |
342 | emit_mov_const(cond, r, val); |
a6fb500b |
343 | hostreg_r[r] = -1; |
5d817c91 |
344 | } |
345 | |
ede7220f |
346 | /* trashes r0 */ |
347 | static void tr_flush_dirty_pmcrs(void) |
348 | { |
349 | u32 i, val = (u32)-1; |
d5276282 |
350 | if (!(dirty_regb & 0x3ff80000)) return; |
ede7220f |
351 | |
d5276282 |
352 | if (dirty_regb & KRREG_PMC) { |
353 | val = known_regs.pmc.v; |
e122fae6 |
354 | emit_mov_const(A_COND_AL, 1, val); |
355 | EOP_STR_IMM(1,7,0x400+SSP_PMC*4); |
ede7220f |
356 | |
d5276282 |
357 | if (known_regs.emu_status & (SSP_PMC_SET|SSP_PMC_HAVE_ADDR)) { |
358 | printf("!! SSP_PMC_SET|SSP_PMC_HAVE_ADDR set on flush\n"); |
359 | tr_unhandled(); |
360 | } |
ede7220f |
361 | } |
362 | for (i = 0; i < 5; i++) |
363 | { |
d5276282 |
364 | if (dirty_regb & (1 << (20+i))) { |
ede7220f |
365 | if (val != known_regs.pmac_read[i]) { |
366 | val = known_regs.pmac_read[i]; |
e122fae6 |
367 | emit_mov_const(A_COND_AL, 1, val); |
ede7220f |
368 | } |
e122fae6 |
369 | EOP_STR_IMM(1,7,0x454+i*4); // pmac_read |
ede7220f |
370 | } |
d5276282 |
371 | if (dirty_regb & (1 << (25+i))) { |
ede7220f |
372 | if (val != known_regs.pmac_write[i]) { |
373 | val = known_regs.pmac_write[i]; |
e122fae6 |
374 | emit_mov_const(A_COND_AL, 1, val); |
ede7220f |
375 | } |
e122fae6 |
376 | EOP_STR_IMM(1,7,0x46c+i*4); // pmac_write |
ede7220f |
377 | } |
378 | } |
d5276282 |
379 | dirty_regb &= ~0x3ff80000; |
e122fae6 |
380 | hostreg_r[1] = -1; |
ede7220f |
381 | } |
382 | |
0e4d7ba5 |
383 | /* read bank word to r0 (upper bits zero). Thrashes r1. */ |
5d817c91 |
384 | static void tr_bank_read(int addr) /* word addr 0-0x1ff */ |
385 | { |
bad5731d |
386 | int breg = 7; |
387 | if (addr > 0x7f) { |
388 | if (hostreg_r[1] != (0x100000|((addr&0x180)<<1))) { |
389 | EOP_ADD_IMM(1,7,30/2,(addr&0x180)>>1); // add r1, r7, ((op&0x180)<<1) |
390 | hostreg_r[1] = 0x100000|((addr&0x180)<<1); |
5d817c91 |
391 | } |
bad5731d |
392 | breg = 1; |
5d817c91 |
393 | } |
bad5731d |
394 | EOP_LDRH_IMM(0,breg,(addr&0x7f)<<1); // ldrh r0, [r1, (op&0x7f)<<1] |
5d817c91 |
395 | hostreg_r[0] = -1; |
396 | } |
397 | |
398 | /* write r0 to bank. Trashes r1. */ |
399 | static void tr_bank_write(int addr) |
400 | { |
401 | int breg = 7; |
402 | if (addr > 0x7f) { |
d274c33b |
403 | if (hostreg_r[1] != (0x100000|((addr&0x180)<<1))) { |
5d817c91 |
404 | EOP_ADD_IMM(1,7,30/2,(addr&0x180)>>1); // add r1, r7, ((op&0x180)<<1) |
d274c33b |
405 | hostreg_r[1] = 0x100000|((addr&0x180)<<1); |
5d817c91 |
406 | } |
407 | breg = 1; |
408 | } |
b9c1d012 |
409 | EOP_STRH_IMM(0,breg,(addr&0x7f)<<1); // strh r0, [r1, (op&0x7f)<<1] |
5d817c91 |
410 | } |
411 | |
89fea1e9 |
412 | /* handle RAM bank pointer modifiers. if need_modulo, trash r1-r3, else nothing */ |
413 | static void tr_ptrr_mod(int r, int mod, int need_modulo, int count) |
5d817c91 |
414 | { |
a6fb500b |
415 | int modulo_shift = -1; /* unknown */ |
5d817c91 |
416 | |
417 | if (mod == 0) return; |
418 | |
419 | if (!need_modulo || mod == 1) // +! |
420 | modulo_shift = 8; |
bad5731d |
421 | else if (need_modulo && (known_regb & KRREG_ST)) { |
422 | modulo_shift = known_regs.gr[SSP_ST].h & 7; |
5d817c91 |
423 | if (modulo_shift == 0) modulo_shift = 8; |
424 | } |
425 | |
89fea1e9 |
426 | if (modulo_shift == -1) |
427 | { |
a6fb500b |
428 | int reg = (r < 4) ? 8 : 9; |
89fea1e9 |
429 | tr_release_pr(r); |
0e4d7ba5 |
430 | if (dirty_regb & KRREG_ST) { |
431 | // avoid flushing ARM flags |
432 | EOP_AND_IMM(1, 6, 0, 0x70); |
433 | EOP_SUB_IMM(1, 1, 0, 0x10); |
434 | EOP_AND_IMM(1, 1, 0, 0x70); |
435 | EOP_ADD_IMM(1, 1, 0, 0x10); |
436 | } else { |
437 | EOP_C_DOP_IMM(A_COND_AL,A_OP_AND,1,6,1,0,0x70); // ands r1, r6, #0x70 |
438 | EOP_C_DOP_IMM(A_COND_EQ,A_OP_MOV,0,0,1,0,0x80); // moveq r1, #0x80 |
439 | } |
89fea1e9 |
440 | EOP_MOV_REG_LSR(1, 1, 4); // mov r1, r1, lsr #4 |
441 | EOP_RSB_IMM(2, 1, 0, 8); // rsb r1, r1, #8 |
442 | EOP_MOV_IMM(3, 8/2, count); // mov r3, #0x01000000 |
443 | if (r&3) |
444 | EOP_ADD_IMM(1, 1, 0, (r&3)*8); // add r1, r1, #(r&3)*8 |
445 | EOP_MOV_REG2_ROR(reg,reg,1); // mov reg, reg, ror r1 |
446 | if (mod == 2) |
447 | EOP_SUB_REG2_LSL(reg,reg,3,2); // sub reg, reg, #0x01000000 << r2 |
448 | else EOP_ADD_REG2_LSL(reg,reg,3,2); |
449 | EOP_RSB_IMM(1, 1, 0, 32); // rsb r1, r1, #32 |
450 | EOP_MOV_REG2_ROR(reg,reg,1); // mov reg, reg, ror r1 |
451 | hostreg_r[1] = hostreg_r[2] = hostreg_r[3] = -1; |
a6fb500b |
452 | } |
453 | else if (known_regb & (1 << (r + 8))) |
454 | { |
455 | int modulo = (1 << modulo_shift) - 1; |
5d817c91 |
456 | if (mod == 2) |
89fea1e9 |
457 | known_regs.r[r] = (known_regs.r[r] & ~modulo) | ((known_regs.r[r] - count) & modulo); |
458 | else known_regs.r[r] = (known_regs.r[r] & ~modulo) | ((known_regs.r[r] + count) & modulo); |
a6fb500b |
459 | } |
460 | else |
461 | { |
5d817c91 |
462 | int reg = (r < 4) ? 8 : 9; |
463 | int ror = ((r&3) + 1)*8 - (8 - modulo_shift); |
464 | EOP_MOV_REG_ROR(reg,reg,ror); |
465 | // {add|sub} reg, reg, #1<<shift |
89fea1e9 |
466 | EOP_C_DOP_IMM(A_COND_AL,(mod==2)?A_OP_SUB:A_OP_ADD,0,reg,reg, 8/2, count << (8 - modulo_shift)); |
5d817c91 |
467 | EOP_MOV_REG_ROR(reg,reg,32-ror); |
468 | } |
469 | } |
470 | |
bad5731d |
471 | /* handle writes r0 to (rX). Trashes r1. |
472 | * fortunately we can ignore modulo increment modes for writes. */ |
0e4d7ba5 |
473 | static void tr_rX_write(int op) |
bad5731d |
474 | { |
475 | if ((op&3) == 3) |
476 | { |
477 | int mod = (op>>2) & 3; // direct addressing |
478 | tr_bank_write((op & 0x100) + mod); |
479 | } |
480 | else |
481 | { |
482 | int r = (op&3) | ((op>>6)&4); |
483 | if (known_regb & (1 << (r + 8))) { |
484 | tr_bank_write((op&0x100) | known_regs.r[r]); |
485 | } else { |
486 | int reg = (r < 4) ? 8 : 9; |
487 | int ror = ((4 - (r&3))*8) & 0x1f; |
488 | EOP_AND_IMM(1,reg,ror/2,0xff); // and r1, r{7,8}, <mask> |
489 | if (r >= 4) |
490 | EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1); // orr r1, r1, 1<<shift |
491 | if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1); // add r1, r7, r1, lsr #lsr |
492 | else EOP_ADD_REG_LSL(1,7,1,1); |
493 | EOP_STRH_SIMPLE(0,1); // strh r0, [r1] |
494 | hostreg_r[1] = -1; |
495 | } |
89fea1e9 |
496 | tr_ptrr_mod(r, (op>>2) & 3, 0, 1); |
497 | } |
498 | } |
499 | |
500 | /* read (rX) to r0. Trashes r1-r3. */ |
501 | static void tr_rX_read(int r, int mod) |
502 | { |
503 | if ((r&3) == 3) |
504 | { |
505 | tr_bank_read(((r << 6) & 0x100) + mod); // direct addressing |
506 | } |
507 | else |
508 | { |
509 | if (known_regb & (1 << (r + 8))) { |
6e39239f |
510 | tr_bank_read(((r << 6) & 0x100) | known_regs.r[r]); |
89fea1e9 |
511 | } else { |
512 | int reg = (r < 4) ? 8 : 9; |
513 | int ror = ((4 - (r&3))*8) & 0x1f; |
514 | EOP_AND_IMM(1,reg,ror/2,0xff); // and r1, r{7,8}, <mask> |
515 | if (r >= 4) |
516 | EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1); // orr r1, r1, 1<<shift |
517 | if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1); // add r1, r7, r1, lsr #lsr |
518 | else EOP_ADD_REG_LSL(1,7,1,1); |
519 | EOP_LDRH_SIMPLE(0,1); // ldrh r0, [r1] |
0e4d7ba5 |
520 | hostreg_r[0] = hostreg_r[1] = -1; |
89fea1e9 |
521 | } |
522 | tr_ptrr_mod(r, mod, 1, 1); |
bad5731d |
523 | } |
524 | } |
525 | |
0e4d7ba5 |
526 | /* read ((rX)) to r0. Trashes r1,r2. */ |
527 | static void tr_rX_read2(int op) |
528 | { |
529 | int r = (op&3) | ((op>>6)&4); // src |
530 | |
531 | if ((r&3) == 3) { |
532 | tr_bank_read((op&0x100) | ((op>>2)&3)); |
533 | } else if (known_regb & (1 << (r+8))) { |
534 | tr_bank_read((op&0x100) | known_regs.r[r]); |
535 | } else { |
536 | int reg = (r < 4) ? 8 : 9; |
537 | int ror = ((4 - (r&3))*8) & 0x1f; |
538 | EOP_AND_IMM(1,reg,ror/2,0xff); // and r1, r{7,8}, <mask> |
539 | if (r >= 4) |
540 | EOP_ORR_IMM(1,1,((ror-8)&0x1f)/2,1); // orr r1, r1, 1<<shift |
541 | if (r&3) EOP_ADD_REG_LSR(1,7,1, (r&3)*8-1); // add r1, r7, r1, lsr #lsr |
542 | else EOP_ADD_REG_LSL(1,7,1,1); |
543 | EOP_LDRH_SIMPLE(0,1); // ldrh r0, [r1] |
544 | } |
545 | EOP_LDR_IMM(2,7,0x48c); // ptr_iram_rom |
546 | EOP_ADD_REG_LSL(2,2,0,1); // add r2, r2, r0, lsl #1 |
547 | EOP_ADD_IMM(0,0,0,1); // add r0, r0, #1 |
548 | if ((r&3) == 3) { |
549 | tr_bank_write((op&0x100) | ((op>>2)&3)); |
550 | } else if (known_regb & (1 << (r+8))) { |
551 | tr_bank_write((op&0x100) | known_regs.r[r]); |
552 | } else { |
553 | EOP_STRH_SIMPLE(0,1); // strh r0, [r1] |
554 | hostreg_r[1] = -1; |
555 | } |
556 | EOP_LDRH_SIMPLE(0,2); // ldrh r0, [r2] |
557 | hostreg_r[0] = hostreg_r[2] = -1; |
558 | } |
89fea1e9 |
559 | |
bad5731d |
560 | /* get ARM cond which would mean that SSP cond is satisfied. No trash. */ |
561 | static int tr_cond_check(int op) |
562 | { |
6e39239f |
563 | int f = (op & 0x100) >> 8; |
bad5731d |
564 | switch (op&0xf0) { |
565 | case 0x00: return A_COND_AL; /* always true */ |
566 | case 0x50: /* Z matches f(?) bit */ |
567 | if (dirty_regb & KRREG_ST) return f ? A_COND_EQ : A_COND_NE; |
568 | EOP_TST_IMM(6, 0, 4); |
569 | return f ? A_COND_NE : A_COND_EQ; |
570 | case 0x70: /* N matches f(?) bit */ |
571 | if (dirty_regb & KRREG_ST) return f ? A_COND_MI : A_COND_PL; |
572 | EOP_TST_IMM(6, 0, 8); |
573 | return f ? A_COND_NE : A_COND_EQ; |
574 | default: |
575 | printf("unimplemented cond?\n"); |
6e39239f |
576 | tr_unhandled(); |
bad5731d |
577 | return 0; |
578 | } |
579 | } |
580 | |
581 | static int tr_neg_cond(int cond) |
582 | { |
583 | switch (cond) { |
584 | case A_COND_AL: printf("neg for AL?\n"); exit(1); |
585 | case A_COND_EQ: return A_COND_NE; |
586 | case A_COND_NE: return A_COND_EQ; |
587 | case A_COND_MI: return A_COND_PL; |
588 | case A_COND_PL: return A_COND_MI; |
589 | default: printf("bad cond for neg\n"); exit(1); |
590 | } |
591 | return 0; |
592 | } |
593 | |
ede7220f |
594 | static int tr_aop_ssp2arm(int op) |
595 | { |
596 | switch (op) { |
597 | case 1: return A_OP_SUB; |
598 | case 3: return A_OP_CMP; |
599 | case 4: return A_OP_ADD; |
600 | case 5: return A_OP_AND; |
601 | case 6: return A_OP_ORR; |
602 | case 7: return A_OP_EOR; |
603 | } |
604 | |
605 | tr_unhandled(); |
606 | return 0; |
607 | } |
608 | |
609 | // ----------------------------------------------------- |
610 | |
b9c1d012 |
611 | //@ r4: XXYY |
612 | //@ r5: A |
613 | //@ r6: STACK and emu flags |
614 | //@ r7: SSP context |
615 | //@ r10: P |
616 | |
bad5731d |
617 | // read general reg to r0. Trashes r1 |
d5276282 |
618 | static void tr_GR0_to_r0(int op) |
d274c33b |
619 | { |
620 | tr_mov16(0, 0xffff); |
621 | } |
622 | |
d5276282 |
623 | static void tr_X_to_r0(int op) |
d274c33b |
624 | { |
625 | if (hostreg_r[0] != (SSP_X<<16)) { |
626 | EOP_MOV_REG_LSR(0, 4, 16); // mov r0, r4, lsr #16 |
627 | hostreg_r[0] = SSP_X<<16; |
628 | } |
629 | } |
630 | |
d5276282 |
631 | static void tr_Y_to_r0(int op) |
d274c33b |
632 | { |
d274c33b |
633 | if (hostreg_r[0] != (SSP_Y<<16)) { |
634 | EOP_MOV_REG_SIMPLE(0, 4); // mov r0, r4 |
635 | hostreg_r[0] = SSP_Y<<16; |
636 | } |
637 | } |
638 | |
d5276282 |
639 | static void tr_A_to_r0(int op) |
d274c33b |
640 | { |
641 | if (hostreg_r[0] != (SSP_A<<16)) { |
642 | EOP_MOV_REG_LSR(0, 5, 16); // mov r0, r5, lsr #16 @ AH |
643 | hostreg_r[0] = SSP_A<<16; |
644 | } |
645 | } |
646 | |
d5276282 |
647 | static void tr_ST_to_r0(int op) |
d274c33b |
648 | { |
649 | // VR doesn't need much accuracy here.. |
650 | EOP_MOV_REG_LSR(0, 6, 4); // mov r0, r6, lsr #4 |
651 | EOP_AND_IMM(0, 0, 0, 0x67); // and r0, r0, #0x67 |
652 | hostreg_r[0] = -1; |
653 | } |
654 | |
d5276282 |
655 | static void tr_STACK_to_r0(int op) |
d274c33b |
656 | { |
657 | // 448 |
658 | EOP_SUB_IMM(6, 6, 8/2, 0x20); // sub r6, r6, #1<<29 |
659 | EOP_ADD_IMM(1, 7, 24/2, 0x04); // add r1, r7, 0x400 |
660 | EOP_ADD_IMM(1, 1, 0, 0x48); // add r1, r1, 0x048 |
661 | EOP_ADD_REG_LSR(1, 1, 6, 28); // add r1, r1, r6, lsr #28 |
662 | EOP_LDRH_SIMPLE(0, 1); // ldrh r0, [r1] |
663 | hostreg_r[0] = hostreg_r[1] = -1; |
664 | } |
665 | |
d5276282 |
666 | static void tr_PC_to_r0(int op) |
d274c33b |
667 | { |
bad5731d |
668 | tr_mov16(0, known_regs.gr[SSP_PC].h); |
d274c33b |
669 | } |
670 | |
d5276282 |
671 | static void tr_P_to_r0(int op) |
d274c33b |
672 | { |
673 | tr_flush_dirty_P(); |
674 | EOP_MOV_REG_LSR(0, 10, 16); // mov r0, r10, lsr #16 |
675 | hostreg_r[0] = -1; |
676 | } |
d5276282 |
677 | |
678 | static void tr_AL_to_r0(int op) |
ede7220f |
679 | { |
d5276282 |
680 | if (op == 0x000f) { |
681 | if (known_regb & KRREG_PMC) { |
682 | known_regs.emu_status &= ~(SSP_PMC_SET|SSP_PMC_HAVE_ADDR); |
683 | } else { |
684 | EOP_LDR_IMM(0,7,0x484); // ldr r1, [r7, #0x484] // emu_status |
685 | EOP_BIC_IMM(0,0,0,SSP_PMC_SET|SSP_PMC_HAVE_ADDR); |
686 | EOP_STR_IMM(0,7,0x484); |
687 | } |
688 | } |
689 | |
690 | if (hostreg_r[0] != (SSP_AL<<16)) { |
691 | EOP_MOV_REG_SIMPLE(0, 5); // mov r0, r5 |
692 | hostreg_r[0] = SSP_AL<<16; |
693 | } |
ede7220f |
694 | } |
ede7220f |
695 | |
d5276282 |
696 | static void tr_PMX_to_r0(int reg) |
ede7220f |
697 | { |
ede7220f |
698 | if ((known_regb & KRREG_PMC) && (known_regs.emu_status & SSP_PMC_SET)) |
699 | { |
d5276282 |
700 | known_regs.pmac_read[reg] = known_regs.pmc.v; |
ede7220f |
701 | known_regs.emu_status &= ~SSP_PMC_SET; |
0336d643 |
702 | known_regb |= 1 << (20+reg); |
d5276282 |
703 | dirty_regb |= 1 << (20+reg); |
704 | return; |
ede7220f |
705 | } |
706 | |
d5276282 |
707 | if ((known_regb & KRREG_PMC) && (known_regb & (1 << (20+reg)))) |
ede7220f |
708 | { |
d5276282 |
709 | u32 pmcv = known_regs.pmac_read[reg]; |
710 | int mode = pmcv>>16; |
711 | known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR; |
712 | |
ede7220f |
713 | if ((mode & 0xfff0) == 0x0800) |
714 | { |
ede7220f |
715 | EOP_LDR_IMM(1,7,0x488); // rom_ptr |
716 | emit_mov_const(A_COND_AL, 0, (pmcv&0xfffff)<<1); |
717 | EOP_LDRH_REG(0,1,0); // ldrh r0, [r1, r0] |
d5276282 |
718 | known_regs.pmac_read[reg] += 1; |
ede7220f |
719 | } |
720 | else if ((mode & 0x47ff) == 0x0018) // DRAM |
721 | { |
722 | int inc = get_inc(mode); |
ede7220f |
723 | EOP_LDR_IMM(1,7,0x490); // dram_ptr |
724 | emit_mov_const(A_COND_AL, 0, (pmcv&0xffff)<<1); |
725 | EOP_LDRH_REG(0,1,0); // ldrh r0, [r1, r0] |
d5276282 |
726 | if (reg == 4 && (pmcv == 0x187f03 || pmcv == 0x187f04)) // wait loop detection |
ede7220f |
727 | { |
728 | int flag = (pmcv == 0x187f03) ? SSP_WAIT_30FE06 : SSP_WAIT_30FE08; |
729 | tr_flush_dirty_ST(); |
730 | EOP_LDR_IMM(1,7,0x484); // ldr r1, [r7, #0x484] // emu_status |
731 | EOP_TST_REG_SIMPLE(0,0); |
71bb1b7b |
732 | EOP_C_DOP_IMM(A_COND_EQ,A_OP_SUB,0,11,11,22/2,1); // subeq r11, r11, #1024 |
d5276282 |
733 | EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1,24/2,flag>>8); // orreq r1, r1, #SSP_WAIT_30FE08 |
ede7220f |
734 | EOP_STR_IMM(1,7,0x484); // str r1, [r7, #0x484] // emu_status |
735 | } |
d5276282 |
736 | known_regs.pmac_read[reg] += inc; |
ede7220f |
737 | } |
738 | else |
739 | { |
740 | tr_unhandled(); |
741 | } |
d5276282 |
742 | known_regs.pmc.v = known_regs.pmac_read[reg]; |
743 | //known_regb |= KRREG_PMC; |
744 | dirty_regb |= KRREG_PMC; |
745 | dirty_regb |= 1 << (20+reg); |
746 | hostreg_r[0] = hostreg_r[1] = -1; |
747 | return; |
748 | } |
ede7220f |
749 | |
d5276282 |
750 | known_regb &= ~KRREG_PMC; |
751 | dirty_regb &= ~KRREG_PMC; |
752 | known_regb &= ~(1 << (20+reg)); |
753 | dirty_regb &= ~(1 << (20+reg)); |
754 | |
755 | // call the C code to handle this |
756 | tr_flush_dirty_ST(); |
757 | //tr_flush_dirty_pmcrs(); |
758 | tr_mov16(0, reg); |
759 | emit_call(ssp_pm_read); |
760 | hostreg_clear(); |
761 | } |
762 | |
763 | static void tr_PM0_to_r0(int op) |
764 | { |
765 | tr_PMX_to_r0(0); |
766 | } |
767 | |
768 | static void tr_PM1_to_r0(int op) |
769 | { |
770 | tr_PMX_to_r0(1); |
771 | } |
772 | |
773 | static void tr_PM2_to_r0(int op) |
774 | { |
775 | tr_PMX_to_r0(2); |
776 | } |
777 | |
778 | static void tr_XST_to_r0(int op) |
779 | { |
780 | EOP_ADD_IMM(0, 7, 24/2, 4); // add r0, r7, #0x400 |
781 | EOP_LDRH_IMM(0, 0, SSP_XST*4+2); |
782 | } |
783 | |
784 | static void tr_PM4_to_r0(int op) |
785 | { |
786 | tr_PMX_to_r0(4); |
787 | } |
788 | |
789 | static void tr_PMC_to_r0(int op) |
790 | { |
791 | if (known_regb & KRREG_PMC) |
792 | { |
793 | if (known_regs.emu_status & SSP_PMC_HAVE_ADDR) { |
794 | known_regs.emu_status |= SSP_PMC_SET; |
795 | known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR; |
796 | // do nothing - this is handled elsewhere |
797 | } else { |
798 | tr_mov16(0, known_regs.pmc.l); |
799 | known_regs.emu_status |= SSP_PMC_HAVE_ADDR; |
800 | } |
801 | } |
802 | else |
803 | { |
804 | EOP_LDR_IMM(1,7,0x484); // ldr r1, [r7, #0x484] // emu_status |
805 | tr_flush_dirty_ST(); |
806 | if (op != 0x000e) |
807 | EOP_LDR_IMM(0, 7, 0x400+SSP_PMC*4); |
808 | EOP_TST_IMM(1, 0, SSP_PMC_HAVE_ADDR); |
809 | EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // orreq r1, r1, #.. |
810 | EOP_C_DOP_IMM(A_COND_NE,A_OP_BIC,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // bicne r1, r1, #.. |
811 | EOP_C_DOP_IMM(A_COND_NE,A_OP_ORR,0, 1, 1, 0, SSP_PMC_SET); // orrne r1, r1, #.. |
812 | EOP_STR_IMM(1,7,0x484); |
813 | hostreg_r[0] = hostreg_r[1] = -1; |
ede7220f |
814 | } |
ede7220f |
815 | } |
816 | |
d274c33b |
817 | |
d5276282 |
818 | typedef void (tr_read_func)(int op); |
d274c33b |
819 | |
d5276282 |
820 | static tr_read_func *tr_read_funcs[16] = |
d274c33b |
821 | { |
822 | tr_GR0_to_r0, |
823 | tr_X_to_r0, |
824 | tr_Y_to_r0, |
825 | tr_A_to_r0, |
826 | tr_ST_to_r0, |
827 | tr_STACK_to_r0, |
828 | tr_PC_to_r0, |
d5276282 |
829 | tr_P_to_r0, |
830 | tr_PM0_to_r0, |
831 | tr_PM1_to_r0, |
832 | tr_PM2_to_r0, |
833 | tr_XST_to_r0, |
834 | tr_PM4_to_r0, |
835 | (tr_read_func *)tr_unhandled, |
836 | tr_PMC_to_r0, |
837 | tr_AL_to_r0 |
d274c33b |
838 | }; |
839 | |
840 | |
b9c1d012 |
841 | // write r0 to general reg handlers. Trashes r1 |
6e39239f |
842 | #define TR_WRITE_R0_TO_REG(reg) \ |
843 | { \ |
844 | hostreg_sspreg_changed(reg); \ |
845 | hostreg_r[0] = (reg)<<16; \ |
846 | if (const_val != -1) { \ |
847 | known_regs.gr[reg].h = const_val; \ |
848 | known_regb |= 1 << (reg); \ |
849 | } else { \ |
850 | known_regb &= ~(1 << (reg)); \ |
851 | } \ |
b9c1d012 |
852 | } |
853 | |
6e39239f |
854 | static void tr_r0_to_GR0(int const_val) |
b9c1d012 |
855 | { |
856 | // do nothing |
857 | } |
858 | |
6e39239f |
859 | static void tr_r0_to_X(int const_val) |
b9c1d012 |
860 | { |
861 | EOP_MOV_REG_LSL(4, 4, 16); // mov r4, r4, lsl #16 |
862 | EOP_MOV_REG_LSR(4, 4, 16); // mov r4, r4, lsr #16 |
863 | EOP_ORR_REG_LSL(4, 4, 0, 16); // orr r4, r4, r0, lsl #16 |
6e39239f |
864 | dirty_regb |= KRREG_P; // touching X or Y makes P dirty. |
865 | TR_WRITE_R0_TO_REG(SSP_X); |
b9c1d012 |
866 | } |
867 | |
6e39239f |
868 | static void tr_r0_to_Y(int const_val) |
b9c1d012 |
869 | { |
870 | EOP_MOV_REG_LSR(4, 4, 16); // mov r4, r4, lsr #16 |
871 | EOP_ORR_REG_LSL(4, 4, 0, 16); // orr r4, r4, r0, lsl #16 |
872 | EOP_MOV_REG_ROR(4, 4, 16); // mov r4, r4, ror #16 |
bad5731d |
873 | dirty_regb |= KRREG_P; |
6e39239f |
874 | TR_WRITE_R0_TO_REG(SSP_Y); |
b9c1d012 |
875 | } |
876 | |
6e39239f |
877 | static void tr_r0_to_A(int const_val) |
b9c1d012 |
878 | { |
879 | EOP_MOV_REG_LSL(5, 5, 16); // mov r5, r5, lsl #16 |
d274c33b |
880 | EOP_MOV_REG_LSR(5, 5, 16); // mov r5, r5, lsr #16 @ AL |
b9c1d012 |
881 | EOP_ORR_REG_LSL(5, 5, 0, 16); // orr r5, r5, r0, lsl #16 |
6e39239f |
882 | TR_WRITE_R0_TO_REG(SSP_A); |
b9c1d012 |
883 | } |
884 | |
6e39239f |
885 | static void tr_r0_to_ST(int const_val) |
b9c1d012 |
886 | { |
887 | // VR doesn't need much accuracy here.. |
888 | EOP_AND_IMM(1, 0, 0, 0x67); // and r1, r0, #0x67 |
889 | EOP_AND_IMM(6, 6, 8/2, 0xe0); // and r6, r6, #7<<29 @ preserve STACK |
890 | EOP_ORR_REG_LSL(6, 6, 1, 4); // orr r6, r6, r1, lsl #4 |
6e39239f |
891 | TR_WRITE_R0_TO_REG(SSP_ST); |
b9c1d012 |
892 | hostreg_r[1] = -1; |
6e39239f |
893 | dirty_regb &= ~KRREG_ST; |
b9c1d012 |
894 | } |
895 | |
6e39239f |
896 | static void tr_r0_to_STACK(int const_val) |
b9c1d012 |
897 | { |
898 | // 448 |
899 | EOP_ADD_IMM(1, 7, 24/2, 0x04); // add r1, r7, 0x400 |
900 | EOP_ADD_IMM(1, 1, 0, 0x48); // add r1, r1, 0x048 |
d274c33b |
901 | EOP_ADD_REG_LSR(1, 1, 6, 28); // add r1, r1, r6, lsr #28 |
b9c1d012 |
902 | EOP_STRH_SIMPLE(0, 1); // strh r0, [r1] |
d274c33b |
903 | EOP_ADD_IMM(6, 6, 8/2, 0x20); // add r6, r6, #1<<29 |
b9c1d012 |
904 | hostreg_r[1] = -1; |
905 | } |
906 | |
6e39239f |
907 | static void tr_r0_to_PC(int const_val) |
b9c1d012 |
908 | { |
909 | EOP_MOV_REG_LSL(1, 0, 16); // mov r1, r0, lsl #16 |
d274c33b |
910 | EOP_STR_IMM(1,7,0x400+6*4); // str r1, [r7, #(0x400+6*8)] |
b9c1d012 |
911 | hostreg_r[1] = -1; |
912 | } |
913 | |
d5276282 |
914 | static void tr_r0_to_AL(int const_val) |
915 | { |
916 | EOP_MOV_REG_LSR(5, 5, 16); // mov r5, r5, lsr #16 |
917 | EOP_ORR_REG_LSL(5, 5, 0, 16); // orr r5, r5, r0, lsl #16 |
918 | EOP_MOV_REG_ROR(5, 5, 16); // mov r5, r5, ror #16 |
919 | hostreg_sspreg_changed(SSP_AL); |
920 | if (const_val != -1) { |
921 | known_regs.gr[SSP_A].l = const_val; |
922 | known_regb |= 1 << SSP_AL; |
923 | } else |
924 | known_regb &= ~(1 << SSP_AL); |
925 | } |
926 | |
927 | static void tr_r0_to_PMX(int reg) |
928 | { |
d5276282 |
929 | if ((known_regb & KRREG_PMC) && (known_regs.emu_status & SSP_PMC_SET)) |
930 | { |
931 | known_regs.pmac_write[reg] = known_regs.pmc.v; |
932 | known_regs.emu_status &= ~SSP_PMC_SET; |
933 | known_regb |= 1 << (25+reg); |
934 | dirty_regb |= 1 << (25+reg); |
935 | return; |
936 | } |
0b5e8296 |
937 | |
d5276282 |
938 | if ((known_regb & KRREG_PMC) && (known_regb & (1 << (25+reg)))) |
939 | { |
940 | int mode, addr; |
941 | |
942 | known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR; |
943 | |
944 | mode = known_regs.pmac_write[reg]>>16; |
945 | addr = known_regs.pmac_write[reg]&0xffff; |
946 | if ((mode & 0x43ff) == 0x0018) // DRAM |
947 | { |
948 | int inc = get_inc(mode); |
949 | if (mode & 0x0400) tr_unhandled(); |
950 | EOP_LDR_IMM(1,7,0x490); // dram_ptr |
951 | emit_mov_const(A_COND_AL, 2, addr<<1); |
952 | EOP_STRH_REG(0,1,2); // strh r0, [r1, r2] |
953 | known_regs.pmac_write[reg] += inc; |
954 | } |
955 | else if ((mode & 0xfbff) == 0x4018) // DRAM, cell inc |
956 | { |
957 | if (mode & 0x0400) tr_unhandled(); |
958 | EOP_LDR_IMM(1,7,0x490); // dram_ptr |
959 | emit_mov_const(A_COND_AL, 2, addr<<1); |
960 | EOP_STRH_REG(0,1,2); // strh r0, [r1, r2] |
961 | known_regs.pmac_write[reg] += (addr&1) ? 31 : 1; |
962 | } |
963 | else if ((mode & 0x47ff) == 0x001c) // IRAM |
964 | { |
965 | int inc = get_inc(mode); |
966 | EOP_LDR_IMM(1,7,0x48c); // iram_ptr |
967 | emit_mov_const(A_COND_AL, 2, (addr&0x3ff)<<1); |
968 | EOP_STRH_REG(0,1,2); // strh r0, [r1, r2] |
e122fae6 |
969 | EOP_MOV_IMM(1,0,1); |
970 | EOP_STR_IMM(1,7,0x494); // iram_dirty |
d5276282 |
971 | known_regs.pmac_write[reg] += inc; |
972 | } |
973 | else |
974 | tr_unhandled(); |
975 | |
976 | known_regs.pmc.v = known_regs.pmac_write[reg]; |
977 | //known_regb |= KRREG_PMC; |
978 | dirty_regb |= KRREG_PMC; |
979 | dirty_regb |= 1 << (25+reg); |
980 | hostreg_r[1] = hostreg_r[2] = -1; |
e122fae6 |
981 | return; |
d5276282 |
982 | } |
983 | |
984 | known_regb &= ~KRREG_PMC; |
985 | dirty_regb &= ~KRREG_PMC; |
986 | known_regb &= ~(1 << (25+reg)); |
987 | dirty_regb &= ~(1 << (25+reg)); |
d5276282 |
988 | |
989 | // call the C code to handle this |
990 | tr_flush_dirty_ST(); |
991 | //tr_flush_dirty_pmcrs(); |
992 | tr_mov16(1, reg); |
993 | emit_call(ssp_pm_write); |
994 | hostreg_clear(); |
995 | } |
996 | |
997 | static void tr_r0_to_PM0(int const_val) |
998 | { |
999 | tr_r0_to_PMX(0); |
1000 | } |
1001 | |
1002 | static void tr_r0_to_PM1(int const_val) |
1003 | { |
1004 | tr_r0_to_PMX(1); |
1005 | } |
1006 | |
1007 | static void tr_r0_to_PM2(int const_val) |
1008 | { |
1009 | tr_r0_to_PMX(2); |
1010 | } |
1011 | |
1012 | static void tr_r0_to_PM4(int const_val) |
1013 | { |
1014 | tr_r0_to_PMX(4); |
1015 | } |
1016 | |
1017 | static void tr_r0_to_PMC(int const_val) |
1018 | { |
1019 | if ((known_regb & KRREG_PMC) && const_val != -1) |
1020 | { |
1021 | if (known_regs.emu_status & SSP_PMC_HAVE_ADDR) { |
1022 | known_regs.emu_status |= SSP_PMC_SET; |
1023 | known_regs.emu_status &= ~SSP_PMC_HAVE_ADDR; |
1024 | known_regs.pmc.h = const_val; |
1025 | } else { |
1026 | known_regs.emu_status |= SSP_PMC_HAVE_ADDR; |
1027 | known_regs.pmc.l = const_val; |
1028 | } |
1029 | } |
1030 | else |
1031 | { |
1032 | tr_flush_dirty_ST(); |
1033 | if (known_regb & KRREG_PMC) { |
1034 | emit_mov_const(A_COND_AL, 1, known_regs.pmc.v); |
1035 | EOP_STR_IMM(1,7,0x400+SSP_PMC*4); |
1036 | known_regb &= ~KRREG_PMC; |
1037 | dirty_regb &= ~KRREG_PMC; |
1038 | } |
1039 | EOP_LDR_IMM(1,7,0x484); // ldr r1, [r7, #0x484] // emu_status |
1040 | EOP_ADD_IMM(2,7,24/2,4); // add r2, r7, #0x400 |
1041 | EOP_TST_IMM(1, 0, SSP_PMC_HAVE_ADDR); |
1042 | EOP_C_AM3_IMM(A_COND_EQ,1,0,2,0,0,1,SSP_PMC*4); // strxx r0, [r2, #SSP_PMC] |
1043 | EOP_C_AM3_IMM(A_COND_NE,1,0,2,0,0,1,SSP_PMC*4+2); |
1044 | EOP_C_DOP_IMM(A_COND_EQ,A_OP_ORR,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // orreq r1, r1, #.. |
1045 | EOP_C_DOP_IMM(A_COND_NE,A_OP_BIC,0, 1, 1, 0, SSP_PMC_HAVE_ADDR); // bicne r1, r1, #.. |
1046 | EOP_C_DOP_IMM(A_COND_NE,A_OP_ORR,0, 1, 1, 0, SSP_PMC_SET); // orrne r1, r1, #.. |
1047 | EOP_STR_IMM(1,7,0x484); |
1048 | hostreg_r[1] = hostreg_r[2] = -1; |
1049 | } |
1050 | } |
1051 | |
6e39239f |
1052 | typedef void (tr_write_func)(int const_val); |
b9c1d012 |
1053 | |
d5276282 |
1054 | static tr_write_func *tr_write_funcs[16] = |
b9c1d012 |
1055 | { |
1056 | tr_r0_to_GR0, |
1057 | tr_r0_to_X, |
1058 | tr_r0_to_Y, |
1059 | tr_r0_to_A, |
1060 | tr_r0_to_ST, |
1061 | tr_r0_to_STACK, |
1062 | tr_r0_to_PC, |
d5276282 |
1063 | (tr_write_func *)tr_unhandled, |
1064 | tr_r0_to_PM0, |
1065 | tr_r0_to_PM1, |
1066 | tr_r0_to_PM2, |
1067 | (tr_write_func *)tr_unhandled, |
1068 | tr_r0_to_PM4, |
1069 | (tr_write_func *)tr_unhandled, |
1070 | tr_r0_to_PMC, |
1071 | tr_r0_to_AL |
b9c1d012 |
1072 | }; |
1073 | |
0e4d7ba5 |
1074 | static void tr_mac_load_XY(int op) |
1075 | { |
1076 | tr_rX_read(op&3, (op>>2)&3); // X |
1077 | EOP_MOV_REG_LSL(4, 0, 16); |
1078 | tr_rX_read(((op>>4)&3)|4, (op>>6)&3); // Y |
1079 | EOP_ORR_REG_SIMPLE(4, 0); |
1080 | dirty_regb |= KRREG_P; |
1081 | hostreg_sspreg_changed(SSP_X); |
1082 | hostreg_sspreg_changed(SSP_Y); |
1083 | known_regb &= ~KRREG_X; |
1084 | known_regb &= ~KRREG_Y; |
1085 | } |
1086 | |
ede7220f |
1087 | // ----------------------------------------------------- |
1088 | |
ede7220f |
1089 | static int tr_detect_set_pm(unsigned int op, int *pc, int imm) |
0e4d7ba5 |
1090 | { |
ede7220f |
1091 | u32 pmcv, tmpv; |
1092 | if (!((op&0xfef0) == 0x08e0 && (PROGRAM(*pc)&0xfef0) == 0x08e0)) return 0; |
1093 | |
1094 | // programming PMC: |
1095 | // ldi PMC, imm1 |
1096 | // ldi PMC, imm2 |
1097 | (*pc)++; |
1098 | pmcv = imm | (PROGRAM((*pc)++) << 16); |
d5276282 |
1099 | known_regs.pmc.v = pmcv; |
ede7220f |
1100 | known_regb |= KRREG_PMC; |
d5276282 |
1101 | dirty_regb |= KRREG_PMC; |
ede7220f |
1102 | known_regs.emu_status |= SSP_PMC_SET; |
71bb1b7b |
1103 | n_in_ops++; |
ede7220f |
1104 | |
1105 | // check for possible reg programming |
1106 | tmpv = PROGRAM(*pc); |
1107 | if ((tmpv & 0xfff8) == 0x08 || (tmpv & 0xff8f) == 0x80) |
1108 | { |
1109 | int is_write = (tmpv & 0xff8f) == 0x80; |
1110 | int reg = is_write ? ((tmpv>>4)&0x7) : (tmpv&0x7); |
1111 | if (reg > 4) tr_unhandled(); |
d5276282 |
1112 | if ((tmpv & 0x0f) != 0 && (tmpv & 0xf0) != 0) tr_unhandled(); |
ede7220f |
1113 | known_regs.pmac_read[is_write ? reg + 5 : reg] = pmcv; |
1114 | known_regb |= is_write ? (1 << (reg+25)) : (1 << (reg+20)); |
d5276282 |
1115 | dirty_regb |= is_write ? (1 << (reg+25)) : (1 << (reg+20)); |
ede7220f |
1116 | known_regs.emu_status &= ~SSP_PMC_SET; |
1117 | (*pc)++; |
71bb1b7b |
1118 | n_in_ops++; |
ede7220f |
1119 | return 5; |
0e4d7ba5 |
1120 | } |
1121 | |
d5276282 |
1122 | tr_unhandled(); |
ede7220f |
1123 | return 4; |
1124 | } |
1125 | |
1126 | static const short pm0_block_seq[] = { 0x0880, 0, 0x0880, 0, 0x0840, 0x60 }; |
1127 | |
1128 | static int tr_detect_pm0_block(unsigned int op, int *pc, int imm) |
1129 | { |
1130 | // ldi ST, 0 |
1131 | // ldi PM0, 0 |
1132 | // ldi PM0, 0 |
1133 | // ldi ST, 60h |
1134 | unsigned short *pp; |
1135 | if (op != 0x0840 || imm != 0) return 0; |
1136 | pp = PROGRAM_P(*pc); |
1137 | if (memcmp(pp, pm0_block_seq, sizeof(pm0_block_seq)) != 0) return 0; |
1138 | |
1139 | EOP_AND_IMM(6, 6, 8/2, 0xe0); // and r6, r6, #7<<29 @ preserve STACK |
1140 | EOP_ORR_IMM(6, 6, 24/2, 6); // orr r6, r6, 0x600 |
1141 | hostreg_sspreg_changed(SSP_ST); |
1142 | known_regs.gr[SSP_ST].h = 0x60; |
1143 | known_regb |= 1 << SSP_ST; |
1144 | dirty_regb &= ~KRREG_ST; |
1145 | (*pc) += 3*2; |
71bb1b7b |
1146 | n_in_ops += 3; |
ede7220f |
1147 | return 4*2; |
0e4d7ba5 |
1148 | } |
5d817c91 |
1149 | |
d5276282 |
1150 | static int tr_detect_rotate(unsigned int op, int *pc, int imm) |
1151 | { |
1152 | // @ 3DA2 and 426A |
1153 | // ld PMC, (r3|00) |
1154 | // ld (r3|00), PMC |
1155 | // ld -, AL |
1156 | if (op != 0x02e3 || PROGRAM(*pc) != 0x04e3 || PROGRAM(*pc + 1) != 0x000f) return 0; |
1157 | |
1158 | tr_bank_read(0); |
1159 | EOP_MOV_REG_LSL(0, 0, 4); |
1160 | EOP_ORR_REG_LSR(0, 0, 0, 16); |
1161 | tr_bank_write(0); |
1162 | (*pc) += 2; |
71bb1b7b |
1163 | n_in_ops += 2; |
d5276282 |
1164 | return 3; |
1165 | } |
1166 | |
ede7220f |
1167 | // ----------------------------------------------------- |
1168 | |
5d817c91 |
1169 | static int translate_op(unsigned int op, int *pc, int imm) |
1170 | { |
0e4d7ba5 |
1171 | u32 tmpv, tmpv2, tmpv3; |
5d817c91 |
1172 | int ret = 0; |
bad5731d |
1173 | known_regs.gr[SSP_PC].h = *pc; |
5d817c91 |
1174 | |
e807ac75 |
1175 | switch (op >> 9) |
1176 | { |
1177 | // ld d, s |
f48f5e3b |
1178 | case 0x00: |
5d817c91 |
1179 | if (op == 0) { ret++; break; } // nop |
d274c33b |
1180 | tmpv = op & 0xf; // src |
1181 | tmpv2 = (op >> 4) & 0xf; // dst |
d274c33b |
1182 | if (tmpv2 == SSP_A && tmpv == SSP_P) { // ld A, P |
1183 | tr_flush_dirty_P(); |
1184 | EOP_MOV_REG_SIMPLE(5, 10); |
d5276282 |
1185 | hostreg_sspreg_changed(SSP_A); |
bad5731d |
1186 | known_regb &= ~(KRREG_A|KRREG_AL); |
d274c33b |
1187 | ret++; break; |
1188 | } |
d5276282 |
1189 | tr_read_funcs[tmpv](op); |
6e39239f |
1190 | tr_write_funcs[tmpv2]((known_regb & (1 << tmpv)) ? known_regs.gr[tmpv].h : -1); |
ede7220f |
1191 | if (tmpv2 == SSP_PC) ret |= 0x10000; |
bad5731d |
1192 | ret++; break; |
1193 | |
1194 | // ld d, (ri) |
89fea1e9 |
1195 | case 0x01: { |
89fea1e9 |
1196 | int r = (op&3) | ((op>>6)&4); |
1197 | int mod = (op>>2)&3; |
1198 | tmpv = (op >> 4) & 0xf; // dst |
d5276282 |
1199 | ret = tr_detect_rotate(op, pc, imm); |
1200 | if (ret > 0) break; |
89fea1e9 |
1201 | if (tmpv != 0) |
1202 | tr_rX_read(r, mod); |
1203 | else tr_ptrr_mod(r, mod, 1, 1); |
6e39239f |
1204 | tr_write_funcs[tmpv](-1); |
ede7220f |
1205 | if (tmpv == SSP_PC) ret |= 0x10000; |
89fea1e9 |
1206 | ret++; break; |
1207 | } |
bad5731d |
1208 | |
1209 | // ld (ri), s |
1210 | case 0x02: |
1211 | tmpv = (op >> 4) & 0xf; // src |
d5276282 |
1212 | tr_read_funcs[tmpv](op); |
0e4d7ba5 |
1213 | tr_rX_write(op); |
d274c33b |
1214 | ret++; break; |
f48f5e3b |
1215 | |
1216 | // ld a, adr |
1217 | case 0x03: |
5d817c91 |
1218 | tr_bank_read(op&0x1ff); |
6e39239f |
1219 | tr_r0_to_A(-1); |
5d817c91 |
1220 | ret++; break; |
1221 | |
b9c1d012 |
1222 | // ldi d, imm |
1223 | case 0x04: |
ede7220f |
1224 | tmpv = (op & 0xf0) >> 4; // dst |
1225 | ret = tr_detect_pm0_block(op, pc, imm); |
1226 | if (ret > 0) break; |
ede7220f |
1227 | ret = tr_detect_set_pm(op, pc, imm); |
1228 | if (ret > 0) break; |
0b5e8296 |
1229 | tr_mov16(0, imm); |
1230 | tr_write_funcs[tmpv](imm); |
ede7220f |
1231 | if (tmpv == SSP_PC) ret |= 0x10000; |
0b5e8296 |
1232 | ret += 2; break; |
b9c1d012 |
1233 | |
bad5731d |
1234 | // ld d, ((ri)) |
0e4d7ba5 |
1235 | case 0x05: |
bad5731d |
1236 | tmpv2 = (op >> 4) & 0xf; // dst |
0e4d7ba5 |
1237 | tr_rX_read2(op); |
6e39239f |
1238 | tr_write_funcs[tmpv2](-1); |
ede7220f |
1239 | if (tmpv2 == SSP_PC) ret |= 0x10000; |
0e4d7ba5 |
1240 | ret += 3; break; |
b9c1d012 |
1241 | |
5d817c91 |
1242 | // ldi (ri), imm |
1243 | case 0x06: |
5d817c91 |
1244 | tr_mov16(0, imm); |
0e4d7ba5 |
1245 | tr_rX_write(op); |
a6fb500b |
1246 | ret += 2; break; |
f48f5e3b |
1247 | |
1248 | // ld adr, a |
1249 | case 0x07: |
d5276282 |
1250 | tr_A_to_r0(op); |
5d817c91 |
1251 | tr_bank_write(op&0x1ff); |
1252 | ret++; break; |
1253 | |
d274c33b |
1254 | // ld d, ri |
1255 | case 0x09: { |
bad5731d |
1256 | int r; |
d274c33b |
1257 | r = (op&3) | ((op>>6)&4); // src |
bad5731d |
1258 | tmpv2 = (op >> 4) & 0xf; // dst |
bad5731d |
1259 | if ((r&3) == 3) tr_unhandled(); |
d274c33b |
1260 | |
bad5731d |
1261 | if (known_regb & (1 << (r+8))) { |
1262 | tr_mov16(0, known_regs.r[r]); |
6e39239f |
1263 | tr_write_funcs[tmpv2](known_regs.r[r]); |
d274c33b |
1264 | } else { |
bad5731d |
1265 | int reg = (r < 4) ? 8 : 9; |
d274c33b |
1266 | if (r&3) EOP_MOV_REG_LSR(0, reg, (r&3)*8); // mov r0, r{7,8}, lsr #lsr |
1267 | EOP_AND_IMM(0, (r&3)?0:reg, 0, 0xff); // and r0, r{7,8}, <mask> |
1268 | hostreg_r[0] = -1; |
6e39239f |
1269 | tr_write_funcs[tmpv2](-1); |
d274c33b |
1270 | } |
d274c33b |
1271 | ret++; break; |
1272 | } |
1273 | |
bad5731d |
1274 | // ld ri, s |
1275 | case 0x0a: { |
1276 | int r; |
1277 | r = (op&3) | ((op>>6)&4); // dst |
1278 | tmpv = (op >> 4) & 0xf; // src |
bad5731d |
1279 | if ((r&3) == 3) tr_unhandled(); |
1280 | |
1281 | if (known_regb & (1 << tmpv)) { |
1282 | known_regs.r[r] = known_regs.gr[tmpv].h; |
1283 | known_regb |= 1 << (r + 8); |
1284 | dirty_regb |= 1 << (r + 8); |
1285 | } else { |
1286 | int reg = (r < 4) ? 8 : 9; |
1287 | int ror = ((4 - (r&3))*8) & 0x1f; |
d5276282 |
1288 | tr_read_funcs[tmpv](op); |
bad5731d |
1289 | EOP_BIC_IMM(reg, reg, ror/2, 0xff); // bic r{7,8}, r{7,8}, <mask> |
1290 | EOP_AND_IMM(0, 0, 0, 0xff); // and r0, r0, 0xff |
1291 | EOP_ORR_REG_LSL(reg, reg, 0, (r&3)*8); // orr r{7,8}, r{7,8}, r0, lsl #lsl |
1292 | hostreg_r[0] = -1; |
1293 | known_regb &= ~(1 << (r+8)); |
1294 | dirty_regb &= ~(1 << (r+8)); |
1295 | } |
1296 | ret++; break; |
1297 | } |
1298 | |
5d817c91 |
1299 | // ldi ri, simm |
1300 | case 0x0c ... 0x0f: |
1301 | tmpv = (op>>8)&7; |
bad5731d |
1302 | known_regs.r[tmpv] = op; |
1303 | known_regb |= 1 << (tmpv + 8); |
5d817c91 |
1304 | dirty_regb |= 1 << (tmpv + 8); |
1305 | ret++; break; |
bad5731d |
1306 | |
a6fb500b |
1307 | // call cond, addr |
6e39239f |
1308 | case 0x24: { |
1309 | u32 *jump_op = NULL; |
a6fb500b |
1310 | tmpv = tr_cond_check(op); |
6e39239f |
1311 | if (tmpv != A_COND_AL) { |
1312 | jump_op = tcache_ptr; |
1313 | EOP_MOV_IMM(0, 0, 0); // placeholder for branch |
1314 | } |
1315 | tr_mov16(0, *pc); |
1316 | tr_r0_to_STACK(*pc); |
1317 | if (tmpv != A_COND_AL) { |
1318 | u32 *real_ptr = tcache_ptr; |
1319 | tcache_ptr = jump_op; |
1320 | EOP_C_B(tr_neg_cond(tmpv),0,real_ptr - jump_op - 2); |
1321 | tcache_ptr = real_ptr; |
1322 | } |
a6fb500b |
1323 | tr_mov16_cond(tmpv, 0, imm); |
1324 | if (tmpv != A_COND_AL) { |
1325 | tr_mov16_cond(tr_neg_cond(tmpv), 0, *pc); |
1326 | } |
6e39239f |
1327 | tr_r0_to_PC(tmpv == A_COND_AL ? imm : -1); |
ede7220f |
1328 | ret |= 0x10000; |
a6fb500b |
1329 | ret += 2; break; |
6e39239f |
1330 | } |
a6fb500b |
1331 | |
bad5731d |
1332 | // ld d, (a) |
1333 | case 0x25: |
bad5731d |
1334 | tmpv2 = (op >> 4) & 0xf; // dst |
d5276282 |
1335 | tr_A_to_r0(op); |
bad5731d |
1336 | EOP_LDR_IMM(1,7,0x48c); // ptr_iram_rom |
1337 | EOP_ADD_REG_LSL(0,1,0,1); // add r0, r1, r0, lsl #1 |
1338 | EOP_LDRH_SIMPLE(0,0); // ldrh r0, [r0] |
1339 | hostreg_r[0] = hostreg_r[1] = -1; |
6e39239f |
1340 | tr_write_funcs[tmpv2](-1); |
ede7220f |
1341 | if (tmpv2 == SSP_PC) ret |= 0x10000; |
a6fb500b |
1342 | ret += 3; break; |
bad5731d |
1343 | |
1344 | // bra cond, addr |
a6fb500b |
1345 | case 0x26: |
bad5731d |
1346 | tmpv = tr_cond_check(op); |
1347 | tr_mov16_cond(tmpv, 0, imm); |
1348 | if (tmpv != A_COND_AL) { |
bad5731d |
1349 | tr_mov16_cond(tr_neg_cond(tmpv), 0, *pc); |
1350 | } |
6e39239f |
1351 | tr_r0_to_PC(tmpv == A_COND_AL ? imm : -1); |
ede7220f |
1352 | ret |= 0x10000; |
a6fb500b |
1353 | ret += 2; break; |
bad5731d |
1354 | |
89fea1e9 |
1355 | // mod cond, op |
89fea1e9 |
1356 | case 0x48: { |
1357 | // check for repeats of this op |
1358 | tmpv = 1; // count |
1359 | while (PROGRAM(*pc) == op && (op & 7) != 6) { |
1360 | (*pc)++; tmpv++; |
71bb1b7b |
1361 | n_in_ops++; |
89fea1e9 |
1362 | } |
6e39239f |
1363 | if ((op&0xf0) != 0) // !always |
1364 | tr_make_dirty_ST(); |
1365 | |
89fea1e9 |
1366 | tmpv2 = tr_cond_check(op); |
1367 | switch (op & 7) { |
1368 | case 2: EOP_C_DOP_REG_XIMM(tmpv2,A_OP_MOV,1,0,5,tmpv,A_AM1_ASR,5); break; // shr (arithmetic) |
1369 | case 3: EOP_C_DOP_REG_XIMM(tmpv2,A_OP_MOV,1,0,5,tmpv,A_AM1_LSL,5); break; // shl |
1370 | case 6: EOP_C_DOP_IMM(tmpv2,A_OP_RSB,1,5,5,0,0); break; // neg |
6e39239f |
1371 | case 7: EOP_C_DOP_REG_XIMM(tmpv2,A_OP_EOR,0,5,1,31,A_AM1_ASR,5); // eor r1, r5, r5, asr #31 |
1372 | EOP_C_DOP_REG_XIMM(tmpv2,A_OP_ADD,1,1,5,31,A_AM1_LSR,5); // adds r5, r1, r5, lsr #31 |
89fea1e9 |
1373 | hostreg_r[1] = -1; break; // abs |
1374 | default: tr_unhandled(); |
1375 | } |
6e39239f |
1376 | |
1377 | hostreg_sspreg_changed(SSP_A); |
1378 | dirty_regb |= KRREG_ST; |
1379 | known_regb &= ~KRREG_ST; |
1380 | known_regb &= ~(KRREG_A|KRREG_AL); |
89fea1e9 |
1381 | ret += tmpv; break; |
1382 | } |
0e4d7ba5 |
1383 | |
bad5731d |
1384 | // mpys? |
1385 | case 0x1b: |
0e4d7ba5 |
1386 | tr_flush_dirty_P(); |
1387 | tr_mac_load_XY(op); |
1388 | tr_make_dirty_ST(); |
1389 | EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_SUB,1,5,5,0,A_AM1_LSL,10); // subs r5, r5, r10 |
1390 | hostreg_sspreg_changed(SSP_A); |
1391 | known_regb &= ~(KRREG_A|KRREG_AL); |
1392 | dirty_regb |= KRREG_ST; |
1393 | ret++; break; |
bad5731d |
1394 | |
1395 | // mpya (rj), (ri), b |
1396 | case 0x4b: |
0e4d7ba5 |
1397 | tr_flush_dirty_P(); |
1398 | tr_mac_load_XY(op); |
1399 | tr_make_dirty_ST(); |
1400 | EOP_C_DOP_REG_XIMM(A_COND_AL,A_OP_ADD,1,5,5,0,A_AM1_LSL,10); // adds r5, r5, r10 |
1401 | hostreg_sspreg_changed(SSP_A); |
1402 | known_regb &= ~(KRREG_A|KRREG_AL); |
1403 | dirty_regb |= KRREG_ST; |
1404 | ret++; break; |
bad5731d |
1405 | |
1406 | // mld (rj), (ri), b |
1407 | case 0x5b: |
0e4d7ba5 |
1408 | EOP_C_DOP_IMM(A_COND_AL,A_OP_MOV,1,0,5,0,0); // movs r5, #0 |
1409 | hostreg_sspreg_changed(SSP_A); |
1410 | known_regs.gr[SSP_A].v = 0; |
bad5731d |
1411 | known_regb |= (KRREG_A|KRREG_AL); |
0e4d7ba5 |
1412 | dirty_regb |= KRREG_ST; |
1413 | tr_mac_load_XY(op); |
1414 | ret++; break; |
1415 | |
1416 | // OP a, s |
1417 | case 0x10: |
1418 | case 0x30: |
1419 | case 0x40: |
1420 | case 0x50: |
1421 | case 0x60: |
1422 | case 0x70: |
1423 | tmpv = op & 0xf; // src |
1424 | tmpv2 = tr_aop_ssp2arm(op>>13); // op |
1425 | tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5; |
0e4d7ba5 |
1426 | if (tmpv == SSP_P) { |
1427 | tr_flush_dirty_P(); |
1428 | EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3, 0,A_AM1_LSL,10); // OPs r5, r5, r10 |
1429 | } else if (tmpv == SSP_A) { |
1430 | EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3, 0,A_AM1_LSL, 5); // OPs r5, r5, r5 |
1431 | } else { |
d5276282 |
1432 | tr_read_funcs[tmpv](op); |
0e4d7ba5 |
1433 | EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL, 0); // OPs r5, r5, r0, lsl #16 |
1434 | } |
1435 | hostreg_sspreg_changed(SSP_A); |
1436 | known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST); |
1437 | dirty_regb |= KRREG_ST; |
1438 | ret++; break; |
1439 | |
1440 | // OP a, (ri) |
1441 | case 0x11: |
1442 | case 0x31: |
1443 | case 0x41: |
1444 | case 0x51: |
1445 | case 0x61: |
1446 | case 0x71: |
1447 | tmpv2 = tr_aop_ssp2arm(op>>13); // op |
1448 | tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5; |
1449 | tr_rX_read((op&3)|((op>>6)&4), (op>>2)&3); |
1450 | EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16 |
1451 | hostreg_sspreg_changed(SSP_A); |
1452 | known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST); |
1453 | dirty_regb |= KRREG_ST; |
1454 | ret++; break; |
1455 | |
1456 | // OP a, adr |
1457 | case 0x13: |
1458 | case 0x33: |
1459 | case 0x43: |
1460 | case 0x53: |
1461 | case 0x63: |
1462 | case 0x73: |
1463 | tmpv2 = tr_aop_ssp2arm(op>>13); // op |
1464 | tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5; |
1465 | tr_bank_read(op&0x1ff); |
1466 | EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16 |
1467 | hostreg_sspreg_changed(SSP_A); |
1468 | known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST); |
1469 | dirty_regb |= KRREG_ST; |
1470 | ret++; break; |
1471 | |
1472 | // OP a, imm |
1473 | case 0x14: |
1474 | case 0x34: |
1475 | case 0x44: |
1476 | case 0x54: |
1477 | case 0x64: |
1478 | case 0x74: |
1479 | tmpv = (op & 0xf0) >> 4; |
1480 | tmpv2 = tr_aop_ssp2arm(op>>13); // op |
1481 | tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5; |
1482 | tr_mov16(0, imm); |
1483 | EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16 |
1484 | hostreg_sspreg_changed(SSP_A); |
1485 | known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST); |
1486 | dirty_regb |= KRREG_ST; |
1487 | ret += 2; break; |
1488 | |
1489 | // OP a, ((ri)) |
1490 | case 0x15: |
1491 | case 0x35: |
1492 | case 0x45: |
1493 | case 0x55: |
1494 | case 0x65: |
1495 | case 0x75: |
1496 | tmpv2 = tr_aop_ssp2arm(op>>13); // op |
1497 | tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5; |
1498 | tr_rX_read2(op); |
1499 | EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16 |
1500 | hostreg_sspreg_changed(SSP_A); |
1501 | known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST); |
1502 | dirty_regb |= KRREG_ST; |
1503 | ret += 3; break; |
1504 | |
1505 | // OP a, ri |
1506 | case 0x19: |
1507 | case 0x39: |
1508 | case 0x49: |
1509 | case 0x59: |
1510 | case 0x69: |
1511 | case 0x79: { |
1512 | int r; |
1513 | tmpv2 = tr_aop_ssp2arm(op>>13); // op |
1514 | tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5; |
1515 | r = (op&3) | ((op>>6)&4); // src |
1516 | if ((r&3) == 3) tr_unhandled(); |
1517 | |
1518 | if (known_regb & (1 << (r+8))) { |
1519 | EOP_C_DOP_IMM(A_COND_AL,tmpv2,1,5,tmpv3,16/2,known_regs.r[r]); // OPs r5, r5, #val<<16 |
1520 | } else { |
1521 | int reg = (r < 4) ? 8 : 9; |
1522 | if (r&3) EOP_MOV_REG_LSR(0, reg, (r&3)*8); // mov r0, r{7,8}, lsr #lsr |
1523 | EOP_AND_IMM(0, (r&3)?0:reg, 0, 0xff); // and r0, r{7,8}, <mask> |
1524 | EOP_C_DOP_REG_XIMM(A_COND_AL,tmpv2,1,5,tmpv3,16,A_AM1_LSL,0); // OPs r5, r5, r0, lsl #16 |
1525 | hostreg_r[0] = -1; |
1526 | } |
1527 | hostreg_sspreg_changed(SSP_A); |
1528 | known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST); |
1529 | dirty_regb |= KRREG_ST; |
1530 | ret++; break; |
1531 | } |
1532 | |
1533 | // OP simm |
1534 | case 0x1c: |
1535 | case 0x3c: |
1536 | case 0x4c: |
1537 | case 0x5c: |
1538 | case 0x6c: |
1539 | case 0x7c: |
1540 | tmpv2 = tr_aop_ssp2arm(op>>13); // op |
1541 | tmpv3 = (tmpv2 == A_OP_CMP) ? 0 : 5; |
1542 | EOP_C_DOP_IMM(A_COND_AL,tmpv2,1,5,tmpv3,16/2,op & 0xff); // OPs r5, r5, #val<<16 |
1543 | hostreg_sspreg_changed(SSP_A); |
1544 | known_regb &= ~(KRREG_A|KRREG_AL|KRREG_ST); |
1545 | dirty_regb |= KRREG_ST; |
bad5731d |
1546 | ret++; break; |
e807ac75 |
1547 | } |
1548 | |
71bb1b7b |
1549 | n_in_ops++; |
1550 | |
5d817c91 |
1551 | return ret; |
e807ac75 |
1552 | } |
1553 | |
71bb1b7b |
1554 | void *ssp_translate_block(int pc) |
726bbb3e |
1555 | { |
e807ac75 |
1556 | unsigned int op, op1, imm, ccount = 0; |
5c129565 |
1557 | unsigned int *block_start; |
ede7220f |
1558 | int ret, ret_prev = -1, tpc; |
5c129565 |
1559 | |
259ed0ea |
1560 | printf("translate %04x -> %04x\n", pc<<1, (tcache_ptr-tcache)<<2); |
5c129565 |
1561 | block_start = tcache_ptr; |
bad5731d |
1562 | known_regb = 0; |
1563 | dirty_regb = KRREG_P; |
d5276282 |
1564 | known_regs.emu_status = 0; |
5d817c91 |
1565 | hostreg_clear(); |
5c129565 |
1566 | |
1567 | emit_block_prologue(); |
726bbb3e |
1568 | |
e807ac75 |
1569 | for (; ccount < 100;) |
726bbb3e |
1570 | { |
1571 | op = PROGRAM(pc++); |
1572 | op1 = op >> 9; |
e807ac75 |
1573 | imm = (u32)-1; |
5c129565 |
1574 | |
e807ac75 |
1575 | if ((op1 & 0xf) == 4 || (op1 & 0xf) == 6) |
1576 | imm = PROGRAM(pc++); // immediate |
ede7220f |
1577 | tpc = pc; |
5c129565 |
1578 | |
5d817c91 |
1579 | ret = translate_op(op, &pc, imm); |
e807ac75 |
1580 | if (ret <= 0) |
1581 | { |
71bb1b7b |
1582 | printf("NULL func! op=%08x (%02x)\n", op, op1); |
1583 | exit(1); |
892b1dd2 |
1584 | } |
e807ac75 |
1585 | else |
ede7220f |
1586 | { |
1587 | ccount += ret & 0xffff; |
1588 | if (ret & 0x10000) break; |
726bbb3e |
1589 | } |
ede7220f |
1590 | |
d274c33b |
1591 | ret_prev = ret; |
726bbb3e |
1592 | } |
5c129565 |
1593 | |
0b5e8296 |
1594 | if (ccount >= 100) |
1595 | emit_pc_dump(pc); |
1596 | |
89fea1e9 |
1597 | tr_flush_dirty_prs(); |
1598 | tr_flush_dirty_ST(); |
ede7220f |
1599 | tr_flush_dirty_pmcrs(); |
e807ac75 |
1600 | emit_block_epilogue(ccount + 1); |
5c129565 |
1601 | *tcache_ptr++ = 0xffffffff; // end of block |
726bbb3e |
1602 | |
892b1dd2 |
1603 | if (tcache_ptr - tcache > TCACHE_SIZE/4) { |
726bbb3e |
1604 | printf("tcache overflow!\n"); |
1605 | fflush(stdout); |
1606 | exit(1); |
1607 | } |
1608 | |
1609 | // stats |
1610 | nblocks++; |
71bb1b7b |
1611 | printf("%i blocks, %i bytes, k=%.3f\n", nblocks, (tcache_ptr - tcache)*4, |
1612 | (double)(tcache_ptr - tcache) / (double)n_in_ops); |
df143b36 |
1613 | |
5d817c91 |
1614 | #ifdef DUMP_BLOCK |
5c129565 |
1615 | { |
1616 | FILE *f = fopen("tcache.bin", "wb"); |
1617 | fwrite(tcache, 1, (tcache_ptr - tcache)*4, f); |
1618 | fclose(f); |
1619 | } |
1620 | exit(0); |
1621 | #endif |
259ed0ea |
1622 | |
1623 | handle_caches(); |
1624 | |
5c129565 |
1625 | return block_start; |
726bbb3e |
1626 | } |
1627 | |
1628 | |
1629 | |
1630 | // ----------------------------------------------------- |
1631 | |
fad24893 |
1632 | static void ssp1601_state_load(void) |
1633 | { |
1634 | ssp->drc.iram_dirty = 1; |
1635 | ssp->drc.iram_context = 0; |
1636 | } |
1637 | |
e807ac75 |
1638 | int ssp1601_dyn_startup(void) |
726bbb3e |
1639 | { |
e807ac75 |
1640 | memset(tcache, 0, TCACHE_SIZE); |
726bbb3e |
1641 | memset(block_table, 0, sizeof(block_table)); |
df143b36 |
1642 | memset(block_table_iram, 0, sizeof(block_table_iram)); |
e807ac75 |
1643 | tcache_ptr = tcache; |
5c129565 |
1644 | *tcache_ptr++ = 0xffffffff; |
726bbb3e |
1645 | |
fad24893 |
1646 | PicoLoadStateHook = ssp1601_state_load; |
1647 | |
d5276282 |
1648 | #ifdef ARM |
1649 | // hle'd blocks |
1650 | block_table[0x400] = (void *) ssp_hle_800; |
71bb1b7b |
1651 | n_in_ops = 3; // # of hled ops |
d5276282 |
1652 | #endif |
1653 | |
726bbb3e |
1654 | return 0; |
1655 | } |
1656 | |
1657 | |
1658 | void ssp1601_dyn_reset(ssp1601_t *ssp) |
1659 | { |
71bb1b7b |
1660 | ssp1601_reset(ssp); |
1661 | ssp->drc.iram_dirty = 1; |
1662 | ssp->drc.iram_context = 0; |
1663 | // must do this here because ssp is not available @ startup() |
1664 | ssp->drc.ptr_rom = (u32) Pico.rom; |
1665 | ssp->drc.ptr_iram_rom = (u32) svp->iram_rom; |
1666 | ssp->drc.ptr_dram = (u32) svp->dram; |
1667 | ssp->drc.ptr_btable = (u32) block_table; |
1668 | ssp->drc.ptr_btable_iram = (u32) block_table_iram; |
726bbb3e |
1669 | } |
1670 | |
726bbb3e |
1671 | void ssp1601_dyn_run(int cycles) |
1672 | { |
b9c1d012 |
1673 | if (ssp->emu_status & SSP_WAIT_MASK) return; |
b9c1d012 |
1674 | |
fad24893 |
1675 | #ifdef DUMP_BLOCK |
1676 | ssp_translate_block(DUMP_BLOCK >> 1); |
1677 | #endif |
1678 | #ifdef ARM |
71bb1b7b |
1679 | ssp_drc_entry(cycles); |
fad24893 |
1680 | #endif |
726bbb3e |
1681 | } |
1682 | |