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1 | // basic, incomplete SSP160x (SSP1601?) interpreter |
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2 | // with SVP memory controller emu |
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3 | |
4 | // (c) Copyright 2008, Grazvydas "notaz" Ignotas |
5 | // Free for non-commercial use. |
6 | |
7 | // For commercial use, separate licencing terms must be obtained. |
8 | |
9 | |
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10 | //#define USE_DEBUGGER |
11 | /* detect ops with unimplemented/invalid fields. |
12 | * Useful for homebrew or if a new VR revision pops up. */ |
13 | //#define DO_CHECKS |
14 | |
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15 | #include "../../PicoInt.h" |
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16 | |
17 | /* |
18 | * Register info |
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19 | * |
20 | * 0. "-" |
21 | * size: 16 |
22 | * desc: Constant register with all bits set (0xffff). |
23 | * |
24 | * 1. "X" |
25 | * size: 16 |
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26 | * desc: Generic register. When set, updates P (P = X * Y * 2) |
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27 | * |
28 | * 2. "Y" |
29 | * size: 16 |
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30 | * desc: Generic register. When set, updates P (P = X * Y * 2) |
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31 | * |
32 | * 3. "A" |
33 | * size: 32 |
34 | * desc: Accumulator. |
35 | * |
36 | * 4. "ST" |
37 | * size: 16 |
38 | * desc: Status register. From MAME: bits 0-9 are CONTROL, other FLAG |
39 | * fedc ba98 7654 3210 |
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40 | * 210 - RPL (?) "Loop size". If non-zero, makes (rX+) and (rX-) respectively |
41 | * modulo-increment and modulo-decrement. The value shows which |
42 | * power of 2 to use, i.e. 4 means modulo by 16. |
43 | * (e: fir16_32.sc, IIR_4B.SC, DECIM.SC) |
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44 | * 43 - RB (?) |
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45 | * 5 - GP0_0 (ST5?) Changed before acessing PM0 (affects banking?). |
46 | * 6 - GP0_1 (ST6?) Cleared before acessing PM0 (affects banking?). Set after. |
47 | * datasheet says these (5,6) bits correspond to hardware pins. |
48 | * 7 - IE (?) Not directly used by SVP code (never set, but preserved)? |
49 | * 8 - OP (?) Not used by SVP code (only cleared)? (MAME: saturated value |
50 | * (probably means clamping? i.e. 0x7ffc + 9 -> 0x7fff)) |
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51 | * 9 - MACS (?) Not used by SVP code (only cleared)? (e: "mac shift") |
52 | * a - GPI_0 Interrupt 0 enable/status? |
53 | * b - GPI_1 Interrupt 1 enable/status? |
54 | * c - L L flag. Carry? |
55 | * d - Z Zero flag. |
56 | * e - OV Overflow flag. |
57 | * f - N Negative flag. |
58 | * seen directly changing code sequences: |
59 | * ldi ST, 0 ld A, ST ld A, ST ld A, ST ldi st, 20h |
60 | * ldi ST, 60h ori A, 60h and A, E8h and A, E8h |
61 | * ld ST, A ld ST, A ori 3 |
62 | * ld ST, A |
63 | * |
64 | * 5. "STACK" |
65 | * size: 16 |
66 | * desc: hw stack of 6 levels (according to datasheet) |
67 | * |
68 | * 6. "PC" |
69 | * size: 16 |
70 | * desc: Program counter. |
71 | * |
72 | * 7. "P" |
73 | * size: 32 |
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74 | * desc: multiply result register. P = X * Y * 2 |
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75 | * probably affected by MACS bit in ST. |
76 | * |
77 | * 8. "PM0" (PM from PMAR name from Tasco's docs) |
78 | * size: 16? |
79 | * desc: Programmable Memory access register. |
80 | * On reset, or when one (both?) GP0 bits are clear, |
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81 | * acts as status for XST, mapped at 015004 at 68k side: |
82 | * bit0: ssp has written something to XST (cleared when 015004 is read) |
83 | * bit1: 68k has written something through a1500{0|2} (cleared on PM0 read) |
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84 | * |
85 | * 9. "PM1" |
86 | * size: 16? |
87 | * desc: Programmable Memory access register. |
88 | * This reg. is only used as PMAR. |
89 | * |
90 | * 10. "PM2" |
91 | * size: 16? |
92 | * desc: Programmable Memory access register. |
93 | * This reg. is only used as PMAR. |
94 | * |
95 | * 11. "XST" |
96 | * size: 16? |
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97 | * desc: eXternal STate. Mapped to a15000 and a15002 at 68k side. |
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98 | * Can be programmed as PMAR? (only seen in test mode code) |
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99 | * Affects PM0 when written to? |
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100 | * |
101 | * 12. "PM4" |
102 | * size: 16? |
103 | * desc: Programmable Memory access register. |
104 | * This reg. is only used as PMAR. The most used PMAR by VR. |
105 | * |
106 | * 13. (unused by VR) |
107 | * |
108 | * 14. "PMC" (PMC from PMAC name from Tasco's docs) |
109 | * size: 32? |
110 | * desc: Programmable Memory access Control. Set using 2 16bit writes, |
111 | * first address, then mode word. After setting PMAC, PMAR sould |
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112 | * be blind accessed (ld -, PMx or ld PMx, -) to program it for |
113 | * reading and writing respectively. |
114 | * Reading the register also shifts it's state (from "waiting for |
115 | * address" to "waiting for mode" and back). Reads always return |
116 | * address related to last PMx register accressed. |
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117 | * (note: addresses do not wrap). |
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118 | * |
119 | * 15. "AL" |
120 | * size: 16 |
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121 | * desc: Accumulator Low. 16 least significant bits of accumulator. |
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122 | * (normally reading acc (ld X, A) you get 16 most significant bits). |
123 | * |
124 | * |
125 | * There are 8 8-bit pointer registers rX. r0-r3 (ri) point to RAM0, r4-r7 (rj) point to RAM1. |
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126 | * They can be accessed directly, or 2 indirection levels can be used [ (rX), ((rX)) ], |
127 | * which work similar to * and ** operators in C, only they use different memory banks and |
128 | * ((rX)) also does post-increment. First indirection level (rX) accesses RAMx, second accesses |
129 | * program memory at address read from (rX), and increments value in (rX). |
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130 | * |
131 | * r0,r1,r2,r4,r5,r6 can be modified [ex: ldi r0, 5]. |
132 | * 3 modifiers can be applied (optional): |
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133 | * + : post-increment [ex: ld a, (r0+) ]. Can be made modulo-increment by setting RPL bits in ST. |
134 | * - : post-decrement. Can be made modulo-decrement by setting RPL bits in ST (not sure). |
135 | * +!: post-increment, unaffected by RPL (probably). |
136 | * These are only used on 1st indirection level, so things like [ld a, ((r0+))] and [ld X, r6-] |
137 | * ar probably invalid. |
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138 | * |
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139 | * r3 and r7 are special and can not be changed (at least Samsung samples and VR code never do). |
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140 | * They are fixed to the start of their RAM banks. (They are probably changeable for ssp1605+, |
141 | * Samsung's old DSP page claims that). |
142 | * 1 of these 4 modifiers must be used (short form direct addressing?): |
143 | * |00: RAMx[0] [ex: (r3|00), 0] (based on sample code) |
144 | * |01: RAMx[1] |
145 | * |10: RAMx[2] ? maybe 10h? accortding to Div_c_dp.sc, 2 |
146 | * |11: RAMx[3] |
147 | * |
148 | * |
149 | * Instruction notes |
150 | * |
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151 | * ld a, * doesn't affect flags! (e: A_LAW.SC, Div_c_dp.sc) |
152 | * |
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153 | * mld (rj), (ri) [, b] |
154 | * operation: A = 0; P = (rj) * (ri) |
155 | * notes: based on IIR_4B.SC sample. flags? what is b??? |
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156 | * |
157 | * mpya (rj), (ri) [, b] |
158 | * name: multiply and add? |
159 | * operation: A += P; P = (rj) * (ri) |
160 | * |
161 | * mpys (rj), (ri), b |
162 | * name: multiply and subtract? |
163 | * notes: not used by VR code. |
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164 | * |
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165 | * mod cond, op |
166 | * mod cond, shr does arithmetic shift |
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167 | * |
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168 | * 'ld -, AL' and probably 'ld AL, -' are for dummy assigns |
169 | * |
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170 | * memory map: |
171 | * 000000 - 1fffff ROM, accessable by both |
172 | * 200000 - 2fffff unused? |
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173 | * 300000 - 31ffff DRAM, both |
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174 | * 320000 - 38ffff unused? |
175 | * 390000 - 3907ff IRAM. can only be accessed by ssp? |
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176 | * 390000 - 39ffff similar mapping to "cell arrange" in Sega CD, 68k only? |
177 | * 3a0000 - 3affff similar mapping to "cell arrange" in Sega CD, a bit different |
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178 | * |
179 | * 30fe02 - 0 if SVP busy, 1 if done (set by SVP, checked and cleared by 68k) |
180 | * 30fe06 - also sync related. |
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181 | * 30fe08 - job number [1-12] for SVP. 0 means no job. Set by 68k, read-cleared by VR. |
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182 | * |
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183 | * Assumptions and limitations in this code |
184 | * only Z and N status flags are emulated (others unused by VR) |
185 | * so all condition checks except N and Z are ignored (not used by VR) |
186 | * modifiers for 'OP a, ri' and ((ri)) are ignored (not used by VR) |
187 | * loop repeat mode when (ri) is destination is ignored |
188 | * ops not used by VR are not implemented |
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189 | */ |
190 | |
191 | #include "../../PicoInt.h" |
192 | |
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193 | #define u32 unsigned int |
194 | |
195 | // 0 |
196 | #define rX ssp->gr[SSP_X].h |
197 | #define rY ssp->gr[SSP_Y].h |
198 | #define rA ssp->gr[SSP_A].h |
199 | #define rST ssp->gr[SSP_ST].h // 4 |
200 | #define rSTACK ssp->gr[SSP_STACK].h |
201 | #define rPC ssp->gr[SSP_PC].h |
202 | #define rP ssp->gr[SSP_P] |
203 | #define rPM0 ssp->gr[SSP_PM0].h // 8 |
204 | #define rPM1 ssp->gr[SSP_PM1].h |
205 | #define rPM2 ssp->gr[SSP_PM2].h |
206 | #define rXST ssp->gr[SSP_XST].h |
207 | #define rPM4 ssp->gr[SSP_PM4].h // 12 |
208 | // 13 |
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209 | #define rPMC ssp->gr[SSP_PMC] // will keep addr in .l, mode in .h |
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210 | #define rAL ssp->gr[SSP_A].l |
211 | |
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212 | #define rA32 ssp->gr[SSP_A].v |
213 | #define rIJ ssp->r |
214 | |
215 | #define IJind (((op>>6)&4)|(op&3)) |
216 | |
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217 | #ifndef EMBED_INTERPRETER |
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218 | #define GET_PC() (PC - (unsigned short *)svp->iram_rom) |
219 | #define GET_PPC_OFFS() ((unsigned int)PC - (unsigned int)svp->iram_rom - 2) |
220 | #define SET_PC(d) PC = (unsigned short *)svp->iram_rom + d |
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221 | #endif |
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222 | |
223 | #define REG_READ(r) (((r) <= 4) ? ssp->gr[r].h : read_handlers[r]()) |
224 | #define REG_WRITE(r,d) { \ |
225 | int r1 = r; \ |
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226 | if (r1 >= 4) write_handlers[r1](d); \ |
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227 | else if (r1 > 0) ssp->gr[r1].h = d; \ |
228 | } |
229 | |
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230 | // flags |
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231 | #define SSP_FLAG_L (1<<0xc) |
232 | #define SSP_FLAG_Z (1<<0xd) |
233 | #define SSP_FLAG_V (1<<0xe) |
234 | #define SSP_FLAG_N (1<<0xf) |
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235 | |
236 | // update ZN according to 32bit ACC. |
237 | #define UPD_ACC_ZN \ |
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238 | rST &= ~(SSP_FLAG_Z|SSP_FLAG_N); \ |
239 | if (!rA32) rST |= SSP_FLAG_Z; \ |
240 | else rST |= (rA32>>16)&SSP_FLAG_N; |
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241 | |
242 | // it seems SVP code never checks for L and OV, so we leave them out. |
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243 | // rST |= (t>>4)&SSP_FLAG_L; |
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244 | #define UPD_LZVN \ |
245 | rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \ |
246 | if (!rA32) rST |= SSP_FLAG_Z; \ |
247 | else rST |= (rA32>>16)&SSP_FLAG_N; |
248 | |
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249 | // standard cond processing. |
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250 | // again, only Z and N is checked, as VR doesn't seem to use any other conds. |
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251 | #define COND_CHECK \ |
252 | switch (op&0xf0) { \ |
253 | case 0x00: cond = 1; break; /* always true */ \ |
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254 | case 0x50: cond = !((rST ^ (op<<5)) & SSP_FLAG_Z); break; /* Z matches f(?) bit */ \ |
255 | case 0x70: cond = !((rST ^ (op<<7)) & SSP_FLAG_N); break; /* N matches f(?) bit */ \ |
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256 | default:elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: unimplemented cond @ %04x", GET_PPC_OFFS()); break; \ |
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257 | } |
258 | |
259 | // ops with accumulator. |
260 | // how is low word really affected by these? |
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261 | // nearly sure 'ld A' doesn't affect flags |
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262 | #define OP_LDA(x) \ |
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263 | ssp->gr[SSP_A].h = x |
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264 | |
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265 | #define OP_LDA32(x) \ |
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266 | rA32 = x |
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267 | |
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268 | #define OP_SUBA(x) { \ |
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269 | rA32 -= (x) << 16; \ |
270 | UPD_LZVN \ |
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271 | } |
272 | |
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273 | #define OP_SUBA32(x) { \ |
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274 | rA32 -= (x); \ |
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275 | UPD_LZVN \ |
276 | } |
277 | |
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278 | #define OP_CMPA(x) { \ |
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279 | u32 t = rA32 - ((x) << 16); \ |
280 | rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \ |
281 | if (!t) rST |= SSP_FLAG_Z; \ |
282 | else rST |= (t>>16)&SSP_FLAG_N; \ |
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283 | } |
284 | |
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285 | #define OP_CMPA32(x) { \ |
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286 | u32 t = rA32 - (x); \ |
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287 | rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \ |
288 | if (!t) rST |= SSP_FLAG_Z; \ |
289 | else rST |= (t>>16)&SSP_FLAG_N; \ |
290 | } |
291 | |
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292 | #define OP_ADDA(x) { \ |
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293 | rA32 += (x) << 16; \ |
294 | UPD_LZVN \ |
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295 | } |
296 | |
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297 | #define OP_ADDA32(x) { \ |
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298 | rA32 += (x); \ |
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299 | UPD_LZVN \ |
300 | } |
301 | |
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302 | #define OP_ANDA(x) \ |
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303 | rA32 &= (x) << 16; \ |
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304 | UPD_ACC_ZN |
305 | |
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306 | #define OP_ANDA32(x) \ |
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307 | rA32 &= (x); \ |
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308 | UPD_ACC_ZN |
309 | |
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310 | #define OP_ORA(x) \ |
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311 | rA32 |= (x) << 16; \ |
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312 | UPD_ACC_ZN |
313 | |
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314 | #define OP_ORA32(x) \ |
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315 | rA32 |= (x); \ |
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316 | UPD_ACC_ZN |
317 | |
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318 | #define OP_EORA(x) \ |
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319 | rA32 ^= (x) << 16; \ |
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320 | UPD_ACC_ZN |
321 | |
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322 | #define OP_EORA32(x) \ |
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323 | rA32 ^= (x); \ |
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324 | UPD_ACC_ZN |
325 | |
326 | |
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327 | #define OP_CHECK32(OP) { \ |
328 | if ((op & 0x0f) == SSP_P) { /* A <- P */ \ |
329 | read_P(); /* update P */ \ |
330 | OP(rP.v); \ |
331 | break; \ |
332 | } \ |
333 | if ((op & 0x0f) == SSP_A) { /* A <- A */ \ |
334 | OP(rA32); \ |
335 | break; \ |
336 | } \ |
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337 | } |
338 | |
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339 | |
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340 | #ifdef DO_CHECKS |
341 | #define CHECK_IMM16() if (op&0x1ff) elprintf(EL_ANOMALY, "imm bits! %04x @ %04x", op, GET_PPC_OFFS()) |
342 | #define CHECK_B_SET() if (op&0x100) elprintf(EL_ANOMALY, "b set! %04x @ %04x", op, GET_PPC_OFFS()) |
343 | #define CHECK_B_CLEAR() if (!(op&0x100)) elprintf(EL_ANOMALY, "b clear! %04x @ %04x", op, GET_PPC_OFFS()) |
344 | #define CHECK_MOD() if (op&0x00c) elprintf(EL_ANOMALY, "mod bits! %04x @ %04x", op, GET_PPC_OFFS()) |
345 | #define CHECK_10f() if (op&0x10f) elprintf(EL_ANOMALY, "bits 10f! %04x @ %04x", op, GET_PPC_OFFS()) |
346 | #define CHECK_008() if (op&0x008) elprintf(EL_ANOMALY, "bits 008! %04x @ %04x", op, GET_PPC_OFFS()) |
347 | #define CHECK_00f() if (op&0x00f) elprintf(EL_ANOMALY, "bits 00f! %04x @ %04x", op, GET_PPC_OFFS()) |
348 | #define CHECK_0f0() if (op&0x0f0) elprintf(EL_ANOMALY, "bits 0f0! %04x @ %04x", op, GET_PPC_OFFS()) |
349 | #define CHECK_1f0() if (op&0x1f0) elprintf(EL_ANOMALY, "bits 1f0! %04x @ %04x", op, GET_PPC_OFFS()) |
350 | #define CHECK_RPL() if (rST&7) elprintf(EL_ANOMALY, "unhandled RPL! %04x @ %04x", op, GET_PPC_OFFS()) |
351 | #define CHECK_ST(d) if((rST^d)&0xf98)elprintf(EL_ANOMALY, "ssp FIXME ST %04x -> %04x @ %04x", rST, d, GET_PPC_OFFS()) |
352 | #else |
353 | #define CHECK_IMM16() |
354 | #define CHECK_B_SET() |
355 | #define CHECK_B_CLEAR() |
356 | #define CHECK_MOD() |
357 | #define CHECK_10f() |
358 | #define CHECK_008() |
359 | #define CHECK_00f() |
360 | #define CHECK_0f0() |
361 | #define CHECK_1f0() |
362 | #define CHECK_RPL() |
363 | #define CHECK_ST(d) |
364 | #endif |
365 | |
e807ac75 |
366 | #ifndef EMBED_INTERPRETER |
367 | static |
368 | #endif |
369 | ssp1601_t *ssp = NULL; |
017512f2 |
370 | static unsigned short *PC; |
371 | static int g_cycles; |
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372 | |
373 | #ifdef USE_DEBUGGER |
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374 | static int running = 0; |
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375 | static int last_iram = 0; |
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376 | #endif |
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377 | #ifdef EMBED_INTERPRETER |
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378 | static int iram_dirty = 0; |
12f0f94d |
379 | #endif |
017512f2 |
380 | |
381 | // ----------------------------------------------------- |
382 | // register i/o handlers |
383 | |
384 | // 0-4, 13 |
385 | static u32 read_unknown(void) |
386 | { |
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387 | elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: unknown read @ %04x", GET_PPC_OFFS()); |
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388 | return 0; |
389 | } |
390 | |
391 | static void write_unknown(u32 d) |
392 | { |
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393 | elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: unknown write @ %04x", GET_PPC_OFFS()); |
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394 | } |
395 | |
396 | // 4 |
397 | static void write_ST(u32 d) |
398 | { |
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399 | CHECK_ST(d); |
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400 | rST = d; |
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401 | } |
402 | |
403 | // 5 |
404 | static u32 read_STACK(void) |
405 | { |
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406 | --rSTACK; |
407 | if ((short)rSTACK < 0) { |
408 | rSTACK = 5; |
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409 | elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: stack underflow! (%i) @ %04x", rSTACK, GET_PPC_OFFS()); |
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410 | } |
411 | return ssp->stack[rSTACK]; |
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412 | } |
413 | |
414 | static void write_STACK(u32 d) |
415 | { |
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416 | if (rSTACK >= 6) { |
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417 | elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: stack overflow! (%i) @ %04x", rSTACK, GET_PPC_OFFS()); |
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418 | rSTACK = 0; |
419 | } |
420 | ssp->stack[rSTACK++] = d; |
017512f2 |
421 | } |
422 | |
423 | // 6 |
424 | static u32 read_PC(void) |
425 | { |
426 | return GET_PC(); |
427 | } |
428 | |
429 | static void write_PC(u32 d) |
430 | { |
431 | SET_PC(d); |
432 | g_cycles--; |
433 | } |
434 | |
435 | // 7 |
436 | static u32 read_P(void) |
437 | { |
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438 | int m1 = (signed short)rX; |
439 | int m2 = (signed short)rY; |
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440 | rP.v = (m1 * m2 * 2); |
017512f2 |
441 | return rP.h; |
442 | } |
443 | |
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444 | // ----------------------------------------------------- |
445 | |
3554b0a4 |
446 | static int get_inc(int mode) |
5de27868 |
447 | { |
3554b0a4 |
448 | int inc = (mode >> 11) & 7; |
449 | if (inc != 0) { |
450 | if (inc != 7) inc--; |
6b6a3e50 |
451 | inc = 1 << inc; // 0 1 2 4 8 16 32 128 |
3554b0a4 |
452 | if (mode & 0x8000) inc = -inc; // decrement mode |
453 | } |
454 | return inc; |
5de27868 |
455 | } |
456 | |
d26dc685 |
457 | #define overwite_write(dst, d) \ |
458 | { \ |
459 | if (d & 0xf000) { dst &= ~0xf000; dst |= d & 0xf000; } \ |
460 | if (d & 0x0f00) { dst &= ~0x0f00; dst |= d & 0x0f00; } \ |
461 | if (d & 0x00f0) { dst &= ~0x00f0; dst |= d & 0x00f0; } \ |
462 | if (d & 0x000f) { dst &= ~0x000f; dst |= d & 0x000f; } \ |
463 | } |
464 | |
017512f2 |
465 | static u32 pm_io(int reg, int write, u32 d) |
466 | { |
67256d4b |
467 | if (ssp->emu_status & SSP_PMC_SET) |
468 | { |
469 | // this MUST be blind r or w |
470 | if ((*(PC-1) & 0xff0f) && (*(PC-1) & 0xfff0)) { |
3554b0a4 |
471 | elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: tried to set PM%i (%c) with non-blind i/o %08x @ %04x", |
67256d4b |
472 | reg, write ? 'w' : 'r', rPMC.v, GET_PPC_OFFS()); |
473 | ssp->emu_status &= ~SSP_PMC_SET; |
474 | return 0; |
475 | } |
5de27868 |
476 | elprintf(EL_SVP, "PM%i (%c) set to %08x @ %04x", reg, write ? 'w' : 'r', rPMC.v, GET_PPC_OFFS()); |
017512f2 |
477 | ssp->pmac_read[write ? reg + 6 : reg] = rPMC.v; |
478 | ssp->emu_status &= ~SSP_PMC_SET; |
12f0f94d |
479 | if ((rPMC.v & 0x7fffff) == 0x1c8000 || (rPMC.v & 0x7fffff) == 0x1c8240) { |
bad5731d |
480 | elprintf(EL_SVP, "ssp IRAM copy from %06x to %04x", (ssp->RAM1[0]-1)<<1, (rPMC.v&0x7fff)<<1); |
3554b0a4 |
481 | #ifdef USE_DEBUGGER |
30752975 |
482 | last_iram = (ssp->RAM1[0]-1)<<1; |
3554b0a4 |
483 | #endif |
30752975 |
484 | } |
017512f2 |
485 | return 0; |
486 | } |
487 | |
5de27868 |
488 | // just in case |
67256d4b |
489 | if (ssp->emu_status & SSP_PMC_HAVE_ADDR) { |
3554b0a4 |
490 | elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: PM%i (%c) with only addr set @ %04x", |
67256d4b |
491 | reg, write ? 'w' : 'r', GET_PPC_OFFS()); |
492 | ssp->emu_status &= ~SSP_PMC_HAVE_ADDR; |
493 | } |
5de27868 |
494 | |
5de27868 |
495 | if (reg == 4 || (rST & 0x60)) |
496 | { |
30752975 |
497 | #define CADDR ((((mode<<16)&0x7f0000)|addr)<<1) |
d26dc685 |
498 | unsigned short *dram = (unsigned short *)svp->dram; |
5de27868 |
499 | if (write) |
500 | { |
6b6a3e50 |
501 | int mode = ssp->pmac_write[reg]>>16; |
502 | int addr = ssp->pmac_write[reg]&0xffff; |
3554b0a4 |
503 | if ((mode & 0xb800) == 0xb800) |
689fb2c0 |
504 | elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: mode %04x", mode); |
3554b0a4 |
505 | if ((mode & 0x43ff) == 0x0018) // DRAM |
506 | { |
507 | int inc = get_inc(mode); |
508 | elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (inc %i, ovrw %i)", |
6b6a3e50 |
509 | reg, CADDR, d, inc, (mode>>10)&1); |
3554b0a4 |
510 | if (mode & 0x0400) { |
511 | overwite_write(dram[addr], d); |
512 | } else dram[addr] = d; |
513 | ssp->pmac_write[reg] += inc; |
514 | } |
515 | else if ((mode & 0xfbff) == 0x4018) // DRAM, cell inc |
516 | { |
517 | elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (cell inc, ovrw %i) @ %04x", |
518 | reg, CADDR, d, (mode>>10)&1, GET_PPC_OFFS()); |
519 | if (mode & 0x0400) { |
520 | overwite_write(dram[addr], d); |
521 | } else dram[addr] = d; |
6b6a3e50 |
522 | ssp->pmac_write[reg] += (addr&1) ? 31 : 1; |
3554b0a4 |
523 | } |
524 | else if ((mode & 0x47ff) == 0x001c) // IRAM |
525 | { |
526 | int inc = get_inc(mode); |
527 | if ((addr&0xfc00) != 0x8000) |
528 | elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: invalid IRAM addr: %04x", addr<<1); |
6b6a3e50 |
529 | elprintf(EL_SVP, "ssp IRAM w [%06x] %04x (inc %i)", (addr<<1)&0x7ff, d, inc); |
3554b0a4 |
530 | ((unsigned short *)svp->iram_rom)[addr&0x3ff] = d; |
531 | ssp->pmac_write[reg] += inc; |
892b1dd2 |
532 | #ifdef EMBED_INTERPRETER |
533 | iram_dirty = 1; |
534 | #endif |
3554b0a4 |
535 | } |
536 | else |
537 | { |
538 | elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: PM%i unhandled write mode %04x, [%06x] %04x @ %04x", |
539 | reg, mode, CADDR, d, GET_PPC_OFFS()); |
5de27868 |
540 | } |
541 | } |
542 | else |
543 | { |
6b6a3e50 |
544 | int mode = ssp->pmac_read[reg]>>16; |
545 | int addr = ssp->pmac_read[reg]&0xffff; |
3554b0a4 |
546 | if ((mode & 0xfff0) == 0x0800) // ROM, inc 1, verified to be correct |
547 | { |
d26dc685 |
548 | elprintf(EL_SVP, "ssp ROM r [%06x] %04x", CADDR, |
549 | ((unsigned short *)Pico.rom)[addr|((mode&0xf)<<16)]); |
6b6a3e50 |
550 | ssp->pmac_read[reg] += 1; |
d26dc685 |
551 | d = ((unsigned short *)Pico.rom)[addr|((mode&0xf)<<16)]; |
d26dc685 |
552 | } |
3554b0a4 |
553 | else if ((mode & 0x47ff) == 0x0018) // DRAM |
554 | { |
555 | int inc = get_inc(mode); |
6b6a3e50 |
556 | elprintf(EL_SVP, "ssp PM%i DRAM r [%06x] %04x (inc %i)", reg, CADDR, dram[addr]); |
3554b0a4 |
557 | d = dram[addr]; |
558 | ssp->pmac_read[reg] += inc; |
559 | } |
560 | else |
561 | { |
562 | elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: PM%i unhandled read mode %04x, [%06x] @ %04x", |
563 | reg, mode, CADDR, GET_PPC_OFFS()); |
564 | d = 0; |
5de27868 |
565 | } |
566 | } |
30752975 |
567 | |
568 | // PMC value corresponds to last PMR accessed (not sure). |
569 | rPMC.v = ssp->pmac_read[write ? reg + 6 : reg]; |
570 | |
571 | return d; |
017512f2 |
572 | } |
573 | |
574 | return (u32)-1; |
575 | } |
576 | |
577 | // 8 |
578 | static u32 read_PM0(void) |
579 | { |
580 | u32 d = pm_io(0, 0, 0); |
581 | if (d != (u32)-1) return d; |
67256d4b |
582 | elprintf(EL_SVP, "PM0 raw r %04x @ %04x", rPM0, GET_PPC_OFFS()); |
d26dc685 |
583 | d = rPM0; |
726bbb3e |
584 | #ifndef EMBED_INTERPRETER |
d26dc685 |
585 | if (!(d & 2) && (GET_PPC_OFFS() == 0x800 || GET_PPC_OFFS() == 0x1851E)) { |
586 | ssp->emu_status |= SSP_WAIT_PM0; elprintf(EL_SVP, "det TIGHT loop: PM0"); |
587 | } |
726bbb3e |
588 | #endif |
d26dc685 |
589 | rPM0 &= ~2; // ? |
590 | return d; |
017512f2 |
591 | } |
592 | |
593 | static void write_PM0(u32 d) |
594 | { |
595 | u32 r = pm_io(0, 1, d); |
596 | if (r != (u32)-1) return; |
5de27868 |
597 | elprintf(EL_SVP, "PM0 raw w %04x @ %04x", d, GET_PPC_OFFS()); |
d26dc685 |
598 | rPM0 = d; |
017512f2 |
599 | } |
600 | |
601 | // 9 |
602 | static u32 read_PM1(void) |
603 | { |
604 | u32 d = pm_io(1, 0, 0); |
605 | if (d != (u32)-1) return d; |
606 | // can be removed? |
d4ca252d |
607 | elprintf(EL_SVP|EL_ANOMALY, "PM1 raw r %04x @ %04x", rPM1, GET_PPC_OFFS()); |
5de27868 |
608 | return rPM1; |
017512f2 |
609 | } |
610 | |
611 | static void write_PM1(u32 d) |
612 | { |
613 | u32 r = pm_io(1, 1, d); |
614 | if (r != (u32)-1) return; |
615 | // can be removed? |
d4ca252d |
616 | elprintf(EL_SVP|EL_ANOMALY, "PM1 raw w %04x @ %04x", d, GET_PPC_OFFS()); |
5de27868 |
617 | rPM1 = d; |
017512f2 |
618 | } |
619 | |
620 | // 10 |
621 | static u32 read_PM2(void) |
622 | { |
623 | u32 d = pm_io(2, 0, 0); |
624 | if (d != (u32)-1) return d; |
625 | // can be removed? |
d4ca252d |
626 | elprintf(EL_SVP|EL_ANOMALY, "PM2 raw r %04x @ %04x", rPM2, GET_PPC_OFFS()); |
5de27868 |
627 | return rPM2; |
017512f2 |
628 | } |
629 | |
630 | static void write_PM2(u32 d) |
631 | { |
632 | u32 r = pm_io(2, 1, d); |
633 | if (r != (u32)-1) return; |
634 | // can be removed? |
d4ca252d |
635 | elprintf(EL_SVP|EL_ANOMALY, "PM2 raw w %04x @ %04x", d, GET_PPC_OFFS()); |
5de27868 |
636 | rPM2 = d; |
017512f2 |
637 | } |
638 | |
639 | // 11 |
640 | static u32 read_XST(void) |
641 | { |
642 | // can be removed? |
643 | u32 d = pm_io(3, 0, 0); |
644 | if (d != (u32)-1) return d; |
645 | |
5de27868 |
646 | elprintf(EL_SVP, "XST raw r %04x @ %04x", rXST, GET_PPC_OFFS()); |
647 | return rXST; |
017512f2 |
648 | } |
f8ef8ff7 |
649 | |
017512f2 |
650 | static void write_XST(u32 d) |
f8ef8ff7 |
651 | { |
017512f2 |
652 | // can be removed? |
653 | u32 r = pm_io(3, 1, d); |
654 | if (r != (u32)-1) return; |
655 | |
5de27868 |
656 | elprintf(EL_SVP, "XST raw w %04x @ %04x", d, GET_PPC_OFFS()); |
d26dc685 |
657 | rPM0 |= 1; |
5de27868 |
658 | rXST = d; |
017512f2 |
659 | } |
660 | |
661 | // 12 |
662 | static u32 read_PM4(void) |
663 | { |
664 | u32 d = pm_io(4, 0, 0); |
726bbb3e |
665 | #ifndef EMBED_INTERPRETER |
30752975 |
666 | if (d == 0) { |
667 | switch (GET_PPC_OFFS()) { |
d26dc685 |
668 | case 0x0854: ssp->emu_status |= SSP_WAIT_30FE08; elprintf(EL_SVP, "det TIGHT loop: [30fe08]"); break; |
669 | case 0x4f12: ssp->emu_status |= SSP_WAIT_30FE06; elprintf(EL_SVP, "det TIGHT loop: [30fe06]"); break; |
30752975 |
670 | } |
671 | } |
726bbb3e |
672 | #endif |
017512f2 |
673 | if (d != (u32)-1) return d; |
674 | // can be removed? |
d4ca252d |
675 | elprintf(EL_SVP|EL_ANOMALY, "PM4 raw r %04x @ %04x", rPM4, GET_PPC_OFFS()); |
5de27868 |
676 | return rPM4; |
017512f2 |
677 | } |
678 | |
679 | static void write_PM4(u32 d) |
680 | { |
681 | u32 r = pm_io(4, 1, d); |
682 | if (r != (u32)-1) return; |
683 | // can be removed? |
d4ca252d |
684 | elprintf(EL_SVP|EL_ANOMALY, "PM4 raw w %04x @ %04x", d, GET_PPC_OFFS()); |
5de27868 |
685 | rPM4 = d; |
017512f2 |
686 | } |
687 | |
688 | // 14 |
689 | static u32 read_PMC(void) |
690 | { |
6b6a3e50 |
691 | elprintf(EL_SVP, "PMC r a %04x (st %c) @ %04x", rPMC.l, |
3554b0a4 |
692 | (ssp->emu_status & SSP_PMC_HAVE_ADDR) ? 'm' : 'a', GET_PPC_OFFS()); |
017512f2 |
693 | if (ssp->emu_status & SSP_PMC_HAVE_ADDR) { |
3554b0a4 |
694 | //if (ssp->emu_status & SSP_PMC_SET) |
695 | // elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS()); |
017512f2 |
696 | ssp->emu_status |= SSP_PMC_SET; |
5de27868 |
697 | ssp->emu_status &= ~SSP_PMC_HAVE_ADDR; |
6b6a3e50 |
698 | return ((rPMC.l << 4) & 0xfff0) | ((rPMC.l >> 4) & 0xf); |
017512f2 |
699 | } else { |
700 | ssp->emu_status |= SSP_PMC_HAVE_ADDR; |
6b6a3e50 |
701 | return rPMC.l; |
017512f2 |
702 | } |
703 | } |
704 | |
705 | static void write_PMC(u32 d) |
706 | { |
707 | if (ssp->emu_status & SSP_PMC_HAVE_ADDR) { |
3554b0a4 |
708 | //if (ssp->emu_status & SSP_PMC_SET) |
709 | // elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS()); |
017512f2 |
710 | ssp->emu_status |= SSP_PMC_SET; |
5de27868 |
711 | ssp->emu_status &= ~SSP_PMC_HAVE_ADDR; |
6b6a3e50 |
712 | rPMC.h = d; |
713 | elprintf(EL_SVP, "PMC w m %04x @ %04x", rPMC.h, GET_PPC_OFFS()); |
017512f2 |
714 | } else { |
715 | ssp->emu_status |= SSP_PMC_HAVE_ADDR; |
6b6a3e50 |
716 | rPMC.l = d; |
717 | elprintf(EL_SVP, "PMC w a %04x @ %04x", rPMC.l, GET_PPC_OFFS()); |
017512f2 |
718 | } |
719 | } |
720 | |
721 | // 15 |
722 | static u32 read_AL(void) |
723 | { |
67256d4b |
724 | if (*(PC-1) == 0x000f) { |
689fb2c0 |
725 | elprintf(EL_SVP, "ssp dummy PM assign %08x @ %04x", rPMC.v, GET_PPC_OFFS()); |
67256d4b |
726 | ssp->emu_status &= ~(SSP_PMC_SET|SSP_PMC_HAVE_ADDR); // ? |
67256d4b |
727 | } |
017512f2 |
728 | return rAL; |
729 | } |
730 | |
731 | static void write_AL(u32 d) |
732 | { |
733 | rAL = d; |
734 | } |
735 | |
736 | |
737 | typedef u32 (*read_func_t)(void); |
738 | typedef void (*write_func_t)(u32 d); |
739 | |
740 | static read_func_t read_handlers[16] = |
741 | { |
742 | read_unknown, read_unknown, read_unknown, read_unknown, // -, X, Y, A |
743 | read_unknown, // 4 ST |
744 | read_STACK, |
745 | read_PC, |
746 | read_P, |
747 | read_PM0, // 8 |
748 | read_PM1, |
749 | read_PM2, |
750 | read_XST, |
751 | read_PM4, // 12 |
752 | read_unknown, // 13 gr13 |
753 | read_PMC, |
754 | read_AL |
755 | }; |
756 | |
757 | static write_func_t write_handlers[16] = |
758 | { |
759 | write_unknown, write_unknown, write_unknown, write_unknown, // -, X, Y, A |
5de27868 |
760 | // write_unknown, // 4 ST |
761 | write_ST, // 4 ST (debug hook) |
017512f2 |
762 | write_STACK, |
763 | write_PC, |
764 | write_unknown, // 7 P |
765 | write_PM0, // 8 |
766 | write_PM1, |
767 | write_PM2, |
768 | write_XST, |
769 | write_PM4, // 12 |
770 | write_unknown, // 13 gr13 |
771 | write_PMC, |
772 | write_AL |
773 | }; |
774 | |
5de27868 |
775 | // ----------------------------------------------------- |
776 | // pointer register handlers |
777 | |
778 | // |
779 | #define ptr1_read(op) ptr1_read_(op&3,(op>>6)&4,(op<<1)&0x18) |
780 | |
781 | static u32 ptr1_read_(int ri, int isj2, int modi3) |
782 | { |
783 | //int t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18); |
30752975 |
784 | u32 mask, add = 0, t = ri | isj2 | modi3; |
785 | unsigned char *rp = NULL; |
5de27868 |
786 | switch (t) |
787 | { |
788 | // mod=0 (00) |
789 | case 0x00: |
790 | case 0x01: |
791 | case 0x02: return ssp->RAM0[ssp->r0[t&3]]; |
792 | case 0x03: return ssp->RAM0[0]; |
793 | case 0x04: |
794 | case 0x05: |
795 | case 0x06: return ssp->RAM1[ssp->r1[t&3]]; |
796 | case 0x07: return ssp->RAM1[0]; |
797 | // mod=1 (01), "+!" |
5de27868 |
798 | case 0x08: |
5de27868 |
799 | case 0x09: |
30752975 |
800 | case 0x0a: return ssp->RAM0[ssp->r0[t&3]++]; |
5de27868 |
801 | case 0x0b: return ssp->RAM0[1]; |
802 | case 0x0c: |
5de27868 |
803 | case 0x0d: |
30752975 |
804 | case 0x0e: return ssp->RAM1[ssp->r1[t&3]++]; |
5de27868 |
805 | case 0x0f: return ssp->RAM1[1]; |
806 | // mod=2 (10), "-" |
807 | case 0x10: |
808 | case 0x11: |
30752975 |
809 | case 0x12: rp = &ssp->r0[t&3]; t = ssp->RAM0[*rp]; |
810 | if (!(rST&7)) { (*rp)--; return t; } |
811 | add = -1; goto modulo; |
5de27868 |
812 | case 0x13: return ssp->RAM0[2]; |
813 | case 0x14: |
814 | case 0x15: |
30752975 |
815 | case 0x16: rp = &ssp->r1[t&3]; t = ssp->RAM1[*rp]; |
816 | if (!(rST&7)) { (*rp)--; return t; } |
817 | add = -1; goto modulo; |
5de27868 |
818 | case 0x17: return ssp->RAM1[2]; |
30752975 |
819 | // mod=3 (11), "+" |
820 | case 0x18: |
821 | case 0x19: |
822 | case 0x1a: rp = &ssp->r0[t&3]; t = ssp->RAM0[*rp]; |
823 | if (!(rST&7)) { (*rp)++; return t; } |
824 | add = 1; goto modulo; |
5de27868 |
825 | case 0x1b: return ssp->RAM0[3]; |
30752975 |
826 | case 0x1c: |
827 | case 0x1d: |
828 | case 0x1e: rp = &ssp->r1[t&3]; t = ssp->RAM1[*rp]; |
829 | if (!(rST&7)) { (*rp)++; return t; } |
830 | add = 1; goto modulo; |
5de27868 |
831 | case 0x1f: return ssp->RAM1[3]; |
832 | } |
833 | |
834 | return 0; |
30752975 |
835 | |
836 | modulo: |
837 | mask = (1 << (rST&7)) - 1; |
838 | *rp = (*rp & ~mask) | ((*rp + add) & mask); |
839 | return t; |
5de27868 |
840 | } |
841 | |
842 | static void ptr1_write(int op, u32 d) |
843 | { |
844 | int t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18); |
845 | switch (t) |
846 | { |
847 | // mod=0 (00) |
848 | case 0x00: |
849 | case 0x01: |
850 | case 0x02: ssp->RAM0[ssp->r0[t&3]] = d; return; |
851 | case 0x03: ssp->RAM0[0] = d; return; |
852 | case 0x04: |
853 | case 0x05: |
854 | case 0x06: ssp->RAM1[ssp->r1[t&3]] = d; return; |
855 | case 0x07: ssp->RAM1[0] = d; return; |
856 | // mod=1 (01), "+!" |
857 | // mod=3, "+" |
858 | case 0x08: |
5de27868 |
859 | case 0x09: |
e477f8f7 |
860 | case 0x0a: ssp->RAM0[ssp->r0[t&3]++] = d; return; |
5de27868 |
861 | case 0x0b: ssp->RAM0[1] = d; return; |
862 | case 0x0c: |
5de27868 |
863 | case 0x0d: |
e477f8f7 |
864 | case 0x0e: ssp->RAM1[ssp->r1[t&3]++] = d; return; |
5de27868 |
865 | case 0x0f: ssp->RAM1[1] = d; return; |
866 | // mod=2 (10), "-" |
867 | case 0x10: |
868 | case 0x11: |
e477f8f7 |
869 | case 0x12: ssp->RAM0[ssp->r0[t&3]--] = d; CHECK_RPL(); return; |
5de27868 |
870 | case 0x13: ssp->RAM0[2] = d; return; |
871 | case 0x14: |
872 | case 0x15: |
e477f8f7 |
873 | case 0x16: ssp->RAM1[ssp->r1[t&3]--] = d; CHECK_RPL(); return; |
5de27868 |
874 | case 0x17: ssp->RAM1[2] = d; return; |
e477f8f7 |
875 | // mod=3 (11), "+" |
876 | case 0x18: |
877 | case 0x19: |
878 | case 0x1a: ssp->RAM0[ssp->r0[t&3]++] = d; CHECK_RPL(); return; |
5de27868 |
879 | case 0x1b: ssp->RAM0[3] = d; return; |
e477f8f7 |
880 | case 0x1c: |
881 | case 0x1d: |
882 | case 0x1e: ssp->RAM1[ssp->r1[t&3]++] = d; CHECK_RPL(); return; |
5de27868 |
883 | case 0x1f: ssp->RAM1[3] = d; return; |
884 | } |
885 | } |
886 | |
887 | static u32 ptr2_read(int op) |
888 | { |
889 | int mv = 0, t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18); |
890 | switch (t) |
891 | { |
892 | // mod=0 (00) |
893 | case 0x00: |
894 | case 0x01: |
895 | case 0x02: mv = ssp->RAM0[ssp->r0[t&3]]++; break; |
896 | case 0x03: mv = ssp->RAM0[0]++; break; |
897 | case 0x04: |
898 | case 0x05: |
899 | case 0x06: mv = ssp->RAM1[ssp->r1[t&3]]++; break; |
900 | case 0x07: mv = ssp->RAM1[0]++; break; |
901 | // mod=1 (01) |
902 | case 0x0b: mv = ssp->RAM0[1]++; break; |
903 | case 0x0f: mv = ssp->RAM1[1]++; break; |
904 | // mod=2 (10) |
905 | case 0x13: mv = ssp->RAM0[2]++; break; |
906 | case 0x17: mv = ssp->RAM1[2]++; break; |
907 | // mod=3 (11) |
908 | case 0x1b: mv = ssp->RAM0[3]++; break; |
909 | case 0x1f: mv = ssp->RAM1[3]++; break; |
30752975 |
910 | default: elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: invalid mod in ((rX))? @ %04x", GET_PPC_OFFS()); |
5de27868 |
911 | return 0; |
912 | } |
913 | |
914 | return ((unsigned short *)svp->iram_rom)[mv]; |
915 | } |
916 | |
917 | |
918 | // ----------------------------------------------------- |
919 | |
df143b36 |
920 | #if defined(USE_DEBUGGER) //|| defined(EMBED_INTERPRETER) |
726bbb3e |
921 | static void debug_dump2file(const char *fname, void *mem, int len) |
922 | { |
923 | FILE *f = fopen(fname, "wb"); |
924 | unsigned short *p = mem; |
925 | int i; |
926 | if (f) { |
927 | for (i = 0; i < len/2; i++) p[i] = (p[i]<<8) | (p[i]>>8); |
928 | fwrite(mem, 1, len, f); |
929 | fclose(f); |
930 | for (i = 0; i < len/2; i++) p[i] = (p[i]<<8) | (p[i]>>8); |
931 | printf("dumped to %s\n", fname); |
932 | } |
933 | else |
934 | printf("dump failed\n"); |
935 | } |
936 | #endif |
937 | |
3554b0a4 |
938 | #ifdef USE_DEBUGGER |
5de27868 |
939 | static void debug_dump(void) |
f8ef8ff7 |
940 | { |
5de27868 |
941 | printf("GR0: %04x X: %04x Y: %04x A: %08x\n", ssp->gr[SSP_GR0].h, rX, rY, ssp->gr[SSP_A].v); |
6b6a3e50 |
942 | printf("PC: %04x (%04x) P: %08x\n", GET_PC(), GET_PC() << 1, rP.v); |
5de27868 |
943 | printf("PM0: %04x PM1: %04x PM2: %04x\n", rPM0, rPM1, rPM2); |
6b6a3e50 |
944 | printf("XST: %04x PM4: %04x PMC: %08x\n", rXST, rPM4, rPMC.v); |
d26dc685 |
945 | printf(" ST: %04x %c%c%c%c, GP0_0 %i, GP0_1 %i\n", rST, rST&SSP_FLAG_N?'N':'n', rST&SSP_FLAG_V?'V':'v', |
946 | rST&SSP_FLAG_Z?'Z':'z', rST&SSP_FLAG_L?'L':'l', (rST>>5)&1, (rST>>6)&1); |
5de27868 |
947 | printf("STACK: %i %04x %04x %04x %04x %04x %04x\n", rSTACK, ssp->stack[0], ssp->stack[1], |
948 | ssp->stack[2], ssp->stack[3], ssp->stack[4], ssp->stack[5]); |
949 | printf("r0-r2: %02x %02x %02x r4-r6: %02x %02x %02x\n", rIJ[0], rIJ[1], rIJ[2], rIJ[4], rIJ[5], rIJ[6]); |
950 | elprintf(EL_SVP, "cycles: %i, emu_status: %x", g_cycles, ssp->emu_status); |
951 | } |
f8ef8ff7 |
952 | |
5de27868 |
953 | static void debug_dump_mem(void) |
954 | { |
955 | int h, i; |
956 | printf("RAM0\n"); |
957 | for (h = 0; h < 32; h++) |
958 | { |
959 | if (h == 16) printf("RAM1\n"); |
960 | printf("%03x:", h*16); |
961 | for (i = 0; i < 16; i++) |
962 | printf(" %04x", ssp->RAM[h*16+i]); |
963 | printf("\n"); |
964 | } |
965 | } |
966 | |
967 | static int bpts[10] = { 0, }; |
968 | |
969 | static void debug(unsigned int pc, unsigned int op) |
970 | { |
971 | static char buffo[64] = {0,}; |
972 | char buff[64] = {0,}; |
973 | int i; |
974 | |
975 | if (running) { |
976 | for (i = 0; i < 10; i++) |
977 | if (pc != 0 && bpts[i] == pc) { |
978 | printf("breakpoint %i\n", i); |
979 | running = 0; |
980 | break; |
981 | } |
982 | } |
983 | if (running) return; |
984 | |
985 | printf("%04x (%02x) @ %04x\n", op, op >> 9, pc<<1); |
986 | |
987 | while (1) |
988 | { |
989 | printf("dbg> "); |
990 | fflush(stdout); |
991 | fgets(buff, sizeof(buff), stdin); |
992 | if (buff[0] == '\n') strcpy(buff, buffo); |
993 | else strcpy(buffo, buff); |
994 | |
995 | switch (buff[0]) { |
996 | case 0: exit(0); |
997 | case 'c': |
998 | case 'r': running = 1; return; |
999 | case 's': |
1000 | case 'n': return; |
1001 | case 'x': debug_dump(); break; |
1002 | case 'm': debug_dump_mem(); break; |
1003 | case 'b': { |
1004 | char *baddr = buff + 2; |
1005 | i = 0; |
1006 | if (buff[3] == ' ') { i = buff[2] - '0'; baddr = buff + 4; } |
1007 | bpts[i] = strtol(baddr, NULL, 16) >> 1; |
1008 | printf("breakpoint %i set @ %04x\n", i, bpts[i]<<1); |
1009 | break; |
1010 | } |
30752975 |
1011 | case 'd': |
1012 | sprintf(buff, "iramrom_%04x.bin", last_iram); |
1013 | debug_dump2file(buff, svp->iram_rom, sizeof(svp->iram_rom)); |
1014 | debug_dump2file("dram.bin", svp->dram, sizeof(svp->dram)); |
5de27868 |
1015 | break; |
5de27868 |
1016 | default: printf("unknown command\n"); break; |
1017 | } |
1018 | } |
1019 | } |
3554b0a4 |
1020 | #endif // USE_DEBUGGER |
1021 | |
5de27868 |
1022 | |
6b6a3e50 |
1023 | void ssp1601_reset(ssp1601_t *l_ssp) |
1024 | { |
1025 | ssp = l_ssp; |
1026 | ssp->emu_status = 0; |
1027 | ssp->gr[SSP_GR0].v = 0xffff0000; |
1028 | rPC = 0x400; |
1029 | rSTACK = 0; // ? using ascending stack |
1030 | rST = 0; |
1031 | } |
1032 | |
1033 | |
5de27868 |
1034 | void ssp1601_run(int cycles) |
1035 | { |
726bbb3e |
1036 | #ifndef EMBED_INTERPRETER |
017512f2 |
1037 | SET_PC(rPC); |
726bbb3e |
1038 | #endif |
017512f2 |
1039 | g_cycles = cycles; |
f8ef8ff7 |
1040 | |
d26dc685 |
1041 | while (g_cycles > 0 && !(ssp->emu_status & SSP_WAIT_MASK)) |
f8ef8ff7 |
1042 | { |
5de27868 |
1043 | int op; |
1044 | u32 tmpv; |
1045 | |
1046 | op = *PC++; |
3554b0a4 |
1047 | #ifdef USE_DEBUGGER |
5de27868 |
1048 | debug(GET_PC()-1, op); |
3554b0a4 |
1049 | #endif |
f8ef8ff7 |
1050 | switch (op >> 9) |
1051 | { |
1052 | // ld d, s |
5de27868 |
1053 | case 0x00: |
e477f8f7 |
1054 | CHECK_B_SET(); |
f8ef8ff7 |
1055 | if (op == 0) break; // nop |
017512f2 |
1056 | if (op == ((SSP_A<<4)|SSP_P)) { // A <- P |
1057 | // not sure. MAME claims that only hi word is transfered. |
1058 | read_P(); // update P |
6b6a3e50 |
1059 | rA32 = rP.v; |
f8ef8ff7 |
1060 | } |
5de27868 |
1061 | else |
f8ef8ff7 |
1062 | { |
5de27868 |
1063 | tmpv = REG_READ(op & 0x0f); |
1064 | REG_WRITE((op & 0xf0) >> 4, tmpv); |
1065 | } |
1066 | break; |
1067 | |
1068 | // ld d, (ri) |
1069 | case 0x01: tmpv = ptr1_read(op); REG_WRITE((op & 0xf0) >> 4, tmpv); break; |
1070 | |
1071 | // ld (ri), s |
1072 | case 0x02: tmpv = REG_READ((op & 0xf0) >> 4); ptr1_write(op, tmpv); break; |
1073 | |
1074 | // ldi d, imm |
e477f8f7 |
1075 | case 0x04: CHECK_10f(); tmpv = *PC++; REG_WRITE((op & 0xf0) >> 4, tmpv); g_cycles--; break; |
5de27868 |
1076 | |
1077 | // ld d, ((ri)) |
e477f8f7 |
1078 | case 0x05: CHECK_MOD(); tmpv = ptr2_read(op); REG_WRITE((op & 0xf0) >> 4, tmpv); g_cycles -= 2; break; |
5de27868 |
1079 | |
1080 | // ldi (ri), imm |
e477f8f7 |
1081 | case 0x06: tmpv = *PC++; ptr1_write(op, tmpv); g_cycles--; break; |
5de27868 |
1082 | |
1083 | // ld adr, a |
1084 | case 0x07: ssp->RAM[op & 0x1ff] = rA; break; |
1085 | |
1086 | // ld d, ri |
e477f8f7 |
1087 | case 0x09: CHECK_MOD(); tmpv = rIJ[(op&3)|((op>>6)&4)]; REG_WRITE((op & 0xf0) >> 4, tmpv); break; |
5de27868 |
1088 | |
1089 | // ld ri, s |
e477f8f7 |
1090 | case 0x0a: CHECK_MOD(); rIJ[(op&3)|((op>>6)&4)] = REG_READ((op & 0xf0) >> 4); break; |
5de27868 |
1091 | |
1092 | // ldi ri, simm |
1093 | case 0x0c: |
1094 | case 0x0d: |
1095 | case 0x0e: |
1096 | case 0x0f: rIJ[(op>>8)&7] = op; break; |
1097 | |
1098 | // call cond, addr |
1099 | case 0x24: { |
1100 | int cond = 0; |
e477f8f7 |
1101 | CHECK_00f(); |
5de27868 |
1102 | COND_CHECK |
e477f8f7 |
1103 | if (cond) { int new_PC = *PC++; write_STACK(GET_PC()); SET_PC(new_PC); } |
5de27868 |
1104 | else PC++; |
e477f8f7 |
1105 | g_cycles--; // always 2 cycles |
5de27868 |
1106 | break; |
1107 | } |
1108 | |
1109 | // ld d, (a) |
e477f8f7 |
1110 | case 0x25: |
1111 | CHECK_10f(); |
1112 | tmpv = ((unsigned short *)svp->iram_rom)[rA]; |
1113 | REG_WRITE((op & 0xf0) >> 4, tmpv); |
1114 | g_cycles -= 2; // 3 cycles total |
1115 | break; |
5de27868 |
1116 | |
1117 | // bra cond, addr |
1118 | case 0x26: { |
1119 | int cond = 0; |
e477f8f7 |
1120 | CHECK_00f(); |
5de27868 |
1121 | COND_CHECK |
e477f8f7 |
1122 | if (cond) { int new_PC = *PC++; SET_PC(new_PC); } |
5de27868 |
1123 | else PC++; |
e477f8f7 |
1124 | g_cycles--; |
5de27868 |
1125 | break; |
1126 | } |
1127 | |
1128 | // mod cond, op |
1129 | case 0x48: { |
1130 | int cond = 0; |
e477f8f7 |
1131 | CHECK_008(); |
5de27868 |
1132 | COND_CHECK |
1133 | if (cond) { |
1134 | switch (op & 7) { |
d26dc685 |
1135 | case 2: rA32 = (signed int)rA32 >> 1; break; // shr (arithmetic) |
5de27868 |
1136 | case 3: rA32 <<= 1; break; // shl |
d26dc685 |
1137 | case 6: rA32 = -(signed int)rA32; break; // neg |
1138 | case 7: if ((int)rA32 < 0) rA32 = -(signed int)rA32; break; // abs |
689fb2c0 |
1139 | default: elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: unhandled mod %i @ %04x", |
1140 | op&7, GET_PPC_OFFS()); |
5de27868 |
1141 | } |
e477f8f7 |
1142 | UPD_ACC_ZN |
f8ef8ff7 |
1143 | } |
1144 | break; |
5de27868 |
1145 | } |
1146 | |
689fb2c0 |
1147 | // mpys? |
30752975 |
1148 | case 0x1b: |
e477f8f7 |
1149 | CHECK_B_CLEAR(); |
30752975 |
1150 | read_P(); // update P |
e477f8f7 |
1151 | rA32 -= rP.v; |
1152 | UPD_ACC_ZN |
1153 | rX = ptr1_read_(op&3, 0, (op<<1)&0x18); |
1154 | rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); |
3554b0a4 |
1155 | break; |
1156 | |
5de27868 |
1157 | // mpya (rj), (ri), b |
1158 | case 0x4b: |
e477f8f7 |
1159 | CHECK_B_CLEAR(); |
5de27868 |
1160 | read_P(); // update P |
e477f8f7 |
1161 | rA32 += rP.v; |
1162 | UPD_ACC_ZN |
1163 | rX = ptr1_read_(op&3, 0, (op<<1)&0x18); |
1164 | rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); |
5de27868 |
1165 | break; |
1166 | |
1167 | // mld (rj), (ri), b |
1168 | case 0x5b: |
e477f8f7 |
1169 | CHECK_B_CLEAR(); |
3554b0a4 |
1170 | rA32 = 0; |
e477f8f7 |
1171 | rST &= 0x0fff; |
1172 | rST |= SSP_FLAG_Z; |
1173 | rX = ptr1_read_(op&3, 0, (op<<1)&0x18); |
1174 | rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); |
5de27868 |
1175 | break; |
1176 | |
1177 | // OP a, s |
e477f8f7 |
1178 | case 0x10: CHECK_1f0(); OP_CHECK32(OP_SUBA32); tmpv = REG_READ(op & 0x0f); OP_SUBA(tmpv); break; |
1179 | case 0x30: CHECK_1f0(); OP_CHECK32(OP_CMPA32); tmpv = REG_READ(op & 0x0f); OP_CMPA(tmpv); break; |
1180 | case 0x40: CHECK_1f0(); OP_CHECK32(OP_ADDA32); tmpv = REG_READ(op & 0x0f); OP_ADDA(tmpv); break; |
1181 | case 0x50: CHECK_1f0(); OP_CHECK32(OP_ANDA32); tmpv = REG_READ(op & 0x0f); OP_ANDA(tmpv); break; |
1182 | case 0x60: CHECK_1f0(); OP_CHECK32(OP_ORA32 ); tmpv = REG_READ(op & 0x0f); OP_ORA (tmpv); break; |
1183 | case 0x70: CHECK_1f0(); OP_CHECK32(OP_EORA32); tmpv = REG_READ(op & 0x0f); OP_EORA(tmpv); break; |
5de27868 |
1184 | |
1185 | // OP a, (ri) |
e477f8f7 |
1186 | case 0x11: CHECK_0f0(); tmpv = ptr1_read(op); OP_SUBA(tmpv); break; |
1187 | case 0x31: CHECK_0f0(); tmpv = ptr1_read(op); OP_CMPA(tmpv); break; |
1188 | case 0x41: CHECK_0f0(); tmpv = ptr1_read(op); OP_ADDA(tmpv); break; |
1189 | case 0x51: CHECK_0f0(); tmpv = ptr1_read(op); OP_ANDA(tmpv); break; |
1190 | case 0x61: CHECK_0f0(); tmpv = ptr1_read(op); OP_ORA (tmpv); break; |
1191 | case 0x71: CHECK_0f0(); tmpv = ptr1_read(op); OP_EORA(tmpv); break; |
5de27868 |
1192 | |
1193 | // OP a, adr |
1194 | case 0x03: tmpv = ssp->RAM[op & 0x1ff]; OP_LDA (tmpv); break; |
1195 | case 0x13: tmpv = ssp->RAM[op & 0x1ff]; OP_SUBA(tmpv); break; |
1196 | case 0x33: tmpv = ssp->RAM[op & 0x1ff]; OP_CMPA(tmpv); break; |
1197 | case 0x43: tmpv = ssp->RAM[op & 0x1ff]; OP_ADDA(tmpv); break; |
1198 | case 0x53: tmpv = ssp->RAM[op & 0x1ff]; OP_ANDA(tmpv); break; |
1199 | case 0x63: tmpv = ssp->RAM[op & 0x1ff]; OP_ORA (tmpv); break; |
1200 | case 0x73: tmpv = ssp->RAM[op & 0x1ff]; OP_EORA(tmpv); break; |
1201 | |
1202 | // OP a, imm |
e477f8f7 |
1203 | case 0x14: CHECK_IMM16(); tmpv = *PC++; OP_SUBA(tmpv); g_cycles--; break; |
1204 | case 0x34: CHECK_IMM16(); tmpv = *PC++; OP_CMPA(tmpv); g_cycles--; break; |
1205 | case 0x44: CHECK_IMM16(); tmpv = *PC++; OP_ADDA(tmpv); g_cycles--; break; |
1206 | case 0x54: CHECK_IMM16(); tmpv = *PC++; OP_ANDA(tmpv); g_cycles--; break; |
1207 | case 0x64: CHECK_IMM16(); tmpv = *PC++; OP_ORA (tmpv); g_cycles--; break; |
1208 | case 0x74: CHECK_IMM16(); tmpv = *PC++; OP_EORA(tmpv); g_cycles--; break; |
5de27868 |
1209 | |
1210 | // OP a, ((ri)) |
e477f8f7 |
1211 | case 0x15: CHECK_MOD(); tmpv = ptr2_read(op); OP_SUBA(tmpv); g_cycles -= 2; break; |
1212 | case 0x35: CHECK_MOD(); tmpv = ptr2_read(op); OP_CMPA(tmpv); g_cycles -= 2; break; |
1213 | case 0x45: CHECK_MOD(); tmpv = ptr2_read(op); OP_ADDA(tmpv); g_cycles -= 2; break; |
1214 | case 0x55: CHECK_MOD(); tmpv = ptr2_read(op); OP_ANDA(tmpv); g_cycles -= 2; break; |
1215 | case 0x65: CHECK_MOD(); tmpv = ptr2_read(op); OP_ORA (tmpv); g_cycles -= 2; break; |
1216 | case 0x75: CHECK_MOD(); tmpv = ptr2_read(op); OP_EORA(tmpv); g_cycles -= 2; break; |
5de27868 |
1217 | |
1218 | // OP a, ri |
e477f8f7 |
1219 | case 0x19: CHECK_MOD(); tmpv = rIJ[IJind]; OP_SUBA(tmpv); break; |
1220 | case 0x39: CHECK_MOD(); tmpv = rIJ[IJind]; OP_CMPA(tmpv); break; |
1221 | case 0x49: CHECK_MOD(); tmpv = rIJ[IJind]; OP_ADDA(tmpv); break; |
1222 | case 0x59: CHECK_MOD(); tmpv = rIJ[IJind]; OP_ANDA(tmpv); break; |
1223 | case 0x69: CHECK_MOD(); tmpv = rIJ[IJind]; OP_ORA (tmpv); break; |
1224 | case 0x79: CHECK_MOD(); tmpv = rIJ[IJind]; OP_EORA(tmpv); break; |
5de27868 |
1225 | |
1226 | // OP simm |
e477f8f7 |
1227 | case 0x1c: CHECK_B_SET(); OP_SUBA(op & 0xff); break; |
1228 | case 0x3c: CHECK_B_SET(); OP_CMPA(op & 0xff); break; |
1229 | case 0x4c: CHECK_B_SET(); OP_ADDA(op & 0xff); break; |
1230 | case 0x5c: CHECK_B_SET(); OP_ANDA(op & 0xff); break; |
1231 | case 0x6c: CHECK_B_SET(); OP_ORA (op & 0xff); break; |
1232 | case 0x7c: CHECK_B_SET(); OP_EORA(op & 0xff); break; |
f8ef8ff7 |
1233 | |
1234 | default: |
3554b0a4 |
1235 | elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME unhandled op %04x @ %04x", op, GET_PPC_OFFS()); |
017512f2 |
1236 | break; |
f8ef8ff7 |
1237 | } |
017512f2 |
1238 | g_cycles--; |
f8ef8ff7 |
1239 | } |
1240 | |
1241 | rPC = GET_PC(); |
726bbb3e |
1242 | read_P(); // update P |
f8ef8ff7 |
1243 | } |
1244 | |