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[picodrive.git] / Pico / carthw / svp / ssp16.c
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f8ef8ff7 1// basic, incomplete SSP160x (SSP1601?) interpreter
2
3/*
4 * Register info
5 * most names taken from MAME code
6 *
7 * 0. "-"
8 * size: 16
9 * desc: Constant register with all bits set (0xffff).
10 *
11 * 1. "X"
12 * size: 16
13 * desc: Generic register. When set, updates P (P = X * Y * 2) ??
14 *
15 * 2. "Y"
16 * size: 16
17 * desc: Generic register. When set, updates P (P = X * Y * 2) ??
18 *
19 * 3. "A"
20 * size: 32
21 * desc: Accumulator.
22 *
23 * 4. "ST"
24 * size: 16
25 * desc: Status register. From MAME: bits 0-9 are CONTROL, other FLAG
26 * fedc ba98 7654 3210
5de27868 27 * 210 - RPL (?) "Loop size". If non-zero, makes (rX+) and (rX-) respectively
28 * modulo-increment and modulo-decrement. The value shows which
29 * power of 2 to use, i.e. 4 means modulo by 16.
30 * (e: fir16_32.sc, IIR_4B.SC, DECIM.SC)
f8ef8ff7 31 * 43 - RB (?)
5de27868 32 * 5 - GP0_0 (ST5?) Changed before acessing PM0 (affects banking?).
33 * 6 - GP0_1 (ST6?) Cleared before acessing PM0 (affects banking?). Set after.
34 * datasheet says these (5,6) bits correspond to hardware pins.
35 * 7 - IE (?) Not directly used by SVP code (never set, but preserved)?
36 * 8 - OP (?) Not used by SVP code (only cleared)? (MAME: saturated value
37 * (probably means clamping? i.e. 0x7ffc + 9 -> 0x7fff))
f8ef8ff7 38 * 9 - MACS (?) Not used by SVP code (only cleared)? (e: "mac shift")
39 * a - GPI_0 Interrupt 0 enable/status?
40 * b - GPI_1 Interrupt 1 enable/status?
41 * c - L L flag. Carry?
42 * d - Z Zero flag.
43 * e - OV Overflow flag.
44 * f - N Negative flag.
45 * seen directly changing code sequences:
46 * ldi ST, 0 ld A, ST ld A, ST ld A, ST ldi st, 20h
47 * ldi ST, 60h ori A, 60h and A, E8h and A, E8h
48 * ld ST, A ld ST, A ori 3
49 * ld ST, A
50 *
51 * 5. "STACK"
52 * size: 16
53 * desc: hw stack of 6 levels (according to datasheet)
54 *
55 * 6. "PC"
56 * size: 16
57 * desc: Program counter.
58 *
59 * 7. "P"
60 * size: 32
61 * desc: multiply result register. Updated after mp* instructions,
62 * or writes to X or Y (P = X * Y * 2) ??
63 * probably affected by MACS bit in ST.
64 *
65 * 8. "PM0" (PM from PMAR name from Tasco's docs)
66 * size: 16?
67 * desc: Programmable Memory access register.
68 * On reset, or when one (both?) GP0 bits are clear,
69 * acts as some additional status reg?
70 *
71 * 9. "PM1"
72 * size: 16?
73 * desc: Programmable Memory access register.
74 * This reg. is only used as PMAR.
75 *
76 * 10. "PM2"
77 * size: 16?
78 * desc: Programmable Memory access register.
79 * This reg. is only used as PMAR.
80 *
81 * 11. "XST"
82 * size: 16?
83 * desc: eXternal STate. Mapped to a15000 at 68k side.
84 * Can be programmed as PMAR? (only seen in test mode code)
85 *
86 * 12. "PM4"
87 * size: 16?
88 * desc: Programmable Memory access register.
89 * This reg. is only used as PMAR. The most used PMAR by VR.
90 *
91 * 13. (unused by VR)
92 *
93 * 14. "PMC" (PMC from PMAC name from Tasco's docs)
94 * size: 32?
95 * desc: Programmable Memory access Control. Set using 2 16bit writes,
96 * first address, then mode word. After setting PMAC, PMAR sould
97 * be accessed to program it.
98 *
99 * 15. "AL"
100 * size: 16
101 * desc: Accumulator Low. 16 least significant bits of accumulator (not 100% sure)
102 * (normally reading acc (ld X, A) you get 16 most significant bits).
103 *
104 *
105 * There are 8 8-bit pointer registers rX. r0-r3 (ri) point to RAM0, r4-r7 (rj) point to RAM1.
5de27868 106 * They can be accessed directly, or 2 indirection levels can be used [ (rX), ((rX)) ],
107 * which work similar to * and ** operators in C, only they use different memory banks and
108 * ((rX)) also does post-increment. First indirection level (rX) accesses RAMx, second accesses
109 * program memory at address read from (rX), and increments value in (rX).
f8ef8ff7 110 *
111 * r0,r1,r2,r4,r5,r6 can be modified [ex: ldi r0, 5].
112 * 3 modifiers can be applied (optional):
5de27868 113 * + : post-increment [ex: ld a, (r0+) ]. Can be made modulo-increment by setting RPL bits in ST.
114 * - : post-decrement. Can be made modulo-decrement by setting RPL bits in ST (not sure).
115 * +!: post-increment, unaffected by RPL (probably).
116 * These are only used on 1st indirection level, so things like [ld a, ((r0+))] and [ld X, r6-]
117 * ar probably invalid.
f8ef8ff7 118 *
119 * r3 and r7 are special and can not be changed (at least Samsung samples and SVP code never do).
120 * They are fixed to the start of their RAM banks. (They are probably changeable for ssp1605+,
121 * Samsung's old DSP page claims that).
122 * 1 of these 4 modifiers must be used (short form direct addressing?):
123 * |00: RAMx[0] [ex: (r3|00), 0] (based on sample code)
124 * |01: RAMx[1]
125 * |10: RAMx[2] ? maybe 10h? accortding to Div_c_dp.sc, 2
126 * |11: RAMx[3]
127 *
128 *
129 * Instruction notes
130 *
131 * mld (rj), (ri) [, b]
132 * operation: A = 0; P = (rj) * (ri)
133 * notes: based on IIR_4B.SC sample. flags? what is b???
134 * TODO: figure out if (rj) and (ri) get loaded in X and Y
135 *
136 * mpya (rj), (ri) [, b]
137 * name: multiply and add?
138 * operation: A += P; P = (rj) * (ri)
139 *
140 * mpys (rj), (ri), b
141 * name: multiply and subtract?
142 * notes: not used by VR code.
017512f2 143 *
30752975 144 * ld a, * doesn't affect flags! (e: A_LAW.SC, Div_c_dp.sc)
145 *
146 * memory map:
147 * 000000 - 1fffff ROM, accessable by both
148 * 200000 - 2fffff unused?
149 * 300000 - 30ffff DRAM, both
150 * 310000 - 31ffff cleared, but never(?) accessed?
151 * 320000 - 38ffff unused?
152 * 390000 - 3907ff IRAM. can only be accessed by ssp?
153 *
154 * 30fe02 - 0 if SVP busy, 1 if done (set by SVP, checked and cleared by 68k)
155 * 30fe06 - also sync related.
156 * 30fe08 - job number [1-12] for SVP. 0 means nothing. Set by 68k, read-cleared by SVP.
017512f2 157 *
158 * Assumptions in this code
159 * P is not directly writeable
5de27868 160 * flags correspond to full 32bit accumulator
161 * only Z and N status flags are emulated (others unused by SVP)
162 * modifiers for 'OP a, ri' are ignored (invalid?/not used by SVP)
163 * modifiers '+' and '+!' act the same (this is most likely wrong)
164 * 'ld d, (a)' loads from program ROM
f8ef8ff7 165 */
166
167#include "../../PicoInt.h"
168
017512f2 169#define u32 unsigned int
170
171// 0
172#define rX ssp->gr[SSP_X].h
173#define rY ssp->gr[SSP_Y].h
174#define rA ssp->gr[SSP_A].h
175#define rST ssp->gr[SSP_ST].h // 4
176#define rSTACK ssp->gr[SSP_STACK].h
177#define rPC ssp->gr[SSP_PC].h
178#define rP ssp->gr[SSP_P]
179#define rPM0 ssp->gr[SSP_PM0].h // 8
180#define rPM1 ssp->gr[SSP_PM1].h
181#define rPM2 ssp->gr[SSP_PM2].h
182#define rXST ssp->gr[SSP_XST].h
183#define rPM4 ssp->gr[SSP_PM4].h // 12
184// 13
185#define rPMC ssp->gr[SSP_PMC] // will keep addr in .h, mode in .l
f8ef8ff7 186#define rAL ssp->gr[SSP_A].l
187
5de27868 188#define rA32 ssp->gr[SSP_A].v
189#define rIJ ssp->r
190
191#define IJind (((op>>6)&4)|(op&3))
192
193#define GET_PC() (PC - (unsigned short *)svp->iram_rom)
194#define GET_PPC_OFFS() ((unsigned int)PC - (unsigned int)svp->iram_rom - 2)
195#define SET_PC(d) PC = (unsigned short *)svp->iram_rom + d
017512f2 196
197#define REG_READ(r) (((r) <= 4) ? ssp->gr[r].h : read_handlers[r]())
198#define REG_WRITE(r,d) { \
199 int r1 = r; \
5de27868 200 if (r1 >= 4) write_handlers[r1](d); \
017512f2 201 else if (r1 > 0) ssp->gr[r1].h = d; \
202}
203
5de27868 204// flags
205#define FLAG_L (1<<0xc)
206#define FLAG_Z (1<<0xd)
207#define FLAG_V (1<<0xe)
208#define FLAG_N (1<<0xf)
209
210// update ZN according to 32bit ACC.
211#define UPD_ACC_ZN \
212 rST &= ~(FLAG_Z|FLAG_N); \
213 if (!rA32) rST |= FLAG_Z; \
214 else rST |= (rA32>>16)&FLAG_N;
215
216// it seems SVP code never checks for L and OV, so we leave them out.
217// rST |= (t>>4)&FLAG_L;
218#define UPD_t_LZVN \
219 rST &= ~(FLAG_L|FLAG_Z|FLAG_V|FLAG_N); \
220 if (!t) rST |= FLAG_Z; \
221 else rST |= t&FLAG_N; \
222
223// standard cond processing.
224// again, only Z and N is checked, as SVP doesn't seem to use any other conds.
225#define COND_CHECK \
226 switch (op&0xf0) { \
227 case 0x00: cond = 1; break; /* always true */ \
228 case 0x50: cond = !((rST ^ (op<<5)) & FLAG_Z); break; /* Z matches f(?) bit */ \
229 case 0x70: cond = !((rST ^ (op<<7)) & FLAG_N); break; /* N matches f(?) bit */ \
230 default:elprintf(EL_SVP, "unimplemented cond @ %04x", GET_PPC_OFFS()); break; \
231 }
232
233// ops with accumulator.
234// how is low word really affected by these?
30752975 235// nearly sure 'ld A' doesn't affect flags
5de27868 236#define OP_LDA(x) \
30752975 237 ssp->gr[SSP_A].h = x
5de27868 238
239#define OP_SUBA(x) { \
240 u32 t = (ssp->gr[SSP_A].v >> 16) - (x); \
241 UPD_t_LZVN \
242 ssp->gr[SSP_A].h = t; \
243}
244
245#define OP_CMPA(x) { \
246 u32 t = (ssp->gr[SSP_A].v >> 16) - (x); \
247 UPD_t_LZVN \
248}
249
250#define OP_ADDA(x) { \
251 u32 t = (ssp->gr[SSP_A].v >> 16) + (x); \
252 UPD_t_LZVN \
253 ssp->gr[SSP_A].h = t; \
254}
255
256#define OP_ANDA(x) \
257 ssp->gr[SSP_A].v &= (x) << 16; \
258 UPD_ACC_ZN
259
260#define OP_ORA(x) \
261 ssp->gr[SSP_A].v |= (x) << 16; \
262 UPD_ACC_ZN
263
264#define OP_EORA(x) \
265 ssp->gr[SSP_A].v ^= (x) << 16; \
266 UPD_ACC_ZN
267
268
017512f2 269static ssp1601_t *ssp = NULL;
270static unsigned short *PC;
271static int g_cycles;
5de27868 272// debug
273static int running = 0;
30752975 274static int last_iram = 0;
017512f2 275
276// -----------------------------------------------------
277// register i/o handlers
278
279// 0-4, 13
280static u32 read_unknown(void)
281{
30752975 282 elprintf(EL_ANOMALY|EL_SVP, "ssp16: FIXME: unknown read @ %04x", GET_PPC_OFFS());
017512f2 283 return 0;
284}
285
286static void write_unknown(u32 d)
287{
30752975 288 elprintf(EL_ANOMALY|EL_SVP, "ssp16: FIXME: unknown write @ %04x", GET_PPC_OFFS());
5de27868 289}
290
291// 4
292static void write_ST(u32 d)
293{
294 if ((rST ^ d) & 7) {
295 elprintf(EL_SVP, "ssp16: RPL %i -> %i @ %04x", rST&7, d&7, GET_PPC_OFFS());
30752975 296// running = 0;
5de27868 297 }
298 rST = d;
017512f2 299}
300
301// 5
302static u32 read_STACK(void)
303{
5de27868 304 //elprintf(EL_SVP, "pop %i @ %04x", rSTACK, GET_PPC_OFFS());
305 --rSTACK;
306 if ((short)rSTACK < 0) {
307 rSTACK = 5;
30752975 308 elprintf(EL_ANOMALY|EL_SVP, "ssp16: FIXME: stack underflow! (%i) @ %04x", rSTACK, GET_PPC_OFFS());
5de27868 309 }
310 return ssp->stack[rSTACK];
017512f2 311}
312
313static void write_STACK(u32 d)
314{
5de27868 315 if (rSTACK >= 6) {
30752975 316 running = 0;
317 elprintf(EL_ANOMALY|EL_SVP, "ssp16: FIXME: stack overflow! (%i) @ %04x", rSTACK, GET_PPC_OFFS());
5de27868 318 rSTACK = 0;
319 }
320 ssp->stack[rSTACK++] = d;
017512f2 321}
322
323// 6
324static u32 read_PC(void)
325{
326 return GET_PC();
327}
328
329static void write_PC(u32 d)
330{
331 SET_PC(d);
332 g_cycles--;
333}
334
335// 7
336static u32 read_P(void)
337{
338 rP.v = (u32)rX * rY * 2;
339 return rP.h;
340}
341
5de27868 342// -----------------------------------------------------
343
344static void iram_write(int addr, u32 d, int reg, int inc)
345{
346 if ((addr&0xfc00) != 0x8000)
30752975 347 elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: invalid IRAM addr: %04x", addr<<1);
5de27868 348 elprintf(EL_SVP, "ssp IRAM w [%06x] %04x (inc %i)", (addr<<1)&0x7ff, d, inc);
349 ((unsigned short *)svp->iram_rom)[addr&0x3ff] = d;
350 ssp->pmac_write[reg] += inc<<16;
351}
352
30752975 353int lil[32] = { 0, }, lilp = 0;
354
355static void debug_dump2file(const char *fname, void *mem, int len);
356
017512f2 357static u32 pm_io(int reg, int write, u32 d)
358{
359 if (ssp->emu_status & SSP_PMC_SET) {
5de27868 360 elprintf(EL_SVP, "PM%i (%c) set to %08x @ %04x", reg, write ? 'w' : 'r', rPMC.v, GET_PPC_OFFS());
017512f2 361 ssp->pmac_read[write ? reg + 6 : reg] = rPMC.v;
362 ssp->emu_status &= ~SSP_PMC_SET;
30752975 363 if ((rPMC.v & 0x7f) == 0x1c && (rPMC.v & 0x7fff0000) == 0) {
364 elprintf(EL_SVP, "IRAM copy from %06x", (ssp->RAM1[0]-1)<<1);
365/*
366 {
367 int i;
368 char buff[64];
369 for (i = 0; i < 32; i++) {
370 if (lil[i] == last_iram) break;
371 if (lil[i] == 0) {
372 lil[i] = last_iram;
373 sprintf(buff, "iramrom_%04x.bin", last_iram);
374 debug_dump2file(buff, svp->iram_rom, sizeof(svp->iram_rom));
375 break;
376 }
377 }
378 }
379*/
380 last_iram = (ssp->RAM1[0]-1)<<1;
381 }
017512f2 382 return 0;
383 }
384
5de27868 385 // just in case
386 ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
387
388// if (ssp->pmac_read[reg] != 0)
389 if (reg == 4 || (rST & 0x60))
390 {
30752975 391 #define CADDR ((((mode<<16)&0x7f0000)|addr)<<1)
5de27868 392 if (write)
393 {
394 int mode = ssp->pmac_write[reg]&0xffff;
395 int addr = ssp->pmac_write[reg]>>16;
396 switch (mode) {
30752975 397 case 0x0018: elprintf(EL_SVP, "ssp DRAM w [%06x] %04x", CADDR, d);
5de27868 398 ((unsigned short *)svp->dram)[addr] = d;
399 break;
30752975 400 case 0x0818: elprintf(EL_SVP, "ssp DRAM w [%06x] %04x (inc 1)", CADDR, d);
5de27868 401 ((unsigned short *)svp->dram)[addr] = d;
402 ssp->pmac_write[reg] += 1<<16;
403 break;
404 case 0x081c: iram_write(addr, d, reg, 1); break; // checked: used by code @ 0902
405 case 0x101c: iram_write(addr, d, reg, 2); break; // checked: used by code @ 3b7c
30752975 406 case 0x4018: elprintf(EL_SVP, "ssp DRAM w [%06x] %04x (cell inc)", CADDR, d);
407 ((unsigned short *)svp->dram)[addr] = d;
408 ssp->pmac_write[reg] += (addr&1) ? (31<<16) : (1<<16);
409 break;
5de27868 410 default: elprintf(EL_SVP|EL_ANOMALY, "ssp PM%i unhandled write mode %04x, [%06x] %04x @ %04x",
30752975 411 reg, mode, CADDR, d, GET_PPC_OFFS()); break;
5de27868 412 }
413 }
414 else
415 {
416 int mode = ssp->pmac_read[reg]&0xffff;
417 int addr = ssp->pmac_read[reg]>>16;
418 switch (mode) {
30752975 419 case 0x0807:
420 case 0x0808:
421 case 0x0809: elprintf(EL_SVP, "ssp ROM r [%06x] %04x", CADDR,
5de27868 422 ((unsigned short *)Pico.rom)[addr|((mode&0xf)<<16)]);
423 // possibly correct, the first word read is some sort of counter, sane values in ROM
30752975 424 ssp->pmac_read[reg] += 1<<16;
425 d = ((unsigned short *)Pico.rom)[addr|((mode&0xf)<<16)];
426 break;
427 case 0x0018: elprintf(EL_SVP, "ssp DRAM r [%06x] %04x", CADDR, ((unsigned short *)svp->dram)[addr]);
428 d = ((unsigned short *)svp->dram)[addr]; // checked
429 break;
430 case 0x0818: elprintf(EL_SVP, "ssp DRAM r [%06x] %04x (inc 1)", CADDR, ((unsigned short *)svp->dram)[addr]);
431 ssp->pmac_read[reg] += 1<<16;
432 d = ((unsigned short *)svp->dram)[addr];
433 break;
434 case 0x3018: elprintf(EL_SVP, "ssp DRAM r [%06x] %04x (inc 32)", CADDR, ((unsigned short *)svp->dram)[addr]);
435 ssp->pmac_read[reg] += 32<<16;
436 d = ((unsigned short *)svp->dram)[addr];
437 break;
438 case 0xa818: elprintf(EL_SVP, "ssp DRAM r [%06x] %04x (dec 16)", CADDR, ((unsigned short *)svp->dram)[addr]);
439 ssp->pmac_read[reg] -= 16<<16;
440 d = ((unsigned short *)svp->dram)[addr];
441 break;
442 case 0xb818: elprintf(EL_SVP, "ssp DRAM r [%06x] %04x (dec 128?)", CADDR, ((unsigned short *)svp->dram)[addr]);
443 ssp->pmac_read[reg] -= 128<<16;
444 d = ((unsigned short *)svp->dram)[addr];
445 break;
5de27868 446 default: elprintf(EL_SVP|EL_ANOMALY, "ssp PM%i unhandled read mode %04x, [%06x] @ %04x",
30752975 447 reg, mode, CADDR, GET_PPC_OFFS());
448 d = 0;
449 break;
5de27868 450 }
451 }
30752975 452
453 // PMC value corresponds to last PMR accessed (not sure).
454 rPMC.v = ssp->pmac_read[write ? reg + 6 : reg];
455
456 return d;
017512f2 457 }
458
459 return (u32)-1;
460}
461
462// 8
463static u32 read_PM0(void)
464{
465 u32 d = pm_io(0, 0, 0);
466 if (d != (u32)-1) return d;
5de27868 467 if (GET_PPC_OFFS() != 0x800 || rPM0 != 0) // debug
468 elprintf(EL_SVP, "PM0 raw r %04x @ %04x", rPM0, GET_PPC_OFFS());
017512f2 469 return rPM0;
470}
471
472static void write_PM0(u32 d)
473{
474 u32 r = pm_io(0, 1, d);
475 if (r != (u32)-1) return;
5de27868 476 elprintf(EL_SVP, "PM0 raw w %04x @ %04x", d, GET_PPC_OFFS());
30752975 477 // rPM0 = d; // ignore
017512f2 478}
479
480// 9
481static u32 read_PM1(void)
482{
483 u32 d = pm_io(1, 0, 0);
484 if (d != (u32)-1) return d;
485 // can be removed?
5de27868 486 elprintf(EL_SVP, "PM1 raw r %04x @ %04x", rPM1, GET_PPC_OFFS());
487 return rPM1;
017512f2 488}
489
490static void write_PM1(u32 d)
491{
492 u32 r = pm_io(1, 1, d);
493 if (r != (u32)-1) return;
494 // can be removed?
5de27868 495 elprintf(EL_SVP, "PM1 raw w %04x @ %04x", d, GET_PPC_OFFS());
496 rPM1 = d;
017512f2 497}
498
499// 10
500static u32 read_PM2(void)
501{
502 u32 d = pm_io(2, 0, 0);
503 if (d != (u32)-1) return d;
504 // can be removed?
5de27868 505 elprintf(EL_SVP, "PM2 raw r %04x @ %04x", rPM2, GET_PPC_OFFS());
506 return rPM2;
017512f2 507}
508
509static void write_PM2(u32 d)
510{
511 u32 r = pm_io(2, 1, d);
512 if (r != (u32)-1) return;
513 // can be removed?
5de27868 514 elprintf(EL_SVP, "PM2 raw w %04x @ %04x", d, GET_PPC_OFFS());
515 rPM2 = d;
017512f2 516}
517
518// 11
519static u32 read_XST(void)
520{
521 // can be removed?
522 u32 d = pm_io(3, 0, 0);
523 if (d != (u32)-1) return d;
524
5de27868 525 elprintf(EL_SVP, "XST raw r %04x @ %04x", rXST, GET_PPC_OFFS());
526 return rXST;
017512f2 527}
f8ef8ff7 528
017512f2 529static void write_XST(u32 d)
f8ef8ff7 530{
017512f2 531 // can be removed?
532 u32 r = pm_io(3, 1, d);
533 if (r != (u32)-1) return;
534
5de27868 535 elprintf(EL_SVP, "XST raw w %04x @ %04x", d, GET_PPC_OFFS());
536 rXST = d;
017512f2 537}
538
539// 12
540static u32 read_PM4(void)
541{
542 u32 d = pm_io(4, 0, 0);
30752975 543 if (d == 0) {
544 switch (GET_PPC_OFFS()) {
545 case 0x0854: ssp->emu_status |= SSP_30FE08_WAIT; elprintf(EL_SVP, "det TIGHT loop: [30fe08]"); break;
546 case 0x4f12: ssp->emu_status |= SSP_30FE06_WAIT; elprintf(EL_SVP, "det TIGHT loop: [30fe06]"); break;
547 }
548 }
017512f2 549 if (d != (u32)-1) return d;
550 // can be removed?
5de27868 551 elprintf(EL_SVP, "PM4 raw r %04x @ %04x", rPM4, GET_PPC_OFFS());
552 return rPM4;
017512f2 553}
554
555static void write_PM4(u32 d)
556{
557 u32 r = pm_io(4, 1, d);
558 if (r != (u32)-1) return;
559 // can be removed?
5de27868 560 elprintf(EL_SVP, "PM4 raw w %04x @ %04x", d, GET_PPC_OFFS());
561 rPM4 = d;
017512f2 562}
563
564// 14
565static u32 read_PMC(void)
566{
30752975 567 elprintf(EL_SVP, "PMC r %08x @ %04x", rPMC.v, GET_PPC_OFFS());
017512f2 568 if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
569 if (ssp->emu_status & SSP_PMC_SET)
5de27868 570 elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS());
017512f2 571 ssp->emu_status |= SSP_PMC_SET;
5de27868 572 ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
017512f2 573 return rPMC.l;
574 } else {
575 ssp->emu_status |= SSP_PMC_HAVE_ADDR;
576 return rPMC.h;
577 }
578}
579
580static void write_PMC(u32 d)
581{
582 if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
583 if (ssp->emu_status & SSP_PMC_SET)
5de27868 584 elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS());
017512f2 585 ssp->emu_status |= SSP_PMC_SET;
5de27868 586 ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
017512f2 587 rPMC.l = d;
588 } else {
589 ssp->emu_status |= SSP_PMC_HAVE_ADDR;
590 rPMC.h = d;
591 }
592}
593
594// 15
595static u32 read_AL(void)
596{
597 // TODO: figure out what's up with those blind reads..
598 return rAL;
599}
600
601static void write_AL(u32 d)
602{
603 rAL = d;
604}
605
606
607typedef u32 (*read_func_t)(void);
608typedef void (*write_func_t)(u32 d);
609
610static read_func_t read_handlers[16] =
611{
612 read_unknown, read_unknown, read_unknown, read_unknown, // -, X, Y, A
613 read_unknown, // 4 ST
614 read_STACK,
615 read_PC,
616 read_P,
617 read_PM0, // 8
618 read_PM1,
619 read_PM2,
620 read_XST,
621 read_PM4, // 12
622 read_unknown, // 13 gr13
623 read_PMC,
624 read_AL
625};
626
627static write_func_t write_handlers[16] =
628{
629 write_unknown, write_unknown, write_unknown, write_unknown, // -, X, Y, A
5de27868 630// write_unknown, // 4 ST
631 write_ST, // 4 ST (debug hook)
017512f2 632 write_STACK,
633 write_PC,
634 write_unknown, // 7 P
635 write_PM0, // 8
636 write_PM1,
637 write_PM2,
638 write_XST,
639 write_PM4, // 12
640 write_unknown, // 13 gr13
641 write_PMC,
642 write_AL
643};
644
5de27868 645// -----------------------------------------------------
646// pointer register handlers
647
648//
649#define ptr1_read(op) ptr1_read_(op&3,(op>>6)&4,(op<<1)&0x18)
650
651static u32 ptr1_read_(int ri, int isj2, int modi3)
652{
653 //int t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
30752975 654 u32 mask, add = 0, t = ri | isj2 | modi3;
655 unsigned char *rp = NULL;
5de27868 656 switch (t)
657 {
658 // mod=0 (00)
659 case 0x00:
660 case 0x01:
661 case 0x02: return ssp->RAM0[ssp->r0[t&3]];
662 case 0x03: return ssp->RAM0[0];
663 case 0x04:
664 case 0x05:
665 case 0x06: return ssp->RAM1[ssp->r1[t&3]];
666 case 0x07: return ssp->RAM1[0];
667 // mod=1 (01), "+!"
5de27868 668 case 0x08:
5de27868 669 case 0x09:
30752975 670 case 0x0a: return ssp->RAM0[ssp->r0[t&3]++];
5de27868 671 case 0x0b: return ssp->RAM0[1];
672 case 0x0c:
5de27868 673 case 0x0d:
30752975 674 case 0x0e: return ssp->RAM1[ssp->r1[t&3]++];
5de27868 675 case 0x0f: return ssp->RAM1[1];
676 // mod=2 (10), "-"
677 case 0x10:
678 case 0x11:
30752975 679 case 0x12: rp = &ssp->r0[t&3]; t = ssp->RAM0[*rp];
680 if (!(rST&7)) { (*rp)--; return t; }
681 add = -1; goto modulo;
5de27868 682 case 0x13: return ssp->RAM0[2];
683 case 0x14:
684 case 0x15:
30752975 685 case 0x16: rp = &ssp->r1[t&3]; t = ssp->RAM1[*rp];
686 if (!(rST&7)) { (*rp)--; return t; }
687 add = -1; goto modulo;
5de27868 688 case 0x17: return ssp->RAM1[2];
30752975 689 // mod=3 (11), "+"
690 case 0x18:
691 case 0x19:
692 case 0x1a: rp = &ssp->r0[t&3]; t = ssp->RAM0[*rp];
693 if (!(rST&7)) { (*rp)++; return t; }
694 add = 1; goto modulo;
5de27868 695 case 0x1b: return ssp->RAM0[3];
30752975 696 case 0x1c:
697 case 0x1d:
698 case 0x1e: rp = &ssp->r1[t&3]; t = ssp->RAM1[*rp];
699 if (!(rST&7)) { (*rp)++; return t; }
700 add = 1; goto modulo;
5de27868 701 case 0x1f: return ssp->RAM1[3];
702 }
703
704 return 0;
30752975 705
706modulo:
707 mask = (1 << (rST&7)) - 1;
708 *rp = (*rp & ~mask) | ((*rp + add) & mask);
709 return t;
5de27868 710}
711
712static void ptr1_write(int op, u32 d)
713{
714 int t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
715 switch (t)
716 {
717 // mod=0 (00)
718 case 0x00:
719 case 0x01:
720 case 0x02: ssp->RAM0[ssp->r0[t&3]] = d; return;
721 case 0x03: ssp->RAM0[0] = d; return;
722 case 0x04:
723 case 0x05:
724 case 0x06: ssp->RAM1[ssp->r1[t&3]] = d; return;
725 case 0x07: ssp->RAM1[0] = d; return;
726 // mod=1 (01), "+!"
727 // mod=3, "+"
728 case 0x08:
729 case 0x18:
730 case 0x09:
731 case 0x19:
732 case 0x0a:
733 case 0x1a: ssp->RAM0[ssp->r0[t&3]++] = d; return;
734 case 0x0b: ssp->RAM0[1] = d; return;
735 case 0x0c:
736 case 0x1c:
737 case 0x0d:
738 case 0x1d:
739 case 0x0e:
740 case 0x1e: ssp->RAM1[ssp->r1[t&3]++] = d; return;
741 case 0x0f: ssp->RAM1[1] = d; return;
742 // mod=2 (10), "-"
743 case 0x10:
744 case 0x11:
745 case 0x12: ssp->RAM0[ssp->r0[t&3]--] = d; return;
746 case 0x13: ssp->RAM0[2] = d; return;
747 case 0x14:
748 case 0x15:
749 case 0x16: ssp->RAM1[ssp->r1[t&3]--] = d; return;
750 case 0x17: ssp->RAM1[2] = d; return;
751 // mod=3 (11)
752 case 0x1b: ssp->RAM0[3] = d; return;
753 case 0x1f: ssp->RAM1[3] = d; return;
754 }
755}
756
757static u32 ptr2_read(int op)
758{
759 int mv = 0, t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
760 switch (t)
761 {
762 // mod=0 (00)
763 case 0x00:
764 case 0x01:
765 case 0x02: mv = ssp->RAM0[ssp->r0[t&3]]++; break;
766 case 0x03: mv = ssp->RAM0[0]++; break;
767 case 0x04:
768 case 0x05:
769 case 0x06: mv = ssp->RAM1[ssp->r1[t&3]]++; break;
770 case 0x07: mv = ssp->RAM1[0]++; break;
771 // mod=1 (01)
772 case 0x0b: mv = ssp->RAM0[1]++; break;
773 case 0x0f: mv = ssp->RAM1[1]++; break;
774 // mod=2 (10)
775 case 0x13: mv = ssp->RAM0[2]++; break;
776 case 0x17: mv = ssp->RAM1[2]++; break;
777 // mod=3 (11)
778 case 0x1b: mv = ssp->RAM0[3]++; break;
779 case 0x1f: mv = ssp->RAM1[3]++; break;
30752975 780 default: elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: invalid mod in ((rX))? @ %04x", GET_PPC_OFFS());
5de27868 781 return 0;
782 }
783
784 return ((unsigned short *)svp->iram_rom)[mv];
785}
786
787
788// -----------------------------------------------------
789
017512f2 790void ssp1601_reset(ssp1601_t *l_ssp)
791{
792 ssp = l_ssp;
f8ef8ff7 793 ssp->emu_status = 0;
017512f2 794 ssp->gr[SSP_GR0].v = 0xffff0000;
f8ef8ff7 795 rPC = 0x400;
5de27868 796 rSTACK = 0; // ? using ascending stack
30752975 797 rST = 0;
f8ef8ff7 798}
799
800
5de27868 801static void debug_dump(void)
f8ef8ff7 802{
5de27868 803 printf("GR0: %04x X: %04x Y: %04x A: %08x\n", ssp->gr[SSP_GR0].h, rX, rY, ssp->gr[SSP_A].v);
804 printf("PC: %04x (%04x) P: %08x\n", GET_PC(), GET_PC() << 1, ssp->gr[SSP_P].v);
805 printf("PM0: %04x PM1: %04x PM2: %04x\n", rPM0, rPM1, rPM2);
806 printf("XST: %04x PM4: %04x PMC: %08x\n", rXST, rPM4, ssp->gr[SSP_PMC].v);
807 printf(" ST: %04x %c%c%c%c, GP0_0 %i, GP0_1 %i\n", rST, rST&FLAG_N?'N':'n', rST&FLAG_V?'V':'v',
808 rST&FLAG_Z?'Z':'z', rST&FLAG_L?'L':'l', (rST>>5)&1, (rST>>6)&1);
809 printf("STACK: %i %04x %04x %04x %04x %04x %04x\n", rSTACK, ssp->stack[0], ssp->stack[1],
810 ssp->stack[2], ssp->stack[3], ssp->stack[4], ssp->stack[5]);
811 printf("r0-r2: %02x %02x %02x r4-r6: %02x %02x %02x\n", rIJ[0], rIJ[1], rIJ[2], rIJ[4], rIJ[5], rIJ[6]);
812 elprintf(EL_SVP, "cycles: %i, emu_status: %x", g_cycles, ssp->emu_status);
813}
f8ef8ff7 814
5de27868 815static void debug_dump_mem(void)
816{
817 int h, i;
818 printf("RAM0\n");
819 for (h = 0; h < 32; h++)
820 {
821 if (h == 16) printf("RAM1\n");
822 printf("%03x:", h*16);
823 for (i = 0; i < 16; i++)
824 printf(" %04x", ssp->RAM[h*16+i]);
825 printf("\n");
826 }
827}
828
30752975 829static void debug_dump2file(const char *fname, void *mem, int len)
830{
831 FILE *f = fopen(fname, "wb");
832 unsigned short *p = mem;
833 int i;
834 if (f) {
835 for (i = 0; i < len/2; i++) p[i] = (p[i]<<8) | (p[i]>>8);
836 fwrite(mem, 1, len, f);
837 fclose(f);
838 for (i = 0; i < len/2; i++) p[i] = (p[i]<<8) | (p[i]>>8);
839 printf("dumped to %s\n", fname);
840 }
841 else
842 printf("dump failed\n");
843}
844
5de27868 845static int bpts[10] = { 0, };
846
847static void debug(unsigned int pc, unsigned int op)
848{
849 static char buffo[64] = {0,};
850 char buff[64] = {0,};
851 int i;
852
853 if (running) {
854 for (i = 0; i < 10; i++)
855 if (pc != 0 && bpts[i] == pc) {
856 printf("breakpoint %i\n", i);
857 running = 0;
858 break;
859 }
860 }
861 if (running) return;
862
863 printf("%04x (%02x) @ %04x\n", op, op >> 9, pc<<1);
864
865 while (1)
866 {
867 printf("dbg> ");
868 fflush(stdout);
869 fgets(buff, sizeof(buff), stdin);
870 if (buff[0] == '\n') strcpy(buff, buffo);
871 else strcpy(buffo, buff);
872
873 switch (buff[0]) {
874 case 0: exit(0);
875 case 'c':
876 case 'r': running = 1; return;
877 case 's':
878 case 'n': return;
879 case 'x': debug_dump(); break;
880 case 'm': debug_dump_mem(); break;
881 case 'b': {
882 char *baddr = buff + 2;
883 i = 0;
884 if (buff[3] == ' ') { i = buff[2] - '0'; baddr = buff + 4; }
885 bpts[i] = strtol(baddr, NULL, 16) >> 1;
886 printf("breakpoint %i set @ %04x\n", i, bpts[i]<<1);
887 break;
888 }
30752975 889 case 'd':
890 sprintf(buff, "iramrom_%04x.bin", last_iram);
891 debug_dump2file(buff, svp->iram_rom, sizeof(svp->iram_rom));
892 debug_dump2file("dram.bin", svp->dram, sizeof(svp->dram));
5de27868 893 break;
5de27868 894 default: printf("unknown command\n"); break;
895 }
896 }
897}
898
899void ssp1601_run(int cycles)
900{
017512f2 901 SET_PC(rPC);
902 g_cycles = cycles;
5de27868 903//running = 0;
f8ef8ff7 904
30752975 905 while (g_cycles > 0 && !(ssp->emu_status&0xc000))
f8ef8ff7 906 {
5de27868 907 int op;
908 u32 tmpv;
909
910 op = *PC++;
911 debug(GET_PC()-1, op);
f8ef8ff7 912 switch (op >> 9)
913 {
914 // ld d, s
5de27868 915 case 0x00:
f8ef8ff7 916 if (op == 0) break; // nop
017512f2 917 if (op == ((SSP_A<<4)|SSP_P)) { // A <- P
918 // not sure. MAME claims that only hi word is transfered.
919 read_P(); // update P
920 ssp->gr[SSP_A].v = ssp->gr[SSP_P].v;
f8ef8ff7 921 }
5de27868 922 else
f8ef8ff7 923 {
5de27868 924 tmpv = REG_READ(op & 0x0f);
925 REG_WRITE((op & 0xf0) >> 4, tmpv);
926 }
927 break;
928
929 // ld d, (ri)
930 case 0x01: tmpv = ptr1_read(op); REG_WRITE((op & 0xf0) >> 4, tmpv); break;
931
932 // ld (ri), s
933 case 0x02: tmpv = REG_READ((op & 0xf0) >> 4); ptr1_write(op, tmpv); break;
934
935 // ldi d, imm
936 case 0x04: tmpv = *PC++; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
937
938 // ld d, ((ri))
939 case 0x05: tmpv = ptr2_read(op); REG_WRITE((op & 0xf0) >> 4, tmpv); break;
940
941 // ldi (ri), imm
942 case 0x06: tmpv = *PC++; ptr1_write(op, tmpv); break;
943
944 // ld adr, a
945 case 0x07: ssp->RAM[op & 0x1ff] = rA; break;
946
947 // ld d, ri
948 case 0x09: tmpv = rIJ[(op&3)|((op>>6)&4)]; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
949
950 // ld ri, s
951 case 0x0a: rIJ[(op&3)|((op>>6)&4)] = REG_READ((op & 0xf0) >> 4); break;
952
953 // ldi ri, simm
954 case 0x0c:
955 case 0x0d:
956 case 0x0e:
957 case 0x0f: rIJ[(op>>8)&7] = op; break;
958
959 // call cond, addr
960 case 0x24: {
961 int cond = 0;
962 COND_CHECK
963 if (cond) { int new_PC = *PC++; write_STACK(GET_PC()); write_PC(new_PC); }
964 else PC++;
965 break;
966 }
967
968 // ld d, (a)
969 case 0x25: tmpv = ((unsigned short *)svp->iram_rom)[rA]; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
970
971 // bra cond, addr
972 case 0x26: {
973 int cond = 0;
974 COND_CHECK
975 if (cond) { int new_PC = *PC++; write_PC(new_PC); }
976 else PC++;
977 break;
978 }
979
980 // mod cond, op
981 case 0x48: {
982 int cond = 0;
983 COND_CHECK
984 if (cond) {
985 switch (op & 7) {
986 case 2: rA32 >>= 1; break; // shr
987 case 3: rA32 <<= 1; break; // shl
988 case 6: rA32 = -(int)rA32; break; // neg
989 case 7: if ((int)rA32 < 0) rA32 = -(int)rA32; break; // abs
990 default: elprintf(EL_SVP, "ssp16: unhandled mod %i @ %04x", op&7, GET_PPC_OFFS());
991 }
30752975 992 UPD_ACC_ZN // ?
f8ef8ff7 993 }
994 break;
5de27868 995 }
996
30752975 997#if 1
998 // mpys?
999 case 0x1b:
1000 // very uncertain about this one. What about b?
1001 if (!(op&0x100)) elprintf(EL_SVP|EL_ANOMALY, "ssp16: FIXME: no b bit @ %04x", GET_PPC_OFFS());
1002 read_P(); // update P
1003 ssp->gr[SSP_A].v -= ssp->gr[SSP_P].v; // maybe only upper word?
1004// UPD_ACC_ZN // I've seen code checking flags after this
1005 rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
1006 rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
1007 break;
1008#endif
5de27868 1009 // mpya (rj), (ri), b
1010 case 0x4b:
1011 // dunno if this is correct. What about b?
30752975 1012 if (!(op&0x100)) elprintf(EL_SVP|EL_ANOMALY, "ssp16: FIXME: no b bit @ %04x", GET_PPC_OFFS());
5de27868 1013 read_P(); // update P
1014 ssp->gr[SSP_A].v += ssp->gr[SSP_P].v; // maybe only upper word?
30752975 1015// UPD_ACC_ZN // ?
5de27868 1016 rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
1017 rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
1018 break;
1019
1020 // mld (rj), (ri), b
1021 case 0x5b:
1022 // dunno if this is correct. What about b?
30752975 1023 if (!(op&0x100)) elprintf(EL_SVP|EL_ANOMALY, "ssp16: FIXME: no b bit @ %04x", GET_PPC_OFFS());
5de27868 1024 ssp->gr[SSP_A].v = 0; // maybe only upper word?
30752975 1025 // UPD_t_LZVN // ?
5de27868 1026 rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
1027 rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
1028 break;
1029
1030 // OP a, s
1031 case 0x10: tmpv = REG_READ(op & 0x0f); OP_SUBA(tmpv); break;
1032 case 0x30: tmpv = REG_READ(op & 0x0f); OP_CMPA(tmpv); break;
1033 case 0x40: tmpv = REG_READ(op & 0x0f); OP_ADDA(tmpv); break;
1034 case 0x50: tmpv = REG_READ(op & 0x0f); OP_ANDA(tmpv); break;
1035 case 0x60: tmpv = REG_READ(op & 0x0f); OP_ORA (tmpv); break;
1036 case 0x70: tmpv = REG_READ(op & 0x0f); OP_EORA(tmpv); break;
1037
1038 // OP a, (ri)
1039 case 0x11: tmpv = ptr1_read(op); OP_SUBA(tmpv); break;
1040 case 0x31: tmpv = ptr1_read(op); OP_CMPA(tmpv); break;
1041 case 0x41: tmpv = ptr1_read(op); OP_ADDA(tmpv); break;
1042 case 0x51: tmpv = ptr1_read(op); OP_ANDA(tmpv); break;
1043 case 0x61: tmpv = ptr1_read(op); OP_ORA (tmpv); break;
1044 case 0x71: tmpv = ptr1_read(op); OP_EORA(tmpv); break;
1045
1046 // OP a, adr
1047 case 0x03: tmpv = ssp->RAM[op & 0x1ff]; OP_LDA (tmpv); break;
1048 case 0x13: tmpv = ssp->RAM[op & 0x1ff]; OP_SUBA(tmpv); break;
1049 case 0x33: tmpv = ssp->RAM[op & 0x1ff]; OP_CMPA(tmpv); break;
1050 case 0x43: tmpv = ssp->RAM[op & 0x1ff]; OP_ADDA(tmpv); break;
1051 case 0x53: tmpv = ssp->RAM[op & 0x1ff]; OP_ANDA(tmpv); break;
1052 case 0x63: tmpv = ssp->RAM[op & 0x1ff]; OP_ORA (tmpv); break;
1053 case 0x73: tmpv = ssp->RAM[op & 0x1ff]; OP_EORA(tmpv); break;
1054
1055 // OP a, imm
1056 case 0x14: tmpv = *PC++; OP_SUBA(tmpv); break;
1057 case 0x34: tmpv = *PC++; OP_CMPA(tmpv); break;
1058 case 0x44: tmpv = *PC++; OP_ADDA(tmpv); break;
1059 case 0x54: tmpv = *PC++; OP_ANDA(tmpv); break;
1060 case 0x64: tmpv = *PC++; OP_ORA (tmpv); break;
1061 case 0x74: tmpv = *PC++; OP_EORA(tmpv); break;
1062
1063 // OP a, ((ri))
1064 case 0x15: tmpv = ptr2_read(op); OP_SUBA(tmpv); break;
1065 case 0x35: tmpv = ptr2_read(op); OP_CMPA(tmpv); break;
1066 case 0x45: tmpv = ptr2_read(op); OP_ADDA(tmpv); break;
1067 case 0x55: tmpv = ptr2_read(op); OP_ANDA(tmpv); break;
1068 case 0x65: tmpv = ptr2_read(op); OP_ORA (tmpv); break;
1069 case 0x75: tmpv = ptr2_read(op); OP_EORA(tmpv); break;
1070
1071 // OP a, ri
1072 case 0x19: tmpv = rIJ[IJind]; OP_SUBA(tmpv); break;
1073 case 0x39: tmpv = rIJ[IJind]; OP_CMPA(tmpv); break;
1074 case 0x49: tmpv = rIJ[IJind]; OP_ADDA(tmpv); break;
1075 case 0x59: tmpv = rIJ[IJind]; OP_ANDA(tmpv); break;
1076 case 0x69: tmpv = rIJ[IJind]; OP_ORA (tmpv); break;
1077 case 0x79: tmpv = rIJ[IJind]; OP_EORA(tmpv); break;
1078
1079 // OP simm
1080 case 0x1c: OP_SUBA(op & 0xff); break;
1081 case 0x3c: OP_CMPA(op & 0xff); break;
1082 case 0x4c: OP_ADDA(op & 0xff); break;
1083 // MAME code only does LSB of top word, but this looks wrong to me.
1084 case 0x5c: OP_ANDA(op & 0xff); break;
1085 case 0x6c: OP_ORA (op & 0xff); break;
1086 case 0x7c: OP_EORA(op & 0xff); break;
f8ef8ff7 1087
1088 default:
5de27868 1089 elprintf(EL_ANOMALY|EL_SVP, "ssp16: unhandled op %04x @ %04x", op, GET_PPC_OFFS());
017512f2 1090 break;
f8ef8ff7 1091 }
017512f2 1092 g_cycles--;
f8ef8ff7 1093 }
1094
017512f2 1095 read_P(); // update P
f8ef8ff7 1096 rPC = GET_PC();
017512f2 1097
1098 if (ssp->gr[SSP_GR0].v != 0xffff0000)
30752975 1099 elprintf(EL_ANOMALY|EL_SVP, "ssp16: FIXME: REG 0 corruption! %08x", ssp->gr[SSP_GR0].v);
f8ef8ff7 1100}
1101
fast MegaDrive/MegaCD/32X emulator