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[picodrive.git] / Pico / carthw / svp / ssp16.c
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f8ef8ff7 1// basic, incomplete SSP160x (SSP1601?) interpreter
2
3/*
4 * Register info
5 * most names taken from MAME code
6 *
7 * 0. "-"
8 * size: 16
9 * desc: Constant register with all bits set (0xffff).
10 *
11 * 1. "X"
12 * size: 16
13 * desc: Generic register. When set, updates P (P = X * Y * 2) ??
14 *
15 * 2. "Y"
16 * size: 16
17 * desc: Generic register. When set, updates P (P = X * Y * 2) ??
18 *
19 * 3. "A"
20 * size: 32
21 * desc: Accumulator.
22 *
23 * 4. "ST"
24 * size: 16
25 * desc: Status register. From MAME: bits 0-9 are CONTROL, other FLAG
26 * fedc ba98 7654 3210
5de27868 27 * 210 - RPL (?) "Loop size". If non-zero, makes (rX+) and (rX-) respectively
28 * modulo-increment and modulo-decrement. The value shows which
29 * power of 2 to use, i.e. 4 means modulo by 16.
30 * (e: fir16_32.sc, IIR_4B.SC, DECIM.SC)
f8ef8ff7 31 * 43 - RB (?)
5de27868 32 * 5 - GP0_0 (ST5?) Changed before acessing PM0 (affects banking?).
33 * 6 - GP0_1 (ST6?) Cleared before acessing PM0 (affects banking?). Set after.
34 * datasheet says these (5,6) bits correspond to hardware pins.
35 * 7 - IE (?) Not directly used by SVP code (never set, but preserved)?
36 * 8 - OP (?) Not used by SVP code (only cleared)? (MAME: saturated value
37 * (probably means clamping? i.e. 0x7ffc + 9 -> 0x7fff))
f8ef8ff7 38 * 9 - MACS (?) Not used by SVP code (only cleared)? (e: "mac shift")
39 * a - GPI_0 Interrupt 0 enable/status?
40 * b - GPI_1 Interrupt 1 enable/status?
41 * c - L L flag. Carry?
42 * d - Z Zero flag.
43 * e - OV Overflow flag.
44 * f - N Negative flag.
45 * seen directly changing code sequences:
46 * ldi ST, 0 ld A, ST ld A, ST ld A, ST ldi st, 20h
47 * ldi ST, 60h ori A, 60h and A, E8h and A, E8h
48 * ld ST, A ld ST, A ori 3
49 * ld ST, A
50 *
51 * 5. "STACK"
52 * size: 16
53 * desc: hw stack of 6 levels (according to datasheet)
54 *
55 * 6. "PC"
56 * size: 16
57 * desc: Program counter.
58 *
59 * 7. "P"
60 * size: 32
61 * desc: multiply result register. Updated after mp* instructions,
62 * or writes to X or Y (P = X * Y * 2) ??
63 * probably affected by MACS bit in ST.
64 *
65 * 8. "PM0" (PM from PMAR name from Tasco's docs)
66 * size: 16?
67 * desc: Programmable Memory access register.
68 * On reset, or when one (both?) GP0 bits are clear,
d26dc685 69 * acts as status for XST, mapped at 015004 at 68k side:
70 * bit0: ssp has written something to XST (cleared when 015004 is read)
71 * bit1: 68k has written something through a1500{0|2} (cleared on PM0 read)
f8ef8ff7 72 *
73 * 9. "PM1"
74 * size: 16?
75 * desc: Programmable Memory access register.
76 * This reg. is only used as PMAR.
77 *
78 * 10. "PM2"
79 * size: 16?
80 * desc: Programmable Memory access register.
81 * This reg. is only used as PMAR.
82 *
83 * 11. "XST"
84 * size: 16?
d26dc685 85 * desc: eXternal STate. Mapped to a15000 and a15002 at 68k side.
f8ef8ff7 86 * Can be programmed as PMAR? (only seen in test mode code)
d26dc685 87 * Affects PM0 when written to?
f8ef8ff7 88 *
89 * 12. "PM4"
90 * size: 16?
91 * desc: Programmable Memory access register.
92 * This reg. is only used as PMAR. The most used PMAR by VR.
93 *
94 * 13. (unused by VR)
95 *
96 * 14. "PMC" (PMC from PMAC name from Tasco's docs)
97 * size: 32?
98 * desc: Programmable Memory access Control. Set using 2 16bit writes,
99 * first address, then mode word. After setting PMAC, PMAR sould
3554b0a4 100 * be blind accessed (ld -, PMx or ld PMx, -) to program it for
101 * reading and writing respectively.
102 * Reading the register also shifts it's state (from "waiting for
103 * address" to "waiting for mode" and back). Reads always return
104 * address related to last PMx register accressed.
f8ef8ff7 105 *
106 * 15. "AL"
107 * size: 16
108 * desc: Accumulator Low. 16 least significant bits of accumulator (not 100% sure)
109 * (normally reading acc (ld X, A) you get 16 most significant bits).
110 *
111 *
112 * There are 8 8-bit pointer registers rX. r0-r3 (ri) point to RAM0, r4-r7 (rj) point to RAM1.
5de27868 113 * They can be accessed directly, or 2 indirection levels can be used [ (rX), ((rX)) ],
114 * which work similar to * and ** operators in C, only they use different memory banks and
115 * ((rX)) also does post-increment. First indirection level (rX) accesses RAMx, second accesses
116 * program memory at address read from (rX), and increments value in (rX).
f8ef8ff7 117 *
118 * r0,r1,r2,r4,r5,r6 can be modified [ex: ldi r0, 5].
119 * 3 modifiers can be applied (optional):
5de27868 120 * + : post-increment [ex: ld a, (r0+) ]. Can be made modulo-increment by setting RPL bits in ST.
121 * - : post-decrement. Can be made modulo-decrement by setting RPL bits in ST (not sure).
122 * +!: post-increment, unaffected by RPL (probably).
123 * These are only used on 1st indirection level, so things like [ld a, ((r0+))] and [ld X, r6-]
124 * ar probably invalid.
f8ef8ff7 125 *
126 * r3 and r7 are special and can not be changed (at least Samsung samples and SVP code never do).
127 * They are fixed to the start of their RAM banks. (They are probably changeable for ssp1605+,
128 * Samsung's old DSP page claims that).
129 * 1 of these 4 modifiers must be used (short form direct addressing?):
130 * |00: RAMx[0] [ex: (r3|00), 0] (based on sample code)
131 * |01: RAMx[1]
132 * |10: RAMx[2] ? maybe 10h? accortding to Div_c_dp.sc, 2
133 * |11: RAMx[3]
134 *
135 *
136 * Instruction notes
137 *
d26dc685 138 * ld a, * doesn't affect flags! (e: A_LAW.SC, Div_c_dp.sc)
139 *
f8ef8ff7 140 * mld (rj), (ri) [, b]
141 * operation: A = 0; P = (rj) * (ri)
142 * notes: based on IIR_4B.SC sample. flags? what is b???
f8ef8ff7 143 *
144 * mpya (rj), (ri) [, b]
145 * name: multiply and add?
146 * operation: A += P; P = (rj) * (ri)
147 *
148 * mpys (rj), (ri), b
149 * name: multiply and subtract?
150 * notes: not used by VR code.
017512f2 151 *
d26dc685 152 * mod cond, op
153 * mod cond, shr does arithmetic shift
30752975 154 *
67256d4b 155 * 'ld -, AL' and probably 'ld AL, -' are for dummy assigns
156 *
30752975 157 * memory map:
158 * 000000 - 1fffff ROM, accessable by both
159 * 200000 - 2fffff unused?
d26dc685 160 * 300000 - 31ffff DRAM, both
30752975 161 * 320000 - 38ffff unused?
162 * 390000 - 3907ff IRAM. can only be accessed by ssp?
d26dc685 163 * 390000 - 39ffff similar mapping to "cell arrange" in Sega CD, 68k only?
164 * 3a0000 - 3affff similar mapping to "cell arrange" in Sega CD, a bit different
30752975 165 *
166 * 30fe02 - 0 if SVP busy, 1 if done (set by SVP, checked and cleared by 68k)
167 * 30fe06 - also sync related.
d26dc685 168 * 30fe08 - job number [1-12] for SVP. 0 means no job. Set by 68k, read-cleared by SVP.
169 *
67256d4b 170 * TODO:
171 * + figure out if 'op A, P' is 32bit (nearly sure it is)
172 * * what exactly is AL?
173 * * does mld, mpya load their operands into X and Y?
174 * * OP simm
175 *
d26dc685 176 * misc:
177 * pressing all buttons while resetting game will kick into test mode
017512f2 178 *
179 * Assumptions in this code
180 * P is not directly writeable
5de27868 181 * flags correspond to full 32bit accumulator
182 * only Z and N status flags are emulated (others unused by SVP)
183 * modifiers for 'OP a, ri' are ignored (invalid?/not used by SVP)
184 * modifiers '+' and '+!' act the same (this is most likely wrong)
185 * 'ld d, (a)' loads from program ROM
f8ef8ff7 186 */
187
188#include "../../PicoInt.h"
189
017512f2 190#define u32 unsigned int
191
3554b0a4 192//#define USE_DEBUGGER
193
017512f2 194// 0
195#define rX ssp->gr[SSP_X].h
196#define rY ssp->gr[SSP_Y].h
197#define rA ssp->gr[SSP_A].h
198#define rST ssp->gr[SSP_ST].h // 4
199#define rSTACK ssp->gr[SSP_STACK].h
200#define rPC ssp->gr[SSP_PC].h
201#define rP ssp->gr[SSP_P]
202#define rPM0 ssp->gr[SSP_PM0].h // 8
203#define rPM1 ssp->gr[SSP_PM1].h
204#define rPM2 ssp->gr[SSP_PM2].h
205#define rXST ssp->gr[SSP_XST].h
206#define rPM4 ssp->gr[SSP_PM4].h // 12
207// 13
208#define rPMC ssp->gr[SSP_PMC] // will keep addr in .h, mode in .l
f8ef8ff7 209#define rAL ssp->gr[SSP_A].l
210
5de27868 211#define rA32 ssp->gr[SSP_A].v
212#define rIJ ssp->r
213
214#define IJind (((op>>6)&4)|(op&3))
215
216#define GET_PC() (PC - (unsigned short *)svp->iram_rom)
217#define GET_PPC_OFFS() ((unsigned int)PC - (unsigned int)svp->iram_rom - 2)
218#define SET_PC(d) PC = (unsigned short *)svp->iram_rom + d
017512f2 219
220#define REG_READ(r) (((r) <= 4) ? ssp->gr[r].h : read_handlers[r]())
221#define REG_WRITE(r,d) { \
222 int r1 = r; \
5de27868 223 if (r1 >= 4) write_handlers[r1](d); \
017512f2 224 else if (r1 > 0) ssp->gr[r1].h = d; \
225}
226
5de27868 227// flags
d26dc685 228#define SSP_FLAG_L (1<<0xc)
229#define SSP_FLAG_Z (1<<0xd)
230#define SSP_FLAG_V (1<<0xe)
231#define SSP_FLAG_N (1<<0xf)
5de27868 232
233// update ZN according to 32bit ACC.
234#define UPD_ACC_ZN \
d26dc685 235 rST &= ~(SSP_FLAG_Z|SSP_FLAG_N); \
236 if (!rA32) rST |= SSP_FLAG_Z; \
237 else rST |= (rA32>>16)&SSP_FLAG_N;
5de27868 238
239// it seems SVP code never checks for L and OV, so we leave them out.
d26dc685 240// rST |= (t>>4)&SSP_FLAG_L;
67256d4b 241#define UPD_LZVN \
242 rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
243 if (!rA32) rST |= SSP_FLAG_Z; \
244 else rST |= (rA32>>16)&SSP_FLAG_N;
245
5de27868 246// standard cond processing.
247// again, only Z and N is checked, as SVP doesn't seem to use any other conds.
248#define COND_CHECK \
249 switch (op&0xf0) { \
250 case 0x00: cond = 1; break; /* always true */ \
d26dc685 251 case 0x50: cond = !((rST ^ (op<<5)) & SSP_FLAG_Z); break; /* Z matches f(?) bit */ \
252 case 0x70: cond = !((rST ^ (op<<7)) & SSP_FLAG_N); break; /* N matches f(?) bit */ \
4bfc6da4 253 default:elprintf(EL_SVP, "ssp FIXME: unimplemented cond @ %04x", GET_PPC_OFFS()); break; \
5de27868 254 }
255
256// ops with accumulator.
257// how is low word really affected by these?
30752975 258// nearly sure 'ld A' doesn't affect flags
5de27868 259#define OP_LDA(x) \
30752975 260 ssp->gr[SSP_A].h = x
5de27868 261
67256d4b 262#define OP_LDA32(x) \
4bfc6da4 263 rA32 = x
67256d4b 264
5de27868 265#define OP_SUBA(x) { \
4bfc6da4 266 rA32 -= (x) << 16; \
267 UPD_LZVN \
5de27868 268}
269
67256d4b 270#define OP_SUBA32(x) { \
4bfc6da4 271 rA32 -= (x); \
67256d4b 272 UPD_LZVN \
273}
274
5de27868 275#define OP_CMPA(x) { \
4bfc6da4 276 u32 t = rA32 - ((x) << 16); \
277 rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
278 if (!t) rST |= SSP_FLAG_Z; \
279 else rST |= (t>>16)&SSP_FLAG_N; \
5de27868 280}
281
67256d4b 282#define OP_CMPA32(x) { \
4bfc6da4 283 u32 t = rA32 - (x); \
67256d4b 284 rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
285 if (!t) rST |= SSP_FLAG_Z; \
286 else rST |= (t>>16)&SSP_FLAG_N; \
287}
288
5de27868 289#define OP_ADDA(x) { \
4bfc6da4 290 rA32 += (x) << 16; \
291 UPD_LZVN \
5de27868 292}
293
67256d4b 294#define OP_ADDA32(x) { \
4bfc6da4 295 rA32 += (x); \
67256d4b 296 UPD_LZVN \
297}
298
5de27868 299#define OP_ANDA(x) \
4bfc6da4 300 rA32 &= (x) << 16; \
5de27868 301 UPD_ACC_ZN
302
67256d4b 303#define OP_ANDA32(x) \
4bfc6da4 304 rA32 &= (x); \
67256d4b 305 UPD_ACC_ZN
306
5de27868 307#define OP_ORA(x) \
4bfc6da4 308 rA32 |= (x) << 16; \
5de27868 309 UPD_ACC_ZN
310
67256d4b 311#define OP_ORA32(x) \
4bfc6da4 312 rA32 |= (x); \
67256d4b 313 UPD_ACC_ZN
314
5de27868 315#define OP_EORA(x) \
4bfc6da4 316 rA32 ^= (x) << 16; \
5de27868 317 UPD_ACC_ZN
318
67256d4b 319#define OP_EORA32(x) \
4bfc6da4 320 rA32 ^= (x); \
67256d4b 321 UPD_ACC_ZN
322
323
324#define OP_CHECK32(OP) \
325 if ((op & 0x0f) == SSP_P) { /* A <- P */ \
326 read_P(); /* update P */ \
327 OP(ssp->gr[SSP_P].v); \
328 break; \
329}
330
5de27868 331
017512f2 332static ssp1601_t *ssp = NULL;
333static unsigned short *PC;
334static int g_cycles;
3554b0a4 335
336#ifdef USE_DEBUGGER
5de27868 337static int running = 0;
30752975 338static int last_iram = 0;
3554b0a4 339#endif
017512f2 340
341// -----------------------------------------------------
342// register i/o handlers
343
344// 0-4, 13
345static u32 read_unknown(void)
346{
3554b0a4 347 elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: unknown read @ %04x", GET_PPC_OFFS());
017512f2 348 return 0;
349}
350
351static void write_unknown(u32 d)
352{
3554b0a4 353 elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: unknown write @ %04x", GET_PPC_OFFS());
5de27868 354}
355
356// 4
357static void write_ST(u32 d)
358{
3554b0a4 359 //if ((rST ^ d) & 0x0007) elprintf(EL_SVP, "ssp RPL %i -> %i @ %04x", rST&7, d&7, GET_PPC_OFFS());
360 if ((rST ^ d) & 0x0f98) elprintf(EL_SVP, "ssp FIXME ST %04x -> %04x @ %04x", rST, d, GET_PPC_OFFS());
5de27868 361 rST = d;
017512f2 362}
363
364// 5
365static u32 read_STACK(void)
366{
5de27868 367 --rSTACK;
368 if ((short)rSTACK < 0) {
369 rSTACK = 5;
3554b0a4 370 elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: stack underflow! (%i) @ %04x", rSTACK, GET_PPC_OFFS());
5de27868 371 }
372 return ssp->stack[rSTACK];
017512f2 373}
374
375static void write_STACK(u32 d)
376{
5de27868 377 if (rSTACK >= 6) {
3554b0a4 378 elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: stack overflow! (%i) @ %04x", rSTACK, GET_PPC_OFFS());
5de27868 379 rSTACK = 0;
380 }
381 ssp->stack[rSTACK++] = d;
017512f2 382}
383
384// 6
385static u32 read_PC(void)
386{
387 return GET_PC();
388}
389
390static void write_PC(u32 d)
391{
392 SET_PC(d);
393 g_cycles--;
394}
395
396// 7
397static u32 read_P(void)
398{
4fd5325d 399 int m1 = (signed short)rX;
400 int m2 = (signed short)rY;
3554b0a4 401 rP.v = (m1 * m2 * 2);
017512f2 402 return rP.h;
403}
404
5de27868 405// -----------------------------------------------------
406
3554b0a4 407static int get_inc(int mode)
5de27868 408{
3554b0a4 409 int inc = (mode >> 11) & 7;
410 if (inc != 0) {
411 if (inc != 7) inc--;
412 inc = (1<<16) << inc; // 0 1 2 4 8 16 32 128
413 if (mode & 0x8000) inc = -inc; // decrement mode
414 }
415 return inc;
5de27868 416}
417
d26dc685 418#define overwite_write(dst, d) \
419{ \
420 if (d & 0xf000) { dst &= ~0xf000; dst |= d & 0xf000; } \
421 if (d & 0x0f00) { dst &= ~0x0f00; dst |= d & 0x0f00; } \
422 if (d & 0x00f0) { dst &= ~0x00f0; dst |= d & 0x00f0; } \
423 if (d & 0x000f) { dst &= ~0x000f; dst |= d & 0x000f; } \
424}
425
017512f2 426static u32 pm_io(int reg, int write, u32 d)
427{
67256d4b 428 if (ssp->emu_status & SSP_PMC_SET)
429 {
430 // this MUST be blind r or w
431 if ((*(PC-1) & 0xff0f) && (*(PC-1) & 0xfff0)) {
3554b0a4 432 elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: tried to set PM%i (%c) with non-blind i/o %08x @ %04x",
67256d4b 433 reg, write ? 'w' : 'r', rPMC.v, GET_PPC_OFFS());
434 ssp->emu_status &= ~SSP_PMC_SET;
435 return 0;
436 }
5de27868 437 elprintf(EL_SVP, "PM%i (%c) set to %08x @ %04x", reg, write ? 'w' : 'r', rPMC.v, GET_PPC_OFFS());
017512f2 438 ssp->pmac_read[write ? reg + 6 : reg] = rPMC.v;
439 ssp->emu_status &= ~SSP_PMC_SET;
30752975 440 if ((rPMC.v & 0x7f) == 0x1c && (rPMC.v & 0x7fff0000) == 0) {
3554b0a4 441 elprintf(EL_SVP, "ssp IRAM copy from %06x", (ssp->RAM1[0]-1)<<1);
442#ifdef USE_DEBUGGER
30752975 443 last_iram = (ssp->RAM1[0]-1)<<1;
3554b0a4 444#endif
30752975 445 }
017512f2 446 return 0;
447 }
448
5de27868 449 // just in case
67256d4b 450 if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
3554b0a4 451 elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: PM%i (%c) with only addr set @ %04x",
67256d4b 452 reg, write ? 'w' : 'r', GET_PPC_OFFS());
453 ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
454 }
5de27868 455
5de27868 456 if (reg == 4 || (rST & 0x60))
457 {
30752975 458 #define CADDR ((((mode<<16)&0x7f0000)|addr)<<1)
d26dc685 459 unsigned short *dram = (unsigned short *)svp->dram;
5de27868 460 if (write)
461 {
462 int mode = ssp->pmac_write[reg]&0xffff;
463 int addr = ssp->pmac_write[reg]>>16;
3554b0a4 464 if ((mode & 0xb800) == 0xb800)
465 elprintf(EL_SVP, "ssp FIXME: mode %04x", mode);
466 if ((mode & 0x43ff) == 0x0018) // DRAM
467 {
468 int inc = get_inc(mode);
469 elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (inc %i, ovrw %i)",
470 reg, CADDR, d, inc >> 16, (mode>>10)&1);
471 if (mode & 0x0400) {
472 overwite_write(dram[addr], d);
473 } else dram[addr] = d;
474 ssp->pmac_write[reg] += inc;
475 }
476 else if ((mode & 0xfbff) == 0x4018) // DRAM, cell inc
477 {
478 elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (cell inc, ovrw %i) @ %04x",
479 reg, CADDR, d, (mode>>10)&1, GET_PPC_OFFS());
480 if (mode & 0x0400) {
481 overwite_write(dram[addr], d);
482 } else dram[addr] = d;
483 ssp->pmac_write[reg] += (addr&1) ? (31<<16) : (1<<16);
484 }
485 else if ((mode & 0x47ff) == 0x001c) // IRAM
486 {
487 int inc = get_inc(mode);
488 if ((addr&0xfc00) != 0x8000)
489 elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: invalid IRAM addr: %04x", addr<<1);
490 elprintf(EL_SVP, "ssp IRAM w [%06x] %04x (inc %i)", (addr<<1)&0x7ff, d, inc >> 16);
491 ((unsigned short *)svp->iram_rom)[addr&0x3ff] = d;
492 ssp->pmac_write[reg] += inc;
493 }
494 else
495 {
496 elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: PM%i unhandled write mode %04x, [%06x] %04x @ %04x",
497 reg, mode, CADDR, d, GET_PPC_OFFS());
5de27868 498 }
499 }
500 else
501 {
502 int mode = ssp->pmac_read[reg]&0xffff;
503 int addr = ssp->pmac_read[reg]>>16;
3554b0a4 504 if ((mode & 0xfff0) == 0x0800) // ROM, inc 1, verified to be correct
505 {
d26dc685 506 elprintf(EL_SVP, "ssp ROM r [%06x] %04x", CADDR,
507 ((unsigned short *)Pico.rom)[addr|((mode&0xf)<<16)]);
508 ssp->pmac_read[reg] += 1<<16;
509 d = ((unsigned short *)Pico.rom)[addr|((mode&0xf)<<16)];
d26dc685 510 }
3554b0a4 511 else if ((mode & 0x47ff) == 0x0018) // DRAM
512 {
513 int inc = get_inc(mode);
514 elprintf(EL_SVP, "ssp PM%i DRAM r [%06x] %04x (inc %i)", reg, CADDR, dram[addr], inc >> 16);
515 d = dram[addr];
516 ssp->pmac_read[reg] += inc;
517 }
518 else
519 {
520 elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: PM%i unhandled read mode %04x, [%06x] @ %04x",
521 reg, mode, CADDR, GET_PPC_OFFS());
522 d = 0;
5de27868 523 }
524 }
30752975 525
526 // PMC value corresponds to last PMR accessed (not sure).
527 rPMC.v = ssp->pmac_read[write ? reg + 6 : reg];
528
529 return d;
017512f2 530 }
531
532 return (u32)-1;
533}
534
535// 8
536static u32 read_PM0(void)
537{
538 u32 d = pm_io(0, 0, 0);
539 if (d != (u32)-1) return d;
67256d4b 540 elprintf(EL_SVP, "PM0 raw r %04x @ %04x", rPM0, GET_PPC_OFFS());
d26dc685 541 d = rPM0;
542 if (!(d & 2) && (GET_PPC_OFFS() == 0x800 || GET_PPC_OFFS() == 0x1851E)) {
543 ssp->emu_status |= SSP_WAIT_PM0; elprintf(EL_SVP, "det TIGHT loop: PM0");
544 }
545 rPM0 &= ~2; // ?
546 return d;
017512f2 547}
548
549static void write_PM0(u32 d)
550{
551 u32 r = pm_io(0, 1, d);
552 if (r != (u32)-1) return;
5de27868 553 elprintf(EL_SVP, "PM0 raw w %04x @ %04x", d, GET_PPC_OFFS());
d26dc685 554 rPM0 = d;
017512f2 555}
556
557// 9
558static u32 read_PM1(void)
559{
560 u32 d = pm_io(1, 0, 0);
561 if (d != (u32)-1) return d;
562 // can be removed?
5de27868 563 elprintf(EL_SVP, "PM1 raw r %04x @ %04x", rPM1, GET_PPC_OFFS());
564 return rPM1;
017512f2 565}
566
567static void write_PM1(u32 d)
568{
569 u32 r = pm_io(1, 1, d);
570 if (r != (u32)-1) return;
571 // can be removed?
5de27868 572 elprintf(EL_SVP, "PM1 raw w %04x @ %04x", d, GET_PPC_OFFS());
573 rPM1 = d;
017512f2 574}
575
576// 10
577static u32 read_PM2(void)
578{
579 u32 d = pm_io(2, 0, 0);
580 if (d != (u32)-1) return d;
581 // can be removed?
5de27868 582 elprintf(EL_SVP, "PM2 raw r %04x @ %04x", rPM2, GET_PPC_OFFS());
583 return rPM2;
017512f2 584}
585
586static void write_PM2(u32 d)
587{
588 u32 r = pm_io(2, 1, d);
589 if (r != (u32)-1) return;
590 // can be removed?
5de27868 591 elprintf(EL_SVP, "PM2 raw w %04x @ %04x", d, GET_PPC_OFFS());
592 rPM2 = d;
017512f2 593}
594
595// 11
596static u32 read_XST(void)
597{
598 // can be removed?
599 u32 d = pm_io(3, 0, 0);
600 if (d != (u32)-1) return d;
601
5de27868 602 elprintf(EL_SVP, "XST raw r %04x @ %04x", rXST, GET_PPC_OFFS());
603 return rXST;
017512f2 604}
f8ef8ff7 605
017512f2 606static void write_XST(u32 d)
f8ef8ff7 607{
017512f2 608 // can be removed?
609 u32 r = pm_io(3, 1, d);
610 if (r != (u32)-1) return;
611
5de27868 612 elprintf(EL_SVP, "XST raw w %04x @ %04x", d, GET_PPC_OFFS());
d26dc685 613 rPM0 |= 1;
5de27868 614 rXST = d;
017512f2 615}
616
617// 12
618static u32 read_PM4(void)
619{
620 u32 d = pm_io(4, 0, 0);
30752975 621 if (d == 0) {
622 switch (GET_PPC_OFFS()) {
d26dc685 623 case 0x0854: ssp->emu_status |= SSP_WAIT_30FE08; elprintf(EL_SVP, "det TIGHT loop: [30fe08]"); break;
624 case 0x4f12: ssp->emu_status |= SSP_WAIT_30FE06; elprintf(EL_SVP, "det TIGHT loop: [30fe06]"); break;
30752975 625 }
626 }
017512f2 627 if (d != (u32)-1) return d;
628 // can be removed?
5de27868 629 elprintf(EL_SVP, "PM4 raw r %04x @ %04x", rPM4, GET_PPC_OFFS());
630 return rPM4;
017512f2 631}
632
633static void write_PM4(u32 d)
634{
635 u32 r = pm_io(4, 1, d);
636 if (r != (u32)-1) return;
637 // can be removed?
5de27868 638 elprintf(EL_SVP, "PM4 raw w %04x @ %04x", d, GET_PPC_OFFS());
639 rPM4 = d;
017512f2 640}
641
642// 14
643static u32 read_PMC(void)
644{
3554b0a4 645 elprintf(EL_SVP, "PMC r a %04x (st %c) @ %04x", rPMC.h,
646 (ssp->emu_status & SSP_PMC_HAVE_ADDR) ? 'm' : 'a', GET_PPC_OFFS());
017512f2 647 if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
3554b0a4 648 //if (ssp->emu_status & SSP_PMC_SET)
649 // elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS());
017512f2 650 ssp->emu_status |= SSP_PMC_SET;
5de27868 651 ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
017512f2 652 } else {
653 ssp->emu_status |= SSP_PMC_HAVE_ADDR;
017512f2 654 }
3554b0a4 655 return rPMC.h;
017512f2 656}
657
658static void write_PMC(u32 d)
659{
660 if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
3554b0a4 661 //if (ssp->emu_status & SSP_PMC_SET)
662 // elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS());
017512f2 663 ssp->emu_status |= SSP_PMC_SET;
5de27868 664 ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
017512f2 665 rPMC.l = d;
67256d4b 666 elprintf(EL_SVP, "PMC w m %04x @ %04x", rPMC.l, GET_PPC_OFFS());
017512f2 667 } else {
668 ssp->emu_status |= SSP_PMC_HAVE_ADDR;
669 rPMC.h = d;
67256d4b 670 elprintf(EL_SVP, "PMC w a %04x @ %04x", rPMC.h, GET_PPC_OFFS());
017512f2 671 }
672}
673
674// 15
675static u32 read_AL(void)
676{
67256d4b 677 if (*(PC-1) == 0x000f) {
3554b0a4 678 elprintf(EL_SVP|EL_ANOMALY, "ssp dummy PM assign %08x @ %04x", rPMC.v, GET_PPC_OFFS());
67256d4b 679 ssp->emu_status &= ~(SSP_PMC_SET|SSP_PMC_HAVE_ADDR); // ?
67256d4b 680 }
017512f2 681 return rAL;
682}
683
684static void write_AL(u32 d)
685{
686 rAL = d;
687}
688
689
690typedef u32 (*read_func_t)(void);
691typedef void (*write_func_t)(u32 d);
692
693static read_func_t read_handlers[16] =
694{
695 read_unknown, read_unknown, read_unknown, read_unknown, // -, X, Y, A
696 read_unknown, // 4 ST
697 read_STACK,
698 read_PC,
699 read_P,
700 read_PM0, // 8
701 read_PM1,
702 read_PM2,
703 read_XST,
704 read_PM4, // 12
705 read_unknown, // 13 gr13
706 read_PMC,
707 read_AL
708};
709
710static write_func_t write_handlers[16] =
711{
712 write_unknown, write_unknown, write_unknown, write_unknown, // -, X, Y, A
5de27868 713// write_unknown, // 4 ST
714 write_ST, // 4 ST (debug hook)
017512f2 715 write_STACK,
716 write_PC,
717 write_unknown, // 7 P
718 write_PM0, // 8
719 write_PM1,
720 write_PM2,
721 write_XST,
722 write_PM4, // 12
723 write_unknown, // 13 gr13
724 write_PMC,
725 write_AL
726};
727
5de27868 728// -----------------------------------------------------
729// pointer register handlers
730
731//
732#define ptr1_read(op) ptr1_read_(op&3,(op>>6)&4,(op<<1)&0x18)
733
734static u32 ptr1_read_(int ri, int isj2, int modi3)
735{
736 //int t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
30752975 737 u32 mask, add = 0, t = ri | isj2 | modi3;
738 unsigned char *rp = NULL;
5de27868 739 switch (t)
740 {
741 // mod=0 (00)
742 case 0x00:
743 case 0x01:
744 case 0x02: return ssp->RAM0[ssp->r0[t&3]];
745 case 0x03: return ssp->RAM0[0];
746 case 0x04:
747 case 0x05:
748 case 0x06: return ssp->RAM1[ssp->r1[t&3]];
749 case 0x07: return ssp->RAM1[0];
750 // mod=1 (01), "+!"
5de27868 751 case 0x08:
5de27868 752 case 0x09:
30752975 753 case 0x0a: return ssp->RAM0[ssp->r0[t&3]++];
5de27868 754 case 0x0b: return ssp->RAM0[1];
755 case 0x0c:
5de27868 756 case 0x0d:
30752975 757 case 0x0e: return ssp->RAM1[ssp->r1[t&3]++];
5de27868 758 case 0x0f: return ssp->RAM1[1];
759 // mod=2 (10), "-"
760 case 0x10:
761 case 0x11:
30752975 762 case 0x12: rp = &ssp->r0[t&3]; t = ssp->RAM0[*rp];
763 if (!(rST&7)) { (*rp)--; return t; }
764 add = -1; goto modulo;
5de27868 765 case 0x13: return ssp->RAM0[2];
766 case 0x14:
767 case 0x15:
30752975 768 case 0x16: rp = &ssp->r1[t&3]; t = ssp->RAM1[*rp];
769 if (!(rST&7)) { (*rp)--; return t; }
770 add = -1; goto modulo;
5de27868 771 case 0x17: return ssp->RAM1[2];
30752975 772 // mod=3 (11), "+"
773 case 0x18:
774 case 0x19:
775 case 0x1a: rp = &ssp->r0[t&3]; t = ssp->RAM0[*rp];
776 if (!(rST&7)) { (*rp)++; return t; }
777 add = 1; goto modulo;
5de27868 778 case 0x1b: return ssp->RAM0[3];
30752975 779 case 0x1c:
780 case 0x1d:
781 case 0x1e: rp = &ssp->r1[t&3]; t = ssp->RAM1[*rp];
782 if (!(rST&7)) { (*rp)++; return t; }
783 add = 1; goto modulo;
5de27868 784 case 0x1f: return ssp->RAM1[3];
785 }
786
787 return 0;
30752975 788
789modulo:
790 mask = (1 << (rST&7)) - 1;
791 *rp = (*rp & ~mask) | ((*rp + add) & mask);
792 return t;
5de27868 793}
794
795static void ptr1_write(int op, u32 d)
796{
797 int t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
798 switch (t)
799 {
800 // mod=0 (00)
801 case 0x00:
802 case 0x01:
803 case 0x02: ssp->RAM0[ssp->r0[t&3]] = d; return;
804 case 0x03: ssp->RAM0[0] = d; return;
805 case 0x04:
806 case 0x05:
807 case 0x06: ssp->RAM1[ssp->r1[t&3]] = d; return;
808 case 0x07: ssp->RAM1[0] = d; return;
809 // mod=1 (01), "+!"
810 // mod=3, "+"
811 case 0x08:
812 case 0x18:
813 case 0x09:
814 case 0x19:
815 case 0x0a:
816 case 0x1a: ssp->RAM0[ssp->r0[t&3]++] = d; return;
817 case 0x0b: ssp->RAM0[1] = d; return;
818 case 0x0c:
819 case 0x1c:
820 case 0x0d:
821 case 0x1d:
822 case 0x0e:
823 case 0x1e: ssp->RAM1[ssp->r1[t&3]++] = d; return;
824 case 0x0f: ssp->RAM1[1] = d; return;
825 // mod=2 (10), "-"
826 case 0x10:
827 case 0x11:
828 case 0x12: ssp->RAM0[ssp->r0[t&3]--] = d; return;
829 case 0x13: ssp->RAM0[2] = d; return;
830 case 0x14:
831 case 0x15:
832 case 0x16: ssp->RAM1[ssp->r1[t&3]--] = d; return;
833 case 0x17: ssp->RAM1[2] = d; return;
834 // mod=3 (11)
835 case 0x1b: ssp->RAM0[3] = d; return;
836 case 0x1f: ssp->RAM1[3] = d; return;
837 }
838}
839
840static u32 ptr2_read(int op)
841{
842 int mv = 0, t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
843 switch (t)
844 {
845 // mod=0 (00)
846 case 0x00:
847 case 0x01:
848 case 0x02: mv = ssp->RAM0[ssp->r0[t&3]]++; break;
849 case 0x03: mv = ssp->RAM0[0]++; break;
850 case 0x04:
851 case 0x05:
852 case 0x06: mv = ssp->RAM1[ssp->r1[t&3]]++; break;
853 case 0x07: mv = ssp->RAM1[0]++; break;
854 // mod=1 (01)
855 case 0x0b: mv = ssp->RAM0[1]++; break;
856 case 0x0f: mv = ssp->RAM1[1]++; break;
857 // mod=2 (10)
858 case 0x13: mv = ssp->RAM0[2]++; break;
859 case 0x17: mv = ssp->RAM1[2]++; break;
860 // mod=3 (11)
861 case 0x1b: mv = ssp->RAM0[3]++; break;
862 case 0x1f: mv = ssp->RAM1[3]++; break;
30752975 863 default: elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: invalid mod in ((rX))? @ %04x", GET_PPC_OFFS());
5de27868 864 return 0;
865 }
866
867 return ((unsigned short *)svp->iram_rom)[mv];
868}
869
870
871// -----------------------------------------------------
872
017512f2 873void ssp1601_reset(ssp1601_t *l_ssp)
874{
875 ssp = l_ssp;
f8ef8ff7 876 ssp->emu_status = 0;
017512f2 877 ssp->gr[SSP_GR0].v = 0xffff0000;
f8ef8ff7 878 rPC = 0x400;
5de27868 879 rSTACK = 0; // ? using ascending stack
30752975 880 rST = 0;
f8ef8ff7 881}
882
883
3554b0a4 884#ifdef USE_DEBUGGER
5de27868 885static void debug_dump(void)
f8ef8ff7 886{
5de27868 887 printf("GR0: %04x X: %04x Y: %04x A: %08x\n", ssp->gr[SSP_GR0].h, rX, rY, ssp->gr[SSP_A].v);
888 printf("PC: %04x (%04x) P: %08x\n", GET_PC(), GET_PC() << 1, ssp->gr[SSP_P].v);
889 printf("PM0: %04x PM1: %04x PM2: %04x\n", rPM0, rPM1, rPM2);
890 printf("XST: %04x PM4: %04x PMC: %08x\n", rXST, rPM4, ssp->gr[SSP_PMC].v);
d26dc685 891 printf(" ST: %04x %c%c%c%c, GP0_0 %i, GP0_1 %i\n", rST, rST&SSP_FLAG_N?'N':'n', rST&SSP_FLAG_V?'V':'v',
892 rST&SSP_FLAG_Z?'Z':'z', rST&SSP_FLAG_L?'L':'l', (rST>>5)&1, (rST>>6)&1);
5de27868 893 printf("STACK: %i %04x %04x %04x %04x %04x %04x\n", rSTACK, ssp->stack[0], ssp->stack[1],
894 ssp->stack[2], ssp->stack[3], ssp->stack[4], ssp->stack[5]);
895 printf("r0-r2: %02x %02x %02x r4-r6: %02x %02x %02x\n", rIJ[0], rIJ[1], rIJ[2], rIJ[4], rIJ[5], rIJ[6]);
896 elprintf(EL_SVP, "cycles: %i, emu_status: %x", g_cycles, ssp->emu_status);
897}
f8ef8ff7 898
5de27868 899static void debug_dump_mem(void)
900{
901 int h, i;
902 printf("RAM0\n");
903 for (h = 0; h < 32; h++)
904 {
905 if (h == 16) printf("RAM1\n");
906 printf("%03x:", h*16);
907 for (i = 0; i < 16; i++)
908 printf(" %04x", ssp->RAM[h*16+i]);
909 printf("\n");
910 }
911}
912
30752975 913static void debug_dump2file(const char *fname, void *mem, int len)
914{
915 FILE *f = fopen(fname, "wb");
916 unsigned short *p = mem;
917 int i;
918 if (f) {
919 for (i = 0; i < len/2; i++) p[i] = (p[i]<<8) | (p[i]>>8);
920 fwrite(mem, 1, len, f);
921 fclose(f);
922 for (i = 0; i < len/2; i++) p[i] = (p[i]<<8) | (p[i]>>8);
923 printf("dumped to %s\n", fname);
924 }
925 else
926 printf("dump failed\n");
927}
928
5de27868 929static int bpts[10] = { 0, };
930
931static void debug(unsigned int pc, unsigned int op)
932{
933 static char buffo[64] = {0,};
934 char buff[64] = {0,};
935 int i;
936
937 if (running) {
938 for (i = 0; i < 10; i++)
939 if (pc != 0 && bpts[i] == pc) {
940 printf("breakpoint %i\n", i);
941 running = 0;
942 break;
943 }
944 }
945 if (running) return;
946
947 printf("%04x (%02x) @ %04x\n", op, op >> 9, pc<<1);
948
949 while (1)
950 {
951 printf("dbg> ");
952 fflush(stdout);
953 fgets(buff, sizeof(buff), stdin);
954 if (buff[0] == '\n') strcpy(buff, buffo);
955 else strcpy(buffo, buff);
956
957 switch (buff[0]) {
958 case 0: exit(0);
959 case 'c':
960 case 'r': running = 1; return;
961 case 's':
962 case 'n': return;
963 case 'x': debug_dump(); break;
964 case 'm': debug_dump_mem(); break;
965 case 'b': {
966 char *baddr = buff + 2;
967 i = 0;
968 if (buff[3] == ' ') { i = buff[2] - '0'; baddr = buff + 4; }
969 bpts[i] = strtol(baddr, NULL, 16) >> 1;
970 printf("breakpoint %i set @ %04x\n", i, bpts[i]<<1);
971 break;
972 }
30752975 973 case 'd':
974 sprintf(buff, "iramrom_%04x.bin", last_iram);
975 debug_dump2file(buff, svp->iram_rom, sizeof(svp->iram_rom));
976 debug_dump2file("dram.bin", svp->dram, sizeof(svp->dram));
5de27868 977 break;
5de27868 978 default: printf("unknown command\n"); break;
979 }
980 }
981}
3554b0a4 982#endif // USE_DEBUGGER
983
5de27868 984
985void ssp1601_run(int cycles)
986{
017512f2 987 SET_PC(rPC);
988 g_cycles = cycles;
f8ef8ff7 989
d26dc685 990 while (g_cycles > 0 && !(ssp->emu_status & SSP_WAIT_MASK))
f8ef8ff7 991 {
5de27868 992 int op;
993 u32 tmpv;
994
995 op = *PC++;
3554b0a4 996#ifdef USE_DEBUGGER
5de27868 997 debug(GET_PC()-1, op);
3554b0a4 998#endif
f8ef8ff7 999 switch (op >> 9)
1000 {
1001 // ld d, s
5de27868 1002 case 0x00:
f8ef8ff7 1003 if (op == 0) break; // nop
017512f2 1004 if (op == ((SSP_A<<4)|SSP_P)) { // A <- P
1005 // not sure. MAME claims that only hi word is transfered.
1006 read_P(); // update P
4bfc6da4 1007 rA32 = ssp->gr[SSP_P].v;
f8ef8ff7 1008 }
5de27868 1009 else
f8ef8ff7 1010 {
5de27868 1011 tmpv = REG_READ(op & 0x0f);
1012 REG_WRITE((op & 0xf0) >> 4, tmpv);
1013 }
1014 break;
1015
1016 // ld d, (ri)
1017 case 0x01: tmpv = ptr1_read(op); REG_WRITE((op & 0xf0) >> 4, tmpv); break;
1018
1019 // ld (ri), s
1020 case 0x02: tmpv = REG_READ((op & 0xf0) >> 4); ptr1_write(op, tmpv); break;
1021
1022 // ldi d, imm
1023 case 0x04: tmpv = *PC++; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
1024
1025 // ld d, ((ri))
1026 case 0x05: tmpv = ptr2_read(op); REG_WRITE((op & 0xf0) >> 4, tmpv); break;
1027
1028 // ldi (ri), imm
1029 case 0x06: tmpv = *PC++; ptr1_write(op, tmpv); break;
1030
1031 // ld adr, a
1032 case 0x07: ssp->RAM[op & 0x1ff] = rA; break;
1033
1034 // ld d, ri
1035 case 0x09: tmpv = rIJ[(op&3)|((op>>6)&4)]; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
1036
1037 // ld ri, s
1038 case 0x0a: rIJ[(op&3)|((op>>6)&4)] = REG_READ((op & 0xf0) >> 4); break;
1039
1040 // ldi ri, simm
1041 case 0x0c:
1042 case 0x0d:
1043 case 0x0e:
1044 case 0x0f: rIJ[(op>>8)&7] = op; break;
1045
1046 // call cond, addr
1047 case 0x24: {
1048 int cond = 0;
1049 COND_CHECK
1050 if (cond) { int new_PC = *PC++; write_STACK(GET_PC()); write_PC(new_PC); }
1051 else PC++;
1052 break;
1053 }
1054
1055 // ld d, (a)
1056 case 0x25: tmpv = ((unsigned short *)svp->iram_rom)[rA]; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
1057
1058 // bra cond, addr
1059 case 0x26: {
1060 int cond = 0;
1061 COND_CHECK
1062 if (cond) { int new_PC = *PC++; write_PC(new_PC); }
1063 else PC++;
1064 break;
1065 }
1066
1067 // mod cond, op
1068 case 0x48: {
1069 int cond = 0;
1070 COND_CHECK
1071 if (cond) {
1072 switch (op & 7) {
d26dc685 1073 case 2: rA32 = (signed int)rA32 >> 1; break; // shr (arithmetic)
5de27868 1074 case 3: rA32 <<= 1; break; // shl
d26dc685 1075 case 6: rA32 = -(signed int)rA32; break; // neg
1076 case 7: if ((int)rA32 < 0) rA32 = -(signed int)rA32; break; // abs
3554b0a4 1077 default: elprintf(EL_SVP, "ssp FIXME: unhandled mod %i @ %04x", op&7, GET_PPC_OFFS());
5de27868 1078 }
30752975 1079 UPD_ACC_ZN // ?
f8ef8ff7 1080 }
1081 break;
5de27868 1082 }
1083
3554b0a4 1084 // ???
30752975 1085 case 0x1b:
3554b0a4 1086#if 0
30752975 1087 // very uncertain about this one. What about b?
3554b0a4 1088 if (!(op&0x100)) elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: no b bit @ %04x", GET_PPC_OFFS());
30752975 1089 read_P(); // update P
4bfc6da4 1090 rA32 -= ssp->gr[SSP_P].v; // maybe only upper word?
1091 // UPD_ACC_ZN // I've seen code checking flags after this
30752975 1092 rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
1093 rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
30752975 1094#endif
3554b0a4 1095 break;
1096
5de27868 1097 // mpya (rj), (ri), b
1098 case 0x4b:
1099 // dunno if this is correct. What about b?
3554b0a4 1100 if (!(op&0x100)) elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: no b bit @ %04x", GET_PPC_OFFS());
5de27868 1101 read_P(); // update P
3554b0a4 1102 rA32 += ssp->gr[SSP_P].v; // confirmed to be 32bit
d26dc685 1103 UPD_ACC_ZN // ?
5de27868 1104 rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
1105 rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
1106 break;
1107
1108 // mld (rj), (ri), b
1109 case 0x5b:
1110 // dunno if this is correct. What about b?
3554b0a4 1111 if (!(op&0x100)) elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: no b bit @ %04x", GET_PPC_OFFS());
1112 rA32 = 0;
4bfc6da4 1113 rST &= 0x0fff; // ?
5de27868 1114 rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
1115 rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
1116 break;
1117
1118 // OP a, s
67256d4b 1119 case 0x10: OP_CHECK32(OP_SUBA32); tmpv = REG_READ(op & 0x0f); OP_SUBA(tmpv); break;
1120 case 0x30: OP_CHECK32(OP_CMPA32); tmpv = REG_READ(op & 0x0f); OP_CMPA(tmpv); break;
1121 case 0x40: OP_CHECK32(OP_ADDA32); tmpv = REG_READ(op & 0x0f); OP_ADDA(tmpv); break;
1122 case 0x50: OP_CHECK32(OP_ANDA32); tmpv = REG_READ(op & 0x0f); OP_ANDA(tmpv); break;
1123 case 0x60: OP_CHECK32(OP_ORA32 ); tmpv = REG_READ(op & 0x0f); OP_ORA (tmpv); break;
1124 case 0x70: OP_CHECK32(OP_EORA32); tmpv = REG_READ(op & 0x0f); OP_EORA(tmpv); break;
5de27868 1125
1126 // OP a, (ri)
1127 case 0x11: tmpv = ptr1_read(op); OP_SUBA(tmpv); break;
1128 case 0x31: tmpv = ptr1_read(op); OP_CMPA(tmpv); break;
1129 case 0x41: tmpv = ptr1_read(op); OP_ADDA(tmpv); break;
1130 case 0x51: tmpv = ptr1_read(op); OP_ANDA(tmpv); break;
1131 case 0x61: tmpv = ptr1_read(op); OP_ORA (tmpv); break;
1132 case 0x71: tmpv = ptr1_read(op); OP_EORA(tmpv); break;
1133
1134 // OP a, adr
1135 case 0x03: tmpv = ssp->RAM[op & 0x1ff]; OP_LDA (tmpv); break;
1136 case 0x13: tmpv = ssp->RAM[op & 0x1ff]; OP_SUBA(tmpv); break;
1137 case 0x33: tmpv = ssp->RAM[op & 0x1ff]; OP_CMPA(tmpv); break;
1138 case 0x43: tmpv = ssp->RAM[op & 0x1ff]; OP_ADDA(tmpv); break;
1139 case 0x53: tmpv = ssp->RAM[op & 0x1ff]; OP_ANDA(tmpv); break;
1140 case 0x63: tmpv = ssp->RAM[op & 0x1ff]; OP_ORA (tmpv); break;
1141 case 0x73: tmpv = ssp->RAM[op & 0x1ff]; OP_EORA(tmpv); break;
1142
1143 // OP a, imm
1144 case 0x14: tmpv = *PC++; OP_SUBA(tmpv); break;
1145 case 0x34: tmpv = *PC++; OP_CMPA(tmpv); break;
1146 case 0x44: tmpv = *PC++; OP_ADDA(tmpv); break;
1147 case 0x54: tmpv = *PC++; OP_ANDA(tmpv); break;
1148 case 0x64: tmpv = *PC++; OP_ORA (tmpv); break;
1149 case 0x74: tmpv = *PC++; OP_EORA(tmpv); break;
1150
1151 // OP a, ((ri))
1152 case 0x15: tmpv = ptr2_read(op); OP_SUBA(tmpv); break;
1153 case 0x35: tmpv = ptr2_read(op); OP_CMPA(tmpv); break;
1154 case 0x45: tmpv = ptr2_read(op); OP_ADDA(tmpv); break;
1155 case 0x55: tmpv = ptr2_read(op); OP_ANDA(tmpv); break;
1156 case 0x65: tmpv = ptr2_read(op); OP_ORA (tmpv); break;
1157 case 0x75: tmpv = ptr2_read(op); OP_EORA(tmpv); break;
1158
1159 // OP a, ri
1160 case 0x19: tmpv = rIJ[IJind]; OP_SUBA(tmpv); break;
1161 case 0x39: tmpv = rIJ[IJind]; OP_CMPA(tmpv); break;
1162 case 0x49: tmpv = rIJ[IJind]; OP_ADDA(tmpv); break;
1163 case 0x59: tmpv = rIJ[IJind]; OP_ANDA(tmpv); break;
1164 case 0x69: tmpv = rIJ[IJind]; OP_ORA (tmpv); break;
1165 case 0x79: tmpv = rIJ[IJind]; OP_EORA(tmpv); break;
1166
1167 // OP simm
4bfc6da4 1168 case 0x1c: OP_SUBA(op & 0xff); if (op&0x100) elprintf(EL_SVP, "FIXME: simm with upper bit set"); break;
1169 case 0x3c: OP_CMPA(op & 0xff); if (op&0x100) elprintf(EL_SVP, "FIXME: simm with upper bit set"); break;
1170 case 0x4c: OP_ADDA(op & 0xff); if (op&0x100) elprintf(EL_SVP, "FIXME: simm with upper bit set"); break;
5de27868 1171 // MAME code only does LSB of top word, but this looks wrong to me.
4bfc6da4 1172 case 0x5c: OP_ANDA(op & 0xff); if (op&0x100) elprintf(EL_SVP, "FIXME: simm with upper bit set"); break;
1173 case 0x6c: OP_ORA (op & 0xff); if (op&0x100) elprintf(EL_SVP, "FIXME: simm with upper bit set"); break;
1174 case 0x7c: OP_EORA(op & 0xff); if (op&0x100) elprintf(EL_SVP, "FIXME: simm with upper bit set"); break;
f8ef8ff7 1175
1176 default:
3554b0a4 1177 elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME unhandled op %04x @ %04x", op, GET_PPC_OFFS());
017512f2 1178 break;
f8ef8ff7 1179 }
017512f2 1180 g_cycles--;
f8ef8ff7 1181 }
1182
017512f2 1183 read_P(); // update P
f8ef8ff7 1184 rPC = GET_PC();
017512f2 1185
1186 if (ssp->gr[SSP_GR0].v != 0xffff0000)
3554b0a4 1187 elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: REG 0 corruption! %08x", ssp->gr[SSP_GR0].v);
f8ef8ff7 1188}
1189
fast MegaDrive/MegaCD/32X emulator