notaz.gp2x.de / picodrive.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
svp is working!!!
[picodrive.git] / Pico / carthw / svp / ssp16.c
CommitLineData
f8ef8ff7 1// basic, incomplete SSP160x (SSP1601?) interpreter
2
3/*
4 * Register info
5 * most names taken from MAME code
6 *
7 * 0. "-"
8 * size: 16
9 * desc: Constant register with all bits set (0xffff).
10 *
11 * 1. "X"
12 * size: 16
13 * desc: Generic register. When set, updates P (P = X * Y * 2) ??
14 *
15 * 2. "Y"
16 * size: 16
17 * desc: Generic register. When set, updates P (P = X * Y * 2) ??
18 *
19 * 3. "A"
20 * size: 32
21 * desc: Accumulator.
22 *
23 * 4. "ST"
24 * size: 16
25 * desc: Status register. From MAME: bits 0-9 are CONTROL, other FLAG
26 * fedc ba98 7654 3210
5de27868 27 * 210 - RPL (?) "Loop size". If non-zero, makes (rX+) and (rX-) respectively
28 * modulo-increment and modulo-decrement. The value shows which
29 * power of 2 to use, i.e. 4 means modulo by 16.
30 * (e: fir16_32.sc, IIR_4B.SC, DECIM.SC)
f8ef8ff7 31 * 43 - RB (?)
5de27868 32 * 5 - GP0_0 (ST5?) Changed before acessing PM0 (affects banking?).
33 * 6 - GP0_1 (ST6?) Cleared before acessing PM0 (affects banking?). Set after.
34 * datasheet says these (5,6) bits correspond to hardware pins.
35 * 7 - IE (?) Not directly used by SVP code (never set, but preserved)?
36 * 8 - OP (?) Not used by SVP code (only cleared)? (MAME: saturated value
37 * (probably means clamping? i.e. 0x7ffc + 9 -> 0x7fff))
f8ef8ff7 38 * 9 - MACS (?) Not used by SVP code (only cleared)? (e: "mac shift")
39 * a - GPI_0 Interrupt 0 enable/status?
40 * b - GPI_1 Interrupt 1 enable/status?
41 * c - L L flag. Carry?
42 * d - Z Zero flag.
43 * e - OV Overflow flag.
44 * f - N Negative flag.
45 * seen directly changing code sequences:
46 * ldi ST, 0 ld A, ST ld A, ST ld A, ST ldi st, 20h
47 * ldi ST, 60h ori A, 60h and A, E8h and A, E8h
48 * ld ST, A ld ST, A ori 3
49 * ld ST, A
50 *
51 * 5. "STACK"
52 * size: 16
53 * desc: hw stack of 6 levels (according to datasheet)
54 *
55 * 6. "PC"
56 * size: 16
57 * desc: Program counter.
58 *
59 * 7. "P"
60 * size: 32
61 * desc: multiply result register. Updated after mp* instructions,
62 * or writes to X or Y (P = X * Y * 2) ??
63 * probably affected by MACS bit in ST.
64 *
65 * 8. "PM0" (PM from PMAR name from Tasco's docs)
66 * size: 16?
67 * desc: Programmable Memory access register.
68 * On reset, or when one (both?) GP0 bits are clear,
d26dc685 69 * acts as status for XST, mapped at 015004 at 68k side:
70 * bit0: ssp has written something to XST (cleared when 015004 is read)
71 * bit1: 68k has written something through a1500{0|2} (cleared on PM0 read)
f8ef8ff7 72 *
73 * 9. "PM1"
74 * size: 16?
75 * desc: Programmable Memory access register.
76 * This reg. is only used as PMAR.
77 *
78 * 10. "PM2"
79 * size: 16?
80 * desc: Programmable Memory access register.
81 * This reg. is only used as PMAR.
82 *
83 * 11. "XST"
84 * size: 16?
d26dc685 85 * desc: eXternal STate. Mapped to a15000 and a15002 at 68k side.
f8ef8ff7 86 * Can be programmed as PMAR? (only seen in test mode code)
d26dc685 87 * Affects PM0 when written to?
f8ef8ff7 88 *
89 * 12. "PM4"
90 * size: 16?
91 * desc: Programmable Memory access register.
92 * This reg. is only used as PMAR. The most used PMAR by VR.
93 *
94 * 13. (unused by VR)
95 *
96 * 14. "PMC" (PMC from PMAC name from Tasco's docs)
97 * size: 32?
98 * desc: Programmable Memory access Control. Set using 2 16bit writes,
99 * first address, then mode word. After setting PMAC, PMAR sould
100 * be accessed to program it.
101 *
102 * 15. "AL"
103 * size: 16
104 * desc: Accumulator Low. 16 least significant bits of accumulator (not 100% sure)
105 * (normally reading acc (ld X, A) you get 16 most significant bits).
106 *
107 *
108 * There are 8 8-bit pointer registers rX. r0-r3 (ri) point to RAM0, r4-r7 (rj) point to RAM1.
5de27868 109 * They can be accessed directly, or 2 indirection levels can be used [ (rX), ((rX)) ],
110 * which work similar to * and ** operators in C, only they use different memory banks and
111 * ((rX)) also does post-increment. First indirection level (rX) accesses RAMx, second accesses
112 * program memory at address read from (rX), and increments value in (rX).
f8ef8ff7 113 *
114 * r0,r1,r2,r4,r5,r6 can be modified [ex: ldi r0, 5].
115 * 3 modifiers can be applied (optional):
5de27868 116 * + : post-increment [ex: ld a, (r0+) ]. Can be made modulo-increment by setting RPL bits in ST.
117 * - : post-decrement. Can be made modulo-decrement by setting RPL bits in ST (not sure).
118 * +!: post-increment, unaffected by RPL (probably).
119 * These are only used on 1st indirection level, so things like [ld a, ((r0+))] and [ld X, r6-]
120 * ar probably invalid.
f8ef8ff7 121 *
122 * r3 and r7 are special and can not be changed (at least Samsung samples and SVP code never do).
123 * They are fixed to the start of their RAM banks. (They are probably changeable for ssp1605+,
124 * Samsung's old DSP page claims that).
125 * 1 of these 4 modifiers must be used (short form direct addressing?):
126 * |00: RAMx[0] [ex: (r3|00), 0] (based on sample code)
127 * |01: RAMx[1]
128 * |10: RAMx[2] ? maybe 10h? accortding to Div_c_dp.sc, 2
129 * |11: RAMx[3]
130 *
131 *
132 * Instruction notes
133 *
d26dc685 134 * ld a, * doesn't affect flags! (e: A_LAW.SC, Div_c_dp.sc)
135 *
f8ef8ff7 136 * mld (rj), (ri) [, b]
137 * operation: A = 0; P = (rj) * (ri)
138 * notes: based on IIR_4B.SC sample. flags? what is b???
f8ef8ff7 139 *
140 * mpya (rj), (ri) [, b]
141 * name: multiply and add?
142 * operation: A += P; P = (rj) * (ri)
143 *
144 * mpys (rj), (ri), b
145 * name: multiply and subtract?
146 * notes: not used by VR code.
017512f2 147 *
d26dc685 148 * mod cond, op
149 * mod cond, shr does arithmetic shift
30752975 150 *
67256d4b 151 * 'ld -, AL' and probably 'ld AL, -' are for dummy assigns
152 *
30752975 153 * memory map:
154 * 000000 - 1fffff ROM, accessable by both
155 * 200000 - 2fffff unused?
d26dc685 156 * 300000 - 31ffff DRAM, both
30752975 157 * 320000 - 38ffff unused?
158 * 390000 - 3907ff IRAM. can only be accessed by ssp?
d26dc685 159 * 390000 - 39ffff similar mapping to "cell arrange" in Sega CD, 68k only?
160 * 3a0000 - 3affff similar mapping to "cell arrange" in Sega CD, a bit different
30752975 161 *
162 * 30fe02 - 0 if SVP busy, 1 if done (set by SVP, checked and cleared by 68k)
163 * 30fe06 - also sync related.
d26dc685 164 * 30fe08 - job number [1-12] for SVP. 0 means no job. Set by 68k, read-cleared by SVP.
165 *
67256d4b 166 * TODO:
167 * + figure out if 'op A, P' is 32bit (nearly sure it is)
168 * * what exactly is AL?
169 * * does mld, mpya load their operands into X and Y?
170 * * OP simm
171 *
d26dc685 172 * misc:
173 * pressing all buttons while resetting game will kick into test mode
017512f2 174 *
175 * Assumptions in this code
176 * P is not directly writeable
5de27868 177 * flags correspond to full 32bit accumulator
178 * only Z and N status flags are emulated (others unused by SVP)
179 * modifiers for 'OP a, ri' are ignored (invalid?/not used by SVP)
180 * modifiers '+' and '+!' act the same (this is most likely wrong)
181 * 'ld d, (a)' loads from program ROM
f8ef8ff7 182 */
183
184#include "../../PicoInt.h"
185
017512f2 186#define u32 unsigned int
187
188// 0
189#define rX ssp->gr[SSP_X].h
190#define rY ssp->gr[SSP_Y].h
191#define rA ssp->gr[SSP_A].h
192#define rST ssp->gr[SSP_ST].h // 4
193#define rSTACK ssp->gr[SSP_STACK].h
194#define rPC ssp->gr[SSP_PC].h
195#define rP ssp->gr[SSP_P]
196#define rPM0 ssp->gr[SSP_PM0].h // 8
197#define rPM1 ssp->gr[SSP_PM1].h
198#define rPM2 ssp->gr[SSP_PM2].h
199#define rXST ssp->gr[SSP_XST].h
200#define rPM4 ssp->gr[SSP_PM4].h // 12
201// 13
202#define rPMC ssp->gr[SSP_PMC] // will keep addr in .h, mode in .l
f8ef8ff7 203#define rAL ssp->gr[SSP_A].l
204
5de27868 205#define rA32 ssp->gr[SSP_A].v
206#define rIJ ssp->r
207
208#define IJind (((op>>6)&4)|(op&3))
209
210#define GET_PC() (PC - (unsigned short *)svp->iram_rom)
211#define GET_PPC_OFFS() ((unsigned int)PC - (unsigned int)svp->iram_rom - 2)
212#define SET_PC(d) PC = (unsigned short *)svp->iram_rom + d
017512f2 213
214#define REG_READ(r) (((r) <= 4) ? ssp->gr[r].h : read_handlers[r]())
215#define REG_WRITE(r,d) { \
216 int r1 = r; \
5de27868 217 if (r1 >= 4) write_handlers[r1](d); \
017512f2 218 else if (r1 > 0) ssp->gr[r1].h = d; \
219}
220
5de27868 221// flags
d26dc685 222#define SSP_FLAG_L (1<<0xc)
223#define SSP_FLAG_Z (1<<0xd)
224#define SSP_FLAG_V (1<<0xe)
225#define SSP_FLAG_N (1<<0xf)
5de27868 226
227// update ZN according to 32bit ACC.
228#define UPD_ACC_ZN \
d26dc685 229 rST &= ~(SSP_FLAG_Z|SSP_FLAG_N); \
230 if (!rA32) rST |= SSP_FLAG_Z; \
231 else rST |= (rA32>>16)&SSP_FLAG_N;
5de27868 232
233// it seems SVP code never checks for L and OV, so we leave them out.
d26dc685 234// rST |= (t>>4)&SSP_FLAG_L;
67256d4b 235#define UPD_LZVN \
236 rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
237 if (!rA32) rST |= SSP_FLAG_Z; \
238 else rST |= (rA32>>16)&SSP_FLAG_N;
239
5de27868 240// standard cond processing.
241// again, only Z and N is checked, as SVP doesn't seem to use any other conds.
242#define COND_CHECK \
243 switch (op&0xf0) { \
244 case 0x00: cond = 1; break; /* always true */ \
d26dc685 245 case 0x50: cond = !((rST ^ (op<<5)) & SSP_FLAG_Z); break; /* Z matches f(?) bit */ \
246 case 0x70: cond = !((rST ^ (op<<7)) & SSP_FLAG_N); break; /* N matches f(?) bit */ \
4bfc6da4 247 default:elprintf(EL_SVP, "ssp FIXME: unimplemented cond @ %04x", GET_PPC_OFFS()); break; \
5de27868 248 }
249
250// ops with accumulator.
251// how is low word really affected by these?
30752975 252// nearly sure 'ld A' doesn't affect flags
5de27868 253#define OP_LDA(x) \
30752975 254 ssp->gr[SSP_A].h = x
5de27868 255
67256d4b 256#define OP_LDA32(x) \
4bfc6da4 257 rA32 = x
67256d4b 258
5de27868 259#define OP_SUBA(x) { \
4bfc6da4 260 rA32 -= (x) << 16; \
261 UPD_LZVN \
5de27868 262}
263
67256d4b 264#define OP_SUBA32(x) { \
4bfc6da4 265 rA32 -= (x); \
67256d4b 266 UPD_LZVN \
267}
268
5de27868 269#define OP_CMPA(x) { \
4bfc6da4 270 u32 t = rA32 - ((x) << 16); \
271 rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
272 if (!t) rST |= SSP_FLAG_Z; \
273 else rST |= (t>>16)&SSP_FLAG_N; \
5de27868 274}
275
67256d4b 276#define OP_CMPA32(x) { \
4bfc6da4 277 u32 t = rA32 - (x); \
67256d4b 278 rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
279 if (!t) rST |= SSP_FLAG_Z; \
280 else rST |= (t>>16)&SSP_FLAG_N; \
281}
282
5de27868 283#define OP_ADDA(x) { \
4bfc6da4 284 rA32 += (x) << 16; \
285 UPD_LZVN \
5de27868 286}
287
67256d4b 288#define OP_ADDA32(x) { \
4bfc6da4 289 rA32 += (x); \
67256d4b 290 UPD_LZVN \
291}
292
5de27868 293#define OP_ANDA(x) \
4bfc6da4 294 rA32 &= (x) << 16; \
5de27868 295 UPD_ACC_ZN
296
67256d4b 297#define OP_ANDA32(x) \
4bfc6da4 298 rA32 &= (x); \
67256d4b 299 UPD_ACC_ZN
300
5de27868 301#define OP_ORA(x) \
4bfc6da4 302 rA32 |= (x) << 16; \
5de27868 303 UPD_ACC_ZN
304
67256d4b 305#define OP_ORA32(x) \
4bfc6da4 306 rA32 |= (x); \
67256d4b 307 UPD_ACC_ZN
308
5de27868 309#define OP_EORA(x) \
4bfc6da4 310 rA32 ^= (x) << 16; \
5de27868 311 UPD_ACC_ZN
312
67256d4b 313#define OP_EORA32(x) \
4bfc6da4 314 rA32 ^= (x); \
67256d4b 315 UPD_ACC_ZN
316
317
318#define OP_CHECK32(OP) \
319 if ((op & 0x0f) == SSP_P) { /* A <- P */ \
320 read_P(); /* update P */ \
321 OP(ssp->gr[SSP_P].v); \
322 break; \
323}
324
5de27868 325
017512f2 326static ssp1601_t *ssp = NULL;
327static unsigned short *PC;
328static int g_cycles;
5de27868 329// debug
330static int running = 0;
30752975 331static int last_iram = 0;
017512f2 332
333// -----------------------------------------------------
334// register i/o handlers
335
336// 0-4, 13
337static u32 read_unknown(void)
338{
30752975 339 elprintf(EL_ANOMALY|EL_SVP, "ssp16: FIXME: unknown read @ %04x", GET_PPC_OFFS());
017512f2 340 return 0;
341}
342
343static void write_unknown(u32 d)
344{
30752975 345 elprintf(EL_ANOMALY|EL_SVP, "ssp16: FIXME: unknown write @ %04x", GET_PPC_OFFS());
5de27868 346}
347
348// 4
349static void write_ST(u32 d)
350{
4fd5325d 351 if ((rST ^ d) & 0x0007) elprintf(EL_SVP, "ssp16: RPL %i -> %i @ %04x", rST&7, d&7, GET_PPC_OFFS());
352 if ((rST ^ d) & 0x0f98) elprintf(EL_SVP, "ssp16: FIXME ST %04x -> %04x @ %04x", rST, d, GET_PPC_OFFS());
5de27868 353 rST = d;
017512f2 354}
355
356// 5
357static u32 read_STACK(void)
358{
5de27868 359 //elprintf(EL_SVP, "pop %i @ %04x", rSTACK, GET_PPC_OFFS());
360 --rSTACK;
361 if ((short)rSTACK < 0) {
362 rSTACK = 5;
30752975 363 elprintf(EL_ANOMALY|EL_SVP, "ssp16: FIXME: stack underflow! (%i) @ %04x", rSTACK, GET_PPC_OFFS());
5de27868 364 }
365 return ssp->stack[rSTACK];
017512f2 366}
367
368static void write_STACK(u32 d)
369{
5de27868 370 if (rSTACK >= 6) {
30752975 371 running = 0;
372 elprintf(EL_ANOMALY|EL_SVP, "ssp16: FIXME: stack overflow! (%i) @ %04x", rSTACK, GET_PPC_OFFS());
5de27868 373 rSTACK = 0;
374 }
375 ssp->stack[rSTACK++] = d;
017512f2 376}
377
378// 6
379static u32 read_PC(void)
380{
381 return GET_PC();
382}
383
384static void write_PC(u32 d)
385{
386 SET_PC(d);
387 g_cycles--;
388}
389
390// 7
391static u32 read_P(void)
392{
4fd5325d 393 int m1 = (signed short)rX;
394 int m2 = (signed short)rY;
395 rP.v = (m1 * m2 * 2); // correct?
017512f2 396 return rP.h;
397}
398
5de27868 399// -----------------------------------------------------
400
401static void iram_write(int addr, u32 d, int reg, int inc)
402{
403 if ((addr&0xfc00) != 0x8000)
30752975 404 elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: invalid IRAM addr: %04x", addr<<1);
5de27868 405 elprintf(EL_SVP, "ssp IRAM w [%06x] %04x (inc %i)", (addr<<1)&0x7ff, d, inc);
406 ((unsigned short *)svp->iram_rom)[addr&0x3ff] = d;
407 ssp->pmac_write[reg] += inc<<16;
408}
409
30752975 410int lil[32] = { 0, }, lilp = 0;
411
412static void debug_dump2file(const char *fname, void *mem, int len);
413
d26dc685 414#define overwite_write(dst, d) \
415{ \
416 if (d & 0xf000) { dst &= ~0xf000; dst |= d & 0xf000; } \
417 if (d & 0x0f00) { dst &= ~0x0f00; dst |= d & 0x0f00; } \
418 if (d & 0x00f0) { dst &= ~0x00f0; dst |= d & 0x00f0; } \
419 if (d & 0x000f) { dst &= ~0x000f; dst |= d & 0x000f; } \
420}
421
017512f2 422static u32 pm_io(int reg, int write, u32 d)
423{
67256d4b 424 if (ssp->emu_status & SSP_PMC_SET)
425 {
426 // this MUST be blind r or w
427 if ((*(PC-1) & 0xff0f) && (*(PC-1) & 0xfff0)) {
428 elprintf(EL_SVP|EL_ANOMALY, "FIXME: tried to set PM%i (%c) with non-blind i/o %08x @ %04x",
429 reg, write ? 'w' : 'r', rPMC.v, GET_PPC_OFFS());
430 ssp->emu_status &= ~SSP_PMC_SET;
431 return 0;
432 }
5de27868 433 elprintf(EL_SVP, "PM%i (%c) set to %08x @ %04x", reg, write ? 'w' : 'r', rPMC.v, GET_PPC_OFFS());
017512f2 434 ssp->pmac_read[write ? reg + 6 : reg] = rPMC.v;
435 ssp->emu_status &= ~SSP_PMC_SET;
30752975 436 if ((rPMC.v & 0x7f) == 0x1c && (rPMC.v & 0x7fff0000) == 0) {
437 elprintf(EL_SVP, "IRAM copy from %06x", (ssp->RAM1[0]-1)<<1);
438/*
439 {
440 int i;
441 char buff[64];
442 for (i = 0; i < 32; i++) {
443 if (lil[i] == last_iram) break;
444 if (lil[i] == 0) {
445 lil[i] = last_iram;
446 sprintf(buff, "iramrom_%04x.bin", last_iram);
447 debug_dump2file(buff, svp->iram_rom, sizeof(svp->iram_rom));
448 break;
449 }
450 }
451 }
452*/
453 last_iram = (ssp->RAM1[0]-1)<<1;
454 }
017512f2 455 return 0;
456 }
457
5de27868 458 // just in case
67256d4b 459 if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
460 elprintf(EL_SVP|EL_ANOMALY, "FIXME: PM%i (%c) with only addr set @ %04x",
461 reg, write ? 'w' : 'r', GET_PPC_OFFS());
462 ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
463 }
5de27868 464
465// if (ssp->pmac_read[reg] != 0)
466 if (reg == 4 || (rST & 0x60))
467 {
30752975 468 #define CADDR ((((mode<<16)&0x7f0000)|addr)<<1)
d26dc685 469 unsigned short *dram = (unsigned short *)svp->dram;
5de27868 470 if (write)
471 {
d26dc685 472 /* TODO: 0c18 mode? */
5de27868 473 int mode = ssp->pmac_write[reg]&0xffff;
474 int addr = ssp->pmac_write[reg]>>16;
475 switch (mode) {
67256d4b 476 case 0x0018: elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x", reg, CADDR, d);
d26dc685 477 dram[addr] = d;
478 break;
67256d4b 479 case 0x0418: elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (overwr)", reg, CADDR, d);
d26dc685 480 overwite_write(dram[addr], d);
5de27868 481 break;
67256d4b 482 case 0x0818: elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (inc 1)", reg, CADDR, d);
d26dc685 483 dram[addr] = d;
5de27868 484 ssp->pmac_write[reg] += 1<<16;
485 break;
486 case 0x081c: iram_write(addr, d, reg, 1); break; // checked: used by code @ 0902
487 case 0x101c: iram_write(addr, d, reg, 2); break; // checked: used by code @ 3b7c
67256d4b 488 case 0x4018: elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (cell inc)", reg, CADDR, d);
d26dc685 489 dram[addr] = d;
490 ssp->pmac_write[reg] += (addr&1) ? (31<<16) : (1<<16);
491 break;
67256d4b 492 case 0x4418: elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (overwr, cell inc)", reg, CADDR, d);
d26dc685 493 overwite_write(dram[addr], d);
30752975 494 ssp->pmac_write[reg] += (addr&1) ? (31<<16) : (1<<16);
495 break;
5de27868 496 default: elprintf(EL_SVP|EL_ANOMALY, "ssp PM%i unhandled write mode %04x, [%06x] %04x @ %04x",
30752975 497 reg, mode, CADDR, d, GET_PPC_OFFS()); break;
5de27868 498 }
499 }
500 else
501 {
502 int mode = ssp->pmac_read[reg]&0xffff;
503 int addr = ssp->pmac_read[reg]>>16;
d26dc685 504 if ((mode & 0xfff0) == 0x0800) { // ROM, inc 1, verified to be correct
505 elprintf(EL_SVP, "ssp ROM r [%06x] %04x", CADDR,
506 ((unsigned short *)Pico.rom)[addr|((mode&0xf)<<16)]);
507 ssp->pmac_read[reg] += 1<<16;
508 d = ((unsigned short *)Pico.rom)[addr|((mode&0xf)<<16)];
509 goto ext_io_end;
510 }
511
5de27868 512 switch (mode) {
d26dc685 513 case 0x0018: elprintf(EL_SVP, "ssp DRAM r [%06x] %04x", CADDR, dram[addr]);
514 d = dram[addr]; // checked
30752975 515 break;
67256d4b 516 case 0x0818: elprintf(EL_SVP, "ssp PM%i DRAM r [%06x] %04x (inc 1)", reg, CADDR, dram[addr]);
30752975 517 ssp->pmac_read[reg] += 1<<16;
d26dc685 518 d = dram[addr];
30752975 519 break;
d26dc685 520 case 0x3018: elprintf(EL_SVP, "ssp DRAM r [%06x] %04x (inc 32)", CADDR, dram[addr]);
30752975 521 ssp->pmac_read[reg] += 32<<16;
d26dc685 522 d = dram[addr];
30752975 523 break;
d26dc685 524 case 0xa818: elprintf(EL_SVP, "ssp DRAM r [%06x] %04x (dec 16)", CADDR, dram[addr]);
30752975 525 ssp->pmac_read[reg] -= 16<<16;
d26dc685 526 d = dram[addr];
30752975 527 break;
d26dc685 528 case 0xb818: elprintf(EL_SVP, "ssp DRAM r [%06x] %04x (dec 128?)", CADDR, dram[addr]);
30752975 529 ssp->pmac_read[reg] -= 128<<16;
d26dc685 530 d = dram[addr];
30752975 531 break;
5de27868 532 default: elprintf(EL_SVP|EL_ANOMALY, "ssp PM%i unhandled read mode %04x, [%06x] @ %04x",
30752975 533 reg, mode, CADDR, GET_PPC_OFFS());
534 d = 0;
535 break;
5de27868 536 }
537 }
30752975 538
d26dc685 539ext_io_end:
30752975 540 // PMC value corresponds to last PMR accessed (not sure).
541 rPMC.v = ssp->pmac_read[write ? reg + 6 : reg];
542
543 return d;
017512f2 544 }
545
546 return (u32)-1;
547}
548
549// 8
550static u32 read_PM0(void)
551{
552 u32 d = pm_io(0, 0, 0);
553 if (d != (u32)-1) return d;
67256d4b 554 elprintf(EL_SVP, "PM0 raw r %04x @ %04x", rPM0, GET_PPC_OFFS());
d26dc685 555 d = rPM0;
556 if (!(d & 2) && (GET_PPC_OFFS() == 0x800 || GET_PPC_OFFS() == 0x1851E)) {
557 ssp->emu_status |= SSP_WAIT_PM0; elprintf(EL_SVP, "det TIGHT loop: PM0");
558 }
559 rPM0 &= ~2; // ?
560 return d;
017512f2 561}
562
563static void write_PM0(u32 d)
564{
565 u32 r = pm_io(0, 1, d);
566 if (r != (u32)-1) return;
5de27868 567 elprintf(EL_SVP, "PM0 raw w %04x @ %04x", d, GET_PPC_OFFS());
d26dc685 568 rPM0 = d;
017512f2 569}
570
571// 9
572static u32 read_PM1(void)
573{
574 u32 d = pm_io(1, 0, 0);
575 if (d != (u32)-1) return d;
576 // can be removed?
5de27868 577 elprintf(EL_SVP, "PM1 raw r %04x @ %04x", rPM1, GET_PPC_OFFS());
578 return rPM1;
017512f2 579}
580
581static void write_PM1(u32 d)
582{
583 u32 r = pm_io(1, 1, d);
584 if (r != (u32)-1) return;
585 // can be removed?
5de27868 586 elprintf(EL_SVP, "PM1 raw w %04x @ %04x", d, GET_PPC_OFFS());
587 rPM1 = d;
017512f2 588}
589
590// 10
591static u32 read_PM2(void)
592{
593 u32 d = pm_io(2, 0, 0);
594 if (d != (u32)-1) return d;
595 // can be removed?
5de27868 596 elprintf(EL_SVP, "PM2 raw r %04x @ %04x", rPM2, GET_PPC_OFFS());
597 return rPM2;
017512f2 598}
599
600static void write_PM2(u32 d)
601{
602 u32 r = pm_io(2, 1, d);
603 if (r != (u32)-1) return;
604 // can be removed?
5de27868 605 elprintf(EL_SVP, "PM2 raw w %04x @ %04x", d, GET_PPC_OFFS());
606 rPM2 = d;
017512f2 607}
608
609// 11
610static u32 read_XST(void)
611{
612 // can be removed?
613 u32 d = pm_io(3, 0, 0);
614 if (d != (u32)-1) return d;
615
5de27868 616 elprintf(EL_SVP, "XST raw r %04x @ %04x", rXST, GET_PPC_OFFS());
617 return rXST;
017512f2 618}
f8ef8ff7 619
017512f2 620static void write_XST(u32 d)
f8ef8ff7 621{
017512f2 622 // can be removed?
623 u32 r = pm_io(3, 1, d);
624 if (r != (u32)-1) return;
625
5de27868 626 elprintf(EL_SVP, "XST raw w %04x @ %04x", d, GET_PPC_OFFS());
d26dc685 627 rPM0 |= 1;
5de27868 628 rXST = d;
017512f2 629}
630
631// 12
632static u32 read_PM4(void)
633{
634 u32 d = pm_io(4, 0, 0);
30752975 635 if (d == 0) {
636 switch (GET_PPC_OFFS()) {
d26dc685 637 case 0x0854: ssp->emu_status |= SSP_WAIT_30FE08; elprintf(EL_SVP, "det TIGHT loop: [30fe08]"); break;
638 case 0x4f12: ssp->emu_status |= SSP_WAIT_30FE06; elprintf(EL_SVP, "det TIGHT loop: [30fe06]"); break;
30752975 639 }
640 }
017512f2 641 if (d != (u32)-1) return d;
642 // can be removed?
5de27868 643 elprintf(EL_SVP, "PM4 raw r %04x @ %04x", rPM4, GET_PPC_OFFS());
644 return rPM4;
017512f2 645}
646
647static void write_PM4(u32 d)
648{
649 u32 r = pm_io(4, 1, d);
650 if (r != (u32)-1) return;
651 // can be removed?
5de27868 652 elprintf(EL_SVP, "PM4 raw w %04x @ %04x", d, GET_PPC_OFFS());
653 rPM4 = d;
017512f2 654}
655
656// 14
657static u32 read_PMC(void)
658{
659 if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
660 if (ssp->emu_status & SSP_PMC_SET)
5de27868 661 elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS());
017512f2 662 ssp->emu_status |= SSP_PMC_SET;
5de27868 663 ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
67256d4b 664 elprintf(EL_SVP, "PMC r m %04x @ %04x", rPMC.l, GET_PPC_OFFS());
017512f2 665 return rPMC.l;
666 } else {
667 ssp->emu_status |= SSP_PMC_HAVE_ADDR;
67256d4b 668 elprintf(EL_SVP, "PMC r a %04x @ %04x", rPMC.h, GET_PPC_OFFS());
017512f2 669 return rPMC.h;
670 }
671}
672
673static void write_PMC(u32 d)
674{
675 if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
676 if (ssp->emu_status & SSP_PMC_SET)
5de27868 677 elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS());
017512f2 678 ssp->emu_status |= SSP_PMC_SET;
5de27868 679 ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
017512f2 680 rPMC.l = d;
67256d4b 681 elprintf(EL_SVP, "PMC w m %04x @ %04x", rPMC.l, GET_PPC_OFFS());
017512f2 682 } else {
683 ssp->emu_status |= SSP_PMC_HAVE_ADDR;
684 rPMC.h = d;
67256d4b 685 elprintf(EL_SVP, "PMC w a %04x @ %04x", rPMC.h, GET_PPC_OFFS());
017512f2 686 }
687}
688
689// 15
690static u32 read_AL(void)
691{
692 // TODO: figure out what's up with those blind reads..
67256d4b 693 if (*(PC-1) == 0x000f) {
694 elprintf(EL_SVP|EL_ANOMALY, "ssp dummy PM assign %08x, ST=%04x @ %04x", rPMC.v, rST, GET_PPC_OFFS());
695 ssp->emu_status &= ~(SSP_PMC_SET|SSP_PMC_HAVE_ADDR); // ?
696 } else {
697 //elprintf(EL_SVP, "ssp AL read, ST=%04x @ %04x", rST, GET_PPC_OFFS());
698 }
017512f2 699 return rAL;
700}
701
702static void write_AL(u32 d)
703{
67256d4b 704 //elprintf(EL_SVP, "ssp AL write %04x, ST=%04x @ %04x", d, rST, GET_PPC_OFFS());
017512f2 705 rAL = d;
706}
707
708
709typedef u32 (*read_func_t)(void);
710typedef void (*write_func_t)(u32 d);
711
712static read_func_t read_handlers[16] =
713{
714 read_unknown, read_unknown, read_unknown, read_unknown, // -, X, Y, A
715 read_unknown, // 4 ST
716 read_STACK,
717 read_PC,
718 read_P,
719 read_PM0, // 8
720 read_PM1,
721 read_PM2,
722 read_XST,
723 read_PM4, // 12
724 read_unknown, // 13 gr13
725 read_PMC,
726 read_AL
727};
728
729static write_func_t write_handlers[16] =
730{
731 write_unknown, write_unknown, write_unknown, write_unknown, // -, X, Y, A
5de27868 732// write_unknown, // 4 ST
733 write_ST, // 4 ST (debug hook)
017512f2 734 write_STACK,
735 write_PC,
736 write_unknown, // 7 P
737 write_PM0, // 8
738 write_PM1,
739 write_PM2,
740 write_XST,
741 write_PM4, // 12
742 write_unknown, // 13 gr13
743 write_PMC,
744 write_AL
745};
746
5de27868 747// -----------------------------------------------------
748// pointer register handlers
749
750//
751#define ptr1_read(op) ptr1_read_(op&3,(op>>6)&4,(op<<1)&0x18)
752
753static u32 ptr1_read_(int ri, int isj2, int modi3)
754{
755 //int t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
30752975 756 u32 mask, add = 0, t = ri | isj2 | modi3;
757 unsigned char *rp = NULL;
5de27868 758 switch (t)
759 {
760 // mod=0 (00)
761 case 0x00:
762 case 0x01:
763 case 0x02: return ssp->RAM0[ssp->r0[t&3]];
764 case 0x03: return ssp->RAM0[0];
765 case 0x04:
766 case 0x05:
767 case 0x06: return ssp->RAM1[ssp->r1[t&3]];
768 case 0x07: return ssp->RAM1[0];
769 // mod=1 (01), "+!"
5de27868 770 case 0x08:
5de27868 771 case 0x09:
30752975 772 case 0x0a: return ssp->RAM0[ssp->r0[t&3]++];
5de27868 773 case 0x0b: return ssp->RAM0[1];
774 case 0x0c:
5de27868 775 case 0x0d:
30752975 776 case 0x0e: return ssp->RAM1[ssp->r1[t&3]++];
5de27868 777 case 0x0f: return ssp->RAM1[1];
778 // mod=2 (10), "-"
779 case 0x10:
780 case 0x11:
30752975 781 case 0x12: rp = &ssp->r0[t&3]; t = ssp->RAM0[*rp];
782 if (!(rST&7)) { (*rp)--; return t; }
783 add = -1; goto modulo;
5de27868 784 case 0x13: return ssp->RAM0[2];
785 case 0x14:
786 case 0x15:
30752975 787 case 0x16: rp = &ssp->r1[t&3]; t = ssp->RAM1[*rp];
788 if (!(rST&7)) { (*rp)--; return t; }
789 add = -1; goto modulo;
5de27868 790 case 0x17: return ssp->RAM1[2];
30752975 791 // mod=3 (11), "+"
792 case 0x18:
793 case 0x19:
794 case 0x1a: rp = &ssp->r0[t&3]; t = ssp->RAM0[*rp];
795 if (!(rST&7)) { (*rp)++; return t; }
796 add = 1; goto modulo;
5de27868 797 case 0x1b: return ssp->RAM0[3];
30752975 798 case 0x1c:
799 case 0x1d:
800 case 0x1e: rp = &ssp->r1[t&3]; t = ssp->RAM1[*rp];
801 if (!(rST&7)) { (*rp)++; return t; }
802 add = 1; goto modulo;
5de27868 803 case 0x1f: return ssp->RAM1[3];
804 }
805
806 return 0;
30752975 807
808modulo:
809 mask = (1 << (rST&7)) - 1;
810 *rp = (*rp & ~mask) | ((*rp + add) & mask);
811 return t;
5de27868 812}
813
814static void ptr1_write(int op, u32 d)
815{
816 int t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
817 switch (t)
818 {
819 // mod=0 (00)
820 case 0x00:
821 case 0x01:
822 case 0x02: ssp->RAM0[ssp->r0[t&3]] = d; return;
823 case 0x03: ssp->RAM0[0] = d; return;
824 case 0x04:
825 case 0x05:
826 case 0x06: ssp->RAM1[ssp->r1[t&3]] = d; return;
827 case 0x07: ssp->RAM1[0] = d; return;
828 // mod=1 (01), "+!"
829 // mod=3, "+"
830 case 0x08:
831 case 0x18:
832 case 0x09:
833 case 0x19:
834 case 0x0a:
835 case 0x1a: ssp->RAM0[ssp->r0[t&3]++] = d; return;
836 case 0x0b: ssp->RAM0[1] = d; return;
837 case 0x0c:
838 case 0x1c:
839 case 0x0d:
840 case 0x1d:
841 case 0x0e:
842 case 0x1e: ssp->RAM1[ssp->r1[t&3]++] = d; return;
843 case 0x0f: ssp->RAM1[1] = d; return;
844 // mod=2 (10), "-"
845 case 0x10:
846 case 0x11:
847 case 0x12: ssp->RAM0[ssp->r0[t&3]--] = d; return;
848 case 0x13: ssp->RAM0[2] = d; return;
849 case 0x14:
850 case 0x15:
851 case 0x16: ssp->RAM1[ssp->r1[t&3]--] = d; return;
852 case 0x17: ssp->RAM1[2] = d; return;
853 // mod=3 (11)
854 case 0x1b: ssp->RAM0[3] = d; return;
855 case 0x1f: ssp->RAM1[3] = d; return;
856 }
857}
858
859static u32 ptr2_read(int op)
860{
861 int mv = 0, t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
862 switch (t)
863 {
864 // mod=0 (00)
865 case 0x00:
866 case 0x01:
867 case 0x02: mv = ssp->RAM0[ssp->r0[t&3]]++; break;
868 case 0x03: mv = ssp->RAM0[0]++; break;
869 case 0x04:
870 case 0x05:
871 case 0x06: mv = ssp->RAM1[ssp->r1[t&3]]++; break;
872 case 0x07: mv = ssp->RAM1[0]++; break;
873 // mod=1 (01)
874 case 0x0b: mv = ssp->RAM0[1]++; break;
875 case 0x0f: mv = ssp->RAM1[1]++; break;
876 // mod=2 (10)
877 case 0x13: mv = ssp->RAM0[2]++; break;
878 case 0x17: mv = ssp->RAM1[2]++; break;
879 // mod=3 (11)
880 case 0x1b: mv = ssp->RAM0[3]++; break;
881 case 0x1f: mv = ssp->RAM1[3]++; break;
30752975 882 default: elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: invalid mod in ((rX))? @ %04x", GET_PPC_OFFS());
5de27868 883 return 0;
884 }
885
886 return ((unsigned short *)svp->iram_rom)[mv];
887}
888
889
890// -----------------------------------------------------
891
017512f2 892void ssp1601_reset(ssp1601_t *l_ssp)
893{
894 ssp = l_ssp;
f8ef8ff7 895 ssp->emu_status = 0;
017512f2 896 ssp->gr[SSP_GR0].v = 0xffff0000;
f8ef8ff7 897 rPC = 0x400;
5de27868 898 rSTACK = 0; // ? using ascending stack
30752975 899 rST = 0;
f8ef8ff7 900}
901
902
5de27868 903static void debug_dump(void)
f8ef8ff7 904{
5de27868 905 printf("GR0: %04x X: %04x Y: %04x A: %08x\n", ssp->gr[SSP_GR0].h, rX, rY, ssp->gr[SSP_A].v);
906 printf("PC: %04x (%04x) P: %08x\n", GET_PC(), GET_PC() << 1, ssp->gr[SSP_P].v);
907 printf("PM0: %04x PM1: %04x PM2: %04x\n", rPM0, rPM1, rPM2);
908 printf("XST: %04x PM4: %04x PMC: %08x\n", rXST, rPM4, ssp->gr[SSP_PMC].v);
d26dc685 909 printf(" ST: %04x %c%c%c%c, GP0_0 %i, GP0_1 %i\n", rST, rST&SSP_FLAG_N?'N':'n', rST&SSP_FLAG_V?'V':'v',
910 rST&SSP_FLAG_Z?'Z':'z', rST&SSP_FLAG_L?'L':'l', (rST>>5)&1, (rST>>6)&1);
5de27868 911 printf("STACK: %i %04x %04x %04x %04x %04x %04x\n", rSTACK, ssp->stack[0], ssp->stack[1],
912 ssp->stack[2], ssp->stack[3], ssp->stack[4], ssp->stack[5]);
913 printf("r0-r2: %02x %02x %02x r4-r6: %02x %02x %02x\n", rIJ[0], rIJ[1], rIJ[2], rIJ[4], rIJ[5], rIJ[6]);
914 elprintf(EL_SVP, "cycles: %i, emu_status: %x", g_cycles, ssp->emu_status);
915}
f8ef8ff7 916
5de27868 917static void debug_dump_mem(void)
918{
919 int h, i;
920 printf("RAM0\n");
921 for (h = 0; h < 32; h++)
922 {
923 if (h == 16) printf("RAM1\n");
924 printf("%03x:", h*16);
925 for (i = 0; i < 16; i++)
926 printf(" %04x", ssp->RAM[h*16+i]);
927 printf("\n");
928 }
929}
930
30752975 931static void debug_dump2file(const char *fname, void *mem, int len)
932{
933 FILE *f = fopen(fname, "wb");
934 unsigned short *p = mem;
935 int i;
936 if (f) {
937 for (i = 0; i < len/2; i++) p[i] = (p[i]<<8) | (p[i]>>8);
938 fwrite(mem, 1, len, f);
939 fclose(f);
940 for (i = 0; i < len/2; i++) p[i] = (p[i]<<8) | (p[i]>>8);
941 printf("dumped to %s\n", fname);
942 }
943 else
944 printf("dump failed\n");
945}
946
5de27868 947static int bpts[10] = { 0, };
948
949static void debug(unsigned int pc, unsigned int op)
950{
951 static char buffo[64] = {0,};
952 char buff[64] = {0,};
953 int i;
954
955 if (running) {
956 for (i = 0; i < 10; i++)
957 if (pc != 0 && bpts[i] == pc) {
958 printf("breakpoint %i\n", i);
959 running = 0;
960 break;
961 }
962 }
963 if (running) return;
964
965 printf("%04x (%02x) @ %04x\n", op, op >> 9, pc<<1);
966
967 while (1)
968 {
969 printf("dbg> ");
970 fflush(stdout);
971 fgets(buff, sizeof(buff), stdin);
972 if (buff[0] == '\n') strcpy(buff, buffo);
973 else strcpy(buffo, buff);
974
975 switch (buff[0]) {
976 case 0: exit(0);
977 case 'c':
978 case 'r': running = 1; return;
979 case 's':
980 case 'n': return;
981 case 'x': debug_dump(); break;
982 case 'm': debug_dump_mem(); break;
983 case 'b': {
984 char *baddr = buff + 2;
985 i = 0;
986 if (buff[3] == ' ') { i = buff[2] - '0'; baddr = buff + 4; }
987 bpts[i] = strtol(baddr, NULL, 16) >> 1;
988 printf("breakpoint %i set @ %04x\n", i, bpts[i]<<1);
989 break;
990 }
30752975 991 case 'd':
992 sprintf(buff, "iramrom_%04x.bin", last_iram);
993 debug_dump2file(buff, svp->iram_rom, sizeof(svp->iram_rom));
994 debug_dump2file("dram.bin", svp->dram, sizeof(svp->dram));
5de27868 995 break;
5de27868 996 default: printf("unknown command\n"); break;
997 }
998 }
999}
1000
1001void ssp1601_run(int cycles)
1002{
017512f2 1003 SET_PC(rPC);
1004 g_cycles = cycles;
f8ef8ff7 1005
d26dc685 1006//if (Pico.m.frame_count == 480) running = 0;
1007
1008 while (g_cycles > 0 && !(ssp->emu_status & SSP_WAIT_MASK))
f8ef8ff7 1009 {
5de27868 1010 int op;
1011 u32 tmpv;
1012
1013 op = *PC++;
1014 debug(GET_PC()-1, op);
f8ef8ff7 1015 switch (op >> 9)
1016 {
1017 // ld d, s
5de27868 1018 case 0x00:
f8ef8ff7 1019 if (op == 0) break; // nop
017512f2 1020 if (op == ((SSP_A<<4)|SSP_P)) { // A <- P
1021 // not sure. MAME claims that only hi word is transfered.
1022 read_P(); // update P
4bfc6da4 1023 rA32 = ssp->gr[SSP_P].v;
f8ef8ff7 1024 }
5de27868 1025 else
f8ef8ff7 1026 {
5de27868 1027 tmpv = REG_READ(op & 0x0f);
1028 REG_WRITE((op & 0xf0) >> 4, tmpv);
1029 }
1030 break;
1031
1032 // ld d, (ri)
1033 case 0x01: tmpv = ptr1_read(op); REG_WRITE((op & 0xf0) >> 4, tmpv); break;
1034
1035 // ld (ri), s
1036 case 0x02: tmpv = REG_READ((op & 0xf0) >> 4); ptr1_write(op, tmpv); break;
1037
1038 // ldi d, imm
1039 case 0x04: tmpv = *PC++; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
1040
1041 // ld d, ((ri))
1042 case 0x05: tmpv = ptr2_read(op); REG_WRITE((op & 0xf0) >> 4, tmpv); break;
1043
1044 // ldi (ri), imm
1045 case 0x06: tmpv = *PC++; ptr1_write(op, tmpv); break;
1046
1047 // ld adr, a
1048 case 0x07: ssp->RAM[op & 0x1ff] = rA; break;
1049
1050 // ld d, ri
1051 case 0x09: tmpv = rIJ[(op&3)|((op>>6)&4)]; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
1052
1053 // ld ri, s
1054 case 0x0a: rIJ[(op&3)|((op>>6)&4)] = REG_READ((op & 0xf0) >> 4); break;
1055
1056 // ldi ri, simm
1057 case 0x0c:
1058 case 0x0d:
1059 case 0x0e:
1060 case 0x0f: rIJ[(op>>8)&7] = op; break;
1061
1062 // call cond, addr
1063 case 0x24: {
1064 int cond = 0;
1065 COND_CHECK
1066 if (cond) { int new_PC = *PC++; write_STACK(GET_PC()); write_PC(new_PC); }
1067 else PC++;
1068 break;
1069 }
1070
1071 // ld d, (a)
1072 case 0x25: tmpv = ((unsigned short *)svp->iram_rom)[rA]; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
1073
1074 // bra cond, addr
1075 case 0x26: {
1076 int cond = 0;
1077 COND_CHECK
1078 if (cond) { int new_PC = *PC++; write_PC(new_PC); }
1079 else PC++;
1080 break;
1081 }
1082
1083 // mod cond, op
1084 case 0x48: {
1085 int cond = 0;
1086 COND_CHECK
1087 if (cond) {
1088 switch (op & 7) {
d26dc685 1089 case 2: rA32 = (signed int)rA32 >> 1; break; // shr (arithmetic)
5de27868 1090 case 3: rA32 <<= 1; break; // shl
d26dc685 1091 case 6: rA32 = -(signed int)rA32; break; // neg
1092 case 7: if ((int)rA32 < 0) rA32 = -(signed int)rA32; break; // abs
1093 default: elprintf(EL_SVP, "ssp16: FIXME unhandled mod %i @ %04x", op&7, GET_PPC_OFFS());
5de27868 1094 }
30752975 1095 UPD_ACC_ZN // ?
f8ef8ff7 1096 }
1097 break;
5de27868 1098 }
1099
30752975 1100#if 1
1101 // mpys?
1102 case 0x1b:
1103 // very uncertain about this one. What about b?
1104 if (!(op&0x100)) elprintf(EL_SVP|EL_ANOMALY, "ssp16: FIXME: no b bit @ %04x", GET_PPC_OFFS());
1105 read_P(); // update P
4bfc6da4 1106 rA32 -= ssp->gr[SSP_P].v; // maybe only upper word?
1107 // UPD_ACC_ZN // I've seen code checking flags after this
30752975 1108 rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
1109 rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
1110 break;
1111#endif
5de27868 1112 // mpya (rj), (ri), b
1113 case 0x4b:
1114 // dunno if this is correct. What about b?
30752975 1115 if (!(op&0x100)) elprintf(EL_SVP|EL_ANOMALY, "ssp16: FIXME: no b bit @ %04x", GET_PPC_OFFS());
5de27868 1116 read_P(); // update P
4bfc6da4 1117 rA32 += ssp->gr[SSP_P].v; // maybe only upper word?
d26dc685 1118 UPD_ACC_ZN // ?
5de27868 1119 rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
1120 rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
1121 break;
1122
1123 // mld (rj), (ri), b
1124 case 0x5b:
1125 // dunno if this is correct. What about b?
30752975 1126 if (!(op&0x100)) elprintf(EL_SVP|EL_ANOMALY, "ssp16: FIXME: no b bit @ %04x", GET_PPC_OFFS());
4bfc6da4 1127 rA32 = 0; // maybe only upper word?
1128 rST &= 0x0fff; // ?
5de27868 1129 rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
1130 rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
1131 break;
1132
1133 // OP a, s
67256d4b 1134 case 0x10: OP_CHECK32(OP_SUBA32); tmpv = REG_READ(op & 0x0f); OP_SUBA(tmpv); break;
1135 case 0x30: OP_CHECK32(OP_CMPA32); tmpv = REG_READ(op & 0x0f); OP_CMPA(tmpv); break;
1136 case 0x40: OP_CHECK32(OP_ADDA32); tmpv = REG_READ(op & 0x0f); OP_ADDA(tmpv); break;
1137 case 0x50: OP_CHECK32(OP_ANDA32); tmpv = REG_READ(op & 0x0f); OP_ANDA(tmpv); break;
1138 case 0x60: OP_CHECK32(OP_ORA32 ); tmpv = REG_READ(op & 0x0f); OP_ORA (tmpv); break;
1139 case 0x70: OP_CHECK32(OP_EORA32); tmpv = REG_READ(op & 0x0f); OP_EORA(tmpv); break;
5de27868 1140
1141 // OP a, (ri)
1142 case 0x11: tmpv = ptr1_read(op); OP_SUBA(tmpv); break;
1143 case 0x31: tmpv = ptr1_read(op); OP_CMPA(tmpv); break;
1144 case 0x41: tmpv = ptr1_read(op); OP_ADDA(tmpv); break;
1145 case 0x51: tmpv = ptr1_read(op); OP_ANDA(tmpv); break;
1146 case 0x61: tmpv = ptr1_read(op); OP_ORA (tmpv); break;
1147 case 0x71: tmpv = ptr1_read(op); OP_EORA(tmpv); break;
1148
1149 // OP a, adr
1150 case 0x03: tmpv = ssp->RAM[op & 0x1ff]; OP_LDA (tmpv); break;
1151 case 0x13: tmpv = ssp->RAM[op & 0x1ff]; OP_SUBA(tmpv); break;
1152 case 0x33: tmpv = ssp->RAM[op & 0x1ff]; OP_CMPA(tmpv); break;
1153 case 0x43: tmpv = ssp->RAM[op & 0x1ff]; OP_ADDA(tmpv); break;
1154 case 0x53: tmpv = ssp->RAM[op & 0x1ff]; OP_ANDA(tmpv); break;
1155 case 0x63: tmpv = ssp->RAM[op & 0x1ff]; OP_ORA (tmpv); break;
1156 case 0x73: tmpv = ssp->RAM[op & 0x1ff]; OP_EORA(tmpv); break;
1157
1158 // OP a, imm
1159 case 0x14: tmpv = *PC++; OP_SUBA(tmpv); break;
1160 case 0x34: tmpv = *PC++; OP_CMPA(tmpv); break;
1161 case 0x44: tmpv = *PC++; OP_ADDA(tmpv); break;
1162 case 0x54: tmpv = *PC++; OP_ANDA(tmpv); break;
1163 case 0x64: tmpv = *PC++; OP_ORA (tmpv); break;
1164 case 0x74: tmpv = *PC++; OP_EORA(tmpv); break;
1165
1166 // OP a, ((ri))
1167 case 0x15: tmpv = ptr2_read(op); OP_SUBA(tmpv); break;
1168 case 0x35: tmpv = ptr2_read(op); OP_CMPA(tmpv); break;
1169 case 0x45: tmpv = ptr2_read(op); OP_ADDA(tmpv); break;
1170 case 0x55: tmpv = ptr2_read(op); OP_ANDA(tmpv); break;
1171 case 0x65: tmpv = ptr2_read(op); OP_ORA (tmpv); break;
1172 case 0x75: tmpv = ptr2_read(op); OP_EORA(tmpv); break;
1173
1174 // OP a, ri
1175 case 0x19: tmpv = rIJ[IJind]; OP_SUBA(tmpv); break;
1176 case 0x39: tmpv = rIJ[IJind]; OP_CMPA(tmpv); break;
1177 case 0x49: tmpv = rIJ[IJind]; OP_ADDA(tmpv); break;
1178 case 0x59: tmpv = rIJ[IJind]; OP_ANDA(tmpv); break;
1179 case 0x69: tmpv = rIJ[IJind]; OP_ORA (tmpv); break;
1180 case 0x79: tmpv = rIJ[IJind]; OP_EORA(tmpv); break;
1181
1182 // OP simm
4bfc6da4 1183 case 0x1c: OP_SUBA(op & 0xff); if (op&0x100) elprintf(EL_SVP, "FIXME: simm with upper bit set"); break;
1184 case 0x3c: OP_CMPA(op & 0xff); if (op&0x100) elprintf(EL_SVP, "FIXME: simm with upper bit set"); break;
1185 case 0x4c: OP_ADDA(op & 0xff); if (op&0x100) elprintf(EL_SVP, "FIXME: simm with upper bit set"); break;
5de27868 1186 // MAME code only does LSB of top word, but this looks wrong to me.
4bfc6da4 1187 case 0x5c: OP_ANDA(op & 0xff); if (op&0x100) elprintf(EL_SVP, "FIXME: simm with upper bit set"); break;
1188 case 0x6c: OP_ORA (op & 0xff); if (op&0x100) elprintf(EL_SVP, "FIXME: simm with upper bit set"); break;
1189 case 0x7c: OP_EORA(op & 0xff); if (op&0x100) elprintf(EL_SVP, "FIXME: simm with upper bit set"); break;
f8ef8ff7 1190
1191 default:
d26dc685 1192 elprintf(EL_ANOMALY|EL_SVP, "ssp16: FIXME unhandled op %04x @ %04x", op, GET_PPC_OFFS());
017512f2 1193 break;
f8ef8ff7 1194 }
017512f2 1195 g_cycles--;
f8ef8ff7 1196 }
1197
017512f2 1198 read_P(); // update P
f8ef8ff7 1199 rPC = GET_PC();
017512f2 1200
1201 if (ssp->gr[SSP_GR0].v != 0xffff0000)
30752975 1202 elprintf(EL_ANOMALY|EL_SVP, "ssp16: FIXME: REG 0 corruption! %08x", ssp->gr[SSP_GR0].v);
f8ef8ff7 1203}
1204
fast MegaDrive/MegaCD/32X emulator