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fixed the arrow problem in VR
[picodrive.git] / Pico / carthw / svp / ssp16.c
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f8ef8ff7 1// basic, incomplete SSP160x (SSP1601?) interpreter
2
3/*
4 * Register info
5 * most names taken from MAME code
6 *
7 * 0. "-"
8 * size: 16
9 * desc: Constant register with all bits set (0xffff).
10 *
11 * 1. "X"
12 * size: 16
13 * desc: Generic register. When set, updates P (P = X * Y * 2) ??
14 *
15 * 2. "Y"
16 * size: 16
17 * desc: Generic register. When set, updates P (P = X * Y * 2) ??
18 *
19 * 3. "A"
20 * size: 32
21 * desc: Accumulator.
22 *
23 * 4. "ST"
24 * size: 16
25 * desc: Status register. From MAME: bits 0-9 are CONTROL, other FLAG
26 * fedc ba98 7654 3210
5de27868 27 * 210 - RPL (?) "Loop size". If non-zero, makes (rX+) and (rX-) respectively
28 * modulo-increment and modulo-decrement. The value shows which
29 * power of 2 to use, i.e. 4 means modulo by 16.
30 * (e: fir16_32.sc, IIR_4B.SC, DECIM.SC)
f8ef8ff7 31 * 43 - RB (?)
5de27868 32 * 5 - GP0_0 (ST5?) Changed before acessing PM0 (affects banking?).
33 * 6 - GP0_1 (ST6?) Cleared before acessing PM0 (affects banking?). Set after.
34 * datasheet says these (5,6) bits correspond to hardware pins.
35 * 7 - IE (?) Not directly used by SVP code (never set, but preserved)?
36 * 8 - OP (?) Not used by SVP code (only cleared)? (MAME: saturated value
37 * (probably means clamping? i.e. 0x7ffc + 9 -> 0x7fff))
f8ef8ff7 38 * 9 - MACS (?) Not used by SVP code (only cleared)? (e: "mac shift")
39 * a - GPI_0 Interrupt 0 enable/status?
40 * b - GPI_1 Interrupt 1 enable/status?
41 * c - L L flag. Carry?
42 * d - Z Zero flag.
43 * e - OV Overflow flag.
44 * f - N Negative flag.
45 * seen directly changing code sequences:
46 * ldi ST, 0 ld A, ST ld A, ST ld A, ST ldi st, 20h
47 * ldi ST, 60h ori A, 60h and A, E8h and A, E8h
48 * ld ST, A ld ST, A ori 3
49 * ld ST, A
50 *
51 * 5. "STACK"
52 * size: 16
53 * desc: hw stack of 6 levels (according to datasheet)
54 *
55 * 6. "PC"
56 * size: 16
57 * desc: Program counter.
58 *
59 * 7. "P"
60 * size: 32
61 * desc: multiply result register. Updated after mp* instructions,
62 * or writes to X or Y (P = X * Y * 2) ??
63 * probably affected by MACS bit in ST.
64 *
65 * 8. "PM0" (PM from PMAR name from Tasco's docs)
66 * size: 16?
67 * desc: Programmable Memory access register.
68 * On reset, or when one (both?) GP0 bits are clear,
d26dc685 69 * acts as status for XST, mapped at 015004 at 68k side:
70 * bit0: ssp has written something to XST (cleared when 015004 is read)
71 * bit1: 68k has written something through a1500{0|2} (cleared on PM0 read)
f8ef8ff7 72 *
73 * 9. "PM1"
74 * size: 16?
75 * desc: Programmable Memory access register.
76 * This reg. is only used as PMAR.
77 *
78 * 10. "PM2"
79 * size: 16?
80 * desc: Programmable Memory access register.
81 * This reg. is only used as PMAR.
82 *
83 * 11. "XST"
84 * size: 16?
d26dc685 85 * desc: eXternal STate. Mapped to a15000 and a15002 at 68k side.
f8ef8ff7 86 * Can be programmed as PMAR? (only seen in test mode code)
d26dc685 87 * Affects PM0 when written to?
f8ef8ff7 88 *
89 * 12. "PM4"
90 * size: 16?
91 * desc: Programmable Memory access register.
92 * This reg. is only used as PMAR. The most used PMAR by VR.
93 *
94 * 13. (unused by VR)
95 *
96 * 14. "PMC" (PMC from PMAC name from Tasco's docs)
97 * size: 32?
98 * desc: Programmable Memory access Control. Set using 2 16bit writes,
99 * first address, then mode word. After setting PMAC, PMAR sould
3554b0a4 100 * be blind accessed (ld -, PMx or ld PMx, -) to program it for
101 * reading and writing respectively.
102 * Reading the register also shifts it's state (from "waiting for
103 * address" to "waiting for mode" and back). Reads always return
104 * address related to last PMx register accressed.
689fb2c0 105 * (note: addresses do not wrap).
f8ef8ff7 106 *
107 * 15. "AL"
108 * size: 16
109 * desc: Accumulator Low. 16 least significant bits of accumulator (not 100% sure)
110 * (normally reading acc (ld X, A) you get 16 most significant bits).
111 *
112 *
113 * There are 8 8-bit pointer registers rX. r0-r3 (ri) point to RAM0, r4-r7 (rj) point to RAM1.
5de27868 114 * They can be accessed directly, or 2 indirection levels can be used [ (rX), ((rX)) ],
115 * which work similar to * and ** operators in C, only they use different memory banks and
116 * ((rX)) also does post-increment. First indirection level (rX) accesses RAMx, second accesses
117 * program memory at address read from (rX), and increments value in (rX).
f8ef8ff7 118 *
119 * r0,r1,r2,r4,r5,r6 can be modified [ex: ldi r0, 5].
120 * 3 modifiers can be applied (optional):
5de27868 121 * + : post-increment [ex: ld a, (r0+) ]. Can be made modulo-increment by setting RPL bits in ST.
122 * - : post-decrement. Can be made modulo-decrement by setting RPL bits in ST (not sure).
123 * +!: post-increment, unaffected by RPL (probably).
124 * These are only used on 1st indirection level, so things like [ld a, ((r0+))] and [ld X, r6-]
125 * ar probably invalid.
f8ef8ff7 126 *
127 * r3 and r7 are special and can not be changed (at least Samsung samples and SVP code never do).
128 * They are fixed to the start of their RAM banks. (They are probably changeable for ssp1605+,
129 * Samsung's old DSP page claims that).
130 * 1 of these 4 modifiers must be used (short form direct addressing?):
131 * |00: RAMx[0] [ex: (r3|00), 0] (based on sample code)
132 * |01: RAMx[1]
133 * |10: RAMx[2] ? maybe 10h? accortding to Div_c_dp.sc, 2
134 * |11: RAMx[3]
135 *
136 *
137 * Instruction notes
138 *
d26dc685 139 * ld a, * doesn't affect flags! (e: A_LAW.SC, Div_c_dp.sc)
140 *
f8ef8ff7 141 * mld (rj), (ri) [, b]
142 * operation: A = 0; P = (rj) * (ri)
143 * notes: based on IIR_4B.SC sample. flags? what is b???
f8ef8ff7 144 *
145 * mpya (rj), (ri) [, b]
146 * name: multiply and add?
147 * operation: A += P; P = (rj) * (ri)
148 *
149 * mpys (rj), (ri), b
150 * name: multiply and subtract?
151 * notes: not used by VR code.
017512f2 152 *
d26dc685 153 * mod cond, op
154 * mod cond, shr does arithmetic shift
30752975 155 *
67256d4b 156 * 'ld -, AL' and probably 'ld AL, -' are for dummy assigns
157 *
30752975 158 * memory map:
159 * 000000 - 1fffff ROM, accessable by both
160 * 200000 - 2fffff unused?
d26dc685 161 * 300000 - 31ffff DRAM, both
30752975 162 * 320000 - 38ffff unused?
163 * 390000 - 3907ff IRAM. can only be accessed by ssp?
d26dc685 164 * 390000 - 39ffff similar mapping to "cell arrange" in Sega CD, 68k only?
165 * 3a0000 - 3affff similar mapping to "cell arrange" in Sega CD, a bit different
30752975 166 *
167 * 30fe02 - 0 if SVP busy, 1 if done (set by SVP, checked and cleared by 68k)
168 * 30fe06 - also sync related.
d26dc685 169 * 30fe08 - job number [1-12] for SVP. 0 means no job. Set by 68k, read-cleared by SVP.
170 *
67256d4b 171 * TODO:
172 * + figure out if 'op A, P' is 32bit (nearly sure it is)
173 * * what exactly is AL?
174 * * does mld, mpya load their operands into X and Y?
175 * * OP simm
176 *
d26dc685 177 * misc:
178 * pressing all buttons while resetting game will kick into test mode
017512f2 179 *
180 * Assumptions in this code
181 * P is not directly writeable
5de27868 182 * flags correspond to full 32bit accumulator
183 * only Z and N status flags are emulated (others unused by SVP)
184 * modifiers for 'OP a, ri' are ignored (invalid?/not used by SVP)
185 * modifiers '+' and '+!' act the same (this is most likely wrong)
186 * 'ld d, (a)' loads from program ROM
f8ef8ff7 187 */
188
189#include "../../PicoInt.h"
190
017512f2 191#define u32 unsigned int
192
3554b0a4 193//#define USE_DEBUGGER
194
017512f2 195// 0
196#define rX ssp->gr[SSP_X].h
197#define rY ssp->gr[SSP_Y].h
198#define rA ssp->gr[SSP_A].h
199#define rST ssp->gr[SSP_ST].h // 4
200#define rSTACK ssp->gr[SSP_STACK].h
201#define rPC ssp->gr[SSP_PC].h
202#define rP ssp->gr[SSP_P]
203#define rPM0 ssp->gr[SSP_PM0].h // 8
204#define rPM1 ssp->gr[SSP_PM1].h
205#define rPM2 ssp->gr[SSP_PM2].h
206#define rXST ssp->gr[SSP_XST].h
207#define rPM4 ssp->gr[SSP_PM4].h // 12
208// 13
209#define rPMC ssp->gr[SSP_PMC] // will keep addr in .h, mode in .l
f8ef8ff7 210#define rAL ssp->gr[SSP_A].l
211
5de27868 212#define rA32 ssp->gr[SSP_A].v
213#define rIJ ssp->r
214
215#define IJind (((op>>6)&4)|(op&3))
216
217#define GET_PC() (PC - (unsigned short *)svp->iram_rom)
218#define GET_PPC_OFFS() ((unsigned int)PC - (unsigned int)svp->iram_rom - 2)
219#define SET_PC(d) PC = (unsigned short *)svp->iram_rom + d
017512f2 220
221#define REG_READ(r) (((r) <= 4) ? ssp->gr[r].h : read_handlers[r]())
222#define REG_WRITE(r,d) { \
223 int r1 = r; \
5de27868 224 if (r1 >= 4) write_handlers[r1](d); \
017512f2 225 else if (r1 > 0) ssp->gr[r1].h = d; \
226}
227
5de27868 228// flags
d26dc685 229#define SSP_FLAG_L (1<<0xc)
230#define SSP_FLAG_Z (1<<0xd)
231#define SSP_FLAG_V (1<<0xe)
232#define SSP_FLAG_N (1<<0xf)
5de27868 233
234// update ZN according to 32bit ACC.
235#define UPD_ACC_ZN \
d26dc685 236 rST &= ~(SSP_FLAG_Z|SSP_FLAG_N); \
237 if (!rA32) rST |= SSP_FLAG_Z; \
238 else rST |= (rA32>>16)&SSP_FLAG_N;
5de27868 239
240// it seems SVP code never checks for L and OV, so we leave them out.
d26dc685 241// rST |= (t>>4)&SSP_FLAG_L;
67256d4b 242#define UPD_LZVN \
243 rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
244 if (!rA32) rST |= SSP_FLAG_Z; \
245 else rST |= (rA32>>16)&SSP_FLAG_N;
246
5de27868 247// standard cond processing.
248// again, only Z and N is checked, as SVP doesn't seem to use any other conds.
249#define COND_CHECK \
250 switch (op&0xf0) { \
251 case 0x00: cond = 1; break; /* always true */ \
d26dc685 252 case 0x50: cond = !((rST ^ (op<<5)) & SSP_FLAG_Z); break; /* Z matches f(?) bit */ \
253 case 0x70: cond = !((rST ^ (op<<7)) & SSP_FLAG_N); break; /* N matches f(?) bit */ \
689fb2c0 254 default:elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: unimplemented cond @ %04x", GET_PPC_OFFS()); break; \
5de27868 255 }
256
257// ops with accumulator.
258// how is low word really affected by these?
30752975 259// nearly sure 'ld A' doesn't affect flags
5de27868 260#define OP_LDA(x) \
30752975 261 ssp->gr[SSP_A].h = x
5de27868 262
67256d4b 263#define OP_LDA32(x) \
4bfc6da4 264 rA32 = x
67256d4b 265
5de27868 266#define OP_SUBA(x) { \
4bfc6da4 267 rA32 -= (x) << 16; \
268 UPD_LZVN \
5de27868 269}
270
67256d4b 271#define OP_SUBA32(x) { \
4bfc6da4 272 rA32 -= (x); \
67256d4b 273 UPD_LZVN \
274}
275
5de27868 276#define OP_CMPA(x) { \
4bfc6da4 277 u32 t = rA32 - ((x) << 16); \
278 rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
279 if (!t) rST |= SSP_FLAG_Z; \
280 else rST |= (t>>16)&SSP_FLAG_N; \
5de27868 281}
282
67256d4b 283#define OP_CMPA32(x) { \
4bfc6da4 284 u32 t = rA32 - (x); \
67256d4b 285 rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
286 if (!t) rST |= SSP_FLAG_Z; \
287 else rST |= (t>>16)&SSP_FLAG_N; \
288}
289
5de27868 290#define OP_ADDA(x) { \
4bfc6da4 291 rA32 += (x) << 16; \
292 UPD_LZVN \
5de27868 293}
294
67256d4b 295#define OP_ADDA32(x) { \
4bfc6da4 296 rA32 += (x); \
67256d4b 297 UPD_LZVN \
298}
299
5de27868 300#define OP_ANDA(x) \
4bfc6da4 301 rA32 &= (x) << 16; \
5de27868 302 UPD_ACC_ZN
303
67256d4b 304#define OP_ANDA32(x) \
4bfc6da4 305 rA32 &= (x); \
67256d4b 306 UPD_ACC_ZN
307
5de27868 308#define OP_ORA(x) \
4bfc6da4 309 rA32 |= (x) << 16; \
5de27868 310 UPD_ACC_ZN
311
67256d4b 312#define OP_ORA32(x) \
4bfc6da4 313 rA32 |= (x); \
67256d4b 314 UPD_ACC_ZN
315
5de27868 316#define OP_EORA(x) \
4bfc6da4 317 rA32 ^= (x) << 16; \
5de27868 318 UPD_ACC_ZN
319
67256d4b 320#define OP_EORA32(x) \
4bfc6da4 321 rA32 ^= (x); \
67256d4b 322 UPD_ACC_ZN
323
324
325#define OP_CHECK32(OP) \
326 if ((op & 0x0f) == SSP_P) { /* A <- P */ \
327 read_P(); /* update P */ \
328 OP(ssp->gr[SSP_P].v); \
329 break; \
330}
331
5de27868 332
017512f2 333static ssp1601_t *ssp = NULL;
334static unsigned short *PC;
335static int g_cycles;
3554b0a4 336
337#ifdef USE_DEBUGGER
5de27868 338static int running = 0;
30752975 339static int last_iram = 0;
3554b0a4 340#endif
017512f2 341
342// -----------------------------------------------------
343// register i/o handlers
344
345// 0-4, 13
346static u32 read_unknown(void)
347{
3554b0a4 348 elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: unknown read @ %04x", GET_PPC_OFFS());
017512f2 349 return 0;
350}
351
352static void write_unknown(u32 d)
353{
3554b0a4 354 elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: unknown write @ %04x", GET_PPC_OFFS());
5de27868 355}
356
357// 4
358static void write_ST(u32 d)
359{
3554b0a4 360 //if ((rST ^ d) & 0x0007) elprintf(EL_SVP, "ssp RPL %i -> %i @ %04x", rST&7, d&7, GET_PPC_OFFS());
689fb2c0 361 if ((rST ^ d) & 0x0f98) elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME ST %04x -> %04x @ %04x", rST, d, GET_PPC_OFFS());
5de27868 362 rST = d;
017512f2 363}
364
365// 5
366static u32 read_STACK(void)
367{
5de27868 368 --rSTACK;
369 if ((short)rSTACK < 0) {
370 rSTACK = 5;
3554b0a4 371 elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: stack underflow! (%i) @ %04x", rSTACK, GET_PPC_OFFS());
5de27868 372 }
373 return ssp->stack[rSTACK];
017512f2 374}
375
376static void write_STACK(u32 d)
377{
5de27868 378 if (rSTACK >= 6) {
3554b0a4 379 elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: stack overflow! (%i) @ %04x", rSTACK, GET_PPC_OFFS());
5de27868 380 rSTACK = 0;
381 }
382 ssp->stack[rSTACK++] = d;
017512f2 383}
384
385// 6
386static u32 read_PC(void)
387{
388 return GET_PC();
389}
390
391static void write_PC(u32 d)
392{
393 SET_PC(d);
394 g_cycles--;
395}
396
397// 7
398static u32 read_P(void)
399{
4fd5325d 400 int m1 = (signed short)rX;
401 int m2 = (signed short)rY;
3554b0a4 402 rP.v = (m1 * m2 * 2);
017512f2 403 return rP.h;
404}
405
5de27868 406// -----------------------------------------------------
407
3554b0a4 408static int get_inc(int mode)
5de27868 409{
3554b0a4 410 int inc = (mode >> 11) & 7;
411 if (inc != 0) {
412 if (inc != 7) inc--;
413 inc = (1<<16) << inc; // 0 1 2 4 8 16 32 128
414 if (mode & 0x8000) inc = -inc; // decrement mode
415 }
416 return inc;
5de27868 417}
418
d26dc685 419#define overwite_write(dst, d) \
420{ \
421 if (d & 0xf000) { dst &= ~0xf000; dst |= d & 0xf000; } \
422 if (d & 0x0f00) { dst &= ~0x0f00; dst |= d & 0x0f00; } \
423 if (d & 0x00f0) { dst &= ~0x00f0; dst |= d & 0x00f0; } \
424 if (d & 0x000f) { dst &= ~0x000f; dst |= d & 0x000f; } \
425}
426
017512f2 427static u32 pm_io(int reg, int write, u32 d)
428{
67256d4b 429 if (ssp->emu_status & SSP_PMC_SET)
430 {
431 // this MUST be blind r or w
432 if ((*(PC-1) & 0xff0f) && (*(PC-1) & 0xfff0)) {
3554b0a4 433 elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: tried to set PM%i (%c) with non-blind i/o %08x @ %04x",
67256d4b 434 reg, write ? 'w' : 'r', rPMC.v, GET_PPC_OFFS());
435 ssp->emu_status &= ~SSP_PMC_SET;
436 return 0;
437 }
5de27868 438 elprintf(EL_SVP, "PM%i (%c) set to %08x @ %04x", reg, write ? 'w' : 'r', rPMC.v, GET_PPC_OFFS());
017512f2 439 ssp->pmac_read[write ? reg + 6 : reg] = rPMC.v;
440 ssp->emu_status &= ~SSP_PMC_SET;
30752975 441 if ((rPMC.v & 0x7f) == 0x1c && (rPMC.v & 0x7fff0000) == 0) {
3554b0a4 442 elprintf(EL_SVP, "ssp IRAM copy from %06x", (ssp->RAM1[0]-1)<<1);
443#ifdef USE_DEBUGGER
30752975 444 last_iram = (ssp->RAM1[0]-1)<<1;
3554b0a4 445#endif
30752975 446 }
017512f2 447 return 0;
448 }
449
5de27868 450 // just in case
67256d4b 451 if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
3554b0a4 452 elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: PM%i (%c) with only addr set @ %04x",
67256d4b 453 reg, write ? 'w' : 'r', GET_PPC_OFFS());
454 ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
455 }
5de27868 456
5de27868 457 if (reg == 4 || (rST & 0x60))
458 {
30752975 459 #define CADDR ((((mode<<16)&0x7f0000)|addr)<<1)
d26dc685 460 unsigned short *dram = (unsigned short *)svp->dram;
5de27868 461 if (write)
462 {
463 int mode = ssp->pmac_write[reg]&0xffff;
464 int addr = ssp->pmac_write[reg]>>16;
3554b0a4 465 if ((mode & 0xb800) == 0xb800)
689fb2c0 466 elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: mode %04x", mode);
3554b0a4 467 if ((mode & 0x43ff) == 0x0018) // DRAM
468 {
469 int inc = get_inc(mode);
470 elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (inc %i, ovrw %i)",
471 reg, CADDR, d, inc >> 16, (mode>>10)&1);
472 if (mode & 0x0400) {
473 overwite_write(dram[addr], d);
474 } else dram[addr] = d;
475 ssp->pmac_write[reg] += inc;
476 }
477 else if ((mode & 0xfbff) == 0x4018) // DRAM, cell inc
478 {
479 elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (cell inc, ovrw %i) @ %04x",
480 reg, CADDR, d, (mode>>10)&1, GET_PPC_OFFS());
481 if (mode & 0x0400) {
482 overwite_write(dram[addr], d);
483 } else dram[addr] = d;
484 ssp->pmac_write[reg] += (addr&1) ? (31<<16) : (1<<16);
485 }
486 else if ((mode & 0x47ff) == 0x001c) // IRAM
487 {
488 int inc = get_inc(mode);
489 if ((addr&0xfc00) != 0x8000)
490 elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: invalid IRAM addr: %04x", addr<<1);
491 elprintf(EL_SVP, "ssp IRAM w [%06x] %04x (inc %i)", (addr<<1)&0x7ff, d, inc >> 16);
492 ((unsigned short *)svp->iram_rom)[addr&0x3ff] = d;
493 ssp->pmac_write[reg] += inc;
494 }
495 else
496 {
497 elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: PM%i unhandled write mode %04x, [%06x] %04x @ %04x",
498 reg, mode, CADDR, d, GET_PPC_OFFS());
5de27868 499 }
500 }
501 else
502 {
503 int mode = ssp->pmac_read[reg]&0xffff;
504 int addr = ssp->pmac_read[reg]>>16;
3554b0a4 505 if ((mode & 0xfff0) == 0x0800) // ROM, inc 1, verified to be correct
506 {
d26dc685 507 elprintf(EL_SVP, "ssp ROM r [%06x] %04x", CADDR,
508 ((unsigned short *)Pico.rom)[addr|((mode&0xf)<<16)]);
689fb2c0 509 if ((signed int)ssp->pmac_read[reg] >> 16 == -1)
510 ssp->pmac_read[reg]++;
d26dc685 511 ssp->pmac_read[reg] += 1<<16;
512 d = ((unsigned short *)Pico.rom)[addr|((mode&0xf)<<16)];
d26dc685 513 }
3554b0a4 514 else if ((mode & 0x47ff) == 0x0018) // DRAM
515 {
516 int inc = get_inc(mode);
517 elprintf(EL_SVP, "ssp PM%i DRAM r [%06x] %04x (inc %i)", reg, CADDR, dram[addr], inc >> 16);
518 d = dram[addr];
519 ssp->pmac_read[reg] += inc;
520 }
521 else
522 {
523 elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: PM%i unhandled read mode %04x, [%06x] @ %04x",
524 reg, mode, CADDR, GET_PPC_OFFS());
525 d = 0;
5de27868 526 }
527 }
30752975 528
529 // PMC value corresponds to last PMR accessed (not sure).
530 rPMC.v = ssp->pmac_read[write ? reg + 6 : reg];
531
532 return d;
017512f2 533 }
534
535 return (u32)-1;
536}
537
538// 8
539static u32 read_PM0(void)
540{
541 u32 d = pm_io(0, 0, 0);
542 if (d != (u32)-1) return d;
67256d4b 543 elprintf(EL_SVP, "PM0 raw r %04x @ %04x", rPM0, GET_PPC_OFFS());
d26dc685 544 d = rPM0;
545 if (!(d & 2) && (GET_PPC_OFFS() == 0x800 || GET_PPC_OFFS() == 0x1851E)) {
546 ssp->emu_status |= SSP_WAIT_PM0; elprintf(EL_SVP, "det TIGHT loop: PM0");
547 }
548 rPM0 &= ~2; // ?
549 return d;
017512f2 550}
551
552static void write_PM0(u32 d)
553{
554 u32 r = pm_io(0, 1, d);
555 if (r != (u32)-1) return;
5de27868 556 elprintf(EL_SVP, "PM0 raw w %04x @ %04x", d, GET_PPC_OFFS());
d26dc685 557 rPM0 = d;
017512f2 558}
559
560// 9
561static u32 read_PM1(void)
562{
563 u32 d = pm_io(1, 0, 0);
564 if (d != (u32)-1) return d;
565 // can be removed?
5de27868 566 elprintf(EL_SVP, "PM1 raw r %04x @ %04x", rPM1, GET_PPC_OFFS());
567 return rPM1;
017512f2 568}
569
570static void write_PM1(u32 d)
571{
572 u32 r = pm_io(1, 1, d);
573 if (r != (u32)-1) return;
574 // can be removed?
5de27868 575 elprintf(EL_SVP, "PM1 raw w %04x @ %04x", d, GET_PPC_OFFS());
576 rPM1 = d;
017512f2 577}
578
579// 10
580static u32 read_PM2(void)
581{
582 u32 d = pm_io(2, 0, 0);
583 if (d != (u32)-1) return d;
584 // can be removed?
5de27868 585 elprintf(EL_SVP, "PM2 raw r %04x @ %04x", rPM2, GET_PPC_OFFS());
586 return rPM2;
017512f2 587}
588
589static void write_PM2(u32 d)
590{
591 u32 r = pm_io(2, 1, d);
592 if (r != (u32)-1) return;
593 // can be removed?
5de27868 594 elprintf(EL_SVP, "PM2 raw w %04x @ %04x", d, GET_PPC_OFFS());
595 rPM2 = d;
017512f2 596}
597
598// 11
599static u32 read_XST(void)
600{
601 // can be removed?
602 u32 d = pm_io(3, 0, 0);
603 if (d != (u32)-1) return d;
604
5de27868 605 elprintf(EL_SVP, "XST raw r %04x @ %04x", rXST, GET_PPC_OFFS());
606 return rXST;
017512f2 607}
f8ef8ff7 608
017512f2 609static void write_XST(u32 d)
f8ef8ff7 610{
017512f2 611 // can be removed?
612 u32 r = pm_io(3, 1, d);
613 if (r != (u32)-1) return;
614
5de27868 615 elprintf(EL_SVP, "XST raw w %04x @ %04x", d, GET_PPC_OFFS());
d26dc685 616 rPM0 |= 1;
5de27868 617 rXST = d;
017512f2 618}
619
620// 12
621static u32 read_PM4(void)
622{
623 u32 d = pm_io(4, 0, 0);
30752975 624 if (d == 0) {
625 switch (GET_PPC_OFFS()) {
d26dc685 626 case 0x0854: ssp->emu_status |= SSP_WAIT_30FE08; elprintf(EL_SVP, "det TIGHT loop: [30fe08]"); break;
627 case 0x4f12: ssp->emu_status |= SSP_WAIT_30FE06; elprintf(EL_SVP, "det TIGHT loop: [30fe06]"); break;
30752975 628 }
629 }
017512f2 630 if (d != (u32)-1) return d;
631 // can be removed?
5de27868 632 elprintf(EL_SVP, "PM4 raw r %04x @ %04x", rPM4, GET_PPC_OFFS());
633 return rPM4;
017512f2 634}
635
636static void write_PM4(u32 d)
637{
638 u32 r = pm_io(4, 1, d);
639 if (r != (u32)-1) return;
640 // can be removed?
5de27868 641 elprintf(EL_SVP, "PM4 raw w %04x @ %04x", d, GET_PPC_OFFS());
642 rPM4 = d;
017512f2 643}
644
645// 14
646static u32 read_PMC(void)
647{
3554b0a4 648 elprintf(EL_SVP, "PMC r a %04x (st %c) @ %04x", rPMC.h,
649 (ssp->emu_status & SSP_PMC_HAVE_ADDR) ? 'm' : 'a', GET_PPC_OFFS());
017512f2 650 if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
3554b0a4 651 //if (ssp->emu_status & SSP_PMC_SET)
652 // elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS());
017512f2 653 ssp->emu_status |= SSP_PMC_SET;
5de27868 654 ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
017512f2 655 } else {
656 ssp->emu_status |= SSP_PMC_HAVE_ADDR;
017512f2 657 }
3554b0a4 658 return rPMC.h;
017512f2 659}
660
661static void write_PMC(u32 d)
662{
663 if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
3554b0a4 664 //if (ssp->emu_status & SSP_PMC_SET)
665 // elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS());
017512f2 666 ssp->emu_status |= SSP_PMC_SET;
5de27868 667 ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
017512f2 668 rPMC.l = d;
67256d4b 669 elprintf(EL_SVP, "PMC w m %04x @ %04x", rPMC.l, GET_PPC_OFFS());
017512f2 670 } else {
671 ssp->emu_status |= SSP_PMC_HAVE_ADDR;
672 rPMC.h = d;
67256d4b 673 elprintf(EL_SVP, "PMC w a %04x @ %04x", rPMC.h, GET_PPC_OFFS());
017512f2 674 }
675}
676
677// 15
678static u32 read_AL(void)
679{
67256d4b 680 if (*(PC-1) == 0x000f) {
689fb2c0 681 elprintf(EL_SVP, "ssp dummy PM assign %08x @ %04x", rPMC.v, GET_PPC_OFFS());
67256d4b 682 ssp->emu_status &= ~(SSP_PMC_SET|SSP_PMC_HAVE_ADDR); // ?
67256d4b 683 }
017512f2 684 return rAL;
685}
686
687static void write_AL(u32 d)
688{
689 rAL = d;
690}
691
692
693typedef u32 (*read_func_t)(void);
694typedef void (*write_func_t)(u32 d);
695
696static read_func_t read_handlers[16] =
697{
698 read_unknown, read_unknown, read_unknown, read_unknown, // -, X, Y, A
699 read_unknown, // 4 ST
700 read_STACK,
701 read_PC,
702 read_P,
703 read_PM0, // 8
704 read_PM1,
705 read_PM2,
706 read_XST,
707 read_PM4, // 12
708 read_unknown, // 13 gr13
709 read_PMC,
710 read_AL
711};
712
713static write_func_t write_handlers[16] =
714{
715 write_unknown, write_unknown, write_unknown, write_unknown, // -, X, Y, A
5de27868 716// write_unknown, // 4 ST
717 write_ST, // 4 ST (debug hook)
017512f2 718 write_STACK,
719 write_PC,
720 write_unknown, // 7 P
721 write_PM0, // 8
722 write_PM1,
723 write_PM2,
724 write_XST,
725 write_PM4, // 12
726 write_unknown, // 13 gr13
727 write_PMC,
728 write_AL
729};
730
5de27868 731// -----------------------------------------------------
732// pointer register handlers
733
734//
735#define ptr1_read(op) ptr1_read_(op&3,(op>>6)&4,(op<<1)&0x18)
736
737static u32 ptr1_read_(int ri, int isj2, int modi3)
738{
739 //int t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
30752975 740 u32 mask, add = 0, t = ri | isj2 | modi3;
741 unsigned char *rp = NULL;
5de27868 742 switch (t)
743 {
744 // mod=0 (00)
745 case 0x00:
746 case 0x01:
747 case 0x02: return ssp->RAM0[ssp->r0[t&3]];
748 case 0x03: return ssp->RAM0[0];
749 case 0x04:
750 case 0x05:
751 case 0x06: return ssp->RAM1[ssp->r1[t&3]];
752 case 0x07: return ssp->RAM1[0];
753 // mod=1 (01), "+!"
5de27868 754 case 0x08:
5de27868 755 case 0x09:
30752975 756 case 0x0a: return ssp->RAM0[ssp->r0[t&3]++];
5de27868 757 case 0x0b: return ssp->RAM0[1];
758 case 0x0c:
5de27868 759 case 0x0d:
30752975 760 case 0x0e: return ssp->RAM1[ssp->r1[t&3]++];
5de27868 761 case 0x0f: return ssp->RAM1[1];
762 // mod=2 (10), "-"
763 case 0x10:
764 case 0x11:
30752975 765 case 0x12: rp = &ssp->r0[t&3]; t = ssp->RAM0[*rp];
766 if (!(rST&7)) { (*rp)--; return t; }
767 add = -1; goto modulo;
5de27868 768 case 0x13: return ssp->RAM0[2];
769 case 0x14:
770 case 0x15:
30752975 771 case 0x16: rp = &ssp->r1[t&3]; t = ssp->RAM1[*rp];
772 if (!(rST&7)) { (*rp)--; return t; }
773 add = -1; goto modulo;
5de27868 774 case 0x17: return ssp->RAM1[2];
30752975 775 // mod=3 (11), "+"
776 case 0x18:
777 case 0x19:
778 case 0x1a: rp = &ssp->r0[t&3]; t = ssp->RAM0[*rp];
779 if (!(rST&7)) { (*rp)++; return t; }
780 add = 1; goto modulo;
5de27868 781 case 0x1b: return ssp->RAM0[3];
30752975 782 case 0x1c:
783 case 0x1d:
784 case 0x1e: rp = &ssp->r1[t&3]; t = ssp->RAM1[*rp];
785 if (!(rST&7)) { (*rp)++; return t; }
786 add = 1; goto modulo;
5de27868 787 case 0x1f: return ssp->RAM1[3];
788 }
789
790 return 0;
30752975 791
792modulo:
793 mask = (1 << (rST&7)) - 1;
794 *rp = (*rp & ~mask) | ((*rp + add) & mask);
795 return t;
5de27868 796}
797
798static void ptr1_write(int op, u32 d)
799{
800 int t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
801 switch (t)
802 {
803 // mod=0 (00)
804 case 0x00:
805 case 0x01:
806 case 0x02: ssp->RAM0[ssp->r0[t&3]] = d; return;
807 case 0x03: ssp->RAM0[0] = d; return;
808 case 0x04:
809 case 0x05:
810 case 0x06: ssp->RAM1[ssp->r1[t&3]] = d; return;
811 case 0x07: ssp->RAM1[0] = d; return;
812 // mod=1 (01), "+!"
813 // mod=3, "+"
814 case 0x08:
815 case 0x18:
816 case 0x09:
817 case 0x19:
818 case 0x0a:
819 case 0x1a: ssp->RAM0[ssp->r0[t&3]++] = d; return;
820 case 0x0b: ssp->RAM0[1] = d; return;
821 case 0x0c:
822 case 0x1c:
823 case 0x0d:
824 case 0x1d:
825 case 0x0e:
826 case 0x1e: ssp->RAM1[ssp->r1[t&3]++] = d; return;
827 case 0x0f: ssp->RAM1[1] = d; return;
828 // mod=2 (10), "-"
829 case 0x10:
830 case 0x11:
831 case 0x12: ssp->RAM0[ssp->r0[t&3]--] = d; return;
832 case 0x13: ssp->RAM0[2] = d; return;
833 case 0x14:
834 case 0x15:
835 case 0x16: ssp->RAM1[ssp->r1[t&3]--] = d; return;
836 case 0x17: ssp->RAM1[2] = d; return;
837 // mod=3 (11)
838 case 0x1b: ssp->RAM0[3] = d; return;
839 case 0x1f: ssp->RAM1[3] = d; return;
840 }
841}
842
843static u32 ptr2_read(int op)
844{
845 int mv = 0, t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
846 switch (t)
847 {
848 // mod=0 (00)
849 case 0x00:
850 case 0x01:
851 case 0x02: mv = ssp->RAM0[ssp->r0[t&3]]++; break;
852 case 0x03: mv = ssp->RAM0[0]++; break;
853 case 0x04:
854 case 0x05:
855 case 0x06: mv = ssp->RAM1[ssp->r1[t&3]]++; break;
856 case 0x07: mv = ssp->RAM1[0]++; break;
857 // mod=1 (01)
858 case 0x0b: mv = ssp->RAM0[1]++; break;
859 case 0x0f: mv = ssp->RAM1[1]++; break;
860 // mod=2 (10)
861 case 0x13: mv = ssp->RAM0[2]++; break;
862 case 0x17: mv = ssp->RAM1[2]++; break;
863 // mod=3 (11)
864 case 0x1b: mv = ssp->RAM0[3]++; break;
865 case 0x1f: mv = ssp->RAM1[3]++; break;
30752975 866 default: elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: invalid mod in ((rX))? @ %04x", GET_PPC_OFFS());
5de27868 867 return 0;
868 }
869
870 return ((unsigned short *)svp->iram_rom)[mv];
871}
872
873
874// -----------------------------------------------------
875
017512f2 876void ssp1601_reset(ssp1601_t *l_ssp)
877{
878 ssp = l_ssp;
f8ef8ff7 879 ssp->emu_status = 0;
017512f2 880 ssp->gr[SSP_GR0].v = 0xffff0000;
f8ef8ff7 881 rPC = 0x400;
5de27868 882 rSTACK = 0; // ? using ascending stack
30752975 883 rST = 0;
f8ef8ff7 884}
885
886
3554b0a4 887#ifdef USE_DEBUGGER
5de27868 888static void debug_dump(void)
f8ef8ff7 889{
5de27868 890 printf("GR0: %04x X: %04x Y: %04x A: %08x\n", ssp->gr[SSP_GR0].h, rX, rY, ssp->gr[SSP_A].v);
891 printf("PC: %04x (%04x) P: %08x\n", GET_PC(), GET_PC() << 1, ssp->gr[SSP_P].v);
892 printf("PM0: %04x PM1: %04x PM2: %04x\n", rPM0, rPM1, rPM2);
893 printf("XST: %04x PM4: %04x PMC: %08x\n", rXST, rPM4, ssp->gr[SSP_PMC].v);
d26dc685 894 printf(" ST: %04x %c%c%c%c, GP0_0 %i, GP0_1 %i\n", rST, rST&SSP_FLAG_N?'N':'n', rST&SSP_FLAG_V?'V':'v',
895 rST&SSP_FLAG_Z?'Z':'z', rST&SSP_FLAG_L?'L':'l', (rST>>5)&1, (rST>>6)&1);
5de27868 896 printf("STACK: %i %04x %04x %04x %04x %04x %04x\n", rSTACK, ssp->stack[0], ssp->stack[1],
897 ssp->stack[2], ssp->stack[3], ssp->stack[4], ssp->stack[5]);
898 printf("r0-r2: %02x %02x %02x r4-r6: %02x %02x %02x\n", rIJ[0], rIJ[1], rIJ[2], rIJ[4], rIJ[5], rIJ[6]);
899 elprintf(EL_SVP, "cycles: %i, emu_status: %x", g_cycles, ssp->emu_status);
900}
f8ef8ff7 901
5de27868 902static void debug_dump_mem(void)
903{
904 int h, i;
905 printf("RAM0\n");
906 for (h = 0; h < 32; h++)
907 {
908 if (h == 16) printf("RAM1\n");
909 printf("%03x:", h*16);
910 for (i = 0; i < 16; i++)
911 printf(" %04x", ssp->RAM[h*16+i]);
912 printf("\n");
913 }
914}
915
30752975 916static void debug_dump2file(const char *fname, void *mem, int len)
917{
918 FILE *f = fopen(fname, "wb");
919 unsigned short *p = mem;
920 int i;
921 if (f) {
922 for (i = 0; i < len/2; i++) p[i] = (p[i]<<8) | (p[i]>>8);
923 fwrite(mem, 1, len, f);
924 fclose(f);
925 for (i = 0; i < len/2; i++) p[i] = (p[i]<<8) | (p[i]>>8);
926 printf("dumped to %s\n", fname);
927 }
928 else
929 printf("dump failed\n");
930}
931
5de27868 932static int bpts[10] = { 0, };
933
934static void debug(unsigned int pc, unsigned int op)
935{
936 static char buffo[64] = {0,};
937 char buff[64] = {0,};
938 int i;
939
940 if (running) {
941 for (i = 0; i < 10; i++)
942 if (pc != 0 && bpts[i] == pc) {
943 printf("breakpoint %i\n", i);
944 running = 0;
945 break;
946 }
947 }
948 if (running) return;
949
950 printf("%04x (%02x) @ %04x\n", op, op >> 9, pc<<1);
951
952 while (1)
953 {
954 printf("dbg> ");
955 fflush(stdout);
956 fgets(buff, sizeof(buff), stdin);
957 if (buff[0] == '\n') strcpy(buff, buffo);
958 else strcpy(buffo, buff);
959
960 switch (buff[0]) {
961 case 0: exit(0);
962 case 'c':
963 case 'r': running = 1; return;
964 case 's':
965 case 'n': return;
966 case 'x': debug_dump(); break;
967 case 'm': debug_dump_mem(); break;
968 case 'b': {
969 char *baddr = buff + 2;
970 i = 0;
971 if (buff[3] == ' ') { i = buff[2] - '0'; baddr = buff + 4; }
972 bpts[i] = strtol(baddr, NULL, 16) >> 1;
973 printf("breakpoint %i set @ %04x\n", i, bpts[i]<<1);
974 break;
975 }
30752975 976 case 'd':
977 sprintf(buff, "iramrom_%04x.bin", last_iram);
978 debug_dump2file(buff, svp->iram_rom, sizeof(svp->iram_rom));
979 debug_dump2file("dram.bin", svp->dram, sizeof(svp->dram));
5de27868 980 break;
5de27868 981 default: printf("unknown command\n"); break;
982 }
983 }
984}
3554b0a4 985#endif // USE_DEBUGGER
986
5de27868 987
988void ssp1601_run(int cycles)
989{
017512f2 990 SET_PC(rPC);
991 g_cycles = cycles;
f8ef8ff7 992
d26dc685 993 while (g_cycles > 0 && !(ssp->emu_status & SSP_WAIT_MASK))
f8ef8ff7 994 {
5de27868 995 int op;
996 u32 tmpv;
997
998 op = *PC++;
3554b0a4 999#ifdef USE_DEBUGGER
5de27868 1000 debug(GET_PC()-1, op);
3554b0a4 1001#endif
f8ef8ff7 1002 switch (op >> 9)
1003 {
1004 // ld d, s
5de27868 1005 case 0x00:
f8ef8ff7 1006 if (op == 0) break; // nop
017512f2 1007 if (op == ((SSP_A<<4)|SSP_P)) { // A <- P
1008 // not sure. MAME claims that only hi word is transfered.
1009 read_P(); // update P
4bfc6da4 1010 rA32 = ssp->gr[SSP_P].v;
f8ef8ff7 1011 }
5de27868 1012 else
f8ef8ff7 1013 {
5de27868 1014 tmpv = REG_READ(op & 0x0f);
1015 REG_WRITE((op & 0xf0) >> 4, tmpv);
1016 }
1017 break;
1018
1019 // ld d, (ri)
1020 case 0x01: tmpv = ptr1_read(op); REG_WRITE((op & 0xf0) >> 4, tmpv); break;
1021
1022 // ld (ri), s
1023 case 0x02: tmpv = REG_READ((op & 0xf0) >> 4); ptr1_write(op, tmpv); break;
1024
1025 // ldi d, imm
1026 case 0x04: tmpv = *PC++; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
1027
1028 // ld d, ((ri))
1029 case 0x05: tmpv = ptr2_read(op); REG_WRITE((op & 0xf0) >> 4, tmpv); break;
1030
1031 // ldi (ri), imm
1032 case 0x06: tmpv = *PC++; ptr1_write(op, tmpv); break;
1033
1034 // ld adr, a
1035 case 0x07: ssp->RAM[op & 0x1ff] = rA; break;
1036
1037 // ld d, ri
1038 case 0x09: tmpv = rIJ[(op&3)|((op>>6)&4)]; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
1039
1040 // ld ri, s
1041 case 0x0a: rIJ[(op&3)|((op>>6)&4)] = REG_READ((op & 0xf0) >> 4); break;
1042
1043 // ldi ri, simm
1044 case 0x0c:
1045 case 0x0d:
1046 case 0x0e:
1047 case 0x0f: rIJ[(op>>8)&7] = op; break;
1048
1049 // call cond, addr
1050 case 0x24: {
1051 int cond = 0;
1052 COND_CHECK
1053 if (cond) { int new_PC = *PC++; write_STACK(GET_PC()); write_PC(new_PC); }
1054 else PC++;
1055 break;
1056 }
1057
1058 // ld d, (a)
1059 case 0x25: tmpv = ((unsigned short *)svp->iram_rom)[rA]; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
1060
1061 // bra cond, addr
1062 case 0x26: {
1063 int cond = 0;
1064 COND_CHECK
1065 if (cond) { int new_PC = *PC++; write_PC(new_PC); }
1066 else PC++;
1067 break;
1068 }
1069
1070 // mod cond, op
1071 case 0x48: {
1072 int cond = 0;
1073 COND_CHECK
1074 if (cond) {
1075 switch (op & 7) {
d26dc685 1076 case 2: rA32 = (signed int)rA32 >> 1; break; // shr (arithmetic)
5de27868 1077 case 3: rA32 <<= 1; break; // shl
d26dc685 1078 case 6: rA32 = -(signed int)rA32; break; // neg
1079 case 7: if ((int)rA32 < 0) rA32 = -(signed int)rA32; break; // abs
689fb2c0 1080 default: elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: unhandled mod %i @ %04x",
1081 op&7, GET_PPC_OFFS());
5de27868 1082 }
30752975 1083 UPD_ACC_ZN // ?
f8ef8ff7 1084 }
1085 break;
5de27868 1086 }
1087
689fb2c0 1088 // mpys?
30752975 1089 case 0x1b:
3554b0a4 1090 if (!(op&0x100)) elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: no b bit @ %04x", GET_PPC_OFFS());
30752975 1091 read_P(); // update P
689fb2c0 1092 rA32 -= ssp->gr[SSP_P].v; // maybe only upper word?
1093 UPD_ACC_ZN // there checking flags after this
30752975 1094 rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
1095 rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
3554b0a4 1096 break;
1097
5de27868 1098 // mpya (rj), (ri), b
1099 case 0x4b:
3554b0a4 1100 if (!(op&0x100)) elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: no b bit @ %04x", GET_PPC_OFFS());
5de27868 1101 read_P(); // update P
3554b0a4 1102 rA32 += ssp->gr[SSP_P].v; // confirmed to be 32bit
d26dc685 1103 UPD_ACC_ZN // ?
5de27868 1104 rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
1105 rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
1106 break;
1107
1108 // mld (rj), (ri), b
1109 case 0x5b:
3554b0a4 1110 if (!(op&0x100)) elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: no b bit @ %04x", GET_PPC_OFFS());
1111 rA32 = 0;
4bfc6da4 1112 rST &= 0x0fff; // ?
5de27868 1113 rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
1114 rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
1115 break;
1116
1117 // OP a, s
67256d4b 1118 case 0x10: OP_CHECK32(OP_SUBA32); tmpv = REG_READ(op & 0x0f); OP_SUBA(tmpv); break;
1119 case 0x30: OP_CHECK32(OP_CMPA32); tmpv = REG_READ(op & 0x0f); OP_CMPA(tmpv); break;
1120 case 0x40: OP_CHECK32(OP_ADDA32); tmpv = REG_READ(op & 0x0f); OP_ADDA(tmpv); break;
1121 case 0x50: OP_CHECK32(OP_ANDA32); tmpv = REG_READ(op & 0x0f); OP_ANDA(tmpv); break;
1122 case 0x60: OP_CHECK32(OP_ORA32 ); tmpv = REG_READ(op & 0x0f); OP_ORA (tmpv); break;
1123 case 0x70: OP_CHECK32(OP_EORA32); tmpv = REG_READ(op & 0x0f); OP_EORA(tmpv); break;
5de27868 1124
1125 // OP a, (ri)
1126 case 0x11: tmpv = ptr1_read(op); OP_SUBA(tmpv); break;
1127 case 0x31: tmpv = ptr1_read(op); OP_CMPA(tmpv); break;
1128 case 0x41: tmpv = ptr1_read(op); OP_ADDA(tmpv); break;
1129 case 0x51: tmpv = ptr1_read(op); OP_ANDA(tmpv); break;
1130 case 0x61: tmpv = ptr1_read(op); OP_ORA (tmpv); break;
1131 case 0x71: tmpv = ptr1_read(op); OP_EORA(tmpv); break;
1132
1133 // OP a, adr
1134 case 0x03: tmpv = ssp->RAM[op & 0x1ff]; OP_LDA (tmpv); break;
1135 case 0x13: tmpv = ssp->RAM[op & 0x1ff]; OP_SUBA(tmpv); break;
1136 case 0x33: tmpv = ssp->RAM[op & 0x1ff]; OP_CMPA(tmpv); break;
1137 case 0x43: tmpv = ssp->RAM[op & 0x1ff]; OP_ADDA(tmpv); break;
1138 case 0x53: tmpv = ssp->RAM[op & 0x1ff]; OP_ANDA(tmpv); break;
1139 case 0x63: tmpv = ssp->RAM[op & 0x1ff]; OP_ORA (tmpv); break;
1140 case 0x73: tmpv = ssp->RAM[op & 0x1ff]; OP_EORA(tmpv); break;
1141
1142 // OP a, imm
1143 case 0x14: tmpv = *PC++; OP_SUBA(tmpv); break;
1144 case 0x34: tmpv = *PC++; OP_CMPA(tmpv); break;
1145 case 0x44: tmpv = *PC++; OP_ADDA(tmpv); break;
1146 case 0x54: tmpv = *PC++; OP_ANDA(tmpv); break;
1147 case 0x64: tmpv = *PC++; OP_ORA (tmpv); break;
1148 case 0x74: tmpv = *PC++; OP_EORA(tmpv); break;
1149
1150 // OP a, ((ri))
1151 case 0x15: tmpv = ptr2_read(op); OP_SUBA(tmpv); break;
1152 case 0x35: tmpv = ptr2_read(op); OP_CMPA(tmpv); break;
1153 case 0x45: tmpv = ptr2_read(op); OP_ADDA(tmpv); break;
1154 case 0x55: tmpv = ptr2_read(op); OP_ANDA(tmpv); break;
1155 case 0x65: tmpv = ptr2_read(op); OP_ORA (tmpv); break;
1156 case 0x75: tmpv = ptr2_read(op); OP_EORA(tmpv); break;
1157
1158 // OP a, ri
1159 case 0x19: tmpv = rIJ[IJind]; OP_SUBA(tmpv); break;
1160 case 0x39: tmpv = rIJ[IJind]; OP_CMPA(tmpv); break;
1161 case 0x49: tmpv = rIJ[IJind]; OP_ADDA(tmpv); break;
1162 case 0x59: tmpv = rIJ[IJind]; OP_ANDA(tmpv); break;
1163 case 0x69: tmpv = rIJ[IJind]; OP_ORA (tmpv); break;
1164 case 0x79: tmpv = rIJ[IJind]; OP_EORA(tmpv); break;
1165
1166 // OP simm
689fb2c0 1167 case 0x1c: OP_SUBA(op & 0xff); if (op&0x100) elprintf(EL_SVP|EL_ANOMALY, "FIXME: simm with upper bit set"); break;
1168 case 0x3c: OP_CMPA(op & 0xff); if (op&0x100) elprintf(EL_SVP|EL_ANOMALY, "FIXME: simm with upper bit set"); break;
1169 case 0x4c: OP_ADDA(op & 0xff); if (op&0x100) elprintf(EL_SVP|EL_ANOMALY, "FIXME: simm with upper bit set"); break;
5de27868 1170 // MAME code only does LSB of top word, but this looks wrong to me.
689fb2c0 1171 case 0x5c: OP_ANDA(op & 0xff); if (op&0x100) elprintf(EL_SVP|EL_ANOMALY, "FIXME: simm with upper bit set"); break;
1172 case 0x6c: OP_ORA (op & 0xff); if (op&0x100) elprintf(EL_SVP|EL_ANOMALY, "FIXME: simm with upper bit set"); break;
1173 case 0x7c: OP_EORA(op & 0xff); if (op&0x100) elprintf(EL_SVP|EL_ANOMALY, "FIXME: simm with upper bit set"); break;
f8ef8ff7 1174
1175 default:
3554b0a4 1176 elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME unhandled op %04x @ %04x", op, GET_PPC_OFFS());
017512f2 1177 break;
f8ef8ff7 1178 }
017512f2 1179 g_cycles--;
f8ef8ff7 1180 }
1181
017512f2 1182 read_P(); // update P
f8ef8ff7 1183 rPC = GET_PC();
017512f2 1184
1185 if (ssp->gr[SSP_GR0].v != 0xffff0000)
3554b0a4 1186 elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: REG 0 corruption! %08x", ssp->gr[SSP_GR0].v);
f8ef8ff7 1187}
1188
fast MegaDrive/MegaCD/32X emulator