notaz.gp2x.de / picodrive.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
more SVP work
[picodrive.git] / Pico / carthw / svp / ssp16.c
CommitLineData
f8ef8ff7 1// basic, incomplete SSP160x (SSP1601?) interpreter
2
3/*
4 * Register info
5 * most names taken from MAME code
6 *
7 * 0. "-"
8 * size: 16
9 * desc: Constant register with all bits set (0xffff).
10 *
11 * 1. "X"
12 * size: 16
13 * desc: Generic register. When set, updates P (P = X * Y * 2) ??
14 *
15 * 2. "Y"
16 * size: 16
17 * desc: Generic register. When set, updates P (P = X * Y * 2) ??
18 *
19 * 3. "A"
20 * size: 32
21 * desc: Accumulator.
22 *
23 * 4. "ST"
24 * size: 16
25 * desc: Status register. From MAME: bits 0-9 are CONTROL, other FLAG
26 * fedc ba98 7654 3210
5de27868 27 * 210 - RPL (?) "Loop size". If non-zero, makes (rX+) and (rX-) respectively
28 * modulo-increment and modulo-decrement. The value shows which
29 * power of 2 to use, i.e. 4 means modulo by 16.
30 * (e: fir16_32.sc, IIR_4B.SC, DECIM.SC)
f8ef8ff7 31 * 43 - RB (?)
5de27868 32 * 5 - GP0_0 (ST5?) Changed before acessing PM0 (affects banking?).
33 * 6 - GP0_1 (ST6?) Cleared before acessing PM0 (affects banking?). Set after.
34 * datasheet says these (5,6) bits correspond to hardware pins.
35 * 7 - IE (?) Not directly used by SVP code (never set, but preserved)?
36 * 8 - OP (?) Not used by SVP code (only cleared)? (MAME: saturated value
37 * (probably means clamping? i.e. 0x7ffc + 9 -> 0x7fff))
f8ef8ff7 38 * 9 - MACS (?) Not used by SVP code (only cleared)? (e: "mac shift")
39 * a - GPI_0 Interrupt 0 enable/status?
40 * b - GPI_1 Interrupt 1 enable/status?
41 * c - L L flag. Carry?
42 * d - Z Zero flag.
43 * e - OV Overflow flag.
44 * f - N Negative flag.
45 * seen directly changing code sequences:
46 * ldi ST, 0 ld A, ST ld A, ST ld A, ST ldi st, 20h
47 * ldi ST, 60h ori A, 60h and A, E8h and A, E8h
48 * ld ST, A ld ST, A ori 3
49 * ld ST, A
50 *
51 * 5. "STACK"
52 * size: 16
53 * desc: hw stack of 6 levels (according to datasheet)
54 *
55 * 6. "PC"
56 * size: 16
57 * desc: Program counter.
58 *
59 * 7. "P"
60 * size: 32
61 * desc: multiply result register. Updated after mp* instructions,
62 * or writes to X or Y (P = X * Y * 2) ??
63 * probably affected by MACS bit in ST.
64 *
65 * 8. "PM0" (PM from PMAR name from Tasco's docs)
66 * size: 16?
67 * desc: Programmable Memory access register.
68 * On reset, or when one (both?) GP0 bits are clear,
69 * acts as some additional status reg?
70 *
71 * 9. "PM1"
72 * size: 16?
73 * desc: Programmable Memory access register.
74 * This reg. is only used as PMAR.
75 *
76 * 10. "PM2"
77 * size: 16?
78 * desc: Programmable Memory access register.
79 * This reg. is only used as PMAR.
80 *
81 * 11. "XST"
82 * size: 16?
83 * desc: eXternal STate. Mapped to a15000 at 68k side.
84 * Can be programmed as PMAR? (only seen in test mode code)
85 *
86 * 12. "PM4"
87 * size: 16?
88 * desc: Programmable Memory access register.
89 * This reg. is only used as PMAR. The most used PMAR by VR.
90 *
91 * 13. (unused by VR)
92 *
93 * 14. "PMC" (PMC from PMAC name from Tasco's docs)
94 * size: 32?
95 * desc: Programmable Memory access Control. Set using 2 16bit writes,
96 * first address, then mode word. After setting PMAC, PMAR sould
97 * be accessed to program it.
98 *
99 * 15. "AL"
100 * size: 16
101 * desc: Accumulator Low. 16 least significant bits of accumulator (not 100% sure)
102 * (normally reading acc (ld X, A) you get 16 most significant bits).
103 *
104 *
105 * There are 8 8-bit pointer registers rX. r0-r3 (ri) point to RAM0, r4-r7 (rj) point to RAM1.
5de27868 106 * They can be accessed directly, or 2 indirection levels can be used [ (rX), ((rX)) ],
107 * which work similar to * and ** operators in C, only they use different memory banks and
108 * ((rX)) also does post-increment. First indirection level (rX) accesses RAMx, second accesses
109 * program memory at address read from (rX), and increments value in (rX).
f8ef8ff7 110 *
111 * r0,r1,r2,r4,r5,r6 can be modified [ex: ldi r0, 5].
112 * 3 modifiers can be applied (optional):
5de27868 113 * + : post-increment [ex: ld a, (r0+) ]. Can be made modulo-increment by setting RPL bits in ST.
114 * - : post-decrement. Can be made modulo-decrement by setting RPL bits in ST (not sure).
115 * +!: post-increment, unaffected by RPL (probably).
116 * These are only used on 1st indirection level, so things like [ld a, ((r0+))] and [ld X, r6-]
117 * ar probably invalid.
f8ef8ff7 118 *
119 * r3 and r7 are special and can not be changed (at least Samsung samples and SVP code never do).
120 * They are fixed to the start of their RAM banks. (They are probably changeable for ssp1605+,
121 * Samsung's old DSP page claims that).
122 * 1 of these 4 modifiers must be used (short form direct addressing?):
123 * |00: RAMx[0] [ex: (r3|00), 0] (based on sample code)
124 * |01: RAMx[1]
125 * |10: RAMx[2] ? maybe 10h? accortding to Div_c_dp.sc, 2
126 * |11: RAMx[3]
127 *
128 *
129 * Instruction notes
130 *
131 * mld (rj), (ri) [, b]
132 * operation: A = 0; P = (rj) * (ri)
133 * notes: based on IIR_4B.SC sample. flags? what is b???
134 * TODO: figure out if (rj) and (ri) get loaded in X and Y
135 *
136 * mpya (rj), (ri) [, b]
137 * name: multiply and add?
138 * operation: A += P; P = (rj) * (ri)
139 *
140 * mpys (rj), (ri), b
141 * name: multiply and subtract?
142 * notes: not used by VR code.
017512f2 143 *
144 *
145 * Assumptions in this code
146 * P is not directly writeable
5de27868 147 * flags correspond to full 32bit accumulator
148 * only Z and N status flags are emulated (others unused by SVP)
149 * modifiers for 'OP a, ri' are ignored (invalid?/not used by SVP)
150 * modifiers '+' and '+!' act the same (this is most likely wrong)
151 * 'ld d, (a)' loads from program ROM
f8ef8ff7 152 */
153
154#include "../../PicoInt.h"
155
017512f2 156#define u32 unsigned int
157
158// 0
159#define rX ssp->gr[SSP_X].h
160#define rY ssp->gr[SSP_Y].h
161#define rA ssp->gr[SSP_A].h
162#define rST ssp->gr[SSP_ST].h // 4
163#define rSTACK ssp->gr[SSP_STACK].h
164#define rPC ssp->gr[SSP_PC].h
165#define rP ssp->gr[SSP_P]
166#define rPM0 ssp->gr[SSP_PM0].h // 8
167#define rPM1 ssp->gr[SSP_PM1].h
168#define rPM2 ssp->gr[SSP_PM2].h
169#define rXST ssp->gr[SSP_XST].h
170#define rPM4 ssp->gr[SSP_PM4].h // 12
171// 13
172#define rPMC ssp->gr[SSP_PMC] // will keep addr in .h, mode in .l
f8ef8ff7 173#define rAL ssp->gr[SSP_A].l
174
5de27868 175#define rA32 ssp->gr[SSP_A].v
176#define rIJ ssp->r
177
178#define IJind (((op>>6)&4)|(op&3))
179
180#define GET_PC() (PC - (unsigned short *)svp->iram_rom)
181#define GET_PPC_OFFS() ((unsigned int)PC - (unsigned int)svp->iram_rom - 2)
182#define SET_PC(d) PC = (unsigned short *)svp->iram_rom + d
017512f2 183
184#define REG_READ(r) (((r) <= 4) ? ssp->gr[r].h : read_handlers[r]())
5de27868 185// if r is 'A', should we set flags?
017512f2 186#define REG_WRITE(r,d) { \
187 int r1 = r; \
5de27868 188 if (r1 >= 4) write_handlers[r1](d); \
017512f2 189 else if (r1 > 0) ssp->gr[r1].h = d; \
190}
191
5de27868 192// flags
193#define FLAG_L (1<<0xc)
194#define FLAG_Z (1<<0xd)
195#define FLAG_V (1<<0xe)
196#define FLAG_N (1<<0xf)
197
198// update ZN according to 32bit ACC.
199#define UPD_ACC_ZN \
200 rST &= ~(FLAG_Z|FLAG_N); \
201 if (!rA32) rST |= FLAG_Z; \
202 else rST |= (rA32>>16)&FLAG_N;
203
204// it seems SVP code never checks for L and OV, so we leave them out.
205// rST |= (t>>4)&FLAG_L;
206#define UPD_t_LZVN \
207 rST &= ~(FLAG_L|FLAG_Z|FLAG_V|FLAG_N); \
208 if (!t) rST |= FLAG_Z; \
209 else rST |= t&FLAG_N; \
210
211// standard cond processing.
212// again, only Z and N is checked, as SVP doesn't seem to use any other conds.
213#define COND_CHECK \
214 switch (op&0xf0) { \
215 case 0x00: cond = 1; break; /* always true */ \
216 case 0x50: cond = !((rST ^ (op<<5)) & FLAG_Z); break; /* Z matches f(?) bit */ \
217 case 0x70: cond = !((rST ^ (op<<7)) & FLAG_N); break; /* N matches f(?) bit */ \
218 default:elprintf(EL_SVP, "unimplemented cond @ %04x", GET_PPC_OFFS()); break; \
219 }
220
221// ops with accumulator.
222// how is low word really affected by these?
223// not sure if 'ld A' affects flags (assume it does..)
224#define OP_LDA(x) \
225 ssp->gr[SSP_A].h = x; \
226 UPD_ACC_ZN
227
228#define OP_SUBA(x) { \
229 u32 t = (ssp->gr[SSP_A].v >> 16) - (x); \
230 UPD_t_LZVN \
231 ssp->gr[SSP_A].h = t; \
232}
233
234#define OP_CMPA(x) { \
235 u32 t = (ssp->gr[SSP_A].v >> 16) - (x); \
236 UPD_t_LZVN \
237}
238
239#define OP_ADDA(x) { \
240 u32 t = (ssp->gr[SSP_A].v >> 16) + (x); \
241 UPD_t_LZVN \
242 ssp->gr[SSP_A].h = t; \
243}
244
245#define OP_ANDA(x) \
246 ssp->gr[SSP_A].v &= (x) << 16; \
247 UPD_ACC_ZN
248
249#define OP_ORA(x) \
250 ssp->gr[SSP_A].v |= (x) << 16; \
251 UPD_ACC_ZN
252
253#define OP_EORA(x) \
254 ssp->gr[SSP_A].v ^= (x) << 16; \
255 UPD_ACC_ZN
256
257
017512f2 258static ssp1601_t *ssp = NULL;
259static unsigned short *PC;
260static int g_cycles;
5de27868 261// debug
262static int running = 0;
017512f2 263
264// -----------------------------------------------------
265// register i/o handlers
266
267// 0-4, 13
268static u32 read_unknown(void)
269{
5de27868 270 elprintf(EL_ANOMALY|EL_SVP, "ssp16: unknown read @ %04x", GET_PPC_OFFS());
017512f2 271 return 0;
272}
273
274static void write_unknown(u32 d)
275{
5de27868 276 elprintf(EL_ANOMALY|EL_SVP, "ssp16: unknown write @ %04x", GET_PPC_OFFS());
277}
278
279// 4
280static void write_ST(u32 d)
281{
282 if ((rST ^ d) & 7) {
283 elprintf(EL_SVP, "ssp16: RPL %i -> %i @ %04x", rST&7, d&7, GET_PPC_OFFS());
284 running = 0;
285 }
286 rST = d;
017512f2 287}
288
289// 5
290static u32 read_STACK(void)
291{
5de27868 292 //elprintf(EL_SVP, "pop %i @ %04x", rSTACK, GET_PPC_OFFS());
293 --rSTACK;
294 if ((short)rSTACK < 0) {
295 rSTACK = 5;
296 elprintf(EL_ANOMALY|EL_SVP, "ssp16: stack underflow! (%i) @ %04x", rSTACK, GET_PPC_OFFS());
297 }
298 return ssp->stack[rSTACK];
017512f2 299}
300
301static void write_STACK(u32 d)
302{
5de27868 303 if (rSTACK >= 6) {
304 //running = 0;
305 elprintf(EL_ANOMALY|EL_SVP, "ssp16: stack overflow! (%i) @ %04x", rSTACK, GET_PPC_OFFS());
306 rSTACK = 0;
307 }
308 ssp->stack[rSTACK++] = d;
017512f2 309}
310
311// 6
312static u32 read_PC(void)
313{
314 return GET_PC();
315}
316
317static void write_PC(u32 d)
318{
319 SET_PC(d);
320 g_cycles--;
321}
322
323// 7
324static u32 read_P(void)
325{
326 rP.v = (u32)rX * rY * 2;
327 return rP.h;
328}
329
5de27868 330// -----------------------------------------------------
331
332static void iram_write(int addr, u32 d, int reg, int inc)
333{
334 if ((addr&0xfc00) != 0x8000)
335 elprintf(EL_SVP|EL_ANOMALY, "ssp invalid IRAM addr: %04x", addr<<1);
336 elprintf(EL_SVP, "ssp IRAM w [%06x] %04x (inc %i)", (addr<<1)&0x7ff, d, inc);
337 ((unsigned short *)svp->iram_rom)[addr&0x3ff] = d;
338 ssp->pmac_write[reg] += inc<<16;
339}
340
017512f2 341static u32 pm_io(int reg, int write, u32 d)
342{
343 if (ssp->emu_status & SSP_PMC_SET) {
5de27868 344 elprintf(EL_SVP, "PM%i (%c) set to %08x @ %04x", reg, write ? 'w' : 'r', rPMC.v, GET_PPC_OFFS());
017512f2 345 ssp->pmac_read[write ? reg + 6 : reg] = rPMC.v;
346 ssp->emu_status &= ~SSP_PMC_SET;
347 return 0;
348 }
349
5de27868 350 // just in case
351 ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
352
353// if (ssp->pmac_read[reg] != 0)
354 if (reg == 4 || (rST & 0x60))
355 {
356 if (write)
357 {
358 int mode = ssp->pmac_write[reg]&0xffff;
359 int addr = ssp->pmac_write[reg]>>16;
360 switch (mode) {
361 case 0x0018: elprintf(EL_SVP, "ssp DRAM w [%06x] %04x", addr<<1, d);
362 ((unsigned short *)svp->dram)[addr] = d;
363 break;
364 case 0x0818: elprintf(EL_SVP, "ssp DRAM w [%06x] %04x (inc 1)", addr<<1, d);
365 ((unsigned short *)svp->dram)[addr] = d;
366 ssp->pmac_write[reg] += 1<<16;
367 break;
368 case 0x081c: iram_write(addr, d, reg, 1); break; // checked: used by code @ 0902
369 case 0x101c: iram_write(addr, d, reg, 2); break; // checked: used by code @ 3b7c
370 default: elprintf(EL_SVP|EL_ANOMALY, "ssp PM%i unhandled write mode %04x, [%06x] %04x @ %04x",
371 reg, mode, addr<<1, d, GET_PPC_OFFS()); break;
372 }
373 }
374 else
375 {
376 int mode = ssp->pmac_read[reg]&0xffff;
377 int addr = ssp->pmac_read[reg]>>16;
378 switch (mode) {
379 case 0x0809: elprintf(EL_SVP, "ssp ROM r [%06x] %04x", (addr|((mode&0xf)<<16))<<1,
380 ((unsigned short *)Pico.rom)[addr|((mode&0xf)<<16)]);
381 // possibly correct, the first word read is some sort of counter, sane values in ROM
382 ssp->pmac_read[reg] += 1<<16;
383 return ((unsigned short *)Pico.rom)[addr|((mode&0xf)<<16)];
384 case 0x0018: elprintf(EL_SVP, "ssp DRAM r [%06x] %04x", addr<<1, ((unsigned short *)svp->dram)[addr]);
385 return ((unsigned short *)svp->dram)[addr]; // checked
386 case 0x0818: elprintf(EL_SVP, "ssp DRAM r [%06x] %04x (inc 1)", addr<<1, ((unsigned short *)svp->dram)[addr]);
387 ssp->pmac_read[reg] += 1<<16;
388 return ((unsigned short *)svp->dram)[addr];
389 case 0x3018: elprintf(EL_SVP, "ssp DRAM r [%06x] %04x (inc 32)", addr<<1, ((unsigned short *)svp->dram)[addr]);
390 ssp->pmac_read[reg] += 32<<16;
391 return ((unsigned short *)svp->dram)[addr];
392 default: elprintf(EL_SVP|EL_ANOMALY, "ssp PM%i unhandled read mode %04x, [%06x] @ %04x",
393 reg, mode, addr<<1, GET_PPC_OFFS()); break;
394 }
395 }
017512f2 396 return 0;
397 }
398
399 return (u32)-1;
400}
401
402// 8
403static u32 read_PM0(void)
404{
405 u32 d = pm_io(0, 0, 0);
406 if (d != (u32)-1) return d;
5de27868 407 if (GET_PPC_OFFS() != 0x800 || rPM0 != 0) // debug
408 elprintf(EL_SVP, "PM0 raw r %04x @ %04x", rPM0, GET_PPC_OFFS());
017512f2 409 return rPM0;
410}
411
412static void write_PM0(u32 d)
413{
414 u32 r = pm_io(0, 1, d);
415 if (r != (u32)-1) return;
5de27868 416 elprintf(EL_SVP, "PM0 raw w %04x @ %04x", d, GET_PPC_OFFS());
017512f2 417 rPM0 = d;
418}
419
420// 9
421static u32 read_PM1(void)
422{
423 u32 d = pm_io(1, 0, 0);
424 if (d != (u32)-1) return d;
425 // can be removed?
5de27868 426 elprintf(EL_SVP, "PM1 raw r %04x @ %04x", rPM1, GET_PPC_OFFS());
427 return rPM1;
017512f2 428}
429
430static void write_PM1(u32 d)
431{
432 u32 r = pm_io(1, 1, d);
433 if (r != (u32)-1) return;
434 // can be removed?
5de27868 435 elprintf(EL_SVP, "PM1 raw w %04x @ %04x", d, GET_PPC_OFFS());
436 rPM1 = d;
017512f2 437}
438
439// 10
440static u32 read_PM2(void)
441{
442 u32 d = pm_io(2, 0, 0);
443 if (d != (u32)-1) return d;
444 // can be removed?
5de27868 445 elprintf(EL_SVP, "PM2 raw r %04x @ %04x", rPM2, GET_PPC_OFFS());
446 return rPM2;
017512f2 447}
448
449static void write_PM2(u32 d)
450{
451 u32 r = pm_io(2, 1, d);
452 if (r != (u32)-1) return;
453 // can be removed?
5de27868 454 elprintf(EL_SVP, "PM2 raw w %04x @ %04x", d, GET_PPC_OFFS());
455 rPM2 = d;
017512f2 456}
457
458// 11
459static u32 read_XST(void)
460{
461 // can be removed?
462 u32 d = pm_io(3, 0, 0);
463 if (d != (u32)-1) return d;
464
5de27868 465 elprintf(EL_SVP, "XST raw r %04x @ %04x", rXST, GET_PPC_OFFS());
466 return rXST;
017512f2 467}
f8ef8ff7 468
017512f2 469static void write_XST(u32 d)
f8ef8ff7 470{
017512f2 471 // can be removed?
472 u32 r = pm_io(3, 1, d);
473 if (r != (u32)-1) return;
474
5de27868 475 elprintf(EL_SVP, "XST raw w %04x @ %04x", d, GET_PPC_OFFS());
476 rXST = d;
017512f2 477}
478
479// 12
480static u32 read_PM4(void)
481{
482 u32 d = pm_io(4, 0, 0);
483 if (d != (u32)-1) return d;
484 // can be removed?
5de27868 485 elprintf(EL_SVP, "PM4 raw r %04x @ %04x", rPM4, GET_PPC_OFFS());
486 return rPM4;
017512f2 487}
488
489static void write_PM4(u32 d)
490{
491 u32 r = pm_io(4, 1, d);
492 if (r != (u32)-1) return;
493 // can be removed?
5de27868 494 elprintf(EL_SVP, "PM4 raw w %04x @ %04x", d, GET_PPC_OFFS());
495 rPM4 = d;
017512f2 496}
497
498// 14
499static u32 read_PMC(void)
500{
501 if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
502 if (ssp->emu_status & SSP_PMC_SET)
5de27868 503 elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS());
017512f2 504 ssp->emu_status |= SSP_PMC_SET;
5de27868 505 ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
017512f2 506 return rPMC.l;
507 } else {
508 ssp->emu_status |= SSP_PMC_HAVE_ADDR;
509 return rPMC.h;
510 }
511}
512
513static void write_PMC(u32 d)
514{
515 if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
516 if (ssp->emu_status & SSP_PMC_SET)
5de27868 517 elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS());
017512f2 518 ssp->emu_status |= SSP_PMC_SET;
5de27868 519 ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
017512f2 520 rPMC.l = d;
521 } else {
522 ssp->emu_status |= SSP_PMC_HAVE_ADDR;
523 rPMC.h = d;
524 }
525}
526
527// 15
528static u32 read_AL(void)
529{
530 // TODO: figure out what's up with those blind reads..
531 return rAL;
532}
533
534static void write_AL(u32 d)
535{
536 rAL = d;
537}
538
539
540typedef u32 (*read_func_t)(void);
541typedef void (*write_func_t)(u32 d);
542
543static read_func_t read_handlers[16] =
544{
545 read_unknown, read_unknown, read_unknown, read_unknown, // -, X, Y, A
546 read_unknown, // 4 ST
547 read_STACK,
548 read_PC,
549 read_P,
550 read_PM0, // 8
551 read_PM1,
552 read_PM2,
553 read_XST,
554 read_PM4, // 12
555 read_unknown, // 13 gr13
556 read_PMC,
557 read_AL
558};
559
560static write_func_t write_handlers[16] =
561{
562 write_unknown, write_unknown, write_unknown, write_unknown, // -, X, Y, A
5de27868 563// write_unknown, // 4 ST
564 write_ST, // 4 ST (debug hook)
017512f2 565 write_STACK,
566 write_PC,
567 write_unknown, // 7 P
568 write_PM0, // 8
569 write_PM1,
570 write_PM2,
571 write_XST,
572 write_PM4, // 12
573 write_unknown, // 13 gr13
574 write_PMC,
575 write_AL
576};
577
5de27868 578// -----------------------------------------------------
579// pointer register handlers
580
581//
582#define ptr1_read(op) ptr1_read_(op&3,(op>>6)&4,(op<<1)&0x18)
583
584static u32 ptr1_read_(int ri, int isj2, int modi3)
585{
586 //int t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
587 int t = ri | isj2 | modi3;
588 switch (t)
589 {
590 // mod=0 (00)
591 case 0x00:
592 case 0x01:
593 case 0x02: return ssp->RAM0[ssp->r0[t&3]];
594 case 0x03: return ssp->RAM0[0];
595 case 0x04:
596 case 0x05:
597 case 0x06: return ssp->RAM1[ssp->r1[t&3]];
598 case 0x07: return ssp->RAM1[0];
599 // mod=1 (01), "+!"
600 // mod=3, "+"
601 case 0x08:
602 case 0x18:
603 case 0x09:
604 case 0x19:
605 case 0x0a:
606 case 0x1a: return ssp->RAM0[ssp->r0[t&3]++];
607 case 0x0b: return ssp->RAM0[1];
608 case 0x0c:
609 case 0x1c:
610 case 0x0d:
611 case 0x1d:
612 case 0x0e:
613 case 0x1e: return ssp->RAM1[ssp->r1[t&3]++];
614 case 0x0f: return ssp->RAM1[1];
615 // mod=2 (10), "-"
616 case 0x10:
617 case 0x11:
618 case 0x12: return ssp->RAM0[ssp->r0[t&3]--];
619 case 0x13: return ssp->RAM0[2];
620 case 0x14:
621 case 0x15:
622 case 0x16: return ssp->RAM1[ssp->r1[t&3]--];
623 case 0x17: return ssp->RAM1[2];
624 // mod=3 (11)
625 case 0x1b: return ssp->RAM0[3];
626 case 0x1f: return ssp->RAM1[3];
627 }
628
629 return 0;
630}
631
632static void ptr1_write(int op, u32 d)
633{
634 int t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
635 switch (t)
636 {
637 // mod=0 (00)
638 case 0x00:
639 case 0x01:
640 case 0x02: ssp->RAM0[ssp->r0[t&3]] = d; return;
641 case 0x03: ssp->RAM0[0] = d; return;
642 case 0x04:
643 case 0x05:
644 case 0x06: ssp->RAM1[ssp->r1[t&3]] = d; return;
645 case 0x07: ssp->RAM1[0] = d; return;
646 // mod=1 (01), "+!"
647 // mod=3, "+"
648 case 0x08:
649 case 0x18:
650 case 0x09:
651 case 0x19:
652 case 0x0a:
653 case 0x1a: ssp->RAM0[ssp->r0[t&3]++] = d; return;
654 case 0x0b: ssp->RAM0[1] = d; return;
655 case 0x0c:
656 case 0x1c:
657 case 0x0d:
658 case 0x1d:
659 case 0x0e:
660 case 0x1e: ssp->RAM1[ssp->r1[t&3]++] = d; return;
661 case 0x0f: ssp->RAM1[1] = d; return;
662 // mod=2 (10), "-"
663 case 0x10:
664 case 0x11:
665 case 0x12: ssp->RAM0[ssp->r0[t&3]--] = d; return;
666 case 0x13: ssp->RAM0[2] = d; return;
667 case 0x14:
668 case 0x15:
669 case 0x16: ssp->RAM1[ssp->r1[t&3]--] = d; return;
670 case 0x17: ssp->RAM1[2] = d; return;
671 // mod=3 (11)
672 case 0x1b: ssp->RAM0[3] = d; return;
673 case 0x1f: ssp->RAM1[3] = d; return;
674 }
675}
676
677static u32 ptr2_read(int op)
678{
679 int mv = 0, t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
680 switch (t)
681 {
682 // mod=0 (00)
683 case 0x00:
684 case 0x01:
685 case 0x02: mv = ssp->RAM0[ssp->r0[t&3]]++; break;
686 case 0x03: mv = ssp->RAM0[0]++; break;
687 case 0x04:
688 case 0x05:
689 case 0x06: mv = ssp->RAM1[ssp->r1[t&3]]++; break;
690 case 0x07: mv = ssp->RAM1[0]++; break;
691 // mod=1 (01)
692 case 0x0b: mv = ssp->RAM0[1]++; break;
693 case 0x0f: mv = ssp->RAM1[1]++; break;
694 // mod=2 (10)
695 case 0x13: mv = ssp->RAM0[2]++; break;
696 case 0x17: mv = ssp->RAM1[2]++; break;
697 // mod=3 (11)
698 case 0x1b: mv = ssp->RAM0[3]++; break;
699 case 0x1f: mv = ssp->RAM1[3]++; break;
700 default: elprintf(EL_SVP|EL_ANOMALY, "invalid mod in ((rX))? @ %04x", GET_PPC_OFFS());
701 return 0;
702 }
703
704 return ((unsigned short *)svp->iram_rom)[mv];
705}
706
707
708// -----------------------------------------------------
709
017512f2 710void ssp1601_reset(ssp1601_t *l_ssp)
711{
712 ssp = l_ssp;
f8ef8ff7 713 ssp->emu_status = 0;
017512f2 714 ssp->gr[SSP_GR0].v = 0xffff0000;
f8ef8ff7 715 rPC = 0x400;
5de27868 716 rSTACK = 0; // ? using ascending stack
f8ef8ff7 717}
718
719
5de27868 720static void debug_dump(void)
f8ef8ff7 721{
5de27868 722 printf("GR0: %04x X: %04x Y: %04x A: %08x\n", ssp->gr[SSP_GR0].h, rX, rY, ssp->gr[SSP_A].v);
723 printf("PC: %04x (%04x) P: %08x\n", GET_PC(), GET_PC() << 1, ssp->gr[SSP_P].v);
724 printf("PM0: %04x PM1: %04x PM2: %04x\n", rPM0, rPM1, rPM2);
725 printf("XST: %04x PM4: %04x PMC: %08x\n", rXST, rPM4, ssp->gr[SSP_PMC].v);
726 printf(" ST: %04x %c%c%c%c, GP0_0 %i, GP0_1 %i\n", rST, rST&FLAG_N?'N':'n', rST&FLAG_V?'V':'v',
727 rST&FLAG_Z?'Z':'z', rST&FLAG_L?'L':'l', (rST>>5)&1, (rST>>6)&1);
728 printf("STACK: %i %04x %04x %04x %04x %04x %04x\n", rSTACK, ssp->stack[0], ssp->stack[1],
729 ssp->stack[2], ssp->stack[3], ssp->stack[4], ssp->stack[5]);
730 printf("r0-r2: %02x %02x %02x r4-r6: %02x %02x %02x\n", rIJ[0], rIJ[1], rIJ[2], rIJ[4], rIJ[5], rIJ[6]);
731 elprintf(EL_SVP, "cycles: %i, emu_status: %x", g_cycles, ssp->emu_status);
732}
f8ef8ff7 733
5de27868 734static void debug_dump_mem(void)
735{
736 int h, i;
737 printf("RAM0\n");
738 for (h = 0; h < 32; h++)
739 {
740 if (h == 16) printf("RAM1\n");
741 printf("%03x:", h*16);
742 for (i = 0; i < 16; i++)
743 printf(" %04x", ssp->RAM[h*16+i]);
744 printf("\n");
745 }
746}
747
748static int bpts[10] = { 0, };
749
750static void debug(unsigned int pc, unsigned int op)
751{
752 static char buffo[64] = {0,};
753 char buff[64] = {0,};
754 int i;
755
756 if (running) {
757 for (i = 0; i < 10; i++)
758 if (pc != 0 && bpts[i] == pc) {
759 printf("breakpoint %i\n", i);
760 running = 0;
761 break;
762 }
763 }
764 if (running) return;
765
766 printf("%04x (%02x) @ %04x\n", op, op >> 9, pc<<1);
767
768 while (1)
769 {
770 printf("dbg> ");
771 fflush(stdout);
772 fgets(buff, sizeof(buff), stdin);
773 if (buff[0] == '\n') strcpy(buff, buffo);
774 else strcpy(buffo, buff);
775
776 switch (buff[0]) {
777 case 0: exit(0);
778 case 'c':
779 case 'r': running = 1; return;
780 case 's':
781 case 'n': return;
782 case 'x': debug_dump(); break;
783 case 'm': debug_dump_mem(); break;
784 case 'b': {
785 char *baddr = buff + 2;
786 i = 0;
787 if (buff[3] == ' ') { i = buff[2] - '0'; baddr = buff + 4; }
788 bpts[i] = strtol(baddr, NULL, 16) >> 1;
789 printf("breakpoint %i set @ %04x\n", i, bpts[i]<<1);
790 break;
791 }
792 case 'd': {
793 FILE *f = fopen("dump.bin", "wb");
794 unsigned short *p = (unsigned short *)svp->iram_rom;
795 int i;
796 if (f) {
797 for (i = 0; i < 0x10000; i++) p[i] = (p[i]<<8) | (p[i]>>8);
798 fwrite(svp->iram_rom, 1, 0x20000, f);
799 fclose(f);
800 for (i = 0; i < 0x10000; i++) p[i] = (p[i]<<8) | (p[i]>>8);
801 printf("dumped to dump.bin\n");
802 }
803 else
804 printf("dump failed\n");
805 break;
806 }
807 default: printf("unknown command\n"); break;
808 }
809 }
810}
811
812void ssp1601_run(int cycles)
813{
017512f2 814 SET_PC(rPC);
815 g_cycles = cycles;
5de27868 816//running = 0;
f8ef8ff7 817
017512f2 818 while (g_cycles > 0)
f8ef8ff7 819 {
5de27868 820 int op;
821 u32 tmpv;
822
823 op = *PC++;
824 debug(GET_PC()-1, op);
f8ef8ff7 825 switch (op >> 9)
826 {
827 // ld d, s
5de27868 828 case 0x00:
f8ef8ff7 829 if (op == 0) break; // nop
017512f2 830 if (op == ((SSP_A<<4)|SSP_P)) { // A <- P
831 // not sure. MAME claims that only hi word is transfered.
832 read_P(); // update P
833 ssp->gr[SSP_A].v = ssp->gr[SSP_P].v;
f8ef8ff7 834 }
5de27868 835 else
f8ef8ff7 836 {
5de27868 837 tmpv = REG_READ(op & 0x0f);
838 REG_WRITE((op & 0xf0) >> 4, tmpv);
839 }
840 break;
841
842 // ld d, (ri)
843 case 0x01: tmpv = ptr1_read(op); REG_WRITE((op & 0xf0) >> 4, tmpv); break;
844
845 // ld (ri), s
846 case 0x02: tmpv = REG_READ((op & 0xf0) >> 4); ptr1_write(op, tmpv); break;
847
848 // ldi d, imm
849 case 0x04: tmpv = *PC++; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
850
851 // ld d, ((ri))
852 case 0x05: tmpv = ptr2_read(op); REG_WRITE((op & 0xf0) >> 4, tmpv); break;
853
854 // ldi (ri), imm
855 case 0x06: tmpv = *PC++; ptr1_write(op, tmpv); break;
856
857 // ld adr, a
858 case 0x07: ssp->RAM[op & 0x1ff] = rA; break;
859
860 // ld d, ri
861 case 0x09: tmpv = rIJ[(op&3)|((op>>6)&4)]; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
862
863 // ld ri, s
864 case 0x0a: rIJ[(op&3)|((op>>6)&4)] = REG_READ((op & 0xf0) >> 4); break;
865
866 // ldi ri, simm
867 case 0x0c:
868 case 0x0d:
869 case 0x0e:
870 case 0x0f: rIJ[(op>>8)&7] = op; break;
871
872 // call cond, addr
873 case 0x24: {
874 int cond = 0;
875 COND_CHECK
876 if (cond) { int new_PC = *PC++; write_STACK(GET_PC()); write_PC(new_PC); }
877 else PC++;
878 break;
879 }
880
881 // ld d, (a)
882 case 0x25: tmpv = ((unsigned short *)svp->iram_rom)[rA]; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
883
884 // bra cond, addr
885 case 0x26: {
886 int cond = 0;
887 COND_CHECK
888 if (cond) { int new_PC = *PC++; write_PC(new_PC); }
889 else PC++;
890 break;
891 }
892
893 // mod cond, op
894 case 0x48: {
895 int cond = 0;
896 COND_CHECK
897 if (cond) {
898 switch (op & 7) {
899 case 2: rA32 >>= 1; break; // shr
900 case 3: rA32 <<= 1; break; // shl
901 case 6: rA32 = -(int)rA32; break; // neg
902 case 7: if ((int)rA32 < 0) rA32 = -(int)rA32; break; // abs
903 default: elprintf(EL_SVP, "ssp16: unhandled mod %i @ %04x", op&7, GET_PPC_OFFS());
904 }
905 UPD_ACC_ZN
f8ef8ff7 906 }
907 break;
5de27868 908 }
909
910 // mpya (rj), (ri), b
911 case 0x4b:
912 // dunno if this is correct. What about b?
913 read_P(); // update P
914 ssp->gr[SSP_A].v += ssp->gr[SSP_P].v; // maybe only upper word?
915 rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
916 rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
917 break;
918
919 // mld (rj), (ri), b
920 case 0x5b:
921 // dunno if this is correct. What about b?
922 ssp->gr[SSP_A].v = 0; // maybe only upper word?
923 rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
924 rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
925 break;
926
927 // OP a, s
928 case 0x10: tmpv = REG_READ(op & 0x0f); OP_SUBA(tmpv); break;
929 case 0x30: tmpv = REG_READ(op & 0x0f); OP_CMPA(tmpv); break;
930 case 0x40: tmpv = REG_READ(op & 0x0f); OP_ADDA(tmpv); break;
931 case 0x50: tmpv = REG_READ(op & 0x0f); OP_ANDA(tmpv); break;
932 case 0x60: tmpv = REG_READ(op & 0x0f); OP_ORA (tmpv); break;
933 case 0x70: tmpv = REG_READ(op & 0x0f); OP_EORA(tmpv); break;
934
935 // OP a, (ri)
936 case 0x11: tmpv = ptr1_read(op); OP_SUBA(tmpv); break;
937 case 0x31: tmpv = ptr1_read(op); OP_CMPA(tmpv); break;
938 case 0x41: tmpv = ptr1_read(op); OP_ADDA(tmpv); break;
939 case 0x51: tmpv = ptr1_read(op); OP_ANDA(tmpv); break;
940 case 0x61: tmpv = ptr1_read(op); OP_ORA (tmpv); break;
941 case 0x71: tmpv = ptr1_read(op); OP_EORA(tmpv); break;
942
943 // OP a, adr
944 case 0x03: tmpv = ssp->RAM[op & 0x1ff]; OP_LDA (tmpv); break;
945 case 0x13: tmpv = ssp->RAM[op & 0x1ff]; OP_SUBA(tmpv); break;
946 case 0x33: tmpv = ssp->RAM[op & 0x1ff]; OP_CMPA(tmpv); break;
947 case 0x43: tmpv = ssp->RAM[op & 0x1ff]; OP_ADDA(tmpv); break;
948 case 0x53: tmpv = ssp->RAM[op & 0x1ff]; OP_ANDA(tmpv); break;
949 case 0x63: tmpv = ssp->RAM[op & 0x1ff]; OP_ORA (tmpv); break;
950 case 0x73: tmpv = ssp->RAM[op & 0x1ff]; OP_EORA(tmpv); break;
951
952 // OP a, imm
953 case 0x14: tmpv = *PC++; OP_SUBA(tmpv); break;
954 case 0x34: tmpv = *PC++; OP_CMPA(tmpv); break;
955 case 0x44: tmpv = *PC++; OP_ADDA(tmpv); break;
956 case 0x54: tmpv = *PC++; OP_ANDA(tmpv); break;
957 case 0x64: tmpv = *PC++; OP_ORA (tmpv); break;
958 case 0x74: tmpv = *PC++; OP_EORA(tmpv); break;
959
960 // OP a, ((ri))
961 case 0x15: tmpv = ptr2_read(op); OP_SUBA(tmpv); break;
962 case 0x35: tmpv = ptr2_read(op); OP_CMPA(tmpv); break;
963 case 0x45: tmpv = ptr2_read(op); OP_ADDA(tmpv); break;
964 case 0x55: tmpv = ptr2_read(op); OP_ANDA(tmpv); break;
965 case 0x65: tmpv = ptr2_read(op); OP_ORA (tmpv); break;
966 case 0x75: tmpv = ptr2_read(op); OP_EORA(tmpv); break;
967
968 // OP a, ri
969 case 0x19: tmpv = rIJ[IJind]; OP_SUBA(tmpv); break;
970 case 0x39: tmpv = rIJ[IJind]; OP_CMPA(tmpv); break;
971 case 0x49: tmpv = rIJ[IJind]; OP_ADDA(tmpv); break;
972 case 0x59: tmpv = rIJ[IJind]; OP_ANDA(tmpv); break;
973 case 0x69: tmpv = rIJ[IJind]; OP_ORA (tmpv); break;
974 case 0x79: tmpv = rIJ[IJind]; OP_EORA(tmpv); break;
975
976 // OP simm
977 case 0x1c: OP_SUBA(op & 0xff); break;
978 case 0x3c: OP_CMPA(op & 0xff); break;
979 case 0x4c: OP_ADDA(op & 0xff); break;
980 // MAME code only does LSB of top word, but this looks wrong to me.
981 case 0x5c: OP_ANDA(op & 0xff); break;
982 case 0x6c: OP_ORA (op & 0xff); break;
983 case 0x7c: OP_EORA(op & 0xff); break;
f8ef8ff7 984
985 default:
5de27868 986 elprintf(EL_ANOMALY|EL_SVP, "ssp16: unhandled op %04x @ %04x", op, GET_PPC_OFFS());
017512f2 987 break;
f8ef8ff7 988 }
017512f2 989 g_cycles--;
f8ef8ff7 990 }
991
017512f2 992 read_P(); // update P
f8ef8ff7 993 rPC = GET_PC();
017512f2 994
995 if (ssp->gr[SSP_GR0].v != 0xffff0000)
996 elprintf(EL_ANOMALY|EL_SVP, "ssp16: REG 0 corruption! %08x", ssp->gr[SSP_GR0].v);
f8ef8ff7 997}
998
fast MegaDrive/MegaCD/32X emulator