notaz.gp2x.de / picodrive.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
svp..
[picodrive.git] / Pico / carthw / svp / ssp16.c
CommitLineData
f8ef8ff7 1// basic, incomplete SSP160x (SSP1601?) interpreter
2
3/*
4 * Register info
5 * most names taken from MAME code
6 *
7 * 0. "-"
8 * size: 16
9 * desc: Constant register with all bits set (0xffff).
10 *
11 * 1. "X"
12 * size: 16
13 * desc: Generic register. When set, updates P (P = X * Y * 2) ??
14 *
15 * 2. "Y"
16 * size: 16
17 * desc: Generic register. When set, updates P (P = X * Y * 2) ??
18 *
19 * 3. "A"
20 * size: 32
21 * desc: Accumulator.
22 *
23 * 4. "ST"
24 * size: 16
25 * desc: Status register. From MAME: bits 0-9 are CONTROL, other FLAG
26 * fedc ba98 7654 3210
5de27868 27 * 210 - RPL (?) "Loop size". If non-zero, makes (rX+) and (rX-) respectively
28 * modulo-increment and modulo-decrement. The value shows which
29 * power of 2 to use, i.e. 4 means modulo by 16.
30 * (e: fir16_32.sc, IIR_4B.SC, DECIM.SC)
f8ef8ff7 31 * 43 - RB (?)
5de27868 32 * 5 - GP0_0 (ST5?) Changed before acessing PM0 (affects banking?).
33 * 6 - GP0_1 (ST6?) Cleared before acessing PM0 (affects banking?). Set after.
34 * datasheet says these (5,6) bits correspond to hardware pins.
35 * 7 - IE (?) Not directly used by SVP code (never set, but preserved)?
36 * 8 - OP (?) Not used by SVP code (only cleared)? (MAME: saturated value
37 * (probably means clamping? i.e. 0x7ffc + 9 -> 0x7fff))
f8ef8ff7 38 * 9 - MACS (?) Not used by SVP code (only cleared)? (e: "mac shift")
39 * a - GPI_0 Interrupt 0 enable/status?
40 * b - GPI_1 Interrupt 1 enable/status?
41 * c - L L flag. Carry?
42 * d - Z Zero flag.
43 * e - OV Overflow flag.
44 * f - N Negative flag.
45 * seen directly changing code sequences:
46 * ldi ST, 0 ld A, ST ld A, ST ld A, ST ldi st, 20h
47 * ldi ST, 60h ori A, 60h and A, E8h and A, E8h
48 * ld ST, A ld ST, A ori 3
49 * ld ST, A
50 *
51 * 5. "STACK"
52 * size: 16
53 * desc: hw stack of 6 levels (according to datasheet)
54 *
55 * 6. "PC"
56 * size: 16
57 * desc: Program counter.
58 *
59 * 7. "P"
60 * size: 32
61 * desc: multiply result register. Updated after mp* instructions,
62 * or writes to X or Y (P = X * Y * 2) ??
63 * probably affected by MACS bit in ST.
64 *
65 * 8. "PM0" (PM from PMAR name from Tasco's docs)
66 * size: 16?
67 * desc: Programmable Memory access register.
68 * On reset, or when one (both?) GP0 bits are clear,
d26dc685 69 * acts as status for XST, mapped at 015004 at 68k side:
70 * bit0: ssp has written something to XST (cleared when 015004 is read)
71 * bit1: 68k has written something through a1500{0|2} (cleared on PM0 read)
f8ef8ff7 72 *
73 * 9. "PM1"
74 * size: 16?
75 * desc: Programmable Memory access register.
76 * This reg. is only used as PMAR.
77 *
78 * 10. "PM2"
79 * size: 16?
80 * desc: Programmable Memory access register.
81 * This reg. is only used as PMAR.
82 *
83 * 11. "XST"
84 * size: 16?
d26dc685 85 * desc: eXternal STate. Mapped to a15000 and a15002 at 68k side.
f8ef8ff7 86 * Can be programmed as PMAR? (only seen in test mode code)
d26dc685 87 * Affects PM0 when written to?
f8ef8ff7 88 *
89 * 12. "PM4"
90 * size: 16?
91 * desc: Programmable Memory access register.
92 * This reg. is only used as PMAR. The most used PMAR by VR.
93 *
94 * 13. (unused by VR)
95 *
96 * 14. "PMC" (PMC from PMAC name from Tasco's docs)
97 * size: 32?
98 * desc: Programmable Memory access Control. Set using 2 16bit writes,
99 * first address, then mode word. After setting PMAC, PMAR sould
100 * be accessed to program it.
101 *
102 * 15. "AL"
103 * size: 16
104 * desc: Accumulator Low. 16 least significant bits of accumulator (not 100% sure)
105 * (normally reading acc (ld X, A) you get 16 most significant bits).
106 *
107 *
108 * There are 8 8-bit pointer registers rX. r0-r3 (ri) point to RAM0, r4-r7 (rj) point to RAM1.
5de27868 109 * They can be accessed directly, or 2 indirection levels can be used [ (rX), ((rX)) ],
110 * which work similar to * and ** operators in C, only they use different memory banks and
111 * ((rX)) also does post-increment. First indirection level (rX) accesses RAMx, second accesses
112 * program memory at address read from (rX), and increments value in (rX).
f8ef8ff7 113 *
114 * r0,r1,r2,r4,r5,r6 can be modified [ex: ldi r0, 5].
115 * 3 modifiers can be applied (optional):
5de27868 116 * + : post-increment [ex: ld a, (r0+) ]. Can be made modulo-increment by setting RPL bits in ST.
117 * - : post-decrement. Can be made modulo-decrement by setting RPL bits in ST (not sure).
118 * +!: post-increment, unaffected by RPL (probably).
119 * These are only used on 1st indirection level, so things like [ld a, ((r0+))] and [ld X, r6-]
120 * ar probably invalid.
f8ef8ff7 121 *
122 * r3 and r7 are special and can not be changed (at least Samsung samples and SVP code never do).
123 * They are fixed to the start of their RAM banks. (They are probably changeable for ssp1605+,
124 * Samsung's old DSP page claims that).
125 * 1 of these 4 modifiers must be used (short form direct addressing?):
126 * |00: RAMx[0] [ex: (r3|00), 0] (based on sample code)
127 * |01: RAMx[1]
128 * |10: RAMx[2] ? maybe 10h? accortding to Div_c_dp.sc, 2
129 * |11: RAMx[3]
130 *
131 *
132 * Instruction notes
133 *
d26dc685 134 * ld a, * doesn't affect flags! (e: A_LAW.SC, Div_c_dp.sc)
135 *
f8ef8ff7 136 * mld (rj), (ri) [, b]
137 * operation: A = 0; P = (rj) * (ri)
138 * notes: based on IIR_4B.SC sample. flags? what is b???
139 * TODO: figure out if (rj) and (ri) get loaded in X and Y
140 *
141 * mpya (rj), (ri) [, b]
142 * name: multiply and add?
143 * operation: A += P; P = (rj) * (ri)
144 *
145 * mpys (rj), (ri), b
146 * name: multiply and subtract?
147 * notes: not used by VR code.
017512f2 148 *
d26dc685 149 * mod cond, op
150 * mod cond, shr does arithmetic shift
30752975 151 *
67256d4b 152 * 'ld -, AL' and probably 'ld AL, -' are for dummy assigns
153 *
30752975 154 * memory map:
155 * 000000 - 1fffff ROM, accessable by both
156 * 200000 - 2fffff unused?
d26dc685 157 * 300000 - 31ffff DRAM, both
30752975 158 * 320000 - 38ffff unused?
159 * 390000 - 3907ff IRAM. can only be accessed by ssp?
d26dc685 160 * 390000 - 39ffff similar mapping to "cell arrange" in Sega CD, 68k only?
161 * 3a0000 - 3affff similar mapping to "cell arrange" in Sega CD, a bit different
30752975 162 *
163 * 30fe02 - 0 if SVP busy, 1 if done (set by SVP, checked and cleared by 68k)
164 * 30fe06 - also sync related.
d26dc685 165 * 30fe08 - job number [1-12] for SVP. 0 means no job. Set by 68k, read-cleared by SVP.
166 *
67256d4b 167 * TODO:
168 * + figure out if 'op A, P' is 32bit (nearly sure it is)
169 * * what exactly is AL?
170 * * does mld, mpya load their operands into X and Y?
171 * * OP simm
172 *
d26dc685 173 * misc:
174 * pressing all buttons while resetting game will kick into test mode
017512f2 175 *
176 * Assumptions in this code
177 * P is not directly writeable
5de27868 178 * flags correspond to full 32bit accumulator
179 * only Z and N status flags are emulated (others unused by SVP)
180 * modifiers for 'OP a, ri' are ignored (invalid?/not used by SVP)
181 * modifiers '+' and '+!' act the same (this is most likely wrong)
182 * 'ld d, (a)' loads from program ROM
f8ef8ff7 183 */
184
185#include "../../PicoInt.h"
186
017512f2 187#define u32 unsigned int
188
189// 0
190#define rX ssp->gr[SSP_X].h
191#define rY ssp->gr[SSP_Y].h
192#define rA ssp->gr[SSP_A].h
193#define rST ssp->gr[SSP_ST].h // 4
194#define rSTACK ssp->gr[SSP_STACK].h
195#define rPC ssp->gr[SSP_PC].h
196#define rP ssp->gr[SSP_P]
197#define rPM0 ssp->gr[SSP_PM0].h // 8
198#define rPM1 ssp->gr[SSP_PM1].h
199#define rPM2 ssp->gr[SSP_PM2].h
200#define rXST ssp->gr[SSP_XST].h
201#define rPM4 ssp->gr[SSP_PM4].h // 12
202// 13
203#define rPMC ssp->gr[SSP_PMC] // will keep addr in .h, mode in .l
f8ef8ff7 204#define rAL ssp->gr[SSP_A].l
205
5de27868 206#define rA32 ssp->gr[SSP_A].v
207#define rIJ ssp->r
208
209#define IJind (((op>>6)&4)|(op&3))
210
211#define GET_PC() (PC - (unsigned short *)svp->iram_rom)
212#define GET_PPC_OFFS() ((unsigned int)PC - (unsigned int)svp->iram_rom - 2)
213#define SET_PC(d) PC = (unsigned short *)svp->iram_rom + d
017512f2 214
215#define REG_READ(r) (((r) <= 4) ? ssp->gr[r].h : read_handlers[r]())
216#define REG_WRITE(r,d) { \
217 int r1 = r; \
5de27868 218 if (r1 >= 4) write_handlers[r1](d); \
017512f2 219 else if (r1 > 0) ssp->gr[r1].h = d; \
220}
221
5de27868 222// flags
d26dc685 223#define SSP_FLAG_L (1<<0xc)
224#define SSP_FLAG_Z (1<<0xd)
225#define SSP_FLAG_V (1<<0xe)
226#define SSP_FLAG_N (1<<0xf)
5de27868 227
228// update ZN according to 32bit ACC.
229#define UPD_ACC_ZN \
d26dc685 230 rST &= ~(SSP_FLAG_Z|SSP_FLAG_N); \
231 if (!rA32) rST |= SSP_FLAG_Z; \
232 else rST |= (rA32>>16)&SSP_FLAG_N;
5de27868 233
234// it seems SVP code never checks for L and OV, so we leave them out.
d26dc685 235// rST |= (t>>4)&SSP_FLAG_L;
67256d4b 236#define UPD_LZVN \
237 rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
238 if (!rA32) rST |= SSP_FLAG_Z; \
239 else rST |= (rA32>>16)&SSP_FLAG_N;
240
5de27868 241#define UPD_t_LZVN \
d26dc685 242 rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
243 if (!t) rST |= SSP_FLAG_Z; \
244 else rST |= t&SSP_FLAG_N; \
5de27868 245
246// standard cond processing.
247// again, only Z and N is checked, as SVP doesn't seem to use any other conds.
248#define COND_CHECK \
249 switch (op&0xf0) { \
250 case 0x00: cond = 1; break; /* always true */ \
d26dc685 251 case 0x50: cond = !((rST ^ (op<<5)) & SSP_FLAG_Z); break; /* Z matches f(?) bit */ \
252 case 0x70: cond = !((rST ^ (op<<7)) & SSP_FLAG_N); break; /* N matches f(?) bit */ \
5de27868 253 default:elprintf(EL_SVP, "unimplemented cond @ %04x", GET_PPC_OFFS()); break; \
254 }
255
256// ops with accumulator.
257// how is low word really affected by these?
30752975 258// nearly sure 'ld A' doesn't affect flags
5de27868 259#define OP_LDA(x) \
30752975 260 ssp->gr[SSP_A].h = x
5de27868 261
67256d4b 262#define OP_LDA32(x) \
263 ssp->gr[SSP_A].v = x
264
5de27868 265#define OP_SUBA(x) { \
266 u32 t = (ssp->gr[SSP_A].v >> 16) - (x); \
267 UPD_t_LZVN \
268 ssp->gr[SSP_A].h = t; \
269}
270
67256d4b 271#define OP_SUBA32(x) { \
272 ssp->gr[SSP_A].v -= (x); \
273 UPD_LZVN \
274}
275
5de27868 276#define OP_CMPA(x) { \
277 u32 t = (ssp->gr[SSP_A].v >> 16) - (x); \
278 UPD_t_LZVN \
279}
280
67256d4b 281#define OP_CMPA32(x) { \
282 u32 t = ssp->gr[SSP_A].v - (x); \
283 rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
284 if (!t) rST |= SSP_FLAG_Z; \
285 else rST |= (t>>16)&SSP_FLAG_N; \
286}
287
5de27868 288#define OP_ADDA(x) { \
289 u32 t = (ssp->gr[SSP_A].v >> 16) + (x); \
290 UPD_t_LZVN \
291 ssp->gr[SSP_A].h = t; \
292}
293
67256d4b 294#define OP_ADDA32(x) { \
295 ssp->gr[SSP_A].v += (x); \
296 UPD_LZVN \
297}
298
5de27868 299#define OP_ANDA(x) \
300 ssp->gr[SSP_A].v &= (x) << 16; \
301 UPD_ACC_ZN
302
67256d4b 303#define OP_ANDA32(x) \
304 ssp->gr[SSP_A].v &= (x); \
305 UPD_ACC_ZN
306
5de27868 307#define OP_ORA(x) \
308 ssp->gr[SSP_A].v |= (x) << 16; \
309 UPD_ACC_ZN
310
67256d4b 311#define OP_ORA32(x) \
312 ssp->gr[SSP_A].v |= (x); \
313 UPD_ACC_ZN
314
5de27868 315#define OP_EORA(x) \
316 ssp->gr[SSP_A].v ^= (x) << 16; \
317 UPD_ACC_ZN
318
67256d4b 319#define OP_EORA32(x) \
320 ssp->gr[SSP_A].v ^= (x); \
321 UPD_ACC_ZN
322
323
324#define OP_CHECK32(OP) \
325 if ((op & 0x0f) == SSP_P) { /* A <- P */ \
326 read_P(); /* update P */ \
327 OP(ssp->gr[SSP_P].v); \
328 break; \
329}
330
5de27868 331
017512f2 332static ssp1601_t *ssp = NULL;
333static unsigned short *PC;
334static int g_cycles;
5de27868 335// debug
336static int running = 0;
30752975 337static int last_iram = 0;
017512f2 338
339// -----------------------------------------------------
340// register i/o handlers
341
342// 0-4, 13
343static u32 read_unknown(void)
344{
30752975 345 elprintf(EL_ANOMALY|EL_SVP, "ssp16: FIXME: unknown read @ %04x", GET_PPC_OFFS());
017512f2 346 return 0;
347}
348
349static void write_unknown(u32 d)
350{
30752975 351 elprintf(EL_ANOMALY|EL_SVP, "ssp16: FIXME: unknown write @ %04x", GET_PPC_OFFS());
5de27868 352}
353
354// 4
355static void write_ST(u32 d)
356{
357 if ((rST ^ d) & 7) {
358 elprintf(EL_SVP, "ssp16: RPL %i -> %i @ %04x", rST&7, d&7, GET_PPC_OFFS());
30752975 359// running = 0;
5de27868 360 }
361 rST = d;
017512f2 362}
363
364// 5
365static u32 read_STACK(void)
366{
5de27868 367 //elprintf(EL_SVP, "pop %i @ %04x", rSTACK, GET_PPC_OFFS());
368 --rSTACK;
369 if ((short)rSTACK < 0) {
370 rSTACK = 5;
30752975 371 elprintf(EL_ANOMALY|EL_SVP, "ssp16: FIXME: stack underflow! (%i) @ %04x", rSTACK, GET_PPC_OFFS());
5de27868 372 }
373 return ssp->stack[rSTACK];
017512f2 374}
375
376static void write_STACK(u32 d)
377{
5de27868 378 if (rSTACK >= 6) {
30752975 379 running = 0;
380 elprintf(EL_ANOMALY|EL_SVP, "ssp16: FIXME: stack overflow! (%i) @ %04x", rSTACK, GET_PPC_OFFS());
5de27868 381 rSTACK = 0;
382 }
383 ssp->stack[rSTACK++] = d;
017512f2 384}
385
386// 6
387static u32 read_PC(void)
388{
389 return GET_PC();
390}
391
392static void write_PC(u32 d)
393{
394 SET_PC(d);
395 g_cycles--;
396}
397
398// 7
399static u32 read_P(void)
400{
401 rP.v = (u32)rX * rY * 2;
402 return rP.h;
403}
404
5de27868 405// -----------------------------------------------------
406
407static void iram_write(int addr, u32 d, int reg, int inc)
408{
409 if ((addr&0xfc00) != 0x8000)
30752975 410 elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: invalid IRAM addr: %04x", addr<<1);
5de27868 411 elprintf(EL_SVP, "ssp IRAM w [%06x] %04x (inc %i)", (addr<<1)&0x7ff, d, inc);
412 ((unsigned short *)svp->iram_rom)[addr&0x3ff] = d;
413 ssp->pmac_write[reg] += inc<<16;
414}
415
30752975 416int lil[32] = { 0, }, lilp = 0;
417
418static void debug_dump2file(const char *fname, void *mem, int len);
419
d26dc685 420#define overwite_write(dst, d) \
421{ \
422 if (d & 0xf000) { dst &= ~0xf000; dst |= d & 0xf000; } \
423 if (d & 0x0f00) { dst &= ~0x0f00; dst |= d & 0x0f00; } \
424 if (d & 0x00f0) { dst &= ~0x00f0; dst |= d & 0x00f0; } \
425 if (d & 0x000f) { dst &= ~0x000f; dst |= d & 0x000f; } \
426}
427
017512f2 428static u32 pm_io(int reg, int write, u32 d)
429{
67256d4b 430 if (ssp->emu_status & SSP_PMC_SET)
431 {
432 // this MUST be blind r or w
433 if ((*(PC-1) & 0xff0f) && (*(PC-1) & 0xfff0)) {
434 elprintf(EL_SVP|EL_ANOMALY, "FIXME: tried to set PM%i (%c) with non-blind i/o %08x @ %04x",
435 reg, write ? 'w' : 'r', rPMC.v, GET_PPC_OFFS());
436 ssp->emu_status &= ~SSP_PMC_SET;
437 return 0;
438 }
5de27868 439 elprintf(EL_SVP, "PM%i (%c) set to %08x @ %04x", reg, write ? 'w' : 'r', rPMC.v, GET_PPC_OFFS());
017512f2 440 ssp->pmac_read[write ? reg + 6 : reg] = rPMC.v;
441 ssp->emu_status &= ~SSP_PMC_SET;
30752975 442 if ((rPMC.v & 0x7f) == 0x1c && (rPMC.v & 0x7fff0000) == 0) {
443 elprintf(EL_SVP, "IRAM copy from %06x", (ssp->RAM1[0]-1)<<1);
444/*
445 {
446 int i;
447 char buff[64];
448 for (i = 0; i < 32; i++) {
449 if (lil[i] == last_iram) break;
450 if (lil[i] == 0) {
451 lil[i] = last_iram;
452 sprintf(buff, "iramrom_%04x.bin", last_iram);
453 debug_dump2file(buff, svp->iram_rom, sizeof(svp->iram_rom));
454 break;
455 }
456 }
457 }
458*/
459 last_iram = (ssp->RAM1[0]-1)<<1;
460 }
017512f2 461 return 0;
462 }
463
5de27868 464 // just in case
67256d4b 465 if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
466 elprintf(EL_SVP|EL_ANOMALY, "FIXME: PM%i (%c) with only addr set @ %04x",
467 reg, write ? 'w' : 'r', GET_PPC_OFFS());
468 ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
469 }
5de27868 470
471// if (ssp->pmac_read[reg] != 0)
472 if (reg == 4 || (rST & 0x60))
473 {
30752975 474 #define CADDR ((((mode<<16)&0x7f0000)|addr)<<1)
d26dc685 475 unsigned short *dram = (unsigned short *)svp->dram;
5de27868 476 if (write)
477 {
d26dc685 478 /* TODO: 0c18 mode? */
5de27868 479 int mode = ssp->pmac_write[reg]&0xffff;
480 int addr = ssp->pmac_write[reg]>>16;
481 switch (mode) {
67256d4b 482 case 0x0018: elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x", reg, CADDR, d);
d26dc685 483 dram[addr] = d;
484 break;
67256d4b 485 case 0x0418: elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (overwr)", reg, CADDR, d);
d26dc685 486 overwite_write(dram[addr], d);
5de27868 487 break;
67256d4b 488 case 0x0818: elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (inc 1)", reg, CADDR, d);
d26dc685 489 dram[addr] = d;
5de27868 490 ssp->pmac_write[reg] += 1<<16;
491 break;
492 case 0x081c: iram_write(addr, d, reg, 1); break; // checked: used by code @ 0902
493 case 0x101c: iram_write(addr, d, reg, 2); break; // checked: used by code @ 3b7c
67256d4b 494 case 0x4018: elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (cell inc)", reg, CADDR, d);
d26dc685 495 dram[addr] = d;
496 ssp->pmac_write[reg] += (addr&1) ? (31<<16) : (1<<16);
497 break;
67256d4b 498 case 0x4418: elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (overwr, cell inc)", reg, CADDR, d);
d26dc685 499 overwite_write(dram[addr], d);
30752975 500 ssp->pmac_write[reg] += (addr&1) ? (31<<16) : (1<<16);
501 break;
5de27868 502 default: elprintf(EL_SVP|EL_ANOMALY, "ssp PM%i unhandled write mode %04x, [%06x] %04x @ %04x",
30752975 503 reg, mode, CADDR, d, GET_PPC_OFFS()); break;
5de27868 504 }
505 }
506 else
507 {
508 int mode = ssp->pmac_read[reg]&0xffff;
509 int addr = ssp->pmac_read[reg]>>16;
d26dc685 510 if ((mode & 0xfff0) == 0x0800) { // ROM, inc 1, verified to be correct
511 elprintf(EL_SVP, "ssp ROM r [%06x] %04x", CADDR,
512 ((unsigned short *)Pico.rom)[addr|((mode&0xf)<<16)]);
513 ssp->pmac_read[reg] += 1<<16;
514 d = ((unsigned short *)Pico.rom)[addr|((mode&0xf)<<16)];
515 goto ext_io_end;
516 }
517
5de27868 518 switch (mode) {
d26dc685 519 case 0x0018: elprintf(EL_SVP, "ssp DRAM r [%06x] %04x", CADDR, dram[addr]);
520 d = dram[addr]; // checked
30752975 521 break;
67256d4b 522 case 0x0818: elprintf(EL_SVP, "ssp PM%i DRAM r [%06x] %04x (inc 1)", reg, CADDR, dram[addr]);
30752975 523 ssp->pmac_read[reg] += 1<<16;
d26dc685 524 d = dram[addr];
30752975 525 break;
d26dc685 526 case 0x3018: elprintf(EL_SVP, "ssp DRAM r [%06x] %04x (inc 32)", CADDR, dram[addr]);
30752975 527 ssp->pmac_read[reg] += 32<<16;
d26dc685 528 d = dram[addr];
30752975 529 break;
d26dc685 530 case 0xa818: elprintf(EL_SVP, "ssp DRAM r [%06x] %04x (dec 16)", CADDR, dram[addr]);
30752975 531 ssp->pmac_read[reg] -= 16<<16;
d26dc685 532 d = dram[addr];
30752975 533 break;
d26dc685 534 case 0xb818: elprintf(EL_SVP, "ssp DRAM r [%06x] %04x (dec 128?)", CADDR, dram[addr]);
30752975 535 ssp->pmac_read[reg] -= 128<<16;
d26dc685 536 d = dram[addr];
30752975 537 break;
5de27868 538 default: elprintf(EL_SVP|EL_ANOMALY, "ssp PM%i unhandled read mode %04x, [%06x] @ %04x",
30752975 539 reg, mode, CADDR, GET_PPC_OFFS());
540 d = 0;
541 break;
5de27868 542 }
543 }
30752975 544
d26dc685 545ext_io_end:
30752975 546 // PMC value corresponds to last PMR accessed (not sure).
547 rPMC.v = ssp->pmac_read[write ? reg + 6 : reg];
548
549 return d;
017512f2 550 }
551
552 return (u32)-1;
553}
554
555// 8
556static u32 read_PM0(void)
557{
558 u32 d = pm_io(0, 0, 0);
559 if (d != (u32)-1) return d;
67256d4b 560 elprintf(EL_SVP, "PM0 raw r %04x @ %04x", rPM0, GET_PPC_OFFS());
d26dc685 561 d = rPM0;
562 if (!(d & 2) && (GET_PPC_OFFS() == 0x800 || GET_PPC_OFFS() == 0x1851E)) {
563 ssp->emu_status |= SSP_WAIT_PM0; elprintf(EL_SVP, "det TIGHT loop: PM0");
564 }
565 rPM0 &= ~2; // ?
566 return d;
017512f2 567}
568
569static void write_PM0(u32 d)
570{
571 u32 r = pm_io(0, 1, d);
572 if (r != (u32)-1) return;
5de27868 573 elprintf(EL_SVP, "PM0 raw w %04x @ %04x", d, GET_PPC_OFFS());
d26dc685 574 rPM0 = d;
017512f2 575}
576
577// 9
578static u32 read_PM1(void)
579{
580 u32 d = pm_io(1, 0, 0);
581 if (d != (u32)-1) return d;
582 // can be removed?
5de27868 583 elprintf(EL_SVP, "PM1 raw r %04x @ %04x", rPM1, GET_PPC_OFFS());
584 return rPM1;
017512f2 585}
586
587static void write_PM1(u32 d)
588{
589 u32 r = pm_io(1, 1, d);
590 if (r != (u32)-1) return;
591 // can be removed?
5de27868 592 elprintf(EL_SVP, "PM1 raw w %04x @ %04x", d, GET_PPC_OFFS());
593 rPM1 = d;
017512f2 594}
595
596// 10
597static u32 read_PM2(void)
598{
599 u32 d = pm_io(2, 0, 0);
600 if (d != (u32)-1) return d;
601 // can be removed?
5de27868 602 elprintf(EL_SVP, "PM2 raw r %04x @ %04x", rPM2, GET_PPC_OFFS());
603 return rPM2;
017512f2 604}
605
606static void write_PM2(u32 d)
607{
608 u32 r = pm_io(2, 1, d);
609 if (r != (u32)-1) return;
610 // can be removed?
5de27868 611 elprintf(EL_SVP, "PM2 raw w %04x @ %04x", d, GET_PPC_OFFS());
612 rPM2 = d;
017512f2 613}
614
615// 11
616static u32 read_XST(void)
617{
618 // can be removed?
619 u32 d = pm_io(3, 0, 0);
620 if (d != (u32)-1) return d;
621
5de27868 622 elprintf(EL_SVP, "XST raw r %04x @ %04x", rXST, GET_PPC_OFFS());
623 return rXST;
017512f2 624}
f8ef8ff7 625
017512f2 626static void write_XST(u32 d)
f8ef8ff7 627{
017512f2 628 // can be removed?
629 u32 r = pm_io(3, 1, d);
630 if (r != (u32)-1) return;
631
5de27868 632 elprintf(EL_SVP, "XST raw w %04x @ %04x", d, GET_PPC_OFFS());
d26dc685 633 rPM0 |= 1;
5de27868 634 rXST = d;
017512f2 635}
636
637// 12
638static u32 read_PM4(void)
639{
640 u32 d = pm_io(4, 0, 0);
30752975 641 if (d == 0) {
642 switch (GET_PPC_OFFS()) {
d26dc685 643 case 0x0854: ssp->emu_status |= SSP_WAIT_30FE08; elprintf(EL_SVP, "det TIGHT loop: [30fe08]"); break;
644 case 0x4f12: ssp->emu_status |= SSP_WAIT_30FE06; elprintf(EL_SVP, "det TIGHT loop: [30fe06]"); break;
30752975 645 }
646 }
017512f2 647 if (d != (u32)-1) return d;
648 // can be removed?
5de27868 649 elprintf(EL_SVP, "PM4 raw r %04x @ %04x", rPM4, GET_PPC_OFFS());
650 return rPM4;
017512f2 651}
652
653static void write_PM4(u32 d)
654{
655 u32 r = pm_io(4, 1, d);
656 if (r != (u32)-1) return;
657 // can be removed?
5de27868 658 elprintf(EL_SVP, "PM4 raw w %04x @ %04x", d, GET_PPC_OFFS());
659 rPM4 = d;
017512f2 660}
661
662// 14
663static u32 read_PMC(void)
664{
665 if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
666 if (ssp->emu_status & SSP_PMC_SET)
5de27868 667 elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS());
017512f2 668 ssp->emu_status |= SSP_PMC_SET;
5de27868 669 ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
67256d4b 670 elprintf(EL_SVP, "PMC r m %04x @ %04x", rPMC.l, GET_PPC_OFFS());
017512f2 671 return rPMC.l;
672 } else {
673 ssp->emu_status |= SSP_PMC_HAVE_ADDR;
67256d4b 674 elprintf(EL_SVP, "PMC r a %04x @ %04x", rPMC.h, GET_PPC_OFFS());
017512f2 675 return rPMC.h;
676 }
677}
678
679static void write_PMC(u32 d)
680{
681 if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
682 if (ssp->emu_status & SSP_PMC_SET)
5de27868 683 elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS());
017512f2 684 ssp->emu_status |= SSP_PMC_SET;
5de27868 685 ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
017512f2 686 rPMC.l = d;
67256d4b 687 elprintf(EL_SVP, "PMC w m %04x @ %04x", rPMC.l, GET_PPC_OFFS());
017512f2 688 } else {
689 ssp->emu_status |= SSP_PMC_HAVE_ADDR;
690 rPMC.h = d;
67256d4b 691 elprintf(EL_SVP, "PMC w a %04x @ %04x", rPMC.h, GET_PPC_OFFS());
017512f2 692 }
693}
694
695// 15
696static u32 read_AL(void)
697{
698 // TODO: figure out what's up with those blind reads..
67256d4b 699 if (*(PC-1) == 0x000f) {
700 elprintf(EL_SVP|EL_ANOMALY, "ssp dummy PM assign %08x, ST=%04x @ %04x", rPMC.v, rST, GET_PPC_OFFS());
701 ssp->emu_status &= ~(SSP_PMC_SET|SSP_PMC_HAVE_ADDR); // ?
702 } else {
703 //elprintf(EL_SVP, "ssp AL read, ST=%04x @ %04x", rST, GET_PPC_OFFS());
704 }
017512f2 705 return rAL;
706}
707
708static void write_AL(u32 d)
709{
67256d4b 710 //elprintf(EL_SVP, "ssp AL write %04x, ST=%04x @ %04x", d, rST, GET_PPC_OFFS());
017512f2 711 rAL = d;
712}
713
714
715typedef u32 (*read_func_t)(void);
716typedef void (*write_func_t)(u32 d);
717
718static read_func_t read_handlers[16] =
719{
720 read_unknown, read_unknown, read_unknown, read_unknown, // -, X, Y, A
721 read_unknown, // 4 ST
722 read_STACK,
723 read_PC,
724 read_P,
725 read_PM0, // 8
726 read_PM1,
727 read_PM2,
728 read_XST,
729 read_PM4, // 12
730 read_unknown, // 13 gr13
731 read_PMC,
732 read_AL
733};
734
735static write_func_t write_handlers[16] =
736{
737 write_unknown, write_unknown, write_unknown, write_unknown, // -, X, Y, A
5de27868 738// write_unknown, // 4 ST
739 write_ST, // 4 ST (debug hook)
017512f2 740 write_STACK,
741 write_PC,
742 write_unknown, // 7 P
743 write_PM0, // 8
744 write_PM1,
745 write_PM2,
746 write_XST,
747 write_PM4, // 12
748 write_unknown, // 13 gr13
749 write_PMC,
750 write_AL
751};
752
5de27868 753// -----------------------------------------------------
754// pointer register handlers
755
756//
757#define ptr1_read(op) ptr1_read_(op&3,(op>>6)&4,(op<<1)&0x18)
758
759static u32 ptr1_read_(int ri, int isj2, int modi3)
760{
761 //int t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
30752975 762 u32 mask, add = 0, t = ri | isj2 | modi3;
763 unsigned char *rp = NULL;
5de27868 764 switch (t)
765 {
766 // mod=0 (00)
767 case 0x00:
768 case 0x01:
769 case 0x02: return ssp->RAM0[ssp->r0[t&3]];
770 case 0x03: return ssp->RAM0[0];
771 case 0x04:
772 case 0x05:
773 case 0x06: return ssp->RAM1[ssp->r1[t&3]];
774 case 0x07: return ssp->RAM1[0];
775 // mod=1 (01), "+!"
5de27868 776 case 0x08:
5de27868 777 case 0x09:
30752975 778 case 0x0a: return ssp->RAM0[ssp->r0[t&3]++];
5de27868 779 case 0x0b: return ssp->RAM0[1];
780 case 0x0c:
5de27868 781 case 0x0d:
30752975 782 case 0x0e: return ssp->RAM1[ssp->r1[t&3]++];
5de27868 783 case 0x0f: return ssp->RAM1[1];
784 // mod=2 (10), "-"
785 case 0x10:
786 case 0x11:
30752975 787 case 0x12: rp = &ssp->r0[t&3]; t = ssp->RAM0[*rp];
788 if (!(rST&7)) { (*rp)--; return t; }
789 add = -1; goto modulo;
5de27868 790 case 0x13: return ssp->RAM0[2];
791 case 0x14:
792 case 0x15:
30752975 793 case 0x16: rp = &ssp->r1[t&3]; t = ssp->RAM1[*rp];
794 if (!(rST&7)) { (*rp)--; return t; }
795 add = -1; goto modulo;
5de27868 796 case 0x17: return ssp->RAM1[2];
30752975 797 // mod=3 (11), "+"
798 case 0x18:
799 case 0x19:
800 case 0x1a: rp = &ssp->r0[t&3]; t = ssp->RAM0[*rp];
801 if (!(rST&7)) { (*rp)++; return t; }
802 add = 1; goto modulo;
5de27868 803 case 0x1b: return ssp->RAM0[3];
30752975 804 case 0x1c:
805 case 0x1d:
806 case 0x1e: rp = &ssp->r1[t&3]; t = ssp->RAM1[*rp];
807 if (!(rST&7)) { (*rp)++; return t; }
808 add = 1; goto modulo;
5de27868 809 case 0x1f: return ssp->RAM1[3];
810 }
811
812 return 0;
30752975 813
814modulo:
815 mask = (1 << (rST&7)) - 1;
816 *rp = (*rp & ~mask) | ((*rp + add) & mask);
817 return t;
5de27868 818}
819
820static void ptr1_write(int op, u32 d)
821{
822 int t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
823 switch (t)
824 {
825 // mod=0 (00)
826 case 0x00:
827 case 0x01:
828 case 0x02: ssp->RAM0[ssp->r0[t&3]] = d; return;
829 case 0x03: ssp->RAM0[0] = d; return;
830 case 0x04:
831 case 0x05:
832 case 0x06: ssp->RAM1[ssp->r1[t&3]] = d; return;
833 case 0x07: ssp->RAM1[0] = d; return;
834 // mod=1 (01), "+!"
835 // mod=3, "+"
836 case 0x08:
837 case 0x18:
838 case 0x09:
839 case 0x19:
840 case 0x0a:
841 case 0x1a: ssp->RAM0[ssp->r0[t&3]++] = d; return;
842 case 0x0b: ssp->RAM0[1] = d; return;
843 case 0x0c:
844 case 0x1c:
845 case 0x0d:
846 case 0x1d:
847 case 0x0e:
848 case 0x1e: ssp->RAM1[ssp->r1[t&3]++] = d; return;
849 case 0x0f: ssp->RAM1[1] = d; return;
850 // mod=2 (10), "-"
851 case 0x10:
852 case 0x11:
853 case 0x12: ssp->RAM0[ssp->r0[t&3]--] = d; return;
854 case 0x13: ssp->RAM0[2] = d; return;
855 case 0x14:
856 case 0x15:
857 case 0x16: ssp->RAM1[ssp->r1[t&3]--] = d; return;
858 case 0x17: ssp->RAM1[2] = d; return;
859 // mod=3 (11)
860 case 0x1b: ssp->RAM0[3] = d; return;
861 case 0x1f: ssp->RAM1[3] = d; return;
862 }
863}
864
865static u32 ptr2_read(int op)
866{
867 int mv = 0, t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
868 switch (t)
869 {
870 // mod=0 (00)
871 case 0x00:
872 case 0x01:
873 case 0x02: mv = ssp->RAM0[ssp->r0[t&3]]++; break;
874 case 0x03: mv = ssp->RAM0[0]++; break;
875 case 0x04:
876 case 0x05:
877 case 0x06: mv = ssp->RAM1[ssp->r1[t&3]]++; break;
878 case 0x07: mv = ssp->RAM1[0]++; break;
879 // mod=1 (01)
880 case 0x0b: mv = ssp->RAM0[1]++; break;
881 case 0x0f: mv = ssp->RAM1[1]++; break;
882 // mod=2 (10)
883 case 0x13: mv = ssp->RAM0[2]++; break;
884 case 0x17: mv = ssp->RAM1[2]++; break;
885 // mod=3 (11)
886 case 0x1b: mv = ssp->RAM0[3]++; break;
887 case 0x1f: mv = ssp->RAM1[3]++; break;
30752975 888 default: elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: invalid mod in ((rX))? @ %04x", GET_PPC_OFFS());
5de27868 889 return 0;
890 }
891
892 return ((unsigned short *)svp->iram_rom)[mv];
893}
894
895
896// -----------------------------------------------------
897
017512f2 898void ssp1601_reset(ssp1601_t *l_ssp)
899{
900 ssp = l_ssp;
f8ef8ff7 901 ssp->emu_status = 0;
017512f2 902 ssp->gr[SSP_GR0].v = 0xffff0000;
f8ef8ff7 903 rPC = 0x400;
5de27868 904 rSTACK = 0; // ? using ascending stack
30752975 905 rST = 0;
f8ef8ff7 906}
907
908
5de27868 909static void debug_dump(void)
f8ef8ff7 910{
5de27868 911 printf("GR0: %04x X: %04x Y: %04x A: %08x\n", ssp->gr[SSP_GR0].h, rX, rY, ssp->gr[SSP_A].v);
912 printf("PC: %04x (%04x) P: %08x\n", GET_PC(), GET_PC() << 1, ssp->gr[SSP_P].v);
913 printf("PM0: %04x PM1: %04x PM2: %04x\n", rPM0, rPM1, rPM2);
914 printf("XST: %04x PM4: %04x PMC: %08x\n", rXST, rPM4, ssp->gr[SSP_PMC].v);
d26dc685 915 printf(" ST: %04x %c%c%c%c, GP0_0 %i, GP0_1 %i\n", rST, rST&SSP_FLAG_N?'N':'n', rST&SSP_FLAG_V?'V':'v',
916 rST&SSP_FLAG_Z?'Z':'z', rST&SSP_FLAG_L?'L':'l', (rST>>5)&1, (rST>>6)&1);
5de27868 917 printf("STACK: %i %04x %04x %04x %04x %04x %04x\n", rSTACK, ssp->stack[0], ssp->stack[1],
918 ssp->stack[2], ssp->stack[3], ssp->stack[4], ssp->stack[5]);
919 printf("r0-r2: %02x %02x %02x r4-r6: %02x %02x %02x\n", rIJ[0], rIJ[1], rIJ[2], rIJ[4], rIJ[5], rIJ[6]);
920 elprintf(EL_SVP, "cycles: %i, emu_status: %x", g_cycles, ssp->emu_status);
921}
f8ef8ff7 922
5de27868 923static void debug_dump_mem(void)
924{
925 int h, i;
926 printf("RAM0\n");
927 for (h = 0; h < 32; h++)
928 {
929 if (h == 16) printf("RAM1\n");
930 printf("%03x:", h*16);
931 for (i = 0; i < 16; i++)
932 printf(" %04x", ssp->RAM[h*16+i]);
933 printf("\n");
934 }
935}
936
30752975 937static void debug_dump2file(const char *fname, void *mem, int len)
938{
939 FILE *f = fopen(fname, "wb");
940 unsigned short *p = mem;
941 int i;
942 if (f) {
943 for (i = 0; i < len/2; i++) p[i] = (p[i]<<8) | (p[i]>>8);
944 fwrite(mem, 1, len, f);
945 fclose(f);
946 for (i = 0; i < len/2; i++) p[i] = (p[i]<<8) | (p[i]>>8);
947 printf("dumped to %s\n", fname);
948 }
949 else
950 printf("dump failed\n");
951}
952
5de27868 953static int bpts[10] = { 0, };
954
955static void debug(unsigned int pc, unsigned int op)
956{
957 static char buffo[64] = {0,};
958 char buff[64] = {0,};
959 int i;
960
961 if (running) {
962 for (i = 0; i < 10; i++)
963 if (pc != 0 && bpts[i] == pc) {
964 printf("breakpoint %i\n", i);
965 running = 0;
966 break;
967 }
968 }
969 if (running) return;
970
971 printf("%04x (%02x) @ %04x\n", op, op >> 9, pc<<1);
972
973 while (1)
974 {
975 printf("dbg> ");
976 fflush(stdout);
977 fgets(buff, sizeof(buff), stdin);
978 if (buff[0] == '\n') strcpy(buff, buffo);
979 else strcpy(buffo, buff);
980
981 switch (buff[0]) {
982 case 0: exit(0);
983 case 'c':
984 case 'r': running = 1; return;
985 case 's':
986 case 'n': return;
987 case 'x': debug_dump(); break;
988 case 'm': debug_dump_mem(); break;
989 case 'b': {
990 char *baddr = buff + 2;
991 i = 0;
992 if (buff[3] == ' ') { i = buff[2] - '0'; baddr = buff + 4; }
993 bpts[i] = strtol(baddr, NULL, 16) >> 1;
994 printf("breakpoint %i set @ %04x\n", i, bpts[i]<<1);
995 break;
996 }
30752975 997 case 'd':
998 sprintf(buff, "iramrom_%04x.bin", last_iram);
999 debug_dump2file(buff, svp->iram_rom, sizeof(svp->iram_rom));
1000 debug_dump2file("dram.bin", svp->dram, sizeof(svp->dram));
5de27868 1001 break;
5de27868 1002 default: printf("unknown command\n"); break;
1003 }
1004 }
1005}
1006
1007void ssp1601_run(int cycles)
1008{
017512f2 1009 SET_PC(rPC);
1010 g_cycles = cycles;
f8ef8ff7 1011
d26dc685 1012//if (Pico.m.frame_count == 480) running = 0;
1013
1014 while (g_cycles > 0 && !(ssp->emu_status & SSP_WAIT_MASK))
f8ef8ff7 1015 {
5de27868 1016 int op;
1017 u32 tmpv;
1018
1019 op = *PC++;
1020 debug(GET_PC()-1, op);
f8ef8ff7 1021 switch (op >> 9)
1022 {
1023 // ld d, s
5de27868 1024 case 0x00:
f8ef8ff7 1025 if (op == 0) break; // nop
017512f2 1026 if (op == ((SSP_A<<4)|SSP_P)) { // A <- P
1027 // not sure. MAME claims that only hi word is transfered.
1028 read_P(); // update P
1029 ssp->gr[SSP_A].v = ssp->gr[SSP_P].v;
f8ef8ff7 1030 }
5de27868 1031 else
f8ef8ff7 1032 {
5de27868 1033 tmpv = REG_READ(op & 0x0f);
1034 REG_WRITE((op & 0xf0) >> 4, tmpv);
1035 }
1036 break;
1037
1038 // ld d, (ri)
1039 case 0x01: tmpv = ptr1_read(op); REG_WRITE((op & 0xf0) >> 4, tmpv); break;
1040
1041 // ld (ri), s
1042 case 0x02: tmpv = REG_READ((op & 0xf0) >> 4); ptr1_write(op, tmpv); break;
1043
1044 // ldi d, imm
1045 case 0x04: tmpv = *PC++; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
1046
1047 // ld d, ((ri))
1048 case 0x05: tmpv = ptr2_read(op); REG_WRITE((op & 0xf0) >> 4, tmpv); break;
1049
1050 // ldi (ri), imm
1051 case 0x06: tmpv = *PC++; ptr1_write(op, tmpv); break;
1052
1053 // ld adr, a
1054 case 0x07: ssp->RAM[op & 0x1ff] = rA; break;
1055
1056 // ld d, ri
1057 case 0x09: tmpv = rIJ[(op&3)|((op>>6)&4)]; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
1058
1059 // ld ri, s
1060 case 0x0a: rIJ[(op&3)|((op>>6)&4)] = REG_READ((op & 0xf0) >> 4); break;
1061
1062 // ldi ri, simm
1063 case 0x0c:
1064 case 0x0d:
1065 case 0x0e:
1066 case 0x0f: rIJ[(op>>8)&7] = op; break;
1067
1068 // call cond, addr
1069 case 0x24: {
1070 int cond = 0;
1071 COND_CHECK
1072 if (cond) { int new_PC = *PC++; write_STACK(GET_PC()); write_PC(new_PC); }
1073 else PC++;
1074 break;
1075 }
1076
1077 // ld d, (a)
1078 case 0x25: tmpv = ((unsigned short *)svp->iram_rom)[rA]; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
1079
1080 // bra cond, addr
1081 case 0x26: {
1082 int cond = 0;
1083 COND_CHECK
1084 if (cond) { int new_PC = *PC++; write_PC(new_PC); }
1085 else PC++;
1086 break;
1087 }
1088
1089 // mod cond, op
1090 case 0x48: {
1091 int cond = 0;
1092 COND_CHECK
1093 if (cond) {
1094 switch (op & 7) {
d26dc685 1095 case 2: rA32 = (signed int)rA32 >> 1; break; // shr (arithmetic)
5de27868 1096 case 3: rA32 <<= 1; break; // shl
d26dc685 1097 case 6: rA32 = -(signed int)rA32; break; // neg
1098 case 7: if ((int)rA32 < 0) rA32 = -(signed int)rA32; break; // abs
1099 default: elprintf(EL_SVP, "ssp16: FIXME unhandled mod %i @ %04x", op&7, GET_PPC_OFFS());
5de27868 1100 }
30752975 1101 UPD_ACC_ZN // ?
f8ef8ff7 1102 }
1103 break;
5de27868 1104 }
1105
30752975 1106#if 1
1107 // mpys?
1108 case 0x1b:
1109 // very uncertain about this one. What about b?
1110 if (!(op&0x100)) elprintf(EL_SVP|EL_ANOMALY, "ssp16: FIXME: no b bit @ %04x", GET_PPC_OFFS());
1111 read_P(); // update P
1112 ssp->gr[SSP_A].v -= ssp->gr[SSP_P].v; // maybe only upper word?
1113// UPD_ACC_ZN // I've seen code checking flags after this
1114 rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
1115 rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
1116 break;
1117#endif
5de27868 1118 // mpya (rj), (ri), b
1119 case 0x4b:
1120 // dunno if this is correct. What about b?
30752975 1121 if (!(op&0x100)) elprintf(EL_SVP|EL_ANOMALY, "ssp16: FIXME: no b bit @ %04x", GET_PPC_OFFS());
5de27868 1122 read_P(); // update P
1123 ssp->gr[SSP_A].v += ssp->gr[SSP_P].v; // maybe only upper word?
d26dc685 1124 UPD_ACC_ZN // ?
5de27868 1125 rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
1126 rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
1127 break;
1128
1129 // mld (rj), (ri), b
1130 case 0x5b:
1131 // dunno if this is correct. What about b?
30752975 1132 if (!(op&0x100)) elprintf(EL_SVP|EL_ANOMALY, "ssp16: FIXME: no b bit @ %04x", GET_PPC_OFFS());
5de27868 1133 ssp->gr[SSP_A].v = 0; // maybe only upper word?
30752975 1134 // UPD_t_LZVN // ?
5de27868 1135 rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
1136 rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
1137 break;
1138
1139 // OP a, s
67256d4b 1140 case 0x10: OP_CHECK32(OP_SUBA32); tmpv = REG_READ(op & 0x0f); OP_SUBA(tmpv); break;
1141 case 0x30: OP_CHECK32(OP_CMPA32); tmpv = REG_READ(op & 0x0f); OP_CMPA(tmpv); break;
1142 case 0x40: OP_CHECK32(OP_ADDA32); tmpv = REG_READ(op & 0x0f); OP_ADDA(tmpv); break;
1143 case 0x50: OP_CHECK32(OP_ANDA32); tmpv = REG_READ(op & 0x0f); OP_ANDA(tmpv); break;
1144 case 0x60: OP_CHECK32(OP_ORA32 ); tmpv = REG_READ(op & 0x0f); OP_ORA (tmpv); break;
1145 case 0x70: OP_CHECK32(OP_EORA32); tmpv = REG_READ(op & 0x0f); OP_EORA(tmpv); break;
5de27868 1146
1147 // OP a, (ri)
1148 case 0x11: tmpv = ptr1_read(op); OP_SUBA(tmpv); break;
1149 case 0x31: tmpv = ptr1_read(op); OP_CMPA(tmpv); break;
1150 case 0x41: tmpv = ptr1_read(op); OP_ADDA(tmpv); break;
1151 case 0x51: tmpv = ptr1_read(op); OP_ANDA(tmpv); break;
1152 case 0x61: tmpv = ptr1_read(op); OP_ORA (tmpv); break;
1153 case 0x71: tmpv = ptr1_read(op); OP_EORA(tmpv); break;
1154
1155 // OP a, adr
1156 case 0x03: tmpv = ssp->RAM[op & 0x1ff]; OP_LDA (tmpv); break;
1157 case 0x13: tmpv = ssp->RAM[op & 0x1ff]; OP_SUBA(tmpv); break;
1158 case 0x33: tmpv = ssp->RAM[op & 0x1ff]; OP_CMPA(tmpv); break;
1159 case 0x43: tmpv = ssp->RAM[op & 0x1ff]; OP_ADDA(tmpv); break;
1160 case 0x53: tmpv = ssp->RAM[op & 0x1ff]; OP_ANDA(tmpv); break;
1161 case 0x63: tmpv = ssp->RAM[op & 0x1ff]; OP_ORA (tmpv); break;
1162 case 0x73: tmpv = ssp->RAM[op & 0x1ff]; OP_EORA(tmpv); break;
1163
1164 // OP a, imm
1165 case 0x14: tmpv = *PC++; OP_SUBA(tmpv); break;
1166 case 0x34: tmpv = *PC++; OP_CMPA(tmpv); break;
1167 case 0x44: tmpv = *PC++; OP_ADDA(tmpv); break;
1168 case 0x54: tmpv = *PC++; OP_ANDA(tmpv); break;
1169 case 0x64: tmpv = *PC++; OP_ORA (tmpv); break;
1170 case 0x74: tmpv = *PC++; OP_EORA(tmpv); break;
1171
1172 // OP a, ((ri))
1173 case 0x15: tmpv = ptr2_read(op); OP_SUBA(tmpv); break;
1174 case 0x35: tmpv = ptr2_read(op); OP_CMPA(tmpv); break;
1175 case 0x45: tmpv = ptr2_read(op); OP_ADDA(tmpv); break;
1176 case 0x55: tmpv = ptr2_read(op); OP_ANDA(tmpv); break;
1177 case 0x65: tmpv = ptr2_read(op); OP_ORA (tmpv); break;
1178 case 0x75: tmpv = ptr2_read(op); OP_EORA(tmpv); break;
1179
1180 // OP a, ri
1181 case 0x19: tmpv = rIJ[IJind]; OP_SUBA(tmpv); break;
1182 case 0x39: tmpv = rIJ[IJind]; OP_CMPA(tmpv); break;
1183 case 0x49: tmpv = rIJ[IJind]; OP_ADDA(tmpv); break;
1184 case 0x59: tmpv = rIJ[IJind]; OP_ANDA(tmpv); break;
1185 case 0x69: tmpv = rIJ[IJind]; OP_ORA (tmpv); break;
1186 case 0x79: tmpv = rIJ[IJind]; OP_EORA(tmpv); break;
1187
1188 // OP simm
1189 case 0x1c: OP_SUBA(op & 0xff); break;
1190 case 0x3c: OP_CMPA(op & 0xff); break;
1191 case 0x4c: OP_ADDA(op & 0xff); break;
1192 // MAME code only does LSB of top word, but this looks wrong to me.
1193 case 0x5c: OP_ANDA(op & 0xff); break;
1194 case 0x6c: OP_ORA (op & 0xff); break;
1195 case 0x7c: OP_EORA(op & 0xff); break;
f8ef8ff7 1196
1197 default:
d26dc685 1198 elprintf(EL_ANOMALY|EL_SVP, "ssp16: FIXME unhandled op %04x @ %04x", op, GET_PPC_OFFS());
017512f2 1199 break;
f8ef8ff7 1200 }
017512f2 1201 g_cycles--;
f8ef8ff7 1202 }
1203
017512f2 1204 read_P(); // update P
f8ef8ff7 1205 rPC = GET_PC();
017512f2 1206
1207 if (ssp->gr[SSP_GR0].v != 0xffff0000)
30752975 1208 elprintf(EL_ANOMALY|EL_SVP, "ssp16: FIXME: REG 0 corruption! %08x", ssp->gr[SSP_GR0].v);
f8ef8ff7 1209}
1210
fast MegaDrive/MegaCD/32X emulator