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svp compiler: more ops, idle detection
[picodrive.git] / Pico / carthw / svp / ssp16.c
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f8ef8ff7 1// basic, incomplete SSP160x (SSP1601?) interpreter
16ebbe9e 2// with SVP memory controller emu
d4ca252d 3
4// (c) Copyright 2008, Grazvydas "notaz" Ignotas
5// Free for non-commercial use.
6
7// For commercial use, separate licencing terms must be obtained.
8
9
10#include "../../PicoInt.h"
f8ef8ff7 11
12/*
13 * Register info
f8ef8ff7 14 *
15 * 0. "-"
16 * size: 16
17 * desc: Constant register with all bits set (0xffff).
18 *
19 * 1. "X"
20 * size: 16
d4ca252d 21 * desc: Generic register. When set, updates P (P = X * Y * 2)
f8ef8ff7 22 *
23 * 2. "Y"
24 * size: 16
d4ca252d 25 * desc: Generic register. When set, updates P (P = X * Y * 2)
f8ef8ff7 26 *
27 * 3. "A"
28 * size: 32
29 * desc: Accumulator.
30 *
31 * 4. "ST"
32 * size: 16
33 * desc: Status register. From MAME: bits 0-9 are CONTROL, other FLAG
34 * fedc ba98 7654 3210
5de27868 35 * 210 - RPL (?) "Loop size". If non-zero, makes (rX+) and (rX-) respectively
36 * modulo-increment and modulo-decrement. The value shows which
37 * power of 2 to use, i.e. 4 means modulo by 16.
38 * (e: fir16_32.sc, IIR_4B.SC, DECIM.SC)
f8ef8ff7 39 * 43 - RB (?)
5de27868 40 * 5 - GP0_0 (ST5?) Changed before acessing PM0 (affects banking?).
41 * 6 - GP0_1 (ST6?) Cleared before acessing PM0 (affects banking?). Set after.
42 * datasheet says these (5,6) bits correspond to hardware pins.
43 * 7 - IE (?) Not directly used by SVP code (never set, but preserved)?
44 * 8 - OP (?) Not used by SVP code (only cleared)? (MAME: saturated value
45 * (probably means clamping? i.e. 0x7ffc + 9 -> 0x7fff))
f8ef8ff7 46 * 9 - MACS (?) Not used by SVP code (only cleared)? (e: "mac shift")
47 * a - GPI_0 Interrupt 0 enable/status?
48 * b - GPI_1 Interrupt 1 enable/status?
49 * c - L L flag. Carry?
50 * d - Z Zero flag.
51 * e - OV Overflow flag.
52 * f - N Negative flag.
53 * seen directly changing code sequences:
54 * ldi ST, 0 ld A, ST ld A, ST ld A, ST ldi st, 20h
55 * ldi ST, 60h ori A, 60h and A, E8h and A, E8h
56 * ld ST, A ld ST, A ori 3
57 * ld ST, A
58 *
59 * 5. "STACK"
60 * size: 16
61 * desc: hw stack of 6 levels (according to datasheet)
62 *
63 * 6. "PC"
64 * size: 16
65 * desc: Program counter.
66 *
67 * 7. "P"
68 * size: 32
d4ca252d 69 * desc: multiply result register. P = X * Y * 2
f8ef8ff7 70 * probably affected by MACS bit in ST.
71 *
72 * 8. "PM0" (PM from PMAR name from Tasco's docs)
73 * size: 16?
74 * desc: Programmable Memory access register.
75 * On reset, or when one (both?) GP0 bits are clear,
d26dc685 76 * acts as status for XST, mapped at 015004 at 68k side:
77 * bit0: ssp has written something to XST (cleared when 015004 is read)
78 * bit1: 68k has written something through a1500{0|2} (cleared on PM0 read)
f8ef8ff7 79 *
80 * 9. "PM1"
81 * size: 16?
82 * desc: Programmable Memory access register.
83 * This reg. is only used as PMAR.
84 *
85 * 10. "PM2"
86 * size: 16?
87 * desc: Programmable Memory access register.
88 * This reg. is only used as PMAR.
89 *
90 * 11. "XST"
91 * size: 16?
d26dc685 92 * desc: eXternal STate. Mapped to a15000 and a15002 at 68k side.
f8ef8ff7 93 * Can be programmed as PMAR? (only seen in test mode code)
d26dc685 94 * Affects PM0 when written to?
f8ef8ff7 95 *
96 * 12. "PM4"
97 * size: 16?
98 * desc: Programmable Memory access register.
99 * This reg. is only used as PMAR. The most used PMAR by VR.
100 *
101 * 13. (unused by VR)
102 *
103 * 14. "PMC" (PMC from PMAC name from Tasco's docs)
104 * size: 32?
105 * desc: Programmable Memory access Control. Set using 2 16bit writes,
106 * first address, then mode word. After setting PMAC, PMAR sould
3554b0a4 107 * be blind accessed (ld -, PMx or ld PMx, -) to program it for
108 * reading and writing respectively.
109 * Reading the register also shifts it's state (from "waiting for
110 * address" to "waiting for mode" and back). Reads always return
111 * address related to last PMx register accressed.
689fb2c0 112 * (note: addresses do not wrap).
f8ef8ff7 113 *
114 * 15. "AL"
115 * size: 16
d4ca252d 116 * desc: Accumulator Low. 16 least significant bits of accumulator.
f8ef8ff7 117 * (normally reading acc (ld X, A) you get 16 most significant bits).
118 *
119 *
120 * There are 8 8-bit pointer registers rX. r0-r3 (ri) point to RAM0, r4-r7 (rj) point to RAM1.
5de27868 121 * They can be accessed directly, or 2 indirection levels can be used [ (rX), ((rX)) ],
122 * which work similar to * and ** operators in C, only they use different memory banks and
123 * ((rX)) also does post-increment. First indirection level (rX) accesses RAMx, second accesses
124 * program memory at address read from (rX), and increments value in (rX).
f8ef8ff7 125 *
126 * r0,r1,r2,r4,r5,r6 can be modified [ex: ldi r0, 5].
127 * 3 modifiers can be applied (optional):
5de27868 128 * + : post-increment [ex: ld a, (r0+) ]. Can be made modulo-increment by setting RPL bits in ST.
129 * - : post-decrement. Can be made modulo-decrement by setting RPL bits in ST (not sure).
130 * +!: post-increment, unaffected by RPL (probably).
131 * These are only used on 1st indirection level, so things like [ld a, ((r0+))] and [ld X, r6-]
132 * ar probably invalid.
f8ef8ff7 133 *
134 * r3 and r7 are special and can not be changed (at least Samsung samples and SVP code never do).
135 * They are fixed to the start of their RAM banks. (They are probably changeable for ssp1605+,
136 * Samsung's old DSP page claims that).
137 * 1 of these 4 modifiers must be used (short form direct addressing?):
138 * |00: RAMx[0] [ex: (r3|00), 0] (based on sample code)
139 * |01: RAMx[1]
140 * |10: RAMx[2] ? maybe 10h? accortding to Div_c_dp.sc, 2
141 * |11: RAMx[3]
142 *
143 *
144 * Instruction notes
145 *
d26dc685 146 * ld a, * doesn't affect flags! (e: A_LAW.SC, Div_c_dp.sc)
147 *
f8ef8ff7 148 * mld (rj), (ri) [, b]
149 * operation: A = 0; P = (rj) * (ri)
150 * notes: based on IIR_4B.SC sample. flags? what is b???
f8ef8ff7 151 *
152 * mpya (rj), (ri) [, b]
153 * name: multiply and add?
154 * operation: A += P; P = (rj) * (ri)
155 *
156 * mpys (rj), (ri), b
157 * name: multiply and subtract?
158 * notes: not used by VR code.
017512f2 159 *
d26dc685 160 * mod cond, op
161 * mod cond, shr does arithmetic shift
30752975 162 *
67256d4b 163 * 'ld -, AL' and probably 'ld AL, -' are for dummy assigns
164 *
30752975 165 * memory map:
166 * 000000 - 1fffff ROM, accessable by both
167 * 200000 - 2fffff unused?
d26dc685 168 * 300000 - 31ffff DRAM, both
30752975 169 * 320000 - 38ffff unused?
170 * 390000 - 3907ff IRAM. can only be accessed by ssp?
d26dc685 171 * 390000 - 39ffff similar mapping to "cell arrange" in Sega CD, 68k only?
172 * 3a0000 - 3affff similar mapping to "cell arrange" in Sega CD, a bit different
30752975 173 *
174 * 30fe02 - 0 if SVP busy, 1 if done (set by SVP, checked and cleared by 68k)
175 * 30fe06 - also sync related.
d26dc685 176 * 30fe08 - job number [1-12] for SVP. 0 means no job. Set by 68k, read-cleared by SVP.
177 *
67256d4b 178 * + figure out if 'op A, P' is 32bit (nearly sure it is)
67256d4b 179 * * does mld, mpya load their operands into X and Y?
180 * * OP simm
181 *
017512f2 182 * Assumptions in this code
183 * P is not directly writeable
5de27868 184 * flags correspond to full 32bit accumulator
185 * only Z and N status flags are emulated (others unused by SVP)
186 * modifiers for 'OP a, ri' are ignored (invalid?/not used by SVP)
f8ef8ff7 187 */
188
189#include "../../PicoInt.h"
190
017512f2 191#define u32 unsigned int
192
3554b0a4 193//#define USE_DEBUGGER
194
017512f2 195// 0
196#define rX ssp->gr[SSP_X].h
197#define rY ssp->gr[SSP_Y].h
198#define rA ssp->gr[SSP_A].h
199#define rST ssp->gr[SSP_ST].h // 4
200#define rSTACK ssp->gr[SSP_STACK].h
201#define rPC ssp->gr[SSP_PC].h
202#define rP ssp->gr[SSP_P]
203#define rPM0 ssp->gr[SSP_PM0].h // 8
204#define rPM1 ssp->gr[SSP_PM1].h
205#define rPM2 ssp->gr[SSP_PM2].h
206#define rXST ssp->gr[SSP_XST].h
207#define rPM4 ssp->gr[SSP_PM4].h // 12
208// 13
6b6a3e50 209#define rPMC ssp->gr[SSP_PMC] // will keep addr in .l, mode in .h
f8ef8ff7 210#define rAL ssp->gr[SSP_A].l
211
5de27868 212#define rA32 ssp->gr[SSP_A].v
213#define rIJ ssp->r
214
215#define IJind (((op>>6)&4)|(op&3))
216
6b6a3e50 217#ifndef EMBED_INTERPRETER
5de27868 218#define GET_PC() (PC - (unsigned short *)svp->iram_rom)
219#define GET_PPC_OFFS() ((unsigned int)PC - (unsigned int)svp->iram_rom - 2)
220#define SET_PC(d) PC = (unsigned short *)svp->iram_rom + d
6b6a3e50 221#endif
017512f2 222
223#define REG_READ(r) (((r) <= 4) ? ssp->gr[r].h : read_handlers[r]())
224#define REG_WRITE(r,d) { \
225 int r1 = r; \
5de27868 226 if (r1 >= 4) write_handlers[r1](d); \
017512f2 227 else if (r1 > 0) ssp->gr[r1].h = d; \
228}
229
5de27868 230// flags
d26dc685 231#define SSP_FLAG_L (1<<0xc)
232#define SSP_FLAG_Z (1<<0xd)
233#define SSP_FLAG_V (1<<0xe)
234#define SSP_FLAG_N (1<<0xf)
5de27868 235
236// update ZN according to 32bit ACC.
237#define UPD_ACC_ZN \
d26dc685 238 rST &= ~(SSP_FLAG_Z|SSP_FLAG_N); \
239 if (!rA32) rST |= SSP_FLAG_Z; \
240 else rST |= (rA32>>16)&SSP_FLAG_N;
5de27868 241
242// it seems SVP code never checks for L and OV, so we leave them out.
d26dc685 243// rST |= (t>>4)&SSP_FLAG_L;
67256d4b 244#define UPD_LZVN \
245 rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
246 if (!rA32) rST |= SSP_FLAG_Z; \
247 else rST |= (rA32>>16)&SSP_FLAG_N;
248
5de27868 249// standard cond processing.
250// again, only Z and N is checked, as SVP doesn't seem to use any other conds.
251#define COND_CHECK \
252 switch (op&0xf0) { \
253 case 0x00: cond = 1; break; /* always true */ \
d26dc685 254 case 0x50: cond = !((rST ^ (op<<5)) & SSP_FLAG_Z); break; /* Z matches f(?) bit */ \
255 case 0x70: cond = !((rST ^ (op<<7)) & SSP_FLAG_N); break; /* N matches f(?) bit */ \
689fb2c0 256 default:elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: unimplemented cond @ %04x", GET_PPC_OFFS()); break; \
5de27868 257 }
258
259// ops with accumulator.
260// how is low word really affected by these?
30752975 261// nearly sure 'ld A' doesn't affect flags
5de27868 262#define OP_LDA(x) \
30752975 263 ssp->gr[SSP_A].h = x
5de27868 264
67256d4b 265#define OP_LDA32(x) \
4bfc6da4 266 rA32 = x
67256d4b 267
5de27868 268#define OP_SUBA(x) { \
4bfc6da4 269 rA32 -= (x) << 16; \
270 UPD_LZVN \
5de27868 271}
272
67256d4b 273#define OP_SUBA32(x) { \
4bfc6da4 274 rA32 -= (x); \
67256d4b 275 UPD_LZVN \
276}
277
5de27868 278#define OP_CMPA(x) { \
4bfc6da4 279 u32 t = rA32 - ((x) << 16); \
280 rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
281 if (!t) rST |= SSP_FLAG_Z; \
282 else rST |= (t>>16)&SSP_FLAG_N; \
5de27868 283}
284
67256d4b 285#define OP_CMPA32(x) { \
4bfc6da4 286 u32 t = rA32 - (x); \
67256d4b 287 rST &= ~(SSP_FLAG_L|SSP_FLAG_Z|SSP_FLAG_V|SSP_FLAG_N); \
288 if (!t) rST |= SSP_FLAG_Z; \
289 else rST |= (t>>16)&SSP_FLAG_N; \
290}
291
5de27868 292#define OP_ADDA(x) { \
4bfc6da4 293 rA32 += (x) << 16; \
294 UPD_LZVN \
5de27868 295}
296
67256d4b 297#define OP_ADDA32(x) { \
4bfc6da4 298 rA32 += (x); \
67256d4b 299 UPD_LZVN \
300}
301
5de27868 302#define OP_ANDA(x) \
4bfc6da4 303 rA32 &= (x) << 16; \
5de27868 304 UPD_ACC_ZN
305
67256d4b 306#define OP_ANDA32(x) \
4bfc6da4 307 rA32 &= (x); \
67256d4b 308 UPD_ACC_ZN
309
5de27868 310#define OP_ORA(x) \
4bfc6da4 311 rA32 |= (x) << 16; \
5de27868 312 UPD_ACC_ZN
313
67256d4b 314#define OP_ORA32(x) \
4bfc6da4 315 rA32 |= (x); \
67256d4b 316 UPD_ACC_ZN
317
5de27868 318#define OP_EORA(x) \
4bfc6da4 319 rA32 ^= (x) << 16; \
5de27868 320 UPD_ACC_ZN
321
67256d4b 322#define OP_EORA32(x) \
4bfc6da4 323 rA32 ^= (x); \
67256d4b 324 UPD_ACC_ZN
325
326
327#define OP_CHECK32(OP) \
328 if ((op & 0x0f) == SSP_P) { /* A <- P */ \
329 read_P(); /* update P */ \
6b6a3e50 330 OP(rP.v); \
67256d4b 331 break; \
332}
333
5de27868 334
e807ac75 335#ifndef EMBED_INTERPRETER
336static
337#endif
338ssp1601_t *ssp = NULL;
017512f2 339static unsigned short *PC;
340static int g_cycles;
3554b0a4 341
342#ifdef USE_DEBUGGER
5de27868 343static int running = 0;
30752975 344static int last_iram = 0;
3554b0a4 345#endif
12f0f94d 346#ifdef EMBED_INTERPRETER
df143b36 347static int iram_dirty = 0;
12f0f94d 348#endif
017512f2 349
350// -----------------------------------------------------
351// register i/o handlers
352
353// 0-4, 13
354static u32 read_unknown(void)
355{
3554b0a4 356 elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: unknown read @ %04x", GET_PPC_OFFS());
017512f2 357 return 0;
358}
359
360static void write_unknown(u32 d)
361{
3554b0a4 362 elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: unknown write @ %04x", GET_PPC_OFFS());
5de27868 363}
364
365// 4
366static void write_ST(u32 d)
367{
3554b0a4 368 //if ((rST ^ d) & 0x0007) elprintf(EL_SVP, "ssp RPL %i -> %i @ %04x", rST&7, d&7, GET_PPC_OFFS());
689fb2c0 369 if ((rST ^ d) & 0x0f98) elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME ST %04x -> %04x @ %04x", rST, d, GET_PPC_OFFS());
5de27868 370 rST = d;
017512f2 371}
372
373// 5
374static u32 read_STACK(void)
375{
5de27868 376 --rSTACK;
377 if ((short)rSTACK < 0) {
378 rSTACK = 5;
3554b0a4 379 elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: stack underflow! (%i) @ %04x", rSTACK, GET_PPC_OFFS());
5de27868 380 }
381 return ssp->stack[rSTACK];
017512f2 382}
383
384static void write_STACK(u32 d)
385{
5de27868 386 if (rSTACK >= 6) {
3554b0a4 387 elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: stack overflow! (%i) @ %04x", rSTACK, GET_PPC_OFFS());
5de27868 388 rSTACK = 0;
389 }
390 ssp->stack[rSTACK++] = d;
017512f2 391}
392
393// 6
394static u32 read_PC(void)
395{
396 return GET_PC();
397}
398
399static void write_PC(u32 d)
400{
401 SET_PC(d);
402 g_cycles--;
403}
404
405// 7
406static u32 read_P(void)
407{
4fd5325d 408 int m1 = (signed short)rX;
409 int m2 = (signed short)rY;
3554b0a4 410 rP.v = (m1 * m2 * 2);
017512f2 411 return rP.h;
412}
413
5de27868 414// -----------------------------------------------------
415
3554b0a4 416static int get_inc(int mode)
5de27868 417{
3554b0a4 418 int inc = (mode >> 11) & 7;
419 if (inc != 0) {
420 if (inc != 7) inc--;
6b6a3e50 421 inc = 1 << inc; // 0 1 2 4 8 16 32 128
3554b0a4 422 if (mode & 0x8000) inc = -inc; // decrement mode
423 }
424 return inc;
5de27868 425}
426
d26dc685 427#define overwite_write(dst, d) \
428{ \
429 if (d & 0xf000) { dst &= ~0xf000; dst |= d & 0xf000; } \
430 if (d & 0x0f00) { dst &= ~0x0f00; dst |= d & 0x0f00; } \
431 if (d & 0x00f0) { dst &= ~0x00f0; dst |= d & 0x00f0; } \
432 if (d & 0x000f) { dst &= ~0x000f; dst |= d & 0x000f; } \
433}
434
017512f2 435static u32 pm_io(int reg, int write, u32 d)
436{
67256d4b 437 if (ssp->emu_status & SSP_PMC_SET)
438 {
439 // this MUST be blind r or w
440 if ((*(PC-1) & 0xff0f) && (*(PC-1) & 0xfff0)) {
3554b0a4 441 elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: tried to set PM%i (%c) with non-blind i/o %08x @ %04x",
67256d4b 442 reg, write ? 'w' : 'r', rPMC.v, GET_PPC_OFFS());
443 ssp->emu_status &= ~SSP_PMC_SET;
444 return 0;
445 }
5de27868 446 elprintf(EL_SVP, "PM%i (%c) set to %08x @ %04x", reg, write ? 'w' : 'r', rPMC.v, GET_PPC_OFFS());
017512f2 447 ssp->pmac_read[write ? reg + 6 : reg] = rPMC.v;
448 ssp->emu_status &= ~SSP_PMC_SET;
12f0f94d 449 if ((rPMC.v & 0x7fffff) == 0x1c8000 || (rPMC.v & 0x7fffff) == 0x1c8240) {
3554b0a4 450 elprintf(EL_SVP, "ssp IRAM copy from %06x", (ssp->RAM1[0]-1)<<1);
451#ifdef USE_DEBUGGER
30752975 452 last_iram = (ssp->RAM1[0]-1)<<1;
3554b0a4 453#endif
30752975 454 }
017512f2 455 return 0;
456 }
457
5de27868 458 // just in case
67256d4b 459 if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
3554b0a4 460 elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: PM%i (%c) with only addr set @ %04x",
67256d4b 461 reg, write ? 'w' : 'r', GET_PPC_OFFS());
462 ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
463 }
5de27868 464
5de27868 465 if (reg == 4 || (rST & 0x60))
466 {
30752975 467 #define CADDR ((((mode<<16)&0x7f0000)|addr)<<1)
d26dc685 468 unsigned short *dram = (unsigned short *)svp->dram;
5de27868 469 if (write)
470 {
6b6a3e50 471 int mode = ssp->pmac_write[reg]>>16;
472 int addr = ssp->pmac_write[reg]&0xffff;
3554b0a4 473 if ((mode & 0xb800) == 0xb800)
689fb2c0 474 elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: mode %04x", mode);
3554b0a4 475 if ((mode & 0x43ff) == 0x0018) // DRAM
476 {
477 int inc = get_inc(mode);
478 elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (inc %i, ovrw %i)",
6b6a3e50 479 reg, CADDR, d, inc, (mode>>10)&1);
3554b0a4 480 if (mode & 0x0400) {
481 overwite_write(dram[addr], d);
482 } else dram[addr] = d;
483 ssp->pmac_write[reg] += inc;
484 }
485 else if ((mode & 0xfbff) == 0x4018) // DRAM, cell inc
486 {
487 elprintf(EL_SVP, "ssp PM%i DRAM w [%06x] %04x (cell inc, ovrw %i) @ %04x",
488 reg, CADDR, d, (mode>>10)&1, GET_PPC_OFFS());
489 if (mode & 0x0400) {
490 overwite_write(dram[addr], d);
491 } else dram[addr] = d;
6b6a3e50 492 ssp->pmac_write[reg] += (addr&1) ? 31 : 1;
3554b0a4 493 }
494 else if ((mode & 0x47ff) == 0x001c) // IRAM
495 {
496 int inc = get_inc(mode);
497 if ((addr&0xfc00) != 0x8000)
498 elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: invalid IRAM addr: %04x", addr<<1);
6b6a3e50 499 elprintf(EL_SVP, "ssp IRAM w [%06x] %04x (inc %i)", (addr<<1)&0x7ff, d, inc);
3554b0a4 500 ((unsigned short *)svp->iram_rom)[addr&0x3ff] = d;
501 ssp->pmac_write[reg] += inc;
892b1dd2 502#ifdef EMBED_INTERPRETER
503 iram_dirty = 1;
504#endif
3554b0a4 505 }
506 else
507 {
508 elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: PM%i unhandled write mode %04x, [%06x] %04x @ %04x",
509 reg, mode, CADDR, d, GET_PPC_OFFS());
5de27868 510 }
511 }
512 else
513 {
6b6a3e50 514 int mode = ssp->pmac_read[reg]>>16;
515 int addr = ssp->pmac_read[reg]&0xffff;
3554b0a4 516 if ((mode & 0xfff0) == 0x0800) // ROM, inc 1, verified to be correct
517 {
d26dc685 518 elprintf(EL_SVP, "ssp ROM r [%06x] %04x", CADDR,
519 ((unsigned short *)Pico.rom)[addr|((mode&0xf)<<16)]);
6b6a3e50 520 ssp->pmac_read[reg] += 1;
d26dc685 521 d = ((unsigned short *)Pico.rom)[addr|((mode&0xf)<<16)];
d26dc685 522 }
3554b0a4 523 else if ((mode & 0x47ff) == 0x0018) // DRAM
524 {
525 int inc = get_inc(mode);
6b6a3e50 526 elprintf(EL_SVP, "ssp PM%i DRAM r [%06x] %04x (inc %i)", reg, CADDR, dram[addr]);
3554b0a4 527 d = dram[addr];
528 ssp->pmac_read[reg] += inc;
529 }
530 else
531 {
532 elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: PM%i unhandled read mode %04x, [%06x] @ %04x",
533 reg, mode, CADDR, GET_PPC_OFFS());
534 d = 0;
5de27868 535 }
536 }
30752975 537
538 // PMC value corresponds to last PMR accessed (not sure).
539 rPMC.v = ssp->pmac_read[write ? reg + 6 : reg];
540
541 return d;
017512f2 542 }
543
544 return (u32)-1;
545}
546
547// 8
548static u32 read_PM0(void)
549{
550 u32 d = pm_io(0, 0, 0);
551 if (d != (u32)-1) return d;
67256d4b 552 elprintf(EL_SVP, "PM0 raw r %04x @ %04x", rPM0, GET_PPC_OFFS());
d26dc685 553 d = rPM0;
726bbb3e 554#ifndef EMBED_INTERPRETER
d26dc685 555 if (!(d & 2) && (GET_PPC_OFFS() == 0x800 || GET_PPC_OFFS() == 0x1851E)) {
556 ssp->emu_status |= SSP_WAIT_PM0; elprintf(EL_SVP, "det TIGHT loop: PM0");
557 }
726bbb3e 558#endif
d26dc685 559 rPM0 &= ~2; // ?
560 return d;
017512f2 561}
562
563static void write_PM0(u32 d)
564{
565 u32 r = pm_io(0, 1, d);
566 if (r != (u32)-1) return;
5de27868 567 elprintf(EL_SVP, "PM0 raw w %04x @ %04x", d, GET_PPC_OFFS());
d26dc685 568 rPM0 = d;
017512f2 569}
570
571// 9
572static u32 read_PM1(void)
573{
574 u32 d = pm_io(1, 0, 0);
575 if (d != (u32)-1) return d;
576 // can be removed?
d4ca252d 577 elprintf(EL_SVP|EL_ANOMALY, "PM1 raw r %04x @ %04x", rPM1, GET_PPC_OFFS());
5de27868 578 return rPM1;
017512f2 579}
580
581static void write_PM1(u32 d)
582{
583 u32 r = pm_io(1, 1, d);
584 if (r != (u32)-1) return;
585 // can be removed?
d4ca252d 586 elprintf(EL_SVP|EL_ANOMALY, "PM1 raw w %04x @ %04x", d, GET_PPC_OFFS());
5de27868 587 rPM1 = d;
017512f2 588}
589
590// 10
591static u32 read_PM2(void)
592{
593 u32 d = pm_io(2, 0, 0);
594 if (d != (u32)-1) return d;
595 // can be removed?
d4ca252d 596 elprintf(EL_SVP|EL_ANOMALY, "PM2 raw r %04x @ %04x", rPM2, GET_PPC_OFFS());
5de27868 597 return rPM2;
017512f2 598}
599
600static void write_PM2(u32 d)
601{
602 u32 r = pm_io(2, 1, d);
603 if (r != (u32)-1) return;
604 // can be removed?
d4ca252d 605 elprintf(EL_SVP|EL_ANOMALY, "PM2 raw w %04x @ %04x", d, GET_PPC_OFFS());
5de27868 606 rPM2 = d;
017512f2 607}
608
609// 11
610static u32 read_XST(void)
611{
612 // can be removed?
613 u32 d = pm_io(3, 0, 0);
614 if (d != (u32)-1) return d;
615
5de27868 616 elprintf(EL_SVP, "XST raw r %04x @ %04x", rXST, GET_PPC_OFFS());
617 return rXST;
017512f2 618}
f8ef8ff7 619
017512f2 620static void write_XST(u32 d)
f8ef8ff7 621{
017512f2 622 // can be removed?
623 u32 r = pm_io(3, 1, d);
624 if (r != (u32)-1) return;
625
5de27868 626 elprintf(EL_SVP, "XST raw w %04x @ %04x", d, GET_PPC_OFFS());
d26dc685 627 rPM0 |= 1;
5de27868 628 rXST = d;
017512f2 629}
630
631// 12
632static u32 read_PM4(void)
633{
634 u32 d = pm_io(4, 0, 0);
726bbb3e 635#ifndef EMBED_INTERPRETER
30752975 636 if (d == 0) {
637 switch (GET_PPC_OFFS()) {
d26dc685 638 case 0x0854: ssp->emu_status |= SSP_WAIT_30FE08; elprintf(EL_SVP, "det TIGHT loop: [30fe08]"); break;
639 case 0x4f12: ssp->emu_status |= SSP_WAIT_30FE06; elprintf(EL_SVP, "det TIGHT loop: [30fe06]"); break;
30752975 640 }
641 }
726bbb3e 642#endif
017512f2 643 if (d != (u32)-1) return d;
644 // can be removed?
d4ca252d 645 elprintf(EL_SVP|EL_ANOMALY, "PM4 raw r %04x @ %04x", rPM4, GET_PPC_OFFS());
5de27868 646 return rPM4;
017512f2 647}
648
649static void write_PM4(u32 d)
650{
651 u32 r = pm_io(4, 1, d);
652 if (r != (u32)-1) return;
653 // can be removed?
d4ca252d 654 elprintf(EL_SVP|EL_ANOMALY, "PM4 raw w %04x @ %04x", d, GET_PPC_OFFS());
5de27868 655 rPM4 = d;
017512f2 656}
657
658// 14
659static u32 read_PMC(void)
660{
6b6a3e50 661 elprintf(EL_SVP, "PMC r a %04x (st %c) @ %04x", rPMC.l,
3554b0a4 662 (ssp->emu_status & SSP_PMC_HAVE_ADDR) ? 'm' : 'a', GET_PPC_OFFS());
017512f2 663 if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
3554b0a4 664 //if (ssp->emu_status & SSP_PMC_SET)
665 // elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS());
017512f2 666 ssp->emu_status |= SSP_PMC_SET;
5de27868 667 ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
6b6a3e50 668 return ((rPMC.l << 4) & 0xfff0) | ((rPMC.l >> 4) & 0xf);
017512f2 669 } else {
670 ssp->emu_status |= SSP_PMC_HAVE_ADDR;
6b6a3e50 671 return rPMC.l;
017512f2 672 }
673}
674
675static void write_PMC(u32 d)
676{
677 if (ssp->emu_status & SSP_PMC_HAVE_ADDR) {
3554b0a4 678 //if (ssp->emu_status & SSP_PMC_SET)
679 // elprintf(EL_ANOMALY|EL_SVP, "prev PMC not used @ %04x", GET_PPC_OFFS());
017512f2 680 ssp->emu_status |= SSP_PMC_SET;
5de27868 681 ssp->emu_status &= ~SSP_PMC_HAVE_ADDR;
6b6a3e50 682 rPMC.h = d;
683 elprintf(EL_SVP, "PMC w m %04x @ %04x", rPMC.h, GET_PPC_OFFS());
017512f2 684 } else {
685 ssp->emu_status |= SSP_PMC_HAVE_ADDR;
6b6a3e50 686 rPMC.l = d;
687 elprintf(EL_SVP, "PMC w a %04x @ %04x", rPMC.l, GET_PPC_OFFS());
017512f2 688 }
689}
690
691// 15
692static u32 read_AL(void)
693{
67256d4b 694 if (*(PC-1) == 0x000f) {
689fb2c0 695 elprintf(EL_SVP, "ssp dummy PM assign %08x @ %04x", rPMC.v, GET_PPC_OFFS());
67256d4b 696 ssp->emu_status &= ~(SSP_PMC_SET|SSP_PMC_HAVE_ADDR); // ?
67256d4b 697 }
017512f2 698 return rAL;
699}
700
701static void write_AL(u32 d)
702{
703 rAL = d;
704}
705
706
707typedef u32 (*read_func_t)(void);
708typedef void (*write_func_t)(u32 d);
709
710static read_func_t read_handlers[16] =
711{
712 read_unknown, read_unknown, read_unknown, read_unknown, // -, X, Y, A
713 read_unknown, // 4 ST
714 read_STACK,
715 read_PC,
716 read_P,
717 read_PM0, // 8
718 read_PM1,
719 read_PM2,
720 read_XST,
721 read_PM4, // 12
722 read_unknown, // 13 gr13
723 read_PMC,
724 read_AL
725};
726
727static write_func_t write_handlers[16] =
728{
729 write_unknown, write_unknown, write_unknown, write_unknown, // -, X, Y, A
5de27868 730// write_unknown, // 4 ST
731 write_ST, // 4 ST (debug hook)
017512f2 732 write_STACK,
733 write_PC,
734 write_unknown, // 7 P
735 write_PM0, // 8
736 write_PM1,
737 write_PM2,
738 write_XST,
739 write_PM4, // 12
740 write_unknown, // 13 gr13
741 write_PMC,
742 write_AL
743};
744
5de27868 745// -----------------------------------------------------
746// pointer register handlers
747
748//
749#define ptr1_read(op) ptr1_read_(op&3,(op>>6)&4,(op<<1)&0x18)
750
751static u32 ptr1_read_(int ri, int isj2, int modi3)
752{
753 //int t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
30752975 754 u32 mask, add = 0, t = ri | isj2 | modi3;
755 unsigned char *rp = NULL;
5de27868 756 switch (t)
757 {
758 // mod=0 (00)
759 case 0x00:
760 case 0x01:
761 case 0x02: return ssp->RAM0[ssp->r0[t&3]];
762 case 0x03: return ssp->RAM0[0];
763 case 0x04:
764 case 0x05:
765 case 0x06: return ssp->RAM1[ssp->r1[t&3]];
766 case 0x07: return ssp->RAM1[0];
767 // mod=1 (01), "+!"
5de27868 768 case 0x08:
5de27868 769 case 0x09:
30752975 770 case 0x0a: return ssp->RAM0[ssp->r0[t&3]++];
5de27868 771 case 0x0b: return ssp->RAM0[1];
772 case 0x0c:
5de27868 773 case 0x0d:
30752975 774 case 0x0e: return ssp->RAM1[ssp->r1[t&3]++];
5de27868 775 case 0x0f: return ssp->RAM1[1];
776 // mod=2 (10), "-"
777 case 0x10:
778 case 0x11:
30752975 779 case 0x12: rp = &ssp->r0[t&3]; t = ssp->RAM0[*rp];
780 if (!(rST&7)) { (*rp)--; return t; }
781 add = -1; goto modulo;
5de27868 782 case 0x13: return ssp->RAM0[2];
783 case 0x14:
784 case 0x15:
30752975 785 case 0x16: rp = &ssp->r1[t&3]; t = ssp->RAM1[*rp];
786 if (!(rST&7)) { (*rp)--; return t; }
787 add = -1; goto modulo;
5de27868 788 case 0x17: return ssp->RAM1[2];
30752975 789 // mod=3 (11), "+"
790 case 0x18:
791 case 0x19:
792 case 0x1a: rp = &ssp->r0[t&3]; t = ssp->RAM0[*rp];
793 if (!(rST&7)) { (*rp)++; return t; }
794 add = 1; goto modulo;
5de27868 795 case 0x1b: return ssp->RAM0[3];
30752975 796 case 0x1c:
797 case 0x1d:
798 case 0x1e: rp = &ssp->r1[t&3]; t = ssp->RAM1[*rp];
799 if (!(rST&7)) { (*rp)++; return t; }
800 add = 1; goto modulo;
5de27868 801 case 0x1f: return ssp->RAM1[3];
802 }
803
804 return 0;
30752975 805
806modulo:
807 mask = (1 << (rST&7)) - 1;
808 *rp = (*rp & ~mask) | ((*rp + add) & mask);
809 return t;
5de27868 810}
811
812static void ptr1_write(int op, u32 d)
813{
814 int t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
815 switch (t)
816 {
817 // mod=0 (00)
818 case 0x00:
819 case 0x01:
820 case 0x02: ssp->RAM0[ssp->r0[t&3]] = d; return;
821 case 0x03: ssp->RAM0[0] = d; return;
822 case 0x04:
823 case 0x05:
824 case 0x06: ssp->RAM1[ssp->r1[t&3]] = d; return;
825 case 0x07: ssp->RAM1[0] = d; return;
826 // mod=1 (01), "+!"
827 // mod=3, "+"
828 case 0x08:
829 case 0x18:
830 case 0x09:
831 case 0x19:
832 case 0x0a:
833 case 0x1a: ssp->RAM0[ssp->r0[t&3]++] = d; return;
834 case 0x0b: ssp->RAM0[1] = d; return;
835 case 0x0c:
836 case 0x1c:
837 case 0x0d:
838 case 0x1d:
839 case 0x0e:
840 case 0x1e: ssp->RAM1[ssp->r1[t&3]++] = d; return;
841 case 0x0f: ssp->RAM1[1] = d; return;
842 // mod=2 (10), "-"
843 case 0x10:
844 case 0x11:
845 case 0x12: ssp->RAM0[ssp->r0[t&3]--] = d; return;
846 case 0x13: ssp->RAM0[2] = d; return;
847 case 0x14:
848 case 0x15:
849 case 0x16: ssp->RAM1[ssp->r1[t&3]--] = d; return;
850 case 0x17: ssp->RAM1[2] = d; return;
851 // mod=3 (11)
852 case 0x1b: ssp->RAM0[3] = d; return;
853 case 0x1f: ssp->RAM1[3] = d; return;
854 }
855}
856
857static u32 ptr2_read(int op)
858{
859 int mv = 0, t = (op&3) | ((op>>6)&4) | ((op<<1)&0x18);
860 switch (t)
861 {
862 // mod=0 (00)
863 case 0x00:
864 case 0x01:
865 case 0x02: mv = ssp->RAM0[ssp->r0[t&3]]++; break;
866 case 0x03: mv = ssp->RAM0[0]++; break;
867 case 0x04:
868 case 0x05:
869 case 0x06: mv = ssp->RAM1[ssp->r1[t&3]]++; break;
870 case 0x07: mv = ssp->RAM1[0]++; break;
871 // mod=1 (01)
872 case 0x0b: mv = ssp->RAM0[1]++; break;
873 case 0x0f: mv = ssp->RAM1[1]++; break;
874 // mod=2 (10)
875 case 0x13: mv = ssp->RAM0[2]++; break;
876 case 0x17: mv = ssp->RAM1[2]++; break;
877 // mod=3 (11)
878 case 0x1b: mv = ssp->RAM0[3]++; break;
879 case 0x1f: mv = ssp->RAM1[3]++; break;
30752975 880 default: elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: invalid mod in ((rX))? @ %04x", GET_PPC_OFFS());
5de27868 881 return 0;
882 }
883
884 return ((unsigned short *)svp->iram_rom)[mv];
885}
886
887
888// -----------------------------------------------------
889
df143b36 890#if defined(USE_DEBUGGER) //|| defined(EMBED_INTERPRETER)
726bbb3e 891static void debug_dump2file(const char *fname, void *mem, int len)
892{
893 FILE *f = fopen(fname, "wb");
894 unsigned short *p = mem;
895 int i;
896 if (f) {
897 for (i = 0; i < len/2; i++) p[i] = (p[i]<<8) | (p[i]>>8);
898 fwrite(mem, 1, len, f);
899 fclose(f);
900 for (i = 0; i < len/2; i++) p[i] = (p[i]<<8) | (p[i]>>8);
901 printf("dumped to %s\n", fname);
902 }
903 else
904 printf("dump failed\n");
905}
906#endif
907
3554b0a4 908#ifdef USE_DEBUGGER
5de27868 909static void debug_dump(void)
f8ef8ff7 910{
5de27868 911 printf("GR0: %04x X: %04x Y: %04x A: %08x\n", ssp->gr[SSP_GR0].h, rX, rY, ssp->gr[SSP_A].v);
6b6a3e50 912 printf("PC: %04x (%04x) P: %08x\n", GET_PC(), GET_PC() << 1, rP.v);
5de27868 913 printf("PM0: %04x PM1: %04x PM2: %04x\n", rPM0, rPM1, rPM2);
6b6a3e50 914 printf("XST: %04x PM4: %04x PMC: %08x\n", rXST, rPM4, rPMC.v);
d26dc685 915 printf(" ST: %04x %c%c%c%c, GP0_0 %i, GP0_1 %i\n", rST, rST&SSP_FLAG_N?'N':'n', rST&SSP_FLAG_V?'V':'v',
916 rST&SSP_FLAG_Z?'Z':'z', rST&SSP_FLAG_L?'L':'l', (rST>>5)&1, (rST>>6)&1);
5de27868 917 printf("STACK: %i %04x %04x %04x %04x %04x %04x\n", rSTACK, ssp->stack[0], ssp->stack[1],
918 ssp->stack[2], ssp->stack[3], ssp->stack[4], ssp->stack[5]);
919 printf("r0-r2: %02x %02x %02x r4-r6: %02x %02x %02x\n", rIJ[0], rIJ[1], rIJ[2], rIJ[4], rIJ[5], rIJ[6]);
920 elprintf(EL_SVP, "cycles: %i, emu_status: %x", g_cycles, ssp->emu_status);
921}
f8ef8ff7 922
5de27868 923static void debug_dump_mem(void)
924{
925 int h, i;
926 printf("RAM0\n");
927 for (h = 0; h < 32; h++)
928 {
929 if (h == 16) printf("RAM1\n");
930 printf("%03x:", h*16);
931 for (i = 0; i < 16; i++)
932 printf(" %04x", ssp->RAM[h*16+i]);
933 printf("\n");
934 }
935}
936
937static int bpts[10] = { 0, };
938
939static void debug(unsigned int pc, unsigned int op)
940{
941 static char buffo[64] = {0,};
942 char buff[64] = {0,};
943 int i;
944
945 if (running) {
946 for (i = 0; i < 10; i++)
947 if (pc != 0 && bpts[i] == pc) {
948 printf("breakpoint %i\n", i);
949 running = 0;
950 break;
951 }
952 }
953 if (running) return;
954
955 printf("%04x (%02x) @ %04x\n", op, op >> 9, pc<<1);
956
957 while (1)
958 {
959 printf("dbg> ");
960 fflush(stdout);
961 fgets(buff, sizeof(buff), stdin);
962 if (buff[0] == '\n') strcpy(buff, buffo);
963 else strcpy(buffo, buff);
964
965 switch (buff[0]) {
966 case 0: exit(0);
967 case 'c':
968 case 'r': running = 1; return;
969 case 's':
970 case 'n': return;
971 case 'x': debug_dump(); break;
972 case 'm': debug_dump_mem(); break;
973 case 'b': {
974 char *baddr = buff + 2;
975 i = 0;
976 if (buff[3] == ' ') { i = buff[2] - '0'; baddr = buff + 4; }
977 bpts[i] = strtol(baddr, NULL, 16) >> 1;
978 printf("breakpoint %i set @ %04x\n", i, bpts[i]<<1);
979 break;
980 }
30752975 981 case 'd':
982 sprintf(buff, "iramrom_%04x.bin", last_iram);
983 debug_dump2file(buff, svp->iram_rom, sizeof(svp->iram_rom));
984 debug_dump2file("dram.bin", svp->dram, sizeof(svp->dram));
5de27868 985 break;
5de27868 986 default: printf("unknown command\n"); break;
987 }
988 }
989}
3554b0a4 990#endif // USE_DEBUGGER
991
5de27868 992
6b6a3e50 993void ssp1601_reset(ssp1601_t *l_ssp)
994{
995 ssp = l_ssp;
996 ssp->emu_status = 0;
997 ssp->gr[SSP_GR0].v = 0xffff0000;
998 rPC = 0x400;
999 rSTACK = 0; // ? using ascending stack
1000 rST = 0;
1001}
1002
1003
5de27868 1004void ssp1601_run(int cycles)
1005{
726bbb3e 1006#ifndef EMBED_INTERPRETER
017512f2 1007 SET_PC(rPC);
726bbb3e 1008#endif
017512f2 1009 g_cycles = cycles;
f8ef8ff7 1010
d26dc685 1011 while (g_cycles > 0 && !(ssp->emu_status & SSP_WAIT_MASK))
f8ef8ff7 1012 {
5de27868 1013 int op;
1014 u32 tmpv;
1015
1016 op = *PC++;
3554b0a4 1017#ifdef USE_DEBUGGER
5de27868 1018 debug(GET_PC()-1, op);
3554b0a4 1019#endif
f8ef8ff7 1020 switch (op >> 9)
1021 {
1022 // ld d, s
5de27868 1023 case 0x00:
f8ef8ff7 1024 if (op == 0) break; // nop
017512f2 1025 if (op == ((SSP_A<<4)|SSP_P)) { // A <- P
1026 // not sure. MAME claims that only hi word is transfered.
1027 read_P(); // update P
6b6a3e50 1028 rA32 = rP.v;
f8ef8ff7 1029 }
5de27868 1030 else
f8ef8ff7 1031 {
5de27868 1032 tmpv = REG_READ(op & 0x0f);
1033 REG_WRITE((op & 0xf0) >> 4, tmpv);
1034 }
1035 break;
1036
1037 // ld d, (ri)
1038 case 0x01: tmpv = ptr1_read(op); REG_WRITE((op & 0xf0) >> 4, tmpv); break;
1039
1040 // ld (ri), s
1041 case 0x02: tmpv = REG_READ((op & 0xf0) >> 4); ptr1_write(op, tmpv); break;
1042
1043 // ldi d, imm
1044 case 0x04: tmpv = *PC++; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
1045
1046 // ld d, ((ri))
1047 case 0x05: tmpv = ptr2_read(op); REG_WRITE((op & 0xf0) >> 4, tmpv); break;
1048
1049 // ldi (ri), imm
1050 case 0x06: tmpv = *PC++; ptr1_write(op, tmpv); break;
1051
1052 // ld adr, a
1053 case 0x07: ssp->RAM[op & 0x1ff] = rA; break;
1054
1055 // ld d, ri
1056 case 0x09: tmpv = rIJ[(op&3)|((op>>6)&4)]; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
1057
1058 // ld ri, s
1059 case 0x0a: rIJ[(op&3)|((op>>6)&4)] = REG_READ((op & 0xf0) >> 4); break;
1060
1061 // ldi ri, simm
1062 case 0x0c:
1063 case 0x0d:
1064 case 0x0e:
1065 case 0x0f: rIJ[(op>>8)&7] = op; break;
1066
1067 // call cond, addr
1068 case 0x24: {
1069 int cond = 0;
1070 COND_CHECK
1071 if (cond) { int new_PC = *PC++; write_STACK(GET_PC()); write_PC(new_PC); }
1072 else PC++;
1073 break;
1074 }
1075
1076 // ld d, (a)
1077 case 0x25: tmpv = ((unsigned short *)svp->iram_rom)[rA]; REG_WRITE((op & 0xf0) >> 4, tmpv); break;
1078
1079 // bra cond, addr
1080 case 0x26: {
1081 int cond = 0;
1082 COND_CHECK
1083 if (cond) { int new_PC = *PC++; write_PC(new_PC); }
1084 else PC++;
1085 break;
1086 }
1087
1088 // mod cond, op
1089 case 0x48: {
1090 int cond = 0;
1091 COND_CHECK
1092 if (cond) {
1093 switch (op & 7) {
d26dc685 1094 case 2: rA32 = (signed int)rA32 >> 1; break; // shr (arithmetic)
5de27868 1095 case 3: rA32 <<= 1; break; // shl
d26dc685 1096 case 6: rA32 = -(signed int)rA32; break; // neg
1097 case 7: if ((int)rA32 < 0) rA32 = -(signed int)rA32; break; // abs
689fb2c0 1098 default: elprintf(EL_SVP|EL_ANOMALY, "ssp FIXME: unhandled mod %i @ %04x",
1099 op&7, GET_PPC_OFFS());
5de27868 1100 }
30752975 1101 UPD_ACC_ZN // ?
f8ef8ff7 1102 }
1103 break;
5de27868 1104 }
1105
689fb2c0 1106 // mpys?
30752975 1107 case 0x1b:
30752975 1108 read_P(); // update P
6b6a3e50 1109 rA32 -= rP.v; // maybe only upper word?
689fb2c0 1110 UPD_ACC_ZN // there checking flags after this
30752975 1111 rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
1112 rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
3554b0a4 1113 break;
1114
5de27868 1115 // mpya (rj), (ri), b
1116 case 0x4b:
5de27868 1117 read_P(); // update P
6b6a3e50 1118 rA32 += rP.v; // confirmed to be 32bit
d26dc685 1119 UPD_ACC_ZN // ?
5de27868 1120 rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
1121 rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
1122 break;
1123
1124 // mld (rj), (ri), b
1125 case 0x5b:
3554b0a4 1126 rA32 = 0;
4bfc6da4 1127 rST &= 0x0fff; // ?
5de27868 1128 rX = ptr1_read_(op&3, 0, (op<<1)&0x18); // ri (maybe rj?)
1129 rY = ptr1_read_((op>>4)&3, 4, (op>>3)&0x18); // rj
1130 break;
1131
1132 // OP a, s
67256d4b 1133 case 0x10: OP_CHECK32(OP_SUBA32); tmpv = REG_READ(op & 0x0f); OP_SUBA(tmpv); break;
1134 case 0x30: OP_CHECK32(OP_CMPA32); tmpv = REG_READ(op & 0x0f); OP_CMPA(tmpv); break;
1135 case 0x40: OP_CHECK32(OP_ADDA32); tmpv = REG_READ(op & 0x0f); OP_ADDA(tmpv); break;
1136 case 0x50: OP_CHECK32(OP_ANDA32); tmpv = REG_READ(op & 0x0f); OP_ANDA(tmpv); break;
1137 case 0x60: OP_CHECK32(OP_ORA32 ); tmpv = REG_READ(op & 0x0f); OP_ORA (tmpv); break;
1138 case 0x70: OP_CHECK32(OP_EORA32); tmpv = REG_READ(op & 0x0f); OP_EORA(tmpv); break;
5de27868 1139
1140 // OP a, (ri)
1141 case 0x11: tmpv = ptr1_read(op); OP_SUBA(tmpv); break;
1142 case 0x31: tmpv = ptr1_read(op); OP_CMPA(tmpv); break;
1143 case 0x41: tmpv = ptr1_read(op); OP_ADDA(tmpv); break;
1144 case 0x51: tmpv = ptr1_read(op); OP_ANDA(tmpv); break;
1145 case 0x61: tmpv = ptr1_read(op); OP_ORA (tmpv); break;
1146 case 0x71: tmpv = ptr1_read(op); OP_EORA(tmpv); break;
1147
1148 // OP a, adr
1149 case 0x03: tmpv = ssp->RAM[op & 0x1ff]; OP_LDA (tmpv); break;
1150 case 0x13: tmpv = ssp->RAM[op & 0x1ff]; OP_SUBA(tmpv); break;
1151 case 0x33: tmpv = ssp->RAM[op & 0x1ff]; OP_CMPA(tmpv); break;
1152 case 0x43: tmpv = ssp->RAM[op & 0x1ff]; OP_ADDA(tmpv); break;
1153 case 0x53: tmpv = ssp->RAM[op & 0x1ff]; OP_ANDA(tmpv); break;
1154 case 0x63: tmpv = ssp->RAM[op & 0x1ff]; OP_ORA (tmpv); break;
1155 case 0x73: tmpv = ssp->RAM[op & 0x1ff]; OP_EORA(tmpv); break;
1156
1157 // OP a, imm
1158 case 0x14: tmpv = *PC++; OP_SUBA(tmpv); break;
1159 case 0x34: tmpv = *PC++; OP_CMPA(tmpv); break;
1160 case 0x44: tmpv = *PC++; OP_ADDA(tmpv); break;
1161 case 0x54: tmpv = *PC++; OP_ANDA(tmpv); break;
1162 case 0x64: tmpv = *PC++; OP_ORA (tmpv); break;
1163 case 0x74: tmpv = *PC++; OP_EORA(tmpv); break;
1164
1165 // OP a, ((ri))
1166 case 0x15: tmpv = ptr2_read(op); OP_SUBA(tmpv); break;
1167 case 0x35: tmpv = ptr2_read(op); OP_CMPA(tmpv); break;
1168 case 0x45: tmpv = ptr2_read(op); OP_ADDA(tmpv); break;
1169 case 0x55: tmpv = ptr2_read(op); OP_ANDA(tmpv); break;
1170 case 0x65: tmpv = ptr2_read(op); OP_ORA (tmpv); break;
1171 case 0x75: tmpv = ptr2_read(op); OP_EORA(tmpv); break;
1172
1173 // OP a, ri
1174 case 0x19: tmpv = rIJ[IJind]; OP_SUBA(tmpv); break;
1175 case 0x39: tmpv = rIJ[IJind]; OP_CMPA(tmpv); break;
1176 case 0x49: tmpv = rIJ[IJind]; OP_ADDA(tmpv); break;
1177 case 0x59: tmpv = rIJ[IJind]; OP_ANDA(tmpv); break;
1178 case 0x69: tmpv = rIJ[IJind]; OP_ORA (tmpv); break;
1179 case 0x79: tmpv = rIJ[IJind]; OP_EORA(tmpv); break;
1180
1181 // OP simm
6b6a3e50 1182 case 0x1c: OP_SUBA(op & 0xff); break;
1183 case 0x3c: OP_CMPA(op & 0xff); break;
1184 case 0x4c: OP_ADDA(op & 0xff); break;
5de27868 1185 // MAME code only does LSB of top word, but this looks wrong to me.
6b6a3e50 1186 case 0x5c: OP_ANDA(op & 0xff); break;
1187 case 0x6c: OP_ORA (op & 0xff); break;
1188 case 0x7c: OP_EORA(op & 0xff); break;
f8ef8ff7 1189
726bbb3e 1190#ifdef EMBED_INTERPRETER
1191 case 0x7f: goto interp_end; /* pseudo op */
1192#endif
f8ef8ff7 1193 default:
3554b0a4 1194 elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME unhandled op %04x @ %04x", op, GET_PPC_OFFS());
017512f2 1195 break;
f8ef8ff7 1196 }
017512f2 1197 g_cycles--;
f8ef8ff7 1198 }
1199
1200 rPC = GET_PC();
726bbb3e 1201#ifdef EMBED_INTERPRETER
1202interp_end:
1203#endif
1204 read_P(); // update P
017512f2 1205
1206 if (ssp->gr[SSP_GR0].v != 0xffff0000)
3554b0a4 1207 elprintf(EL_ANOMALY|EL_SVP, "ssp FIXME: REG 0 corruption! %08x", ssp->gr[SSP_GR0].v);
f8ef8ff7 1208}
1209
fast MegaDrive/MegaCD/32X emulator