[picodrive.git] / Pico / carthw / svp / stub_arm.S

@ vim:filetype=armasm

.if 0
#include "compiler.h"
.endif

.global tcache

.global flush_inval_caches
.global regfile_load
.global regfile_store
.global ssp_hle_800

@ translation cache buffer
.text
.align 12 @ 4096
.size tcache, TCACHE_SIZE
tcache:
 .space TCACHE_SIZE


.text
.align 2


flush_inval_caches:
    mov     r2, #0x0  @ must be 0
    swi     0x9f0002
    bx      lr


@       SSP_GR0, SSP_X,     SSP_Y,   SSP_A,
@       SSP_ST,  SSP_STACK, SSP_PC,  SSP_P,
@       SSP_PM0, SSP_PM1,   SSP_PM2, SSP_XST,
@       SSP_PM4, SSP_gr13,  SSP_PMC, SSP_AL

@ register map:
@ r4:  XXYY
@ r5:  A
@ r6:  STACK and emu flags: sss0 * .uu. .lll NZCV (NZCV is PSR bits from ARM)
@ r7:  SSP context
@ r8:  r0-r2 (.210)
@ r9:  r4-r6 (.654)
@ r10: P
@ r11: cycles

@ trashes r2,r3

regfile_load:
    ldr     r7, =ssp
    ldr     r7, [r7]
    add     r2, r7, #0x400
    add     r2, r2, #4
    ldmia   r2, {r3,r4,r5,r6,r8}
    mov     r3, r3, lsr #16
    mov     r3, r3, lsl #16
    orr     r4, r3, r4, lsr #16         @ XXYY

    and     r8, r8, #0x0f0000
    mov     r8, r8, lsl #13             @ sss0 *
    and     r9, r6, #0x670000
    tst     r6,     #0x80000000
    orrne   r8, r8, #0x8
    tst     r6,     #0x20000000
    orrne   r8, r8, #0x4                @ sss0 *           NZ..
    orr     r6, r8, r9, lsr #12         @ sss0 * .uu. .lll NZ..

    ldr     r8, [r7, #0x440]            @ r0-r2
    ldr     r9, [r7, #0x444]            @ r4-r6
    ldr     r10,[r7, #(0x400+7*4)]      @ P
    bx      lr


regfile_store:
    str     r10,[r7, #(0x400+7*4)]      @ P
    str     r8, [r7, #0x440]            @ r0-r2
    str     r9, [r7, #0x444]            @ r4-r6

    mov     r9, r6, lsr #13
    and     r9, r9, #(7<<16)            @ STACK
    mov     r3, r6, lsl #28
    msr     cpsr_flg, r3                @ to to ARM PSR
    and     r6, r6, #0x670
    mov     r6, r6, lsl #12
    orrmi   r6, r6, #0x80000000         @ N
    orreq   r6, r6, #0x20000000         @ Z

    mov     r3, r4, lsl #16             @ Y
    mov     r2, r4, lsr #16
    mov     r2, r2, lsl #16             @ X
    add     r8, r7, #0x400
    add     r8, r8, #4
    stmia   r8, {r2,r3,r5,r6,r9}
    bx      lr


#define SSP_OFFS_GR    0x400
#define SSP_OFFS_EMUST 0x484
#define SSP_PM0            8
#define SSP_PC             6
#define SSP_WAIT_PM0  0x2000

@ ld      A, PM0
@ andi    2
@ bra     z=1, gloc_0800
ssp_hle_800:
    @ block prologue
    stmfd   sp!, {r4-r11, lr}
    bl      regfile_load
    mov     r11, #0
    
    ldr     r0, [r7, #(SSP_OFFS_GR+SSP_PM0*4)]
    ldr     r1, [r7, #SSP_OFFS_EMUST]
    tst     r0, #0x20000
    orreq   r1, r1, #SSP_WAIT_PM0
    addeq   r11,r11, #1024
    streq   r1, [r7, #SSP_OFFS_EMUST]
    movne   r0,     #0x04000000
    orrne   r0, r0, #0x00040000
    strne   r0, [r7, #(SSP_OFFS_GR+SSP_PC*4)]

    bl      regfile_store
    add     r0, r11, #3
    ldmfd   sp!, {r4-r11, lr}
    bx      lr
Commit	Line	Data
e807ac75	1	@ vim:filetype=armasm
	2
	3	.if 0
	4	#include "compiler.h"
	5	.endif
	6
	7	.global tcache
	8
	9	.global flush_inval_caches
	10	.global regfile_load
	11	.global regfile_store
d5276282	12	.global ssp_hle_800
e807ac75	13
	14	@ translation cache buffer
	15	.text
	16	.align 12 @ 4096
	17	.size tcache, TCACHE_SIZE
	18	tcache:
	19	.space TCACHE_SIZE
	20
	21
	22	.text
	23	.align 2
	24
	25
	26	flush_inval_caches:
	27	mov r2, #0x0 @ must be 0
	28	swi 0x9f0002
	29	bx lr
	30
	31
	32	@ SSP_GR0, SSP_X, SSP_Y, SSP_A,
	33	@ SSP_ST, SSP_STACK, SSP_PC, SSP_P,
	34	@ SSP_PM0, SSP_PM1, SSP_PM2, SSP_XST,
	35	@ SSP_PM4, SSP_gr13, SSP_PMC, SSP_AL
	36
	37	@ register map:
	38	@ r4: XXYY
	39	@ r5: A
b9c1d012	40	@ r6: STACK and emu flags: sss0 * .uu. .lll NZCV (NZCV is PSR bits from ARM)
e807ac75	41	@ r7: SSP context
5d817c91	42	@ r8: r0-r2 (.210)
5d817c91	43	@ r9: r4-r6 (.654)
e807ac75	44	@ r10: P
	45	@ r11: cycles
	46
	47	@ trashes r2,r3
	48
	49	regfile_load:
	50	ldr r7, =ssp
	51	ldr r7, [r7]
	52	add r2, r7, #0x400
	53	add r2, r2, #4
	54	ldmia r2, {r3,r4,r5,r6,r8}
	55	mov r3, r3, lsr #16
	56	mov r3, r3, lsl #16
	57	orr r4, r3, r4, lsr #16 @ XXYY
b9c1d012	58
	59	and r8, r8, #0x0f0000
	60	mov r8, r8, lsl #13 @ sss0 *
	61	and r9, r6, #0x670000
	62	tst r6, #0x80000000
	63	orrne r8, r8, #0x8
	64	tst r6, #0x20000000
	65	orrne r8, r8, #0x4 @ sss0 * NZ..
a6fb500b	66	orr r6, r8, r9, lsr #12 @ sss0 * .uu. .lll NZ..
b9c1d012	67
e807ac75	68	ldr r8, [r7, #0x440] @ r0-r2
	69	ldr r9, [r7, #0x444] @ r4-r6
	70	ldr r10,[r7, #(0x400+7*4)] @ P
	71	bx lr
	72
	73
	74	regfile_store:
	75	str r10,[r7, #(0x400+7*4)] @ P
	76	str r8, [r7, #0x440] @ r0-r2
	77	str r9, [r7, #0x444] @ r4-r6
b9c1d012	78
b9c1d012	79	mov r9, r6, lsr #13
e807ac75	80	and r9, r9, #(7<<16) @ STACK
b9c1d012	81	mov r3, r6, lsl #28
	82	msr cpsr_flg, r3 @ to to ARM PSR
	83	and r6, r6, #0x670
	84	mov r6, r6, lsl #12
	85	orrmi r6, r6, #0x80000000 @ N
	86	orreq r6, r6, #0x20000000 @ Z
	87
e807ac75	88	mov r3, r4, lsl #16 @ Y
	89	mov r2, r4, lsr #16
	90	mov r2, r2, lsl #16 @ X
	91	add r8, r7, #0x400
	92	add r8, r8, #4
	93	stmia r8, {r2,r3,r5,r6,r9}
	94	bx lr
	95
	96
d5276282	97	#define SSP_OFFS_GR 0x400
	98	#define SSP_OFFS_EMUST 0x484
	99	#define SSP_PM0 8
	100	#define SSP_PC 6
	101	#define SSP_WAIT_PM0 0x2000
	102
	103	@ ld A, PM0
	104	@ andi 2
	105	@ bra z=1, gloc_0800
	106	ssp_hle_800:
	107	@ block prologue
	108	stmfd sp!, {r4-r11, lr}
	109	bl regfile_load
	110	mov r11, #0
	111
	112	ldr r0, [r7, #(SSP_OFFS_GR+SSP_PM0*4)]
	113	ldr r1, [r7, #SSP_OFFS_EMUST]
	114	tst r0, #0x20000
	115	orreq r1, r1, #SSP_WAIT_PM0
	116	addeq r11,r11, #1024
	117	streq r1, [r7, #SSP_OFFS_EMUST]
	118	movne r0, #0x04000000
	119	orrne r0, r0, #0x00040000
	120	strne r0, [r7, #(SSP_OFFS_GR+SSP_PC*4)]
	121
	122	bl regfile_store
	123	add r0, r11, #3
	124	ldmfd sp!, {r4-r11, lr}
	125	bx lr
	126
e807ac75	127