cc68a136 |
1 | // This is part of Pico Library\r |
2 | \r |
3 | // (c) Copyright 2004 Dave, All rights reserved.\r |
4 | // (c) Copyright 2006 notaz, All rights reserved.\r |
5 | // Free for non-commercial use.\r |
6 | \r |
7 | // For commercial use, separate licencing terms must be obtained.\r |
8 | \r |
9 | // A68K no longer supported here\r |
10 | \r |
11 | //#define __debug_io\r |
12 | \r |
13 | #include "../PicoInt.h"\r |
14 | \r |
15 | #include "../sound/sound.h"\r |
16 | #include "../sound/ym2612.h"\r |
17 | #include "../sound/sn76496.h"\r |
18 | \r |
cb4a513a |
19 | #include "gfx_cd.h"\r |
20 | \r |
cc68a136 |
21 | typedef unsigned char u8;\r |
22 | typedef unsigned short u16;\r |
23 | typedef unsigned int u32;\r |
24 | \r |
25 | //#define __debug_io\r |
26 | //#define __debug_io2\r |
cb4a513a |
27 | //#define rdprintf dprintf\r |
28 | #define rdprintf(...)\r |
cc68a136 |
29 | \r |
30 | // -----------------------------------------------------------------\r |
31 | \r |
8c1952f0 |
32 | // extern m68ki_cpu_core m68ki_cpu;\r |
cc68a136 |
33 | \r |
34 | extern int counter75hz;\r |
35 | \r |
36 | \r |
cb4a513a |
37 | static u32 m68k_reg_read16(u32 a)\r |
cc68a136 |
38 | {\r |
39 | u32 d=0;\r |
40 | a &= 0x3e;\r |
672ad671 |
41 | // dprintf("m68k_regs r%2i: [%02x] @%06x", realsize&~1, a+(realsize&1), SekPc);\r |
cc68a136 |
42 | \r |
43 | switch (a) {\r |
672ad671 |
44 | case 0:\r |
c459aefd |
45 | d = ((Pico_mcd->s68k_regs[0x33]<<13)&0x8000) | Pico_mcd->m.busreq; // here IFL2 is always 0, just like in Gens\r |
672ad671 |
46 | goto end;\r |
cc68a136 |
47 | case 2:\r |
672ad671 |
48 | d = (Pico_mcd->s68k_regs[a]<<8) | (Pico_mcd->s68k_regs[a+1]&0xc7);\r |
bf098bc5 |
49 | dprintf("m68k_regs r3: %02x @%06x", (u8)d, SekPc);\r |
cc68a136 |
50 | goto end;\r |
c459aefd |
51 | case 4:\r |
52 | d = Pico_mcd->s68k_regs[4]<<8;\r |
53 | goto end;\r |
54 | case 6:\r |
55 | d = Pico_mcd->m.hint_vector;\r |
56 | goto end;\r |
cc68a136 |
57 | case 8:\r |
cc68a136 |
58 | d = Read_CDC_Host(0);\r |
59 | goto end;\r |
c459aefd |
60 | case 0xA:\r |
61 | dprintf("m68k reserved read");\r |
62 | goto end;\r |
cc68a136 |
63 | case 0xC:\r |
64 | dprintf("m68k stopwatch read");\r |
65 | break;\r |
66 | }\r |
67 | \r |
cc68a136 |
68 | if (a < 0x30) {\r |
69 | // comm flag/cmd/status (0xE-0x2F)\r |
70 | d = (Pico_mcd->s68k_regs[a]<<8) | Pico_mcd->s68k_regs[a+1];\r |
71 | goto end;\r |
72 | }\r |
73 | \r |
74 | dprintf("m68k_regs invalid read @ %02x", a);\r |
75 | \r |
76 | end:\r |
77 | \r |
672ad671 |
78 | // dprintf("ret = %04x", d);\r |
cc68a136 |
79 | return d;\r |
80 | }\r |
81 | \r |
cb4a513a |
82 | static void m68k_reg_write8(u32 a, u32 d)\r |
cc68a136 |
83 | {\r |
84 | a &= 0x3f;\r |
672ad671 |
85 | // dprintf("m68k_regs w%2i: [%02x] %02x @%06x", realsize, a, d, SekPc);\r |
cc68a136 |
86 | \r |
87 | switch (a) {\r |
88 | case 0:\r |
672ad671 |
89 | d &= 1;\r |
cc68a136 |
90 | if ((d&1) && (Pico_mcd->s68k_regs[0x33]&(1<<2))) { dprintf("m68k: s68k irq 2"); SekInterruptS68k(2); }\r |
c459aefd |
91 | return;\r |
cc68a136 |
92 | case 1:\r |
672ad671 |
93 | d &= 3;\r |
cc68a136 |
94 | if (!(d&1)) PicoMCD |= 2; // reset pending, needed to be sure we fetch the right vectors on reset\r |
c459aefd |
95 | if ( (Pico_mcd->m.busreq&1) != (d&1)) dprintf("m68k: s68k reset %i", !(d&1));\r |
96 | if ( (Pico_mcd->m.busreq&2) != (d&2)) dprintf("m68k: s68k brq %i", (d&2)>>1);\r |
97 | if ((PicoMCD&2) && (d&3)==1) {\r |
cc68a136 |
98 | SekResetS68k(); // S68k comes out of RESET or BRQ state\r |
99 | PicoMCD&=~2;\r |
672ad671 |
100 | dprintf("m68k: resetting s68k, cycles=%i", SekCyclesLeft);\r |
cc68a136 |
101 | }\r |
c459aefd |
102 | Pico_mcd->m.busreq = d;\r |
103 | return;\r |
672ad671 |
104 | case 2:\r |
105 | Pico_mcd->s68k_regs[2] = d; // really use s68k side register\r |
106 | return;\r |
cc68a136 |
107 | case 3:\r |
bf098bc5 |
108 | dprintf("m68k_regs w3: %02x @%06x", (u8)d, SekPc);\r |
672ad671 |
109 | d &= 0xc2;\r |
110 | if ((Pico_mcd->s68k_regs[3]>>6) != ((d>>6)&3))\r |
111 | dprintf("m68k: prg bank: %i -> %i", (Pico_mcd->s68k_regs[a]>>6), ((d>>6)&3));\r |
112 | //if ((Pico_mcd->s68k_regs[3]&4) != (d&4)) dprintf("m68k: ram mode %i mbit", (d&4) ? 1 : 2);\r |
113 | //if ((Pico_mcd->s68k_regs[3]&2) != (d&2)) dprintf("m68k: %s", (d&4) ? ((d&2) ? "word swap req" : "noop?") :\r |
114 | // ((d&2) ? "word ram to s68k" : "word ram to m68k"));\r |
115 | d |= Pico_mcd->s68k_regs[3]&0x1d;\r |
d0d47c5b |
116 | if (!(d & 4) && (d & 2)) d &= ~1; // return word RAM to s68k in 2M mode\r |
672ad671 |
117 | Pico_mcd->s68k_regs[3] = d; // really use s68k side register\r |
118 | return;\r |
c459aefd |
119 | case 6:\r |
120 | *((char *)&Pico_mcd->m.hint_vector+1) = d;\r |
121 | return;\r |
122 | case 7:\r |
123 | *(char *)&Pico_mcd->m.hint_vector = d;\r |
124 | return;\r |
cc68a136 |
125 | case 0xe:\r |
672ad671 |
126 | //dprintf("m68k: comm flag: %02x", d);\r |
cc68a136 |
127 | \r |
672ad671 |
128 | //dprintf("s68k @ %06x", SekPcS68k);\r |
cc68a136 |
129 | \r |
130 | Pico_mcd->s68k_regs[0xe] = d;\r |
c459aefd |
131 | return;\r |
672ad671 |
132 | }\r |
133 | \r |
134 | if ((a&0xf0) == 0x10) {\r |
cc68a136 |
135 | Pico_mcd->s68k_regs[a] = d;\r |
672ad671 |
136 | return;\r |
cc68a136 |
137 | }\r |
138 | \r |
c459aefd |
139 | dprintf("m68k: invalid write? [%02x] %02x", a, d);\r |
cc68a136 |
140 | }\r |
141 | \r |
142 | \r |
143 | \r |
cb4a513a |
144 | static u32 s68k_reg_read16(u32 a)\r |
cc68a136 |
145 | {\r |
146 | u32 d=0;\r |
cc68a136 |
147 | \r |
672ad671 |
148 | // dprintf("s68k_regs r%2i: [%02x] @ %06x", realsize&~1, a+(realsize&1), SekPcS68k);\r |
cc68a136 |
149 | \r |
150 | switch (a) {\r |
151 | case 0:\r |
cb4a513a |
152 | d = ((Pico_mcd->s68k_regs[0]&3)<<8) | 1; // ver = 0, not in reset state\r |
c459aefd |
153 | goto end;\r |
672ad671 |
154 | case 2:\r |
155 | d = (Pico_mcd->s68k_regs[a]<<8) | (Pico_mcd->s68k_regs[a+1]&0x1f);\r |
bf098bc5 |
156 | dprintf("s68k_regs r3: %02x @%06x", (u8)d, SekPc);\r |
672ad671 |
157 | goto end;\r |
cc68a136 |
158 | case 6:\r |
159 | d = CDC_Read_Reg();\r |
160 | goto end;\r |
161 | case 8:\r |
cb4a513a |
162 | d = Read_CDC_Host(1); // Gens returns 0 here on byte reads\r |
cc68a136 |
163 | goto end;\r |
164 | case 0xC:\r |
165 | dprintf("s68k stopwatch read");\r |
166 | break;\r |
167 | case 0x34: // fader\r |
168 | d = 0; // no busy bit\r |
169 | goto end;\r |
170 | }\r |
171 | \r |
172 | d = (Pico_mcd->s68k_regs[a]<<8) | Pico_mcd->s68k_regs[a+1];\r |
173 | \r |
174 | end:\r |
175 | \r |
672ad671 |
176 | // dprintf("ret = %04x", d);\r |
cc68a136 |
177 | \r |
178 | return d;\r |
179 | }\r |
180 | \r |
cb4a513a |
181 | static void s68k_reg_write8(u32 a, u32 d)\r |
cc68a136 |
182 | {\r |
672ad671 |
183 | //dprintf("s68k_regs w%2i: [%02x] %02x @ %06x", realsize, a, d, SekPcS68k);\r |
cc68a136 |
184 | \r |
185 | // TODO: review against Gens\r |
186 | switch (a) {\r |
672ad671 |
187 | case 2:\r |
188 | return; // only m68k can change WP\r |
189 | case 3:\r |
bf098bc5 |
190 | dprintf("s68k_regs w3: %02x @%06x", (u8)d, SekPc);\r |
672ad671 |
191 | d &= 0x1d;\r |
d0d47c5b |
192 | if (d&4) {\r |
193 | d |= Pico_mcd->s68k_regs[3]&0xc2;\r |
194 | if ((d ^ Pico_mcd->s68k_regs[3]) & 5) d &= ~2; // in case of mode or bank change we clear DMNA (m68k req) bit\r |
195 | } else {\r |
196 | d |= Pico_mcd->s68k_regs[3]&0xc3;\r |
197 | if (d&1) d &= ~2; // return word RAM to m68k in 2M mode\r |
198 | }\r |
672ad671 |
199 | break;\r |
cc68a136 |
200 | case 4:\r |
201 | dprintf("s68k CDC dest: %x", d&7);\r |
202 | Pico_mcd->s68k_regs[4] = (Pico_mcd->s68k_regs[4]&0xC0) | (d&7); // CDC mode\r |
203 | return;\r |
204 | case 5:\r |
c459aefd |
205 | //dprintf("s68k CDC reg addr: %x", d&0xf);\r |
cc68a136 |
206 | break;\r |
207 | case 7:\r |
208 | CDC_Write_Reg(d);\r |
209 | return;\r |
210 | case 0xa:\r |
211 | dprintf("s68k set CDC dma addr");\r |
212 | break;\r |
213 | case 0x33: // IRQ mask\r |
214 | dprintf("s68k irq mask: %02x", d);\r |
215 | if ((d&(1<<4)) && (Pico_mcd->s68k_regs[0x37]&4) && !(Pico_mcd->s68k_regs[0x33]&(1<<4))) {\r |
216 | CDD_Export_Status();\r |
217 | // counter75hz = 0; // ???\r |
218 | }\r |
219 | break;\r |
220 | case 0x34: // fader\r |
221 | Pico_mcd->s68k_regs[a] = (u8) d & 0x7f;\r |
222 | return;\r |
672ad671 |
223 | case 0x36:\r |
224 | return; // d/m bit is unsetable\r |
225 | case 0x37: {\r |
226 | u32 d_old = Pico_mcd->s68k_regs[0x37];\r |
227 | Pico_mcd->s68k_regs[0x37] = d&7;\r |
228 | if ((d&4) && !(d_old&4)) {\r |
cc68a136 |
229 | CDD_Export_Status();\r |
230 | // counter75hz = 0; // ???\r |
231 | }\r |
672ad671 |
232 | return;\r |
233 | }\r |
cc68a136 |
234 | case 0x4b:\r |
235 | Pico_mcd->s68k_regs[a] = (u8) d;\r |
236 | CDD_Import_Command();\r |
237 | return;\r |
238 | }\r |
239 | \r |
240 | if ((a&0x1f0) == 0x10 || a == 0x0e || (a >= 0x38 && a < 0x42))\r |
241 | {\r |
242 | dprintf("m68k: invalid write @ %02x?", a);\r |
243 | return;\r |
244 | }\r |
245 | \r |
246 | Pico_mcd->s68k_regs[a] = (u8) d;\r |
247 | }\r |
248 | \r |
249 | \r |
250 | \r |
251 | \r |
252 | \r |
253 | static int PadRead(int i)\r |
254 | {\r |
255 | int pad=0,value=0,TH;\r |
256 | pad=~PicoPad[i]; // Get inverse of pad MXYZ SACB RLDU\r |
257 | TH=Pico.ioports[i+1]&0x40;\r |
258 | \r |
259 | if(PicoOpt & 0x20) { // 6 button gamepad enabled\r |
260 | int phase = Pico.m.padTHPhase[i];\r |
261 | \r |
262 | if(phase == 2 && !TH) {\r |
263 | value=(pad&0xc0)>>2; // ?0SA 0000\r |
264 | goto end;\r |
265 | } else if(phase == 3 && TH) {\r |
266 | value=(pad&0x30)|((pad>>8)&0xf); // ?1CB MXYZ\r |
267 | goto end;\r |
268 | } else if(phase == 3 && !TH) {\r |
269 | value=((pad&0xc0)>>2)|0x0f; // ?0SA 1111\r |
270 | goto end;\r |
271 | }\r |
272 | }\r |
273 | \r |
274 | if(TH) value=(pad&0x3f); // ?1CB RLDU\r |
275 | else value=((pad&0xc0)>>2)|(pad&3); // ?0SA 00DU\r |
276 | \r |
277 | end:\r |
278 | \r |
279 | // orr the bits, which are set as output\r |
280 | value |= Pico.ioports[i+1]&Pico.ioports[i+4];\r |
281 | \r |
282 | return value; // will mirror later\r |
283 | }\r |
284 | \r |
285 | static u8 z80Read8(u32 a)\r |
286 | {\r |
287 | if(Pico.m.z80Run&1) return 0;\r |
288 | \r |
289 | a&=0x1fff;\r |
290 | \r |
291 | if(!(PicoOpt&4)) {\r |
292 | // Z80 disabled, do some faking\r |
293 | static u8 zerosent = 0;\r |
294 | if(a == Pico.m.z80_lastaddr) { // probably polling something\r |
295 | u8 d = Pico.m.z80_fakeval;\r |
296 | if((d & 0xf) == 0xf && !zerosent) {\r |
297 | d = 0; zerosent = 1;\r |
298 | } else {\r |
299 | Pico.m.z80_fakeval++;\r |
300 | zerosent = 0;\r |
301 | }\r |
302 | return d;\r |
303 | } else {\r |
304 | Pico.m.z80_fakeval = 0;\r |
305 | }\r |
306 | }\r |
307 | \r |
308 | Pico.m.z80_lastaddr = (u16) a;\r |
309 | return Pico.zram[a];\r |
310 | }\r |
311 | \r |
312 | \r |
313 | // for nonstandard reads\r |
314 | static u32 UnusualRead16(u32 a, int realsize)\r |
315 | {\r |
316 | u32 d=0;\r |
317 | \r |
318 | dprintf("unusual r%i: %06x @%06x", realsize&~1, (a&0xfffffe)+(realsize&1), SekPc);\r |
319 | \r |
320 | \r |
321 | dprintf("ret = %04x", d);\r |
322 | return d;\r |
323 | }\r |
324 | \r |
325 | static u32 OtherRead16(u32 a, int realsize)\r |
326 | {\r |
327 | u32 d=0;\r |
328 | \r |
329 | if ((a&0xff0000)==0xa00000) {\r |
330 | if ((a&0x4000)==0x0000) { d=z80Read8(a); d|=d<<8; goto end; } // Z80 ram (not byteswaped)\r |
331 | if ((a&0x6000)==0x4000) { if(PicoOpt&1) d=YM2612Read(); else d=Pico.m.rotate++&3; goto end; } // 0x4000-0x5fff, Fudge if disabled\r |
332 | d=0xffff; goto end;\r |
333 | }\r |
334 | if ((a&0xffffe0)==0xa10000) { // I/O ports\r |
335 | a=(a>>1)&0xf;\r |
336 | switch(a) {\r |
337 | case 0: d=Pico.m.hardware; break; // Hardware value (Version register)\r |
338 | case 1: d=PadRead(0); d|=Pico.ioports[1]&0x80; break;\r |
339 | case 2: d=PadRead(1); d|=Pico.ioports[2]&0x80; break;\r |
340 | default: d=Pico.ioports[a]; break; // IO ports can be used as RAM\r |
341 | }\r |
342 | d|=d<<8;\r |
343 | goto end;\r |
344 | }\r |
345 | // |=0x80 for Shadow of the Beast & Super Offroad; rotate fakes next fetched instruction for Time Killers\r |
346 | if (a==0xa11100) { d=((Pico.m.z80Run&1)<<8)|0x8000|Pico.m.rotate++; goto end; }\r |
347 | \r |
348 | if ((a&0xe700e0)==0xc00000) { d=PicoVideoRead(a); goto end; }\r |
349 | \r |
672ad671 |
350 | if ((a&0xffffc0)==0xa12000) {\r |
cb4a513a |
351 | d=m68k_reg_read16(a);\r |
672ad671 |
352 | goto end;\r |
353 | }\r |
cc68a136 |
354 | \r |
355 | d = UnusualRead16(a, realsize);\r |
356 | \r |
357 | end:\r |
358 | return d;\r |
359 | }\r |
360 | \r |
361 | //extern UINT32 mz80GetRegisterValue(void *, UINT32);\r |
362 | \r |
363 | static void OtherWrite8(u32 a,u32 d,int realsize)\r |
364 | {\r |
365 | if ((a&0xe700f9)==0xc00011||(a&0xff7ff9)==0xa07f11) { if(PicoOpt&2) SN76496Write(d); return; } // PSG Sound\r |
366 | if ((a&0xff4000)==0xa00000) { if(!(Pico.m.z80Run&1)) Pico.zram[a&0x1fff]=(u8)d; return; } // Z80 ram\r |
367 | if ((a&0xff6000)==0xa04000) { if(PicoOpt&1) emustatus|=YM2612Write(a&3, d); return; } // FM Sound\r |
368 | if ((a&0xffffe0)==0xa10000) { // I/O ports\r |
369 | a=(a>>1)&0xf;\r |
370 | // 6 button gamepad: if TH went from 0 to 1, gamepad changes state\r |
371 | if(PicoOpt&0x20) {\r |
372 | if(a==1) {\r |
373 | Pico.m.padDelay[0] = 0;\r |
374 | if(!(Pico.ioports[1]&0x40) && (d&0x40)) Pico.m.padTHPhase[0]++;\r |
375 | }\r |
376 | else if(a==2) {\r |
377 | Pico.m.padDelay[1] = 0;\r |
378 | if(!(Pico.ioports[2]&0x40) && (d&0x40)) Pico.m.padTHPhase[1]++;\r |
379 | }\r |
380 | }\r |
381 | Pico.ioports[a]=(u8)d; // IO ports can be used as RAM\r |
382 | return;\r |
383 | }\r |
384 | if (a==0xa11100) {\r |
385 | extern int z80startCycle, z80stopCycle;\r |
386 | //int lineCycles=(488-SekCyclesLeft)&0x1ff;\r |
387 | d&=1; d^=1;\r |
388 | if(!d) {\r |
389 | // hack: detect a nasty situation where Z80 was enabled and disabled in the same 68k timeslice (Golden Axe III)\r |
390 | if((PicoOpt&4) && Pico.m.z80Run==1) z80_run(20);\r |
391 | z80stopCycle = SekCyclesDone();\r |
392 | //z80ExtraCycles += (lineCycles>>1)-(lineCycles>>5); // only meaningful in PicoFrameHints()\r |
393 | } else {\r |
394 | z80startCycle = SekCyclesDone();\r |
395 | //if(Pico.m.scanline != -1)\r |
396 | //z80ExtraCycles -= (lineCycles>>1)-(lineCycles>>5)+16;\r |
397 | }\r |
398 | //dprintf("set_zrun: %i [%i|%i] zPC=%04x @%06x", d, Pico.m.scanline, SekCyclesDone(), mz80GetRegisterValue(NULL, 0), SekPc);\r |
399 | Pico.m.z80Run=(u8)d; return;\r |
400 | }\r |
401 | if (a==0xa11200) { if(!(d&1)) z80_reset(); return; }\r |
402 | \r |
403 | if ((a&0xff7f00)==0xa06000) // Z80 BANK register\r |
404 | {\r |
405 | Pico.m.z80_bank68k>>=1;\r |
406 | Pico.m.z80_bank68k|=(d&1)<<8;\r |
407 | Pico.m.z80_bank68k&=0x1ff; // 9 bits and filled in the new top one\r |
408 | return;\r |
409 | }\r |
410 | \r |
411 | if ((a&0xe700e0)==0xc00000) { PicoVideoWrite(a,(u16)(d|(d<<8))); return; } // Byte access gets mirrored\r |
412 | \r |
cb4a513a |
413 | if ((a&0xffffc0)==0xa12000) { m68k_reg_write8(a, d); return; }\r |
cc68a136 |
414 | \r |
415 | dprintf("strange w%i: %06x, %08x @%06x", realsize, a&0xffffff, d, SekPc);\r |
416 | }\r |
417 | \r |
418 | static void OtherWrite16(u32 a,u32 d)\r |
419 | {\r |
420 | if ((a&0xe700e0)==0xc00000) { PicoVideoWrite(a,(u16)d); return; }\r |
421 | if ((a&0xff4000)==0xa00000) { if(!(Pico.m.z80Run&1)) Pico.zram[a&0x1fff]=(u8)(d>>8); return; } // Z80 ram (MSB only)\r |
422 | \r |
423 | if ((a&0xffffe0)==0xa10000) { // I/O ports\r |
424 | a=(a>>1)&0xf;\r |
425 | // 6 button gamepad: if TH went from 0 to 1, gamepad changes state\r |
426 | if(PicoOpt&0x20) {\r |
427 | if(a==1) {\r |
428 | Pico.m.padDelay[0] = 0;\r |
429 | if(!(Pico.ioports[1]&0x40) && (d&0x40)) Pico.m.padTHPhase[0]++;\r |
430 | }\r |
431 | else if(a==2) {\r |
432 | Pico.m.padDelay[1] = 0;\r |
433 | if(!(Pico.ioports[2]&0x40) && (d&0x40)) Pico.m.padTHPhase[1]++;\r |
434 | }\r |
435 | }\r |
436 | Pico.ioports[a]=(u8)d; // IO ports can be used as RAM\r |
437 | return;\r |
438 | }\r |
439 | if (a==0xa11100) { OtherWrite8(a, d>>8, 16); return; }\r |
440 | if (a==0xa11200) { if(!(d&0x100)) z80_reset(); return; }\r |
441 | \r |
442 | OtherWrite8(a, d>>8, 16);\r |
443 | OtherWrite8(a+1,d&0xff, 16);\r |
444 | }\r |
445 | \r |
446 | // -----------------------------------------------------------------\r |
447 | // Read Rom and read Ram\r |
448 | \r |
449 | u8 PicoReadM68k8(u32 a)\r |
450 | {\r |
451 | u32 d=0;\r |
452 | \r |
453 | if ((a&0xe00000)==0xe00000) { d = *(u8 *)(Pico.ram+((a^1)&0xffff)); goto end; } // Ram\r |
454 | \r |
455 | a&=0xffffff;\r |
456 | \r |
457 | if (a < 0x20000) { d = *(u8 *)(Pico_mcd->bios+(a^1)); goto end; } // bios\r |
458 | \r |
459 | // prg RAM\r |
460 | if ((a&0xfe0000)==0x020000) {\r |
672ad671 |
461 | u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];\r |
cc68a136 |
462 | d = *(prg_bank+((a^1)&0x1ffff));\r |
463 | goto end;\r |
464 | }\r |
465 | \r |
d0d47c5b |
466 | // word RAM\r |
467 | if ((a&0xfc0000)==0x200000) {\r |
468 | dprintf("m68k_wram r8: [%06x] @%06x", a, SekPc);\r |
469 | if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?\r |
bf098bc5 |
470 | if (a >= 0x220000) {\r |
471 | dprintf("cell");\r |
472 | } else {\r |
473 | a=((a&0x1fffe)<<1)|(a&1);\r |
474 | if (Pico_mcd->s68k_regs[3]&1) a+=2;\r |
475 | d = Pico_mcd->word_ram[a^1];\r |
476 | }\r |
d0d47c5b |
477 | } else {\r |
478 | // allow access in any mode, like Gens does\r |
479 | d = Pico_mcd->word_ram[(a^1)&0x3ffff];\r |
480 | }\r |
481 | dprintf("ret = %02x", (u8)d);\r |
482 | goto end;\r |
483 | }\r |
484 | \r |
cc68a136 |
485 | if ((a&0xff4000)==0xa00000) { d=z80Read8(a); goto end; } // Z80 Ram\r |
486 | \r |
c459aefd |
487 | if ((a&0xffffc0)==0xa12000)\r |
488 | rdprintf("m68k_regs r8: [%02x] @%06x", a&0x3f, SekPc);\r |
672ad671 |
489 | \r |
cc68a136 |
490 | d=OtherRead16(a&~1, 8|(a&1)); if ((a&1)==0) d>>=8;\r |
491 | \r |
c459aefd |
492 | if ((a&0xffffc0)==0xa12000)\r |
493 | rdprintf("ret = %02x", (u8)d);\r |
672ad671 |
494 | \r |
cc68a136 |
495 | end:\r |
496 | \r |
497 | #ifdef __debug_io\r |
498 | dprintf("r8 : %06x, %02x @%06x", a&0xffffff, (u8)d, SekPc);\r |
499 | #endif\r |
500 | return (u8)d;\r |
501 | }\r |
502 | \r |
503 | u16 PicoReadM68k16(u32 a)\r |
504 | {\r |
505 | u16 d=0;\r |
506 | \r |
507 | if ((a&0xe00000)==0xe00000) { d=*(u16 *)(Pico.ram+(a&0xfffe)); goto end; } // Ram\r |
508 | \r |
509 | a&=0xfffffe;\r |
510 | \r |
511 | if (a < 0x20000) { d = *(u16 *)(Pico_mcd->bios+a); goto end; } // bios\r |
512 | \r |
513 | // prg RAM\r |
514 | if ((a&0xfe0000)==0x020000) {\r |
672ad671 |
515 | u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];\r |
cc68a136 |
516 | d = *(u16 *)(prg_bank+(a&0x1fffe));\r |
517 | goto end;\r |
518 | }\r |
519 | \r |
d0d47c5b |
520 | // word RAM\r |
521 | if ((a&0xfc0000)==0x200000) {\r |
522 | dprintf("m68k_wram r16: [%06x] @%06x", a, SekPc);\r |
523 | if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?\r |
bf098bc5 |
524 | if (a >= 0x220000) {\r |
525 | dprintf("cell");\r |
526 | } else {\r |
527 | a=((a&0x1fffe)<<1);\r |
528 | if (Pico_mcd->s68k_regs[3]&1) a+=2;\r |
529 | d = *(u16 *)(Pico_mcd->word_ram+a);\r |
530 | }\r |
d0d47c5b |
531 | } else {\r |
532 | // allow access in any mode, like Gens does\r |
533 | d = *(u16 *)(Pico_mcd->word_ram+(a&0x3fffe));\r |
534 | }\r |
535 | dprintf("ret = %04x", d);\r |
536 | goto end;\r |
537 | }\r |
538 | \r |
c459aefd |
539 | if ((a&0xffffc0)==0xa12000)\r |
540 | rdprintf("m68k_regs r16: [%02x] @%06x", a&0x3f, SekPc);\r |
672ad671 |
541 | \r |
cc68a136 |
542 | d = (u16)OtherRead16(a, 16);\r |
543 | \r |
c459aefd |
544 | if ((a&0xffffc0)==0xa12000)\r |
545 | rdprintf("ret = %04x", d);\r |
672ad671 |
546 | \r |
cc68a136 |
547 | end:\r |
548 | \r |
549 | #ifdef __debug_io\r |
550 | dprintf("r16: %06x, %04x @%06x", a&0xffffff, d, SekPc);\r |
551 | #endif\r |
552 | return d;\r |
553 | }\r |
554 | \r |
555 | u32 PicoReadM68k32(u32 a)\r |
556 | {\r |
557 | u32 d=0;\r |
558 | \r |
559 | if ((a&0xe00000)==0xe00000) { u16 *pm=(u16 *)(Pico.ram+(a&0xfffe)); d = (pm[0]<<16)|pm[1]; goto end; } // Ram\r |
560 | \r |
561 | a&=0xfffffe;\r |
562 | \r |
563 | if (a < 0x20000) { u16 *pm=(u16 *)(Pico_mcd->bios+a); d = (pm[0]<<16)|pm[1]; goto end; } // bios\r |
564 | \r |
565 | // prg RAM\r |
566 | if ((a&0xfe0000)==0x020000) {\r |
672ad671 |
567 | u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];\r |
cc68a136 |
568 | u16 *pm=(u16 *)(prg_bank+(a&0x1fffe));\r |
569 | d = (pm[0]<<16)|pm[1];\r |
570 | goto end;\r |
571 | }\r |
572 | \r |
d0d47c5b |
573 | // word RAM\r |
574 | if ((a&0xfc0000)==0x200000) {\r |
575 | dprintf("m68k_wram r32: [%06x] @%06x", a, SekPc);\r |
576 | if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?\r |
bf098bc5 |
577 | if (a >= 0x220000) {\r |
578 | dprintf("cell");\r |
579 | } else {\r |
580 | u16 *pm;\r |
581 | a=((a&0x1fffe)<<1);\r |
582 | if (Pico_mcd->s68k_regs[3]&1) a+=2;\r |
583 | pm=(u16 *)(Pico_mcd->word_ram+a);\r |
584 | d = (pm[0]<<16)|pm[1];\r |
585 | }\r |
d0d47c5b |
586 | } else {\r |
587 | // allow access in any mode, like Gens does\r |
588 | u16 *pm=(u16 *)(Pico_mcd->word_ram+(a&0x3fffe)); d = (pm[0]<<16)|pm[1];\r |
589 | }\r |
590 | dprintf("ret = %08x", d);\r |
591 | goto end;\r |
592 | }\r |
593 | \r |
c459aefd |
594 | if ((a&0xffffc0)==0xa12000)\r |
595 | rdprintf("m68k_regs r32: [%02x] @%06x", a&0x3f, SekPc);\r |
672ad671 |
596 | \r |
cc68a136 |
597 | d = (OtherRead16(a, 32)<<16)|OtherRead16(a+2, 32);\r |
598 | \r |
c459aefd |
599 | if ((a&0xffffc0)==0xa12000)\r |
600 | rdprintf("ret = %08x", d);\r |
672ad671 |
601 | \r |
cc68a136 |
602 | end:\r |
603 | #ifdef __debug_io\r |
604 | dprintf("r32: %06x, %08x @%06x", a&0xffffff, d, SekPc);\r |
605 | #endif\r |
606 | return d;\r |
607 | }\r |
608 | \r |
609 | // -----------------------------------------------------------------\r |
610 | // Write Ram\r |
611 | \r |
612 | void PicoWriteM68k8(u32 a,u8 d)\r |
613 | {\r |
614 | #ifdef __debug_io\r |
615 | dprintf("w8 : %06x, %02x @%06x", a&0xffffff, d, SekPc);\r |
616 | #endif\r |
617 | //if ((a&0xe0ffff)==0xe0a9ba+0x69c)\r |
618 | // dprintf("w8 : %06x, %02x @%06x", a&0xffffff, d, SekPc);\r |
619 | \r |
620 | \r |
621 | if ((a&0xe00000)==0xe00000) { u8 *pm=(u8 *)(Pico.ram+((a^1)&0xffff)); pm[0]=d; return; } // Ram\r |
622 | \r |
623 | a&=0xffffff;\r |
624 | \r |
625 | // prg RAM\r |
626 | if ((a&0xfe0000)==0x020000) {\r |
672ad671 |
627 | u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];\r |
bf098bc5 |
628 | *(u8 *)(prg_bank+((a^1)&0x1ffff))=d;\r |
cc68a136 |
629 | return;\r |
630 | }\r |
631 | \r |
d0d47c5b |
632 | // word RAM\r |
633 | if ((a&0xfc0000)==0x200000) {\r |
634 | dprintf("m68k_wram w8: [%06x] %02x @%06x", a, d, SekPc);\r |
635 | if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?\r |
bf098bc5 |
636 | if (a >= 0x220000) {\r |
637 | dprintf("cell");\r |
638 | } else {\r |
639 | a=((a&0x1fffe)<<1)|(a&1);\r |
640 | if (Pico_mcd->s68k_regs[3]&1) a+=2;\r |
641 | *(u8 *)(Pico_mcd->word_ram+(a^1))=d;\r |
642 | }\r |
d0d47c5b |
643 | } else {\r |
644 | // allow access in any mode, like Gens does\r |
bf098bc5 |
645 | *(u8 *)(Pico_mcd->word_ram+((a^1)&0x3ffff))=d;\r |
d0d47c5b |
646 | }\r |
647 | return;\r |
648 | }\r |
649 | \r |
c459aefd |
650 | if ((a&0xffffc0)==0xa12000)\r |
651 | rdprintf("m68k_regs w8: [%02x] %02x @%06x", a&0x3f, d, SekPc);\r |
672ad671 |
652 | \r |
cc68a136 |
653 | OtherWrite8(a,d,8);\r |
654 | }\r |
655 | \r |
656 | void PicoWriteM68k16(u32 a,u16 d)\r |
657 | {\r |
658 | #ifdef __debug_io\r |
659 | dprintf("w16: %06x, %04x", a&0xffffff, d);\r |
660 | #endif\r |
cc68a136 |
661 | // dprintf("w16: %06x, %04x @%06x", a&0xffffff, d, SekPc);\r |
662 | \r |
663 | if ((a&0xe00000)==0xe00000) { *(u16 *)(Pico.ram+(a&0xfffe))=d; return; } // Ram\r |
664 | \r |
665 | a&=0xfffffe;\r |
666 | \r |
667 | // prg RAM\r |
668 | if ((a&0xfe0000)==0x020000) {\r |
672ad671 |
669 | u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];\r |
cc68a136 |
670 | *(u16 *)(prg_bank+(a&0x1fffe))=d;\r |
671 | return;\r |
672 | }\r |
673 | \r |
d0d47c5b |
674 | // word RAM\r |
675 | if ((a&0xfc0000)==0x200000) {\r |
676 | dprintf("m68k_wram w16: [%06x] %04x @%06x", a, d, SekPc);\r |
677 | if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?\r |
bf098bc5 |
678 | if (a >= 0x220000) {\r |
679 | dprintf("cell");\r |
680 | } else {\r |
681 | a=((a&0x1fffe)<<1);\r |
682 | if (Pico_mcd->s68k_regs[3]&1) a+=2;\r |
683 | *(u16 *)(Pico_mcd->word_ram+a)=d;\r |
684 | }\r |
d0d47c5b |
685 | } else {\r |
686 | // allow access in any mode, like Gens does\r |
687 | *(u16 *)(Pico_mcd->word_ram+(a&0x3fffe))=d;\r |
688 | }\r |
689 | return;\r |
690 | }\r |
691 | \r |
c459aefd |
692 | if ((a&0xffffc0)==0xa12000)\r |
693 | rdprintf("m68k_regs w16: [%02x] %04x @%06x", a&0x3f, d, SekPc);\r |
cc68a136 |
694 | \r |
695 | OtherWrite16(a,d);\r |
696 | }\r |
697 | \r |
698 | void PicoWriteM68k32(u32 a,u32 d)\r |
699 | {\r |
700 | #ifdef __debug_io\r |
701 | dprintf("w32: %06x, %08x", a&0xffffff, d);\r |
702 | #endif\r |
703 | \r |
704 | if ((a&0xe00000)==0xe00000)\r |
705 | {\r |
706 | // Ram:\r |
707 | u16 *pm=(u16 *)(Pico.ram+(a&0xfffe));\r |
708 | pm[0]=(u16)(d>>16); pm[1]=(u16)d;\r |
709 | return;\r |
710 | }\r |
711 | \r |
712 | a&=0xfffffe;\r |
713 | \r |
714 | // prg RAM\r |
715 | if ((a&0xfe0000)==0x020000) {\r |
672ad671 |
716 | u8 *prg_bank = Pico_mcd->prg_ram_b[Pico_mcd->s68k_regs[3]>>6];\r |
cc68a136 |
717 | u16 *pm=(u16 *)(prg_bank+(a&0x1fffe));\r |
718 | pm[0]=(u16)(d>>16); pm[1]=(u16)d;\r |
719 | return;\r |
720 | }\r |
721 | \r |
672ad671 |
722 | // word RAM\r |
d0d47c5b |
723 | if ((a&0xfc0000)==0x200000) {\r |
724 | if (d != 0) // don't log clears\r |
725 | dprintf("m68k_wram w32: [%06x] %08x @%06x", a, d, SekPc);\r |
726 | if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?\r |
bf098bc5 |
727 | if (a >= 0x220000) {\r |
728 | dprintf("cell");\r |
729 | } else {\r |
730 | u16 *pm;\r |
731 | a=((a&0x1fffe)<<1);\r |
732 | if (Pico_mcd->s68k_regs[3]&1) a+=2;\r |
733 | pm=(u16 *)(Pico_mcd->word_ram+a);\r |
734 | pm[0]=(u16)(d>>16); pm[1]=(u16)d;\r |
735 | }\r |
d0d47c5b |
736 | } else {\r |
737 | // allow access in any mode, like Gens does\r |
738 | u16 *pm=(u16 *)(Pico_mcd->word_ram+(a&0x3fffe));\r |
739 | pm[0]=(u16)(d>>16); pm[1]=(u16)d;\r |
740 | }\r |
672ad671 |
741 | return;\r |
d0d47c5b |
742 | }\r |
672ad671 |
743 | \r |
c459aefd |
744 | if ((a&0xffffc0)==0xa12000)\r |
745 | rdprintf("m68k_regs w32: [%02x] %08x @%06x", a&0x3f, d, SekPc);\r |
cc68a136 |
746 | \r |
747 | OtherWrite16(a, (u16)(d>>16));\r |
748 | OtherWrite16(a+2,(u16)d);\r |
749 | }\r |
750 | \r |
751 | \r |
752 | // -----------------------------------------------------------------\r |
753 | \r |
754 | \r |
755 | u8 PicoReadS68k8(u32 a)\r |
756 | {\r |
757 | u32 d=0;\r |
758 | \r |
759 | a&=0xffffff;\r |
760 | \r |
761 | // prg RAM\r |
762 | if (a < 0x80000) {\r |
763 | d = *(Pico_mcd->prg_ram+(a^1));\r |
764 | goto end;\r |
765 | }\r |
766 | \r |
767 | // regs\r |
768 | if ((a&0xfffe00) == 0xff8000) {\r |
cb4a513a |
769 | a &= 0x1ff;\r |
770 | rdprintf("s68k_regs r8: [%02x] @ %06x", a, SekPcS68k);\r |
771 | if (a >= 0x50 && a < 0x68)\r |
772 | d = gfx_cd_read(a&~1);\r |
773 | else d = s68k_reg_read16(a&~1);\r |
774 | if ((a&1)==0) d>>=8;\r |
c459aefd |
775 | rdprintf("ret = %02x", (u8)d);\r |
cc68a136 |
776 | goto end;\r |
777 | }\r |
778 | \r |
d0d47c5b |
779 | // word RAM (2M area)\r |
780 | if ((a&0xfc0000)==0x080000) { // 080000-0bffff\r |
781 | dprintf("s68k_wram2M r8: [%06x] @%06x", a, SekPc);\r |
782 | if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?\r |
783 | // TODO (decode)\r |
784 | dprintf("(decode)");\r |
785 | } else {\r |
786 | // allow access in any mode, like Gens does\r |
787 | d = Pico_mcd->word_ram[(a^1)&0x3ffff];\r |
788 | }\r |
789 | dprintf("ret = %02x", (u8)d);\r |
790 | goto end;\r |
791 | }\r |
792 | \r |
793 | // word RAM (1M area)\r |
794 | if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff\r |
795 | dprintf("s68k_wram1M r8: [%06x] @%06x", a, SekPc);\r |
bf098bc5 |
796 | a=((a&0x1fffe)<<1)|(a&1);\r |
797 | if (!(Pico_mcd->s68k_regs[3]&1)) a+=2;\r |
798 | d = Pico_mcd->word_ram[a^1];\r |
799 | dprintf("ret = %02x", (u8)d);\r |
d0d47c5b |
800 | goto end;\r |
801 | }\r |
802 | \r |
cc68a136 |
803 | dprintf("s68k r8 : %06x, %02x @%06x", a&0xffffff, (u8)d, SekPcS68k);\r |
804 | \r |
805 | end:\r |
806 | \r |
807 | #ifdef __debug_io2\r |
808 | dprintf("s68k r8 : %06x, %02x @%06x", a&0xffffff, (u8)d, SekPcS68k);\r |
809 | #endif\r |
810 | return (u8)d;\r |
811 | }\r |
812 | \r |
813 | u16 PicoReadS68k16(u32 a)\r |
814 | {\r |
815 | u16 d=0;\r |
816 | \r |
817 | a&=0xfffffe;\r |
818 | \r |
819 | // prg RAM\r |
820 | if (a < 0x80000) {\r |
821 | d = *(u16 *)(Pico_mcd->prg_ram+a);\r |
822 | goto end;\r |
823 | }\r |
824 | \r |
825 | // regs\r |
826 | if ((a&0xfffe00) == 0xff8000) {\r |
cb4a513a |
827 | a &= 0x1fe;\r |
828 | rdprintf("s68k_regs r16: [%02x] @ %06x", a, SekPcS68k);\r |
829 | if (a >= 0x50 && a < 0x68)\r |
830 | d = gfx_cd_read(a);\r |
831 | else d = s68k_reg_read16(a);\r |
c459aefd |
832 | rdprintf("ret = %04x", d);\r |
cc68a136 |
833 | goto end;\r |
834 | }\r |
835 | \r |
d0d47c5b |
836 | // word RAM (2M area)\r |
837 | if ((a&0xfc0000)==0x080000) { // 080000-0bffff\r |
838 | dprintf("s68k_wram2M r16: [%06x] @%06x", a, SekPc);\r |
839 | if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?\r |
840 | // TODO (decode)\r |
841 | dprintf("(decode)");\r |
842 | } else {\r |
843 | // allow access in any mode, like Gens does\r |
844 | d = *(u16 *)(Pico_mcd->word_ram+(a&0x3fffe));\r |
845 | }\r |
846 | dprintf("ret = %04x", (u8)d);\r |
847 | goto end;\r |
848 | }\r |
849 | \r |
850 | // word RAM (1M area)\r |
851 | if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff\r |
852 | dprintf("s68k_wram1M r16: [%06x] @%06x", a, SekPc);\r |
bf098bc5 |
853 | a=((a&0x1fffe)<<1);\r |
854 | if (!(Pico_mcd->s68k_regs[3]&1)) a+=2;\r |
855 | d = *(u16 *)(Pico_mcd->word_ram+a);\r |
856 | dprintf("ret = %04x", (u8)d);\r |
d0d47c5b |
857 | goto end;\r |
858 | }\r |
859 | \r |
cc68a136 |
860 | dprintf("s68k r16: %06x, %04x @%06x", a&0xffffff, d, SekPcS68k);\r |
861 | \r |
862 | end:\r |
863 | \r |
864 | #ifdef __debug_io2\r |
865 | dprintf("s68k r16: %06x, %04x @%06x", a&0xffffff, d, SekPcS68k);\r |
866 | #endif\r |
867 | return d;\r |
868 | }\r |
869 | \r |
870 | u32 PicoReadS68k32(u32 a)\r |
871 | {\r |
872 | u32 d=0;\r |
873 | \r |
874 | a&=0xfffffe;\r |
875 | \r |
876 | // prg RAM\r |
877 | if (a < 0x80000) {\r |
878 | u16 *pm=(u16 *)(Pico_mcd->prg_ram+a);\r |
879 | d = (pm[0]<<16)|pm[1];\r |
880 | goto end;\r |
881 | }\r |
882 | \r |
883 | // regs\r |
884 | if ((a&0xfffe00) == 0xff8000) {\r |
cb4a513a |
885 | a &= 0x1fe;\r |
886 | rdprintf("s68k_regs r32: [%02x] @ %06x", a, SekPcS68k);\r |
887 | if (a >= 0x50 && a < 0x68)\r |
888 | d = (gfx_cd_read(a)<<16)|gfx_cd_read(a+2);\r |
889 | else d = (s68k_reg_read16(a)<<16)|s68k_reg_read16(a+2);\r |
c459aefd |
890 | rdprintf("ret = %08x", d);\r |
cc68a136 |
891 | goto end;\r |
892 | }\r |
893 | \r |
d0d47c5b |
894 | // word RAM (2M area)\r |
895 | if ((a&0xfc0000)==0x080000) { // 080000-0bffff\r |
896 | dprintf("s68k_wram2M r32: [%06x] @%06x", a, SekPc);\r |
897 | if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?\r |
898 | // TODO (decode)\r |
899 | dprintf("(decode)");\r |
900 | } else {\r |
901 | // allow access in any mode, like Gens does\r |
902 | u16 *pm=(u16 *)(Pico_mcd->word_ram+(a&0x3fffe)); d = (pm[0]<<16)|pm[1];\r |
903 | }\r |
904 | dprintf("ret = %08x", (u8)d);\r |
905 | goto end;\r |
906 | }\r |
907 | \r |
908 | // word RAM (1M area)\r |
909 | if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff\r |
bf098bc5 |
910 | u16 *pm;\r |
d0d47c5b |
911 | dprintf("s68k_wram1M 32: [%06x] @%06x", a, SekPc);\r |
bf098bc5 |
912 | a=((a&0x1fffe)<<1);\r |
913 | if (!(Pico_mcd->s68k_regs[3]&1)) a+=2;\r |
914 | pm=(u16 *)(Pico_mcd->word_ram+a);\r |
915 | d = (pm[0]<<16)|pm[1];\r |
916 | dprintf("ret = %08x", (u8)d);\r |
d0d47c5b |
917 | goto end;\r |
918 | }\r |
919 | \r |
cc68a136 |
920 | dprintf("s68k r32: %06x, %08x @%06x", a&0xffffff, d, SekPcS68k);\r |
921 | \r |
922 | end:\r |
923 | \r |
924 | #ifdef __debug_io2\r |
925 | dprintf("s68k r32: %06x, %08x @%06x", a&0xffffff, d, SekPcS68k);\r |
926 | #endif\r |
927 | return d;\r |
928 | }\r |
929 | \r |
930 | // -----------------------------------------------------------------\r |
931 | \r |
932 | void PicoWriteS68k8(u32 a,u8 d)\r |
933 | {\r |
934 | #ifdef __debug_io2\r |
935 | dprintf("s68k w8 : %06x, %02x @%06x", a&0xffffff, d, SekPcS68k);\r |
936 | #endif\r |
937 | \r |
938 | a&=0xffffff;\r |
939 | \r |
940 | // prg RAM\r |
941 | if (a < 0x80000) {\r |
942 | u8 *pm=(u8 *)(Pico_mcd->prg_ram+(a^1));\r |
943 | *pm=d;\r |
944 | return;\r |
945 | }\r |
946 | \r |
672ad671 |
947 | if (a != 0xff0011 && (a&0xff8000) == 0xff0000) // PCM hack\r |
948 | return;\r |
949 | \r |
cc68a136 |
950 | // regs\r |
951 | if ((a&0xfffe00) == 0xff8000) {\r |
cb4a513a |
952 | a &= 0x1ff;\r |
953 | rdprintf("s68k_regs w8: [%02x] %02x @ %06x", a, d, SekPcS68k);\r |
954 | if (a >= 0x50 && a < 0x68)\r |
955 | gfx_cd_write(a&~1, (d<<8)|d);\r |
956 | else s68k_reg_write8(a,d);\r |
cc68a136 |
957 | return;\r |
958 | }\r |
959 | \r |
d0d47c5b |
960 | // word RAM (2M area)\r |
961 | if ((a&0xfc0000)==0x080000) { // 080000-0bffff\r |
962 | dprintf("s68k_wram2M w8: [%06x] %02x @%06x", a, d, SekPc);\r |
963 | if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?\r |
964 | // TODO (decode)\r |
965 | dprintf("(decode)");\r |
966 | } else {\r |
967 | // allow access in any mode, like Gens does\r |
bf098bc5 |
968 | *(u8 *)(Pico_mcd->word_ram+((a^1)&0x3ffff))=d;\r |
d0d47c5b |
969 | }\r |
970 | return;\r |
971 | }\r |
972 | \r |
973 | // word RAM (1M area)\r |
974 | if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff\r |
975 | if (d)\r |
976 | dprintf("s68k_wram1M w8: [%06x] %02x @%06x", a, d, SekPc);\r |
bf098bc5 |
977 | a=((a&0x1fffe)<<1)|(a&1);\r |
978 | if (!(Pico_mcd->s68k_regs[3]&1)) a+=2;\r |
979 | *(u8 *)(Pico_mcd->word_ram+(a^1))=d;\r |
d0d47c5b |
980 | return;\r |
981 | }\r |
982 | \r |
cc68a136 |
983 | dprintf("s68k w8 : %06x, %02x @%06x", a&0xffffff, d, SekPcS68k);\r |
984 | }\r |
985 | \r |
986 | void PicoWriteS68k16(u32 a,u16 d)\r |
987 | {\r |
988 | #ifdef __debug_io2\r |
989 | dprintf("s68k w16: %06x, %04x @%06x", a&0xffffff, d, SekPcS68k);\r |
990 | #endif\r |
991 | \r |
992 | a&=0xfffffe;\r |
993 | \r |
994 | // prg RAM\r |
995 | if (a < 0x80000) {\r |
996 | *(u16 *)(Pico_mcd->prg_ram+a)=d;\r |
997 | return;\r |
998 | }\r |
999 | \r |
1000 | // regs\r |
1001 | if ((a&0xfffe00) == 0xff8000) {\r |
cb4a513a |
1002 | a &= 0x1fe;\r |
1003 | rdprintf("s68k_regs w16: [%02x] %04x @ %06x", a, d, SekPcS68k);\r |
1004 | if (a >= 0x50 && a < 0x68)\r |
1005 | gfx_cd_write(a, d);\r |
1006 | else {\r |
1007 | s68k_reg_write8(a, d>>8);\r |
1008 | s68k_reg_write8(a+1,d&0xff);\r |
1009 | }\r |
cc68a136 |
1010 | return;\r |
1011 | }\r |
1012 | \r |
d0d47c5b |
1013 | // word RAM (2M area)\r |
1014 | if ((a&0xfc0000)==0x080000) { // 080000-0bffff\r |
1015 | dprintf("s68k_wram2M w16: [%06x] %04x @%06x", a, d, SekPc);\r |
1016 | if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?\r |
1017 | // TODO (decode)\r |
1018 | dprintf("(decode)");\r |
1019 | } else {\r |
1020 | // allow access in any mode, like Gens does\r |
1021 | *(u16 *)(Pico_mcd->word_ram+(a&0x3fffe))=d;\r |
1022 | }\r |
1023 | return;\r |
1024 | }\r |
1025 | \r |
1026 | // word RAM (1M area)\r |
1027 | if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff\r |
1028 | if (d)\r |
1029 | dprintf("s68k_wram1M w16: [%06x] %04x @%06x", a, d, SekPc);\r |
bf098bc5 |
1030 | a=((a&0x1fffe)<<1);\r |
1031 | if (!(Pico_mcd->s68k_regs[3]&1)) a+=2;\r |
1032 | *(u16 *)(Pico_mcd->word_ram+a)=d;\r |
d0d47c5b |
1033 | return;\r |
1034 | }\r |
1035 | \r |
cc68a136 |
1036 | dprintf("s68k w16: %06x, %04x @%06x", a&0xffffff, d, SekPcS68k);\r |
1037 | }\r |
1038 | \r |
1039 | void PicoWriteS68k32(u32 a,u32 d)\r |
1040 | {\r |
1041 | #ifdef __debug_io2\r |
1042 | dprintf("s68k w32: %06x, %08x @%06x", a&0xffffff, d, SekPcS68k);\r |
1043 | #endif\r |
1044 | \r |
1045 | a&=0xfffffe;\r |
1046 | \r |
1047 | // prg RAM\r |
1048 | if (a < 0x80000) {\r |
1049 | u16 *pm=(u16 *)(Pico_mcd->prg_ram+a);\r |
1050 | pm[0]=(u16)(d>>16); pm[1]=(u16)d;\r |
1051 | return;\r |
1052 | }\r |
1053 | \r |
1054 | // regs\r |
1055 | if ((a&0xfffe00) == 0xff8000) {\r |
cb4a513a |
1056 | a &= 0x1fe;\r |
1057 | rdprintf("s68k_regs w32: [%02x] %08x @ %06x", a, d, SekPcS68k);\r |
1058 | if (a >= 0x50 && a < 0x68) {\r |
1059 | gfx_cd_write(a, d>>16);\r |
1060 | gfx_cd_write(a+2, d&0xffff);\r |
1061 | } else {\r |
1062 | s68k_reg_write8(a, d>>24);\r |
1063 | s68k_reg_write8(a+1,(d>>16)&0xff);\r |
1064 | s68k_reg_write8(a+2,(d>>8) &0xff);\r |
1065 | s68k_reg_write8(a+3, d &0xff);\r |
1066 | }\r |
cc68a136 |
1067 | return;\r |
1068 | }\r |
1069 | \r |
d0d47c5b |
1070 | // word RAM (2M area)\r |
1071 | if ((a&0xfc0000)==0x080000) { // 080000-0bffff\r |
1072 | dprintf("s68k_wram2M w32: [%06x] %08x @%06x", a, d, SekPc);\r |
1073 | if (Pico_mcd->s68k_regs[3]&4) { // 1M mode?\r |
1074 | // TODO (decode)\r |
1075 | dprintf("(decode)");\r |
1076 | } else {\r |
1077 | // allow access in any mode, like Gens does\r |
1078 | u16 *pm=(u16 *)(Pico_mcd->word_ram+(a&0x3fffe));\r |
1079 | pm[0]=(u16)(d>>16); pm[1]=(u16)d;\r |
1080 | }\r |
1081 | return;\r |
1082 | }\r |
1083 | \r |
1084 | // word RAM (1M area)\r |
1085 | if ((a&0xfe0000)==0x0c0000 && (Pico_mcd->s68k_regs[3]&4)) { // 0c0000-0dffff\r |
bf098bc5 |
1086 | u16 *pm;\r |
d0d47c5b |
1087 | if (d)\r |
1088 | dprintf("s68k_wram1M w32: [%06x] %08x @%06x", a, d, SekPc);\r |
bf098bc5 |
1089 | a=((a&0x1fffe)<<1);\r |
1090 | if (!(Pico_mcd->s68k_regs[3]&1)) a+=2;\r |
1091 | pm=(u16 *)(Pico_mcd->word_ram+a);\r |
1092 | pm[0]=(u16)(d>>16); pm[1]=(u16)d;\r |
d0d47c5b |
1093 | return;\r |
1094 | }\r |
cc68a136 |
1095 | dprintf("s68k w32: %06x, %08x @%06x", a&0xffffff, d, SekPcS68k);\r |
1096 | }\r |
1097 | \r |
1098 | \r |
1099 | \r |
1100 | // -----------------------------------------------------------------\r |
1101 | \r |
1102 | #ifdef EMU_M68K\r |
1103 | unsigned char PicoReadCD8w (unsigned int a) {\r |
1104 | return m68ki_cpu_p == &PicoS68kCPU ? PicoReadS68k8(a) : PicoReadM68k8(a);\r |
1105 | }\r |
1106 | unsigned short PicoReadCD16w(unsigned int a) {\r |
1107 | return m68ki_cpu_p == &PicoS68kCPU ? PicoReadS68k16(a) : PicoReadM68k16(a);\r |
1108 | }\r |
1109 | unsigned int PicoReadCD32w(unsigned int a) {\r |
1110 | return m68ki_cpu_p == &PicoS68kCPU ? PicoReadS68k32(a) : PicoReadM68k32(a);\r |
1111 | }\r |
1112 | void PicoWriteCD8w (unsigned int a, unsigned char d) {\r |
1113 | if (m68ki_cpu_p == &PicoS68kCPU) PicoWriteS68k8(a, d); else PicoWriteM68k8(a, d);\r |
1114 | }\r |
1115 | void PicoWriteCD16w(unsigned int a, unsigned short d) {\r |
1116 | if (m68ki_cpu_p == &PicoS68kCPU) PicoWriteS68k16(a, d); else PicoWriteM68k16(a, d);\r |
1117 | }\r |
1118 | void PicoWriteCD32w(unsigned int a, unsigned int d) {\r |
1119 | if (m68ki_cpu_p == &PicoS68kCPU) PicoWriteS68k32(a, d); else PicoWriteM68k32(a, d);\r |
1120 | }\r |
1121 | \r |
1122 | // these are allowed to access RAM\r |
1123 | unsigned int m68k_read_pcrelative_CD8 (unsigned int a) {\r |
1124 | a&=0xffffff;\r |
1125 | if(m68ki_cpu_p == &PicoS68kCPU) {\r |
1126 | if (a < 0x80000) return *(u8 *)(Pico_mcd->prg_ram+(a^1)); // PRG Ram\r |
1127 | else dprintf("s68k read_pcrel8 @ %06x", a);\r |
1128 | } else {\r |
1129 | if(a<Pico.romsize) return *(u8 *)(Pico.rom+(a^1)); // Rom\r |
1130 | if((a&0xe00000)==0xe00000) return *(u8 *)(Pico.ram+((a^1)&0xffff)); // Ram\r |
1131 | }\r |
1132 | return 0;//(u8) lastread_d;\r |
1133 | }\r |
1134 | unsigned int m68k_read_pcrelative_CD16(unsigned int a) {\r |
1135 | a&=0xffffff;\r |
1136 | if(m68ki_cpu_p == &PicoS68kCPU) {\r |
1137 | if (a < 0x80000) return *(u16 *)(Pico_mcd->prg_ram+(a&~1)); // PRG Ram\r |
1138 | else dprintf("s68k read_pcrel16 @ %06x", a);\r |
1139 | } else {\r |
1140 | if(a<Pico.romsize) return *(u16 *)(Pico.rom+(a&~1)); // Rom\r |
1141 | if((a&0xe00000)==0xe00000) return *(u16 *)(Pico.ram+(a&0xfffe)); // Ram\r |
1142 | }\r |
1143 | return 0;//(u16) lastread_d;\r |
1144 | }\r |
1145 | unsigned int m68k_read_pcrelative_CD32(unsigned int a) {\r |
1146 | a&=0xffffff;\r |
1147 | if(m68ki_cpu_p == &PicoS68kCPU) {\r |
1148 | if (a < 0x80000) { u16 *pm=(u16 *)(Pico_mcd->prg_ram+(a&~1)); return (pm[0]<<16)|pm[1]; } // PRG Ram\r |
1149 | else dprintf("s68k read_pcrel32 @ %06x", a);\r |
1150 | } else {\r |
1151 | if(a<Pico.romsize) { u16 *pm=(u16 *)(Pico.rom+(a&~1)); return (pm[0]<<16)|pm[1]; }\r |
1152 | if((a&0xe00000)==0xe00000) { u16 *pm=(u16 *)(Pico.ram+(a&0xfffe)); return (pm[0]<<16)|pm[1]; } // Ram\r |
1153 | }\r |
1154 | return 0; //lastread_d;\r |
1155 | }\r |
1156 | #endif // EMU_M68K\r |
1157 | \r |