0.0088 release
[picodrive.git] / cpu / Cyclone / Cyclone.h
CommitLineData
cc68a136 1\r
2// Cyclone 68000 Emulator - Header File\r
3\r
0e11c502 4// (c) Copyright 2004 Dave, All rights reserved.\r
5// (c) 2005-2007 notaz\r
cc68a136 6// Cyclone 68000 is free for non-commercial use.\r
7\r
8// For commercial use, separate licencing terms must be obtained.\r
9\r
0e11c502 10\r
11#ifndef __CYCLONE_H__\r
12#define __CYCLONE_H__\r
13\r
cc68a136 14#ifdef __cplusplus\r
15extern "C" {\r
16#endif\r
17\r
18extern int CycloneVer; // Version number of library\r
19\r
20struct Cyclone\r
21{\r
85a36a57 22 unsigned int d[8]; // [r7,#0x00]\r
23 unsigned int a[8]; // [r7,#0x20]\r
0e11c502 24 unsigned int pc; // [r7,#0x40] Memory Base (.membase) + 68k PC\r
85a36a57 25 unsigned char srh; // [r7,#0x44] Status Register high (T_S__III)\r
26 unsigned char unused; // [r7,#0x45] Unused\r
27 unsigned char flags; // [r7,#0x46] Flags (ARM order: ____NZCV) [68k order is XNZVC]\r
28 unsigned char irq; // [r7,#0x47] IRQ level\r
29 unsigned int osp; // [r7,#0x48] Other Stack Pointer (USP/SSP)\r
30 unsigned int xc; // [r7,#0x4c] Extend flag (bit29: ??X? _)\r
0e11c502 31 unsigned int prev_pc; // [r7,#0x50] Set to start address of currently executed opcode + 2 (if enabled in config.h)\r
32 unsigned int reserved;// [r7,#0x54] Reserved for possible future use\r
33 int state_flags; // [r7,#0x58] bit: 0: stopped state, 1: trace state, 2: activity bit, 3: addr error, 4: fatal halt\r
34 int cycles; // [r7,#0x5c] Number of cycles to execute - 1. Updates to cycles left after CycloneRun()\r
85a36a57 35 int membase; // [r7,#0x60] Memory Base (ARM address minus 68000 address)\r
0e11c502 36 unsigned int (*checkpc)(unsigned int pc); // [r7,#0x64] called to recalc Memory Base+pc\r
37 unsigned int (*read8 )(unsigned int a); // [r7,#0x68]\r
38 unsigned int (*read16 )(unsigned int a); // [r7,#0x6c]\r
39 unsigned int (*read32 )(unsigned int a); // [r7,#0x70]\r
cc68a136 40 void (*write8 )(unsigned int a,unsigned char d); // [r7,#0x74]\r
41 void (*write16)(unsigned int a,unsigned short d); // [r7,#0x78]\r
42 void (*write32)(unsigned int a,unsigned int d); // [r7,#0x7c]\r
0e11c502 43 unsigned int (*fetch8 )(unsigned int a); // [r7,#0x80]\r
44 unsigned int (*fetch16)(unsigned int a); // [r7,#0x84]\r
45 unsigned int (*fetch32)(unsigned int a); // [r7,#0x88]\r
46 int (*IrqCallback)(int int_level); // [r7,#0x8c] optional irq callback function, see config.h\r
47 void (*ResetCallback)(void); // [r7,#0x90] if enabled in config.h, calls this whenever RESET opcode is encountered.\r
48 int (*UnrecognizedCallback)(void); // [r7,#0x94] if enabled in config.h, calls this whenever unrecognized opcode is encountered.\r
49 unsigned int internal[6]; // [r7,#0x98] reserved for internal use, do not change.\r
cc68a136 50};\r
51\r
0e11c502 52// Initialize. Used only if Cyclone was compiled with compressed jumptable, see config.h\r
53void CycloneInit(void);\r
cc68a136 54\r
0e11c502 55// Run cyclone. Cycles should be specified in context (pcy->cycles)\r
cc68a136 56void CycloneRun(struct Cyclone *pcy);\r
57\r
0e11c502 58// Utility functions to get and set SR\r
59void CycloneSetSr(struct Cyclone *pcy, unsigned int sr);\r
60unsigned int CycloneGetSr(const struct Cyclone *pcy);\r
61\r
62// Generates irq exception if needed (if pcy->irq > mask).\r
63// Returns cycles used for exception if it was generated, 0 otherwise.\r
64int CycloneFlushIrq(struct Cyclone *pcy);\r
65\r
66// Functions for saving and restoring state.\r
67// CycloneUnpack() uses checkpc(), so it must be initialized.\r
68// save_buffer must point to buffer of 128 (0x80) bytes of size.\r
69void CyclonePack(const struct Cyclone *pcy, void *save_buffer);\r
70void CycloneUnpack(struct Cyclone *pcy, const void *save_buffer);\r
cc68a136 71\r
c008977e 72// genesis: if 1, switch to normal TAS handlers\r
73void CycloneSetRealTAS(int use_real);\r
74\r
0e11c502 75\r
76// These values are special return values for IrqCallback.\r
77\r
78// Causes an interrupt autovector (0x18 + interrupt level) to be taken.\r
79// This happens in a real 68K if VPA or AVEC is asserted during an interrupt\r
80// acknowledge cycle instead of DTACK (the most common situation).\r
81#define CYCLONE_INT_ACK_AUTOVECTOR -1\r
82\r
83// Causes the spurious interrupt vector (0x18) to be taken\r
84// This happens in a real 68K if BERR is asserted during the interrupt\r
85// acknowledge cycle (i.e. no devices responded to the acknowledge).\r
86#define CYCLONE_INT_ACK_SPURIOUS -2\r
87\r
88\r
cc68a136 89#ifdef __cplusplus\r
90} // End of extern "C"\r
91#endif\r
0e11c502 92\r
93#endif // __CYCLONE_H__\r
94\r