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0.0088 release
[picodrive.git] / cpu / Cyclone / Main.cpp
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cc68a136 1\r
2#include "app.h"\r
3\r
4static FILE *AsmFile=NULL;\r
5\r
0e11c502 6static int CycloneVer=0x0088; // Version number of library\r
cc68a136 7int *CyJump=NULL; // Jump table\r
8int ms=USE_MS_SYNTAX; // If non-zero, output in Microsoft ARMASM format\r
9char *Narm[4]={ "b", "h","",""}; // Normal ARM Extensions for operand sizes 0,1,2\r
10char *Sarm[4]={"sb","sh","",""}; // Sign-extend ARM Extensions for operand sizes 0,1,2\r
11int Cycles; // Current cycles for opcode\r
cfb3dfa0 12int pc_dirty; // something changed PC during processing\r
ee5e024c 13int arm_op_count;\r
cc68a136 14\r
15\r
16void ot(const char *format, ...)\r
17{\r
18 va_list valist=NULL;\r
19 int i, len;\r
20\r
21 // notaz: stop me from leaving newlines in the middle of format string\r
22 // and generating bad code\r
23 for(i=0, len=strlen(format); i < len && format[i] != '\n'; i++);\r
24 if(i < len-1 && format[len-1] != '\n') printf("\nWARNING: possible improper newline placement:\n%s\n", format);\r
25\r
b637c56a 26 if (format[0] == ' ' && format[1] == ' ' && format[2] != ' ' && format[2] != '.')\r
27 arm_op_count++;\r
28\r
cc68a136 29 va_start(valist,format);\r
30 if (AsmFile) vfprintf(AsmFile,format,valist);\r
31 va_end(valist);\r
32}\r
33\r
34void ltorg()\r
35{\r
36 if (ms) ot(" LTORG\n");\r
37 else ot(" .ltorg\n");\r
38}\r
39\r
a9a5a6e0 40#if (CYCLONE_FOR_GENESIS == 2)\r
c008977e 41// r12=ptr to tas in table, trashes r0,r1\r
42static void ChangeTAS(int norm)\r
43{\r
44 ot(" ldr r0,=Op4ad0%s\n",norm?"_":"");\r
45 ot(" mov r1,#8\n");\r
46 ot("setrtas_loop%i0%s ;@ 4ad0-4ad7\n",norm,ms?"":":");\r
47 ot(" subs r1,r1,#1\n");\r
48 ot(" str r0,[r12],#4\n");\r
49 ot(" bne setrtas_loop%i0\n",norm);\r
50 ot(" ldr r0,=Op4ad8%s\n",norm?"_":"");\r
51 ot(" mov r1,#7\n");\r
52 ot("setrtas_loop%i1%s ;@ 4ad8-4ade\n",norm,ms?"":":");\r
53 ot(" subs r1,r1,#1\n");\r
54 ot(" str r0,[r12],#4\n");\r
55 ot(" bne setrtas_loop%i1\n",norm);\r
56 ot(" ldr r0,=Op4adf%s\n",norm?"_":"");\r
57 ot(" str r0,[r12],#4\n");\r
58 ot(" ldr r0,=Op4ae0%s\n",norm?"_":"");\r
59 ot(" mov r1,#7\n");\r
60 ot("setrtas_loop%i2%s ;@ 4ae0-4ae6\n",norm,ms?"":":");\r
61 ot(" subs r1,r1,#1\n");\r
62 ot(" str r0,[r12],#4\n");\r
63 ot(" bne setrtas_loop%i2\n",norm);\r
64 ot(" ldr r0,=Op4ae7%s\n",norm?"_":"");\r
65 ot(" str r0,[r12],#4\n");\r
66 ot(" ldr r0,=Op4ae8%s\n",norm?"_":"");\r
67 ot(" mov r1,#8\n");\r
68 ot("setrtas_loop%i3%s ;@ 4ae8-4aef\n",norm,ms?"":":");\r
69 ot(" subs r1,r1,#1\n");\r
70 ot(" str r0,[r12],#4\n");\r
71 ot(" bne setrtas_loop%i3\n",norm);\r
72 ot(" ldr r0,=Op4af0%s\n",norm?"_":"");\r
73 ot(" mov r1,#8\n");\r
74 ot("setrtas_loop%i4%s ;@ 4af0-4af7\n",norm,ms?"":":");\r
75 ot(" subs r1,r1,#1\n");\r
76 ot(" str r0,[r12],#4\n");\r
77 ot(" bne setrtas_loop%i4\n",norm);\r
78 ot(" ldr r0,=Op4af8%s\n",norm?"_":"");\r
79 ot(" str r0,[r12],#4\n");\r
80 ot(" ldr r0,=Op4af9%s\n",norm?"_":"");\r
81 ot(" str r0,[r12],#4\n");\r
82}\r
83#endif\r
84\r
0e11c502 85#if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO\r
86static void AddressErrorWrapper(char rw, char *dataprg, int iw)\r
cc68a136 87{\r
0e11c502 88 ot("ExceptionAddressError_%c_%s%s\n", rw, dataprg, ms?"":":");\r
89 ot(" ldr r1,[r7,#0x44]\n");\r
90 ot(" mov r10,#0x%02x\n", iw);\r
91 ot(" mov r11,r0\n");\r
92 ot(" tst r1,#0x20\n");\r
93 ot(" orrne r10,r10,#4\n");\r
94 ot(" b ExceptionAddressError\n");\r
cc68a136 95 ot("\n");\r
cc68a136 96}\r
0e11c502 97#endif\r
cc68a136 98\r
cfb3dfa0 99void FlushPC(void)\r
100{\r
101#if MEMHANDLERS_NEED_PC\r
102 if (pc_dirty)\r
103 ot(" str r4,[r7,#0x40] ;@ Save PC\n");\r
104#endif\r
105 pc_dirty = 0;\r
106}\r
107\r
cc68a136 108static void PrintFramework()\r
109{\r
0e11c502 110 int state_flags_to_check = 1; // stopped\r
111#if EMULATE_TRACE\r
112 state_flags_to_check |= 2; // tracing\r
113#endif\r
114#if EMULATE_HALT\r
115 state_flags_to_check |= 0x10; // halted\r
116#endif\r
117\r
cc68a136 118 ot(";@ --------------------------- Framework --------------------------\n");\r
119 if (ms) ot("CycloneRun\n");\r
120 else ot("CycloneRun:\n");\r
121\r
122 ot(" stmdb sp!,{r4-r11,lr}\n");\r
123\r
124 ot(" mov r7,r0 ;@ r7 = Pointer to Cpu Context\n");\r
125 ot(" ;@ r0-3 = Temporary registers\n");\r
126 ot(" ldrb r9,[r7,#0x46] ;@ r9 = Flags (NZCV)\n");\r
7336a99a 127 ot(" ldr r6,=CycloneJumpTab ;@ r6 = Opcode Jump table\n");\r
cc68a136 128 ot(" ldr r5,[r7,#0x5c] ;@ r5 = Cycles\n");\r
129 ot(" ldr r4,[r7,#0x40] ;@ r4 = Current PC + Memory Base\n");\r
130 ot(" ;@ r8 = Current Opcode\n");\r
66fdc0f0 131 ot(" ldr r1,[r7,#0x44] ;@ Get SR high T_S__III and irq level\n");\r
cc68a136 132 ot(" mov r9,r9,lsl #28 ;@ r9 = Flags 0xf0000000, cpsr format\n");\r
133 ot(" ;@ r10 = Source value / Memory Base\n");\r
134 ot("\n");\r
0e11c502 135#if (CYCLONE_FOR_GENESIS == 2) || EMULATE_TRACE\r
136 ot(" mov r2,#0\n");\r
137 ot(" str r2,[r7,#0x98] ;@ clear custom CycloneEnd\n");\r
138#endif\r
cc68a136 139 ot(";@ CheckInterrupt:\n");\r
66fdc0f0 140 ot(" movs r0,r1,lsr #24 ;@ Get IRQ level\n"); // same as ldrb r0,[r7,#0x47]\r
cc68a136 141 ot(" beq NoInts0\n");\r
142 ot(" cmp r0,#6 ;@ irq>6 ?\n");\r
cc68a136 143 ot(" andle r1,r1,#7 ;@ Get interrupt mask\n");\r
144 ot(" cmple r0,r1 ;@ irq<=6: Is irq<=mask ?\n");\r
ee5e024c 145 ot(" bgt CycloneDoInterrupt\n");\r
cc68a136 146 ot("NoInts0%s\n", ms?"":":");\r
147 ot("\n");\r
0e11c502 148 ot(";@ Check if our processor is in special state\n");\r
149 ot(";@ and jump to opcode handler if not\n");\r
150 ot(" ldr r0,[r7,#0x58] ;@ state_flags\n");\r
cc68a136 151 ot(" ldrh r8,[r4],#2 ;@ Fetch first opcode\n");\r
0e11c502 152 ot(" tst r0,#0x%02x ;@ special state?\n", state_flags_to_check);\r
153 ot(" ldreq pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r
154 ot("\n");\r
155 ot("CycloneSpecial%s\n", ms?"":":");\r
156#if EMULATE_TRACE\r
157 ot(" tst r0,#2 ;@ tracing?\n");\r
158 ot(" bne CycloneDoTrace\n");\r
159#endif\r
160 ot(";@ stopped or halted\n");\r
161 ot(" mov r5,#0\n");\r
162 ot(" str r5,[r7,#0x5C] ;@ eat all cycles\n");\r
163 ot(" ldmia sp!,{r4-r11,pc} ;@ we are stopped, do nothing!\n");\r
cc68a136 164 ot("\n");\r
165 ot("\n");\r
166\r
167 ot(";@ We come back here after execution\n");\r
168 ot("CycloneEnd%s\n", ms?"":":");\r
169 ot(" sub r4,r4,#2\n");\r
170 ot("CycloneEndNoBack%s\n", ms?"":":");\r
0e11c502 171#if (CYCLONE_FOR_GENESIS == 2) || EMULATE_TRACE\r
172 ot(" ldr r1,[r7,#0x98]\n");\r
cc68a136 173 ot(" mov r9,r9,lsr #28\n");\r
7336a99a 174 ot(" tst r1,r1\n");\r
175 ot(" bxne r1 ;@ jump to alternative CycloneEnd\n");\r
176#else\r
177 ot(" mov r9,r9,lsr #28\n");\r
178#endif\r
cc68a136 179 ot(" str r4,[r7,#0x40] ;@ Save Current PC + Memory Base\n");\r
180 ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");\r
181 ot(" strb r9,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r
182 ot(" ldmia sp!,{r4-r11,pc}\n");\r
0e11c502 183 ltorg();\r
cc68a136 184 ot("\n");\r
cc68a136 185 ot("\n");\r
186\r
0e11c502 187 ot("CycloneInit%s\n", ms?"":":");\r
cc68a136 188#if COMPRESS_JUMPTABLE\r
0e11c502 189 ot(";@ decompress jump table\n");\r
190 ot(" ldr r12,=CycloneJumpTab\n");\r
191 ot(" add r0,r12,#0xe000*4 ;@ ctrl code pointer\n");\r
192 ot(" ldr r1,[r0,#-4]\n");\r
193 ot(" tst r1,r1\n");\r
194 ot(" movne pc,lr ;@ already uncompressed\n");\r
195 ot(" add r3,r12,#0xa000*4 ;@ handler table pointer, r12=dest\n");\r
196 ot("unc_loop%s\n", ms?"":":");\r
197 ot(" ldrh r1,[r0],#2\n");\r
198 ot(" and r2,r1,#0xf\n");\r
199 ot(" bic r1,r1,#0xf\n");\r
200 ot(" ldr r1,[r3,r1,lsr #2] ;@ r1=handler\n");\r
201 ot(" cmp r2,#0xf\n");\r
202 ot(" addeq r2,r2,#1 ;@ 0xf is really 0x10\n");\r
203 ot(" tst r2,r2\n");\r
204 ot(" ldreqh r2,[r0],#2 ;@ counter is in next word\n");\r
205 ot(" tst r2,r2\n");\r
206 ot(" beq unc_finish ;@ done decompressing\n");\r
207 ot(" tst r1,r1\n");\r
208 ot(" addeq r12,r12,r2,lsl #2 ;@ 0 handler means we should skip those bytes\n");\r
209 ot(" beq unc_loop\n");\r
210 ot("unc_loop_in%s\n", ms?"":":");\r
211 ot(" subs r2,r2,#1\n");\r
212 ot(" str r1,[r12],#4\n");\r
213 ot(" bgt unc_loop_in\n");\r
214 ot(" b unc_loop\n");\r
215 ot("unc_finish%s\n", ms?"":":");\r
216 ot(" ldr r12,=CycloneJumpTab\n");\r
217 ot(" ;@ set a-line and f-line handlers\n");\r
218 ot(" add r0,r12,#0xa000*4\n");\r
219 ot(" ldr r1,[r0,#4] ;@ a-line handler\n");\r
220 ot(" ldr r3,[r0,#8] ;@ f-line handler\n");\r
221 ot(" mov r2,#0x1000\n");\r
222 ot("unc_fill3%s\n", ms?"":":");\r
223 ot(" subs r2,r2,#1\n");\r
224 ot(" str r1,[r0],#4\n");\r
225 ot(" bgt unc_fill3\n");\r
226 ot(" add r0,r12,#0xf000*4\n");\r
227 ot(" mov r2,#0x1000\n");\r
228 ot("unc_fill4%s\n", ms?"":":");\r
229 ot(" subs r2,r2,#1\n");\r
230 ot(" str r3,[r0],#4\n");\r
231 ot(" bgt unc_fill4\n");\r
232 ot(" bx lr\n");\r
233 ltorg();\r
cc68a136 234#else\r
0e11c502 235 ot(";@ do nothing\n");\r
236 ot(" bx lr\n");\r
cc68a136 237#endif\r
0e11c502 238 ot("\n");\r
239\r
240 // --------------\r
85a36a57 241 // 68k: XNZVC, ARM: NZCV\r
0e11c502 242 ot("CycloneSetSr%s\n", ms?"":":");\r
cc68a136 243 ot(" mov r2,r1,lsr #8\n");\r
0e11c502 244// ot(" ldrb r3,[r0,#0x44] ;@ get SR high\n");\r
245// ot(" eor r3,r3,r2\n");\r
246// ot(" tst r3,#0x20\n");\r
247#if EMULATE_TRACE\r
248 ot(" and r2,r2,#0xa7 ;@ only defined bits\n");\r
249#else\r
250 ot(" and r2,r2,#0x27 ;@ only defined bits\n");\r
251#endif\r
cc68a136 252 ot(" strb r2,[r0,#0x44] ;@ set SR high\n");\r
85a36a57 253 ot(" mov r2,r1,lsl #25\n");\r
254 ot(" str r2,[r0,#0x4c] ;@ the X flag\n");\r
cc68a136 255 ot(" bic r2,r1,#0xf3\n");\r
256 ot(" tst r1,#1\n");\r
257 ot(" orrne r2,r2,#2\n");\r
258 ot(" tst r1,#2\n");\r
259 ot(" orrne r2,r2,#1\n");\r
260 ot(" strb r2,[r0,#0x46] ;@ flags\n");\r
261 ot(" bx lr\n");\r
262 ot("\n");\r
263\r
0e11c502 264 // --------------\r
265 ot("CycloneGetSr%s\n", ms?"":":");\r
cc68a136 266 ot(" ldrb r1,[r0,#0x46] ;@ flags\n");\r
267 ot(" bic r2,r1,#0xf3\n");\r
268 ot(" tst r1,#1\n");\r
269 ot(" orrne r2,r2,#2\n");\r
270 ot(" tst r1,#2\n");\r
271 ot(" orrne r2,r2,#1\n");\r
85a36a57 272 ot(" ldr r1,[r0,#0x4c] ;@ the X flag\n");\r
273 ot(" tst r1,#0x20000000\n");\r
cc68a136 274 ot(" orrne r2,r2,#0x10\n");\r
275 ot(" ldrb r1,[r0,#0x44] ;@ the SR high\n");\r
276 ot(" orr r0,r2,r1,lsl #8\n");\r
277 ot(" bx lr\n");\r
278 ot("\n");\r
279\r
0e11c502 280 // --------------\r
281 ot("CyclonePack%s\n", ms?"":":");\r
282 ot(" stmfd sp!,{r4,r5,lr}\n");\r
283 ot(" mov r4,r0\n");\r
284 ot(" mov r5,r1\n");\r
285 ot(" mov r3,#16\n");\r
286 ot(";@ 0x00-0x3f: DA registers\n");\r
287 ot("c_pack_loop%s\n",ms?"":":");\r
288 ot(" ldr r1,[r0],#4\n");\r
289 ot(" subs r3,r3,#1\n");\r
290 ot(" str r1,[r5],#4\n");\r
291 ot(" bne c_pack_loop\n");\r
292 ot(";@ 0x40: PC\n");\r
293 ot(" ldr r0,[r4,#0x40] ;@ PC + Memory Base\n");\r
294 ot(" ldr r1,[r4,#0x60] ;@ Memory base\n");\r
295 ot(" sub r0,r0,r1\n");\r
296 ot(" str r0,[r5],#4\n");\r
297 ot(";@ 0x44: SR\n");\r
298 ot(" mov r0,r4\n");\r
299 ot(" bl CycloneGetSr\n");\r
300 ot(" strh r0,[r5],#2\n");\r
301 ot(";@ 0x46: IRQ level\n");\r
302 ot(" ldrb r0,[r4,#0x47]\n");\r
303 ot(" strb r0,[r5],#2\n");\r
304 ot(";@ 0x48: other SP\n");\r
305 ot(" ldr r0,[r4,#0x48]\n");\r
306 ot(" str r0,[r5],#4\n");\r
307 ot(";@ 0x4c: CPU state flags\n");\r
308 ot(" ldr r0,[r4,#0x58]\n");\r
309 ot(" str r0,[r5],#4\n");\r
310 ot(" ldmfd sp!,{r4,r5,pc}\n");\r
311 ot("\n");\r
312\r
313 // --------------\r
314 ot("CycloneUnpack%s\n", ms?"":":");\r
315 ot(" stmfd sp!,{r4,r5,lr}\n");\r
316 ot(" mov r4,r0\n");\r
317 ot(" mov r5,r1\n");\r
318 ot(" mov r3,#16\n");\r
319 ot(";@ 0x00-0x3f: DA registers\n");\r
320 ot("c_unpack_loop%s\n",ms?"":":");\r
321 ot(" ldr r1,[r5],#4\n");\r
322 ot(" subs r3,r3,#1\n");\r
323 ot(" str r1,[r0],#4\n");\r
324 ot(" bne c_unpack_loop\n");\r
325 ot(";@ 0x40: PC\n");\r
326 ot(" ldr r0,[r5],#4 ;@ PC\n");\r
327#if USE_CHECKPC_CALLBACK\r
328 ot(" mov r1,#0\n");\r
329 ot(" str r1,[r4,#0x60] ;@ Memory base\n");\r
330 ot(" mov lr,pc\n");\r
331 ot(" ldr pc,[r4,#0x64] ;@ Call checkpc()\n");\r
332#else\r
333 ot(" ldr r1,[r4,#0x60] ;@ Memory base\n");\r
334 ot(" add r0,r0,r1 ;@ r0 = Memory Base + New PC\n");\r
335#endif\r
336 ot(" str r0,[r4,#0x40] ;@ PC + Memory Base\n");\r
337 ot(";@ 0x44: SR\n");\r
338 ot(" ldrh r1,[r5],#2\n");\r
339 ot(" mov r0,r4\n");\r
340 ot(" bl CycloneSetSr\n");\r
341 ot(";@ 0x46: IRQ level\n");\r
342 ot(" ldrb r0,[r5],#2\n");\r
343 ot(" strb r0,[r4,#0x47]\n");\r
344 ot(";@ 0x48: other SP\n");\r
345 ot(" ldr r0,[r5],#4\n");\r
346 ot(" str r0,[r4,#0x48]\n");\r
347 ot(";@ 0x4c: CPU state flags\n");\r
348 ot(" ldr r0,[r5],#4\n");\r
349 ot(" str r0,[r4,#0x58]\n");\r
350 ot(" ldmfd sp!,{r4,r5,pc}\n");\r
351 ot("\n");\r
352\r
353 // --------------\r
354 ot("CycloneFlushIrq%s\n", ms?"":":");\r
355 ot(" ldr r1,[r0,#0x44] ;@ Get SR high T_S__III and irq level\n");\r
356 ot(" mov r2,r1,lsr #24 ;@ Get IRQ level\n"); // same as ldrb r0,[r7,#0x47]\r
357 ot(" cmp r2,#6 ;@ irq>6 ?\n");\r
358 ot(" andle r1,r1,#7 ;@ Get interrupt mask\n");\r
359 ot(" cmple r2,r1 ;@ irq<=6: Is irq<=mask ?\n");\r
360 ot(" movle r0,#0\n");\r
361 ot(" bxle lr ;@ no ints\n");\r
362 ot("\n");\r
363 ot(" stmdb sp!,{r4,r5,r7-r11,lr}\n");\r
364 ot(" mov r7,r0\n");\r
365 ot(" mov r0,r2\n");\r
366 ot(" ldrb r9,[r7,#0x46] ;@ r9 = Flags (NZCV)\n");\r
367 ot(" mov r5,#0\n");\r
368 ot(" ldr r4,[r7,#0x40] ;@ r4 = Current PC + Memory Base\n");\r
369 ot(" mov r9,r9,lsl #28 ;@ r9 = Flags 0xf0000000, cpsr format\n");\r
370 ot(" adr r2,CycloneFlushIrqEnd\n");\r
371 ot(" str r2,[r7,#0x98] ;@ set custom CycloneEnd\n");\r
372 ot(" b CycloneDoInterrupt\n");\r
373 ot("\n");\r
374 ot("CycloneFlushIrqEnd%s\n", ms?"":":");\r
375 ot(" rsb r0,r5,#0\n");\r
376 ot(" str r4,[r7,#0x40] ;@ Save Current PC + Memory Base\n");\r
377 ot(" strb r9,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r
378 ot(" ldmia sp!,{r4,r5,r7-r11,lr}\n");\r
379 ot(" bx lr\n");\r
380 ot("\n");\r
381 ot("\n");\r
382\r
383 // --------------\r
384 ot("CycloneSetRealTAS%s\n", ms?"":":");\r
a9a5a6e0 385#if (CYCLONE_FOR_GENESIS == 2)\r
c008977e 386 ot(" ldr r12,=CycloneJumpTab\n");\r
387 ot(" tst r0,r0\n");\r
388 ot(" add r12,r12,#0x4a00*4\n");\r
389 ot(" add r12,r12,#0x00d0*4\n");\r
390 ot(" beq setrtas_off\n");\r
391 ChangeTAS(1);\r
392 ot(" bx lr\n");\r
393 ot("setrtas_off%s\n",ms?"":":");\r
394 ChangeTAS(0);\r
395 ot(" bx lr\n");\r
396 ltorg();\r
c008977e 397#else\r
398 ot(" bx lr\n");\r
c008977e 399#endif\r
0e11c502 400 ot("\n");\r
c008977e 401\r
0e11c502 402 // --------------\r
403 ot(";@ DoInterrupt - r0=IRQ level\n");\r
ee5e024c 404 ot("CycloneDoInterruptGoBack%s\n", ms?"":":");\r
405 ot(" sub r4,r4,#2\n");\r
7336a99a 406 ot("CycloneDoInterrupt%s\n", ms?"":":");\r
0e11c502 407 ot(" bic r8,r8,#0xff000000\n");\r
408 ot(" orr r8,r8,r0,lsl #29 ;@ abuse r8\n");\r
409\r
410 // Steps are from "M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL", p. 6-4\r
411 // but their order is based on http://pasti.fxatari.com/68kdocs/68kPrefetch.html\r
412 // 1. Make a temporary copy of the status register and set the status register for exception processing.\r
413 ot(" ldr r2,[r7,#0x58] ;@ state flags\n");\r
414 ot(" and r0,r0,#7\n");\r
415 ot(" orr r3,r0,#0x20 ;@ Supervisor mode + IRQ level\n");\r
416 ot(" bic r2,r2,#3 ;@ clear stopped and trace states\n");\r
417#if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO\r
418 ot(" orr r2,r2,#4 ;@ set activity bit: 'not processing instruction'\n");\r
419#endif\r
cc68a136 420 ot(" str r2,[r7,#0x58]\n");\r
0e11c502 421 ot(" ldrb r10,[r7,#0x44] ;@ Get old SR high\n");\r
422 ot(" strb r3,[r7,#0x44] ;@ Put new SR high\n");\r
423 ot("\n");\r
424\r
425 // 3. Save the current processor context.\r
426 ot(" ldr r1,[r7,#0x60] ;@ Get Memory base\n");\r
427 ot(" ldr r11,[r7,#0x3c] ;@ Get A7\n");\r
428 ot(" tst r10,#0x20\n");\r
429 ot(";@ get our SP:\n");\r
430 ot(" ldreq r2,[r7,#0x48] ;@ ...or OSP as our stack pointer\n");\r
431 ot(" streq r11,[r7,#0x48]\n");\r
432 ot(" moveq r11,r2\n");\r
433 ot(";@ Push old PC onto stack\n");\r
434 ot(" sub r0,r11,#4 ;@ Predecremented A7\n");\r
435 ot(" sub r1,r4,r1 ;@ r1 = Old PC\n");\r
436 MemHandler(1,2);\r
437 ot(";@ Push old SR:\n");\r
438 ot(" ldr r0,[r7,#0x4c] ;@ X bit\n");\r
439 ot(" mov r1,r9,lsr #28 ;@ ____NZCV\n");\r
440 ot(" eor r2,r1,r1,ror #1 ;@ Bit 0=C^V\n");\r
441 ot(" tst r2,#1 ;@ 1 if C!=V\n");\r
442 ot(" eorne r1,r1,#3 ;@ ____NZVC\n");\r
443 ot(" and r0,r0,#0x20000000\n");\r
444 ot(" orr r1,r1,r0,lsr #25 ;@ ___XNZVC\n");\r
445 ot(" orr r1,r1,r10,lsl #8 ;@ Include old SR high\n");\r
446 ot(" sub r0,r11,#6 ;@ Predecrement A7\n");\r
447 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
448 MemHandler(1,1,0,0); // already checked for address error by prev MemHandler\r
cc68a136 449 ot("\n");\r
0e11c502 450\r
451 // 2. Obtain the exception vector.\r
452 ot(" mov r11,r8,lsr #29\n");\r
453 ot(" mov r0,r11\n");\r
cc68a136 454#if USE_INT_ACK_CALLBACK\r
0e11c502 455 ot(";@ call IrqCallback if it is defined\n");\r
cc68a136 456#if INT_ACK_NEEDS_STUFF\r
457 ot(" str r4,[r7,#0x40] ;@ Save PC\n");\r
458 ot(" mov r1,r9,lsr #28\n");\r
459 ot(" strb r1,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r
460 ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");\r
461#endif\r
0e11c502 462 ot(" ldr r3,[r7,#0x8c] ;@ IrqCallback\n");\r
463 ot(" add lr,pc,#4*3\n");\r
464 ot(" tst r3,r3\n");\r
465 ot(" streqb r3,[r7,#0x47] ;@ just clear IRQ if there is no callback\n");\r
466 ot(" mvneq r0,#0 ;@ and simulate -1 return\n");\r
467 ot(" bxne r3\n");\r
468#if INT_ACK_CHANGES_CYCLES\r
cc68a136 469 ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");\r
cc68a136 470#endif\r
0e11c502 471 ot(";@ get IRQ vector address:\n");\r
472 ot(" cmn r0,#1 ;@ returned -1?\n");\r
473 ot(" addeq r0,r11,#0x18 ;@ use autovector then\n");\r
474 ot(" cmn r0,#2 ;@ returned -2?\n"); // should be safe as above add should never result in -2\r
475 ot(" moveq r0,#0x18 ;@ use spurious interrupt then\n");\r
ee5e024c 476#else // !USE_INT_ACK_CALLBACK\r
cc68a136 477 ot(";@ Clear irq:\n");\r
0e11c502 478 ot(" mov r2,#0\n");\r
ee5e024c 479 ot(" strb r2,[r7,#0x47]\n");\r
0e11c502 480 ot(" add r0,r0,#0x18 ;@ use autovector\n");\r
481#endif\r
482 ot(" mov r0,r0,lsl #2 ;@ get vector address\n");\r
483 ot("\n");\r
484 ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");\r
485 ot(";@ Read IRQ Vector:\n");\r
486 MemHandler(0,2,0,0);\r
487 ot(" tst r0,r0 ;@ uninitialized int vector?\n");\r
488 ot(" moveq r0,#0x3c\n");\r
489 ot(" moveq lr,pc\n");\r
490 ot(" ldreq pc,[r7,#0x70] ;@ Call read32(r0) handler\n");\r
491#if USE_CHECKPC_CALLBACK\r
492 ot(" add lr,pc,#4\n");\r
493 ot(" add r0,r0,r10 ;@ r0 = Memory Base + New PC\n");\r
494 ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r
495 #if EMULATE_ADDRESS_ERRORS_JUMP\r
496 ot(" mov r4,r0\n");\r
497 #else\r
498 ot(" bic r4,r0,#1\n");\r
499 #endif\r
500#else\r
501 ot(" add r4,r0,r10 ;@ r4 = Memory Base + New PC\n");\r
502 #if EMULATE_ADDRESS_ERRORS_JUMP\r
503 ot(" bic r4,r4,#1\n");\r
504 #endif\r
505#endif\r
506 ot("\n");\r
507\r
508 // 4. Obtain a new context and resume instruction processing.\r
509 // note: the obtain part was already done in previous steps\r
510#if EMULATE_ADDRESS_ERRORS_JUMP\r
511 ot(" tst r4,#1\n");\r
512 ot(" bne ExceptionAddressError_r_prg_r4\n");\r
cc68a136 513#endif\r
ee5e024c 514 ot(" ldrh r8,[r4],#2 ;@ Fetch next opcode\n");\r
515 ot(" subs r5,r5,#44 ;@ Subtract cycles\n");\r
516 ot(" ldrge pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r
517 ot(" b CycloneEnd\n");\r
cc68a136 518 ot("\n");\r
519 \r
0e11c502 520 // --------------\r
521 // trashes all temp regs\r
cc68a136 522 ot("Exception%s\n", ms?"":":");\r
0e11c502 523 ot(" ;@ Cause an Exception - Vector number in r0\n");\r
524 ot(" mov r11,lr ;@ Preserve ARM return address\n");\r
525 ot(" bic r8,r8,#0xff000000\n");\r
526 ot(" orr r8,r8,r0,lsl #24 ;@ abuse r8\n");\r
527\r
528 // 1. Make a temporary copy of the status register and set the status register for exception processing.\r
529 ot(" ldr r10,[r7,#0x44] ;@ Get old SR high\n");\r
530 ot(" ldr r2,[r7,#0x58] ;@ state flags\n");\r
531 ot(" and r3,r10,#0x27 ;@ clear trace and unused flags\n");\r
532 ot(" orr r3,r3,#0x20 ;@ set supervisor mode\n");\r
533 ot(" bic r2,r2,#3 ;@ clear stopped and trace states\n");\r
534 ot(" str r2,[r7,#0x58]\n");\r
535 ot(" strb r3,[r7,#0x44] ;@ Put new SR high\n");\r
536 ot("\n");\r
537\r
538 // 3. Save the current processor context.\r
539 ot(" ldr r0,[r7,#0x3c] ;@ Get A7\n");\r
540 ot(" tst r10,#0x20\n");\r
541 ot(";@ get our SP:\n");\r
542 ot(" ldreq r2,[r7,#0x48] ;@ ...or OSP as our stack pointer\n");\r
543 ot(" streq r0,[r7,#0x48]\n");\r
544 ot(" moveq r0,r2\n");\r
545 ot(";@ Push old PC onto stack\n");\r
546 ot(" ldr r1,[r7,#0x60] ;@ Get Memory base\n");\r
547 ot(" sub r0,r0,#4 ;@ Predecremented A7\n");\r
548 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
549 ot(" sub r1,r4,r1 ;@ r1 = Old PC\n");\r
550 MemHandler(1,2);\r
551 ot(";@ Push old SR:\n");\r
552 ot(" ldr r0,[r7,#0x4c] ;@ X bit\n");\r
553 ot(" mov r1,r9,lsr #28 ;@ ____NZCV\n");\r
554 ot(" eor r2,r1,r1,ror #1 ;@ Bit 0=C^V\n");\r
555 ot(" tst r2,#1 ;@ 1 if C!=V\n");\r
556 ot(" eorne r1,r1,#3 ;@ ____NZVC\n");\r
557 ot(" and r0,r0,#0x20000000\n");\r
558 ot(" orr r1,r1,r0,lsr #25 ;@ ___XNZVC\n");\r
559 ot(" ldr r0,[r7,#0x3c] ;@ A7\n");\r
560 ot(" orr r1,r1,r10,lsl #8 ;@ Include SR high\n");\r
561 ot(" sub r0,r0,#2 ;@ Predecrement A7\n");\r
562 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
563 MemHandler(1,1,0,0);\r
564 ot("\n");\r
565\r
566 // 2. Obtain the exception vector\r
567 ot(";@ Read Exception Vector:\n");\r
568 ot(" mov r0,r8,lsr #24\n");\r
569 ot(" mov r0,r0,lsl #2\n");\r
570 MemHandler(0,2,0,0);\r
571 ot(" ldr r3,[r7,#0x60] ;@ Get Memory base\n");\r
572#if USE_CHECKPC_CALLBACK\r
573 ot(" add lr,pc,#4\n");\r
574 ot(" add r0,r0,r3 ;@ r0 = Memory Base + New PC\n");\r
575 ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r
576 #if EMULATE_ADDRESS_ERRORS_JUMP\r
577 ot(" mov r4,r0\n");\r
578 #else\r
579 ot(" bic r4,r0,#1\n");\r
580 #endif\r
581#else\r
582 ot(" add r4,r0,r3 ;@ r4 = Memory Base + New PC\n");\r
583 #if EMULATE_ADDRESS_ERRORS_JUMP\r
584 ot(" bic r4,r4,#1\n");\r
585 #endif\r
586#endif\r
587 ot("\n");\r
588\r
589 // 4. Resume execution.\r
590#if EMULATE_ADDRESS_ERRORS_JUMP\r
591 ot(" tst r4,#1\n");\r
592 ot(" bne ExceptionAddressError_r_prg_r4\n");\r
593#endif\r
594 ot(" bx r11 ;@ Return\n");\r
595 ot("\n");\r
596\r
597 // --------------\r
598#if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO\r
599 // first some wrappers: I see no point inlining this code,\r
600 // as it will be executed in really rare cases.\r
601 AddressErrorWrapper('r', "data", 0x11);\r
602 AddressErrorWrapper('r', "prg", 0x12);\r
603 AddressErrorWrapper('w', "data", 0x01);\r
604 // there are no program writes\r
605 // cpu space is only for bus errors?\r
606 ot("ExceptionAddressError_r_prg_r4%s\n", ms?"":":");\r
607 ot(" ldr r1,[r7,#0x44]\n");\r
608 ot(" ldr r3,[r7,#0x60] ;@ Get Memory base\n");\r
609 ot(" mov r10,#0x12\n");\r
610 ot(" sub r11,r4,r3\n");\r
611 ot(" tst r1,#0x20\n");\r
612 ot(" orrne r10,r10,#4\n");\r
613 ot("\n");\r
614\r
615 ot("ExceptionAddressError%s\n", ms?"":":");\r
616 ot(";@ r10 - info word (without instruction/not bit), r11 - faulting address\n");\r
617\r
618 // 1. Make a temporary copy of the status register and set the status register for exception processing.\r
619 ot(" ldrb r0,[r7,#0x44] ;@ Get old SR high\n");\r
620 ot(" ldr r2,[r7,#0x58] ;@ state flags\n");\r
621 ot(" and r3,r0,#0x27 ;@ clear trace and unused flags\n");\r
622 ot(" orr r3,r3,#0x20 ;@ set supervisor mode\n");\r
623 ot(" strb r3,[r7,#0x44] ;@ Put new SR high\n");\r
624 ot(" bic r2,r2,#3 ;@ clear stopped and trace states\n");\r
625 ot(" tst r2,#4\n");\r
626 ot(" orrne r10,r10,#8 ;@ complete info word\n");\r
627 ot(" orr r2,r2,#4 ;@ set activity bit: 'not processing instruction'\n");\r
628#if EMULATE_HALT\r
629 ot(" tst r2,#8\n");\r
630 ot(" orrne r2,r2,#0x10 ;@ HALT\n");\r
631 ot(" orr r2,r2,#8 ;@ processing address error\n");\r
632 ot(" str r2,[r7,#0x58]\n");\r
633 ot(" movne r5,#0\n");\r
634 ot(" bne CycloneEndNoBack ;@ bye bye\n");\r
635#else\r
636 ot(" str r2,[r7,#0x58]\n");\r
637#endif\r
638 ot(" and r9,r9,#0xf0000000\n");\r
639 ot(" orr r9,r9,r0,lsl #4 ;@ some preparations for SR push\n");\r
640 ot("\n");\r
641\r
642 // 3. Save the current processor context + additional information.\r
643 ot(" ldr r0,[r7,#0x3c] ;@ Get A7\n");\r
644 ot(" tst r9,#0x200\n");\r
645 ot(";@ get our SP:\n");\r
646 ot(" ldreq r2,[r7,#0x48] ;@ ...or OSP as our stack pointer\n");\r
647 ot(" streq r0,[r7,#0x48]\n");\r
648 ot(" moveq r0,r2\n");\r
649 // PC\r
650 ot(";@ Push old PC onto stack\n");\r
651 ot(" ldr r1,[r7,#0x60] ;@ Get Memory base\n");\r
652 ot(" sub r0,r0,#4 ;@ Predecremented A7\n");\r
653 ot(" sub r1,r4,r1 ;@ r1 = Old PC\n");\r
654 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
655 MemHandler(1,2,0,EMULATE_HALT);\r
656 // SR\r
657 ot(";@ Push old SR:\n");\r
658 ot(" ldr r0,[r7,#0x4c] ;@ X bit\n");\r
659 ot(" mov r1,r9,ror #28 ;@ ____NZCV\n");\r
660 ot(" eor r2,r1,r1,ror #1 ;@ Bit 0=C^V\n");\r
661 ot(" tst r2,#1 ;@ 1 if C!=V\n");\r
662 ot(" eorne r1,r1,#3 ;@ ____NZVC\n");\r
663 ot(" and r0,r0,#0x20000000\n");\r
664 ot(" orr r1,r1,r0,lsr #25 ;@ ___XNZVC\n");\r
665 ot(" ldr r0,[r7,#0x3c] ;@ A7\n");\r
666 ot(" and r9,r9,#0xf0000000\n");\r
667 ot(" sub r0,r0,#2 ;@ Predecrement A7\n");\r
668 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
669 MemHandler(1,1,0,0);\r
670 // IR (instruction register)\r
671 ot(";@ Push IR:\n");\r
672 ot(" ldr r0,[r7,#0x3c] ;@ A7\n");\r
673 ot(" mov r1,r8\n");\r
674 ot(" sub r0,r0,#2 ;@ Predecrement A7\n");\r
675 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
676 MemHandler(1,1,0,0);\r
677 // access address\r
678 ot(";@ Push address:\n");\r
679 ot(" ldr r0,[r7,#0x3c] ;@ A7\n");\r
680 ot(" mov r1,r11\n");\r
681 ot(" sub r0,r0,#4 ;@ Predecrement A7\n");\r
682 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
683 MemHandler(1,2,0,0);\r
684 // information word\r
685 ot(";@ Push info word:\n");\r
686 ot(" ldr r0,[r7,#0x3c] ;@ A7\n");\r
687 ot(" mov r1,r10\n");\r
688 ot(" sub r0,r0,#2 ;@ Predecrement A7\n");\r
689 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
690 MemHandler(1,1,0,0);\r
691 ot("\n");\r
692\r
693 // 2. Obtain the exception vector\r
694 ot(";@ Read Exception Vector:\n");\r
695 ot(" mov r0,#0x0c\n");\r
696 MemHandler(0,2,0,0);\r
697 ot(" ldr r3,[r7,#0x60] ;@ Get Memory base\n");\r
698#if USE_CHECKPC_CALLBACK\r
699 ot(" add lr,pc,#4\n");\r
700 ot(" add r0,r0,r3 ;@ r0 = Memory Base + New PC\n");\r
701 ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r
702 ot(" mov r4,r0\n");\r
703#else\r
704 ot(" add r4,r0,r3 ;@ r4 = Memory Base + New PC\n");\r
705#endif\r
706 ot("\n");\r
707\r
708#if EMULATE_ADDRESS_ERRORS_JUMP && EMULATE_HALT\r
709 ot(" tst r4,#1\n");\r
710 ot(" bne ExceptionAddressError_r_prg_r4\n");\r
711#else\r
712 ot(" bic r4,r4,#1\n");\r
713#endif\r
714\r
715 // 4. Resume execution.\r
716 ot(" ldrh r8,[r4],#2 ;@ Fetch next opcode\n");\r
717 ot(" subs r5,r5,#50 ;@ Subtract cycles\n");\r
718 ot(" ldrge pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r
719 ot(" b CycloneEnd\n");\r
720 ot("\n");\r
721#endif\r
722\r
723 // --------------\r
724#if EMULATE_TRACE\r
725 // expects srh and irq level in r1, next opcode already fetched to r8\r
726 ot("CycloneDoTraceWithChecks%s\n", ms?"":":");\r
727 ot(" ldr r0,[r7,#0x58]\n");\r
728 ot(" cmp r5,#0\n");\r
729 ot(" orr r0,r0,#2 ;@ go to trace mode\n");\r
730 ot(" str r0,[r7,#0x58]\n");\r
731 ot(" blt CycloneEnd\n"); // should take care of situation where we come here when already tracing\r
732 ot(";@ CheckInterrupt:\n");\r
733 ot(" movs r0,r1,lsr #24 ;@ Get IRQ level\n");\r
734 ot(" beq CycloneDoTrace\n");\r
735 ot(" cmp r0,#6 ;@ irq>6 ?\n");\r
736 ot(" andle r1,r1,#7 ;@ Get interrupt mask\n");\r
737 ot(" cmple r0,r1 ;@ irq<=6: Is irq<=mask ?\n");\r
738 ot(" bgt CycloneDoInterruptGoBack\n");\r
739 ot("\n");\r
740\r
741 // expects next opcode to be already fetched to r8\r
742 ot("CycloneDoTrace%s\n", ms?"":":");\r
743 ot(" str r5,[r7,#0x9c] ;@ save cycles\n");\r
744 ot(" ldr r1,[r7,#0x98]\n");\r
745 ot(" mov r5,#0\n");\r
746 ot(" str r1,[r7,#0xa0]\n");\r
747 ot(" adr r0,TraceEnd\n");\r
748 ot(" str r0,[r7,#0x98] ;@ store TraceEnd as CycloneEnd hadler\n");\r
749 ot(" ldr pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r
750 ot("\n");\r
751\r
752 ot("TraceEnd%s\n", ms?"":":");\r
753 ot(" ldr r2,[r7,#0x58]\n");\r
754 ot(" ldr r0,[r7,#0x9c] ;@ restore cycles\n");\r
755 ot(" ldr r1,[r7,#0xa0] ;@ old CycloneEnd handler\n");\r
756 ot(" mov r9,r9,lsl #28\n");\r
757 ot(" add r5,r0,r5\n");\r
758 ot(" str r1,[r7,#0x98]\n");\r
759 ot(";@ still tracing?\n"); // exception might have happend\r
760 ot(" tst r2,#2\n");\r
761 ot(" beq TraceDisabled\n");\r
762 ot(";@ trace exception\n");\r
763#if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO\r
764 ot(" ldr r1,[r7,#0x58]\n");\r
765 ot(" mov r0,#9\n");\r
766 ot(" orr r1,r1,#4 ;@ set activity bit: 'not processing instruction'\n");\r
767 ot(" str r1,[r7,#0x58]\n");\r
768#else\r
769 ot(" mov r0,#9\n");\r
770#endif\r
771 ot(" bl Exception\n");\r
772 ot(" ldrh r8,[r4],#2 ;@ Fetch next opcode\n");\r
773 ot(" subs r5,r5,#34 ;@ Subtract cycles\n");\r
774 ot(" ldrge pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r
775 ot(" b CycloneEnd\n");\r
cc68a136 776 ot("\n");\r
0e11c502 777 ot("TraceDisabled%s\n", ms?"":":");\r
778 ot(" ldrh r8,[r4],#2 ;@ Fetch next opcode\n");\r
779 ot(" cmp r5,#0\n");\r
780 ot(" ldrge pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r
781 ot(" b CycloneEnd\n");\r
782 ot("\n");\r
783#endif\r
cc68a136 784}\r
785\r
786// ---------------------------------------------------------------------------\r
787// Call Read(r0), Write(r0,r1) or Fetch(r0)\r
788// Trashes r0-r3,r12,lr\r
0e11c502 789int MemHandler(int type,int size,int addrreg,int need_addrerr_check)\r
cc68a136 790{\r
791 int func=0;\r
792 func=0x68+type*0xc+(size<<2); // Find correct offset\r
793\r
cc68a136 794#if MEMHANDLERS_NEED_FLAGS\r
795 ot(" mov r3,r9,lsr #28\n");\r
796 ot(" strb r3,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r
797#endif\r
cfb3dfa0 798 FlushPC();\r
cc68a136 799\r
a6785576 800#if (MEMHANDLERS_ADDR_MASK & 0xff000000)\r
cfb3dfa0 801 ot(" bic r0,r%i,#0x%08x\n", addrreg, MEMHANDLERS_ADDR_MASK & 0xff000000);\r
802 addrreg=0;\r
a6785576 803#endif\r
804#if (MEMHANDLERS_ADDR_MASK & 0x00ff0000)\r
cfb3dfa0 805 ot(" bic r0,r%i,#0x%08x\n", addrreg, MEMHANDLERS_ADDR_MASK & 0x00ff0000);\r
806 addrreg=0;\r
a6785576 807#endif\r
808#if (MEMHANDLERS_ADDR_MASK & 0x0000ff00)\r
cfb3dfa0 809 ot(" bic r0,r%i,#0x%08x\n", addrreg, MEMHANDLERS_ADDR_MASK & 0x0000ff00);\r
810 addrreg=0;\r
a6785576 811#endif\r
812#if (MEMHANDLERS_ADDR_MASK & 0x000000ff)\r
cfb3dfa0 813 ot(" bic r0,r%i,#0x%08x\n", addrreg, MEMHANDLERS_ADDR_MASK & 0x000000ff);\r
814 addrreg=0;\r
a6785576 815#endif\r
0e11c502 816\r
817#if EMULATE_ADDRESS_ERRORS_IO\r
818 if (size > 0 && need_addrerr_check)\r
819 {\r
820 ot(" add lr,pc,#4*%i\n", addrreg==0?2:3); // helps to prevent interlocks\r
821 if (addrreg != 0) ot(" mov r0,r%i\n", addrreg);\r
822 ot(" tst r0,#1 ;@ address error?\n");\r
823 switch (type) {\r
824 case 0: ot(" bne ExceptionAddressError_r_data\n"); break;\r
825 case 1: ot(" bne ExceptionAddressError_w_data\n"); break;\r
826 case 2: ot(" bne ExceptionAddressError_r_prg\n"); break;\r
827 }\r
828 }\r
829 else\r
830#endif\r
cfb3dfa0 831 if (addrreg != 0)\r
85a36a57 832 {\r
0e11c502 833 ot(" add lr,pc,#4\n");\r
cfb3dfa0 834 ot(" mov r0,r%i\n", addrreg);\r
85a36a57 835 }\r
836 else\r
837 ot(" mov lr,pc\n");\r
cc68a136 838 ot(" ldr pc,[r7,#0x%x] ;@ Call ",func);\r
839\r
840 // Document what we are calling:\r
841 if (type==0) ot("read");\r
842 if (type==1) ot("write");\r
843 if (type==2) ot("fetch");\r
844\r
845 if (type==1) ot("%d(r0,r1)",8<<size);\r
846 else ot("%d(r0)", 8<<size);\r
847 ot(" handler\n");\r
848\r
cc68a136 849#if MEMHANDLERS_CHANGE_FLAGS\r
850 ot(" ldrb r9,[r7,#0x46] ;@ r9 = Load Flags (NZCV)\n");\r
851 ot(" mov r9,r9,lsl #28\n");\r
852#endif\r
853#if MEMHANDLERS_CHANGE_PC\r
854 ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");\r
855#endif\r
856\r
857 return 0;\r
858}\r
859\r
860static void PrintOpcodes()\r
861{\r
862 int op=0;\r
b637c56a 863\r
cc68a136 864 printf("Creating Opcodes: [");\r
865\r
866 ot(";@ ---------------------------- Opcodes ---------------------------\n");\r
867\r
868 // Emit null opcode:\r
869 ot("Op____%s ;@ Called if an opcode is not recognised\n", ms?"":":");\r
0e11c502 870#if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO\r
871 ot(" ldr r1,[r7,#0x58]\n");\r
cc68a136 872 ot(" sub r4,r4,#2\n");\r
0e11c502 873 ot(" orr r1,r1,#4 ;@ set activity bit: 'not processing instruction'\n");\r
874 ot(" str r1,[r7,#0x58]\n");\r
875#else\r
876 ot(" sub r4,r4,#2\n");\r
877#endif\r
cc68a136 878#if USE_UNRECOGNIZED_CALLBACK\r
879 ot(" str r4,[r7,#0x40] ;@ Save PC\n");\r
880 ot(" mov r1,r9,lsr #28\n");\r
881 ot(" strb r1,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r
882 ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");\r
883 ot(" ldr r11,[r7,#0x94] ;@ UnrecognizedCallback\n");\r
884 ot(" tst r11,r11\n");\r
885 ot(" movne lr,pc\n");\r
886 ot(" movne pc,r11 ;@ call UnrecognizedCallback if it is defined\n");\r
887 ot(" ldrb r9,[r7,#0x46] ;@ r9 = Load Flags (NZCV)\n");\r
888 ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");\r
889 ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");\r
890 ot(" mov r9,r9,lsl #28\n");\r
891 ot(" tst r0,r0\n");\r
0e11c502 892 ot(" moveq r0,#4\n");\r
cc68a136 893 ot(" bleq Exception\n");\r
894#else\r
0e11c502 895 ot(" mov r0,#4\n");\r
cc68a136 896 ot(" bl Exception\n");\r
897#endif\r
85a36a57 898 ot("\n");\r
cc68a136 899 Cycles=34;\r
900 OpEnd();\r
901\r
902 // Unrecognised a-line and f-line opcodes throw an exception:\r
903 ot("Op__al%s ;@ Unrecognised a-line opcode\n", ms?"":":");\r
904 ot(" sub r4,r4,#2\n");\r
905#if USE_AFLINE_CALLBACK\r
906 ot(" str r4,[r7,#0x40] ;@ Save PC\n");\r
907 ot(" mov r1,r9,lsr #28\n");\r
908 ot(" strb r1,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r
909 ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");\r
910 ot(" ldr r11,[r7,#0x94] ;@ UnrecognizedCallback\n");\r
911 ot(" tst r11,r11\n");\r
912 ot(" movne lr,pc\n");\r
913 ot(" movne pc,r11 ;@ call UnrecognizedCallback if it is defined\n");\r
914 ot(" ldrb r9,[r7,#0x46] ;@ r9 = Load Flags (NZCV)\n");\r
915 ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");\r
916 ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");\r
917 ot(" mov r9,r9,lsl #28\n");\r
918 ot(" tst r0,r0\n");\r
0e11c502 919 ot(" moveq r0,#0x0a\n");\r
cc68a136 920 ot(" bleq Exception\n");\r
921#else\r
0e11c502 922 ot(" mov r0,#0x0a\n");\r
cc68a136 923 ot(" bl Exception\n");\r
924#endif\r
85a36a57 925 ot("\n");\r
cc68a136 926 Cycles=4;\r
927 OpEnd();\r
928\r
929 ot("Op__fl%s ;@ Unrecognised f-line opcode\n", ms?"":":");\r
930 ot(" sub r4,r4,#2\n");\r
931#if USE_AFLINE_CALLBACK\r
932 ot(" str r4,[r7,#0x40] ;@ Save PC\n");\r
933 ot(" mov r1,r9,lsr #28\n");\r
934 ot(" strb r1,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r
935 ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");\r
936 ot(" ldr r11,[r7,#0x94] ;@ UnrecognizedCallback\n");\r
937 ot(" tst r11,r11\n");\r
938 ot(" movne lr,pc\n");\r
939 ot(" movne pc,r11 ;@ call UnrecognizedCallback if it is defined\n");\r
940 ot(" ldrb r9,[r7,#0x46] ;@ r9 = Load Flags (NZCV)\n");\r
941 ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");\r
942 ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");\r
943 ot(" mov r9,r9,lsl #28\n");\r
944 ot(" tst r0,r0\n");\r
0e11c502 945 ot(" moveq r0,#0x0b\n");\r
cc68a136 946 ot(" bleq Exception\n");\r
947#else\r
0e11c502 948 ot(" mov r0,#0x0b\n");\r
cc68a136 949 ot(" bl Exception\n");\r
950#endif\r
85a36a57 951 ot("\n");\r
cc68a136 952 Cycles=4;\r
953 OpEnd();\r
954\r
955\r
956 for (op=0;op<0x10000;op++)\r
957 {\r
958 if ((op&0xfff)==0) { printf("%x",op>>12); fflush(stdout); } // Update progress\r
959\r
960 OpAny(op);\r
961 }\r
962\r
963 ot("\n");\r
964\r
965 printf("]\n");\r
966}\r
967\r
968// helper\r
969static void ott(const char *str, int par, const char *nl, int nlp, int counter, int size)\r
970{\r
971 switch(size) {\r
972 case 0: if((counter&7)==0) ot(ms?" dcb ":" .byte "); break;\r
973 case 1: if((counter&7)==0) ot(ms?" dcw ":" .hword "); break;\r
974 case 2: if((counter&7)==0) ot(ms?" dcd ":" .long "); break;\r
975 }\r
976 ot(str, par);\r
977 if((counter&7)==7) ot(nl,nlp); else ot(",");\r
978}\r
979\r
980static void PrintJumpTable()\r
981{\r
982 int i=0,op=0,len=0;\r
983\r
984 ot(";@ -------------------------- Jump Table --------------------------\n");\r
985\r
c008977e 986 // space for decompressed table\r
987 ot(ms?" area |.data|, data\n":" .data\n .align 4\n\n");\r
988\r
cc68a136 989#if COMPRESS_JUMPTABLE\r
990 int handlers=0,reps=0,*indexes,ip,u,out;\r
991 // use some weird compression on the jump table\r
a6785576 992 indexes=(int *)malloc(0x10000*4);\r
993 if(!indexes) { printf("ERROR: out of memory\n"); exit(1); }\r
994 len=0x10000;\r
cc68a136 995\r
a6785576 996 ot("CycloneJumpTab%s\n", ms?"":":");\r
997 if(ms) {\r
998 for(i = 0; i < 0xa000/8; i++)\r
999 ot(" dcd 0,0,0,0,0,0,0,0\n");\r
1000 } else\r
1001 ot(" .rept 0x%x\n .long 0,0,0,0,0,0,0,0\n .endr\n", 0xa000/8);\r
cc68a136 1002\r
1003 // hanlers live in "a-line" part of the table\r
a6785576 1004 // first output nop,a-line,f-line handlers\r
1005 ot(ms?" dcd Op____,Op__al,Op__fl,":" .long Op____,Op__al,Op__fl,");\r
1006 handlers=3;\r
cc68a136 1007\r
a6785576 1008 for(i=0;i<len;i++)\r
cc68a136 1009 {\r
1010 op=CyJump[i];\r
1011\r
a6785576 1012 for(u=i-1; u>=0; u--) if(op == CyJump[u]) break; // already done with this op?\r
1013 if(u==-1 && op >= 0) {\r
1014 ott("Op%.4x",op," ;@ %.4x\n",i,handlers,2);\r
1015 indexes[op] = handlers;\r
1016 handlers++;\r
cc68a136 1017 }\r
a6785576 1018 }\r
1019 if(handlers&7) {\r
1020 fseek(AsmFile, -1, SEEK_CUR); // remove last comma\r
1021 for(i = 8-(handlers&7); i > 0; i--)\r
1022 ot(",000000");\r
1023 ot("\n");\r
1024 }\r
1025 if(ms) {\r
1026 for(i = (0x4000-handlers)/8; i > 0; i--)\r
1027 ot(" dcd 0,0,0,0,0,0,0,0\n");\r
1028 } else {\r
1029 ot(ms?"":" .rept 0x%x\n .long 0,0,0,0,0,0,0,0\n .endr\n", (0x4000-handlers)/8);\r
1030 }\r
cc68a136 1031 printf("total distinct hanlers: %i\n",handlers);\r
a6785576 1032 // output data\r
1033 for(i=0,ip=0; i < 0xf000; i++, ip++) {\r
cc68a136 1034 op=CyJump[i];\r
a6785576 1035 if(op == -2) {\r
1036 // it must skip a-line area, because we keep our data there\r
1037 ott("0x%.4x", handlers<<4, "\n",0,ip++,1);\r
1038 ott("0x%.4x", 0x1000, "\n",0,ip,1);\r
1039 i+=0xfff;\r
1040 continue;\r
1041 }\r
1042 for(reps=1; i < 0xf000; i++, reps++) if(op != CyJump[i+1]) break;\r
1043 if(op>=0) out=indexes[op]<<4; else out=0; // unrecognised\r
1044 if(reps <= 0xe || reps==0x10) {\r
1045 if(reps!=0x10) out|=reps; else out|=0xf; // 0xf means 0x10 (0xf appeared to be unused anyway)\r
1046 ott("0x%.4x", out, "\n",0,ip,1);\r
cc68a136 1047 } else {\r
a6785576 1048 ott("0x%.4x", out, "\n",0,ip++,1);\r
1049 ott("0x%.4x", reps,"\n",0,ip,1);\r
1050 }\r
cc68a136 1051 }\r
a6785576 1052 if(ip&1) ott("0x%.4x", 0, "\n",0,ip++,1);\r
1053 if(ip&7) fseek(AsmFile, -1, SEEK_CUR); // remove last comma\r
a6785576 1054 if(ip&7) {\r
1055 for(i = 8-(ip&7); i > 0; i--)\r
1056 ot(",0x0000");\r
a6785576 1057 }\r
547045e3 1058 ot("\n");\r
a6785576 1059 if(ms) {\r
1060 for(i = (0x2000-ip/2)/8+1; i > 0; i--)\r
1061 ot(" dcd 0,0,0,0,0,0,0,0\n");\r
1062 } else {\r
1063 ot(" .rept 0x%x\n .long 0,0,0,0,0,0,0,0\n .endr\n", (0x2000-ip/2)/8+1);\r
1064 }\r
1065 ot("\n");\r
1066 free(indexes);\r
cc68a136 1067#else\r
a6785576 1068 ot("CycloneJumpTab%s\n", ms?"":":");\r
cc68a136 1069 len=0xfffe; // Hmmm, armasm 2.50.8684 messes up with a 0x10000 long jump table\r
1070 // notaz: same thing with GNU as 2.9-psion-98r2 (reloc overflow)\r
1071 // this is due to COFF objects using only 2 bytes for reloc count\r
1072\r
1073 for (i=0;i<len;i++)\r
1074 {\r
1075 op=CyJump[i];\r
1076 \r
1077 if(op>=0) ott("Op%.4x",op," ;@ %.4x\n",i-7,i,2);\r
1078 else if(op==-2) ott("Op__al",0, " ;@ %.4x\n",i-7,i,2);\r
1079 else if(op==-3) ott("Op__fl",0, " ;@ %.4x\n",i-7,i,2);\r
1080 else ott("Op____",0, " ;@ %.4x\n",i-7,i,2);\r
1081 }\r
a6785576 1082 if(i&7) fseek(AsmFile, -1, SEEK_CUR); // remove last comma\r
cc68a136 1083\r
1084 ot("\n");\r
1085 ot(";@ notaz: we don't want to crash if we run into those 2 missing opcodes\n");\r
1086 ot(";@ so we leave this pattern to patch it later\n");\r
1087 ot("%s 0x78563412\n", ms?" dcd":" .long");\r
1088 ot("%s 0x56341290\n", ms?" dcd":" .long");\r
1089#endif\r
1090}\r
1091\r
1092static int CycloneMake()\r
1093{\r
1094 int i;\r
1095 char *name="Cyclone.s";\r
0e11c502 1096 const char *globl=ms?"export":".global";\r
cc68a136 1097 \r
1098 // Open the assembly file\r
1099 if (ms) name="Cyclone.asm";\r
1100 AsmFile=fopen(name,"wt"); if (AsmFile==NULL) return 1;\r
1101 \r
1102 printf("Making %s...\n",name);\r
1103\r
1104 ot("\n;@ Dave's Cyclone 68000 Emulator v%x.%.3x - Assembler Output\n\n",CycloneVer>>12,CycloneVer&0xfff);\r
1105\r
1106 ot(";@ (c) Copyright 2003 Dave, All rights reserved.\n");\r
547045e3 1107 ot(";@ some code (c) Copyright 2005-2007 notaz, All rights reserved.\n");\r
cc68a136 1108 ot(";@ Cyclone 68000 is free for non-commercial use.\n\n");\r
1109 ot(";@ For commercial use, separate licencing terms must be obtained.\n\n");\r
1110\r
1111 CyJump=(int *)malloc(0x40000); if (CyJump==NULL) return 1;\r
1112 memset(CyJump,0xff,0x40000); // Init to -1\r
1113 for(i=0xa000; i<0xb000; i++) CyJump[i] = -2; // a-line emulation\r
1114 for(i=0xf000; i<0x10000; i++) CyJump[i] = -3; // f-line emulation\r
1115\r
0e11c502 1116 ot(ms?" area |.text|, code\n":" .text\n .align 4\n\n");\r
1117 ot(" %s CycloneInit\n",globl);\r
1118 ot(" %s CycloneRun\n",globl);\r
1119 ot(" %s CycloneSetSr\n",globl);\r
1120 ot(" %s CycloneGetSr\n",globl);\r
1121 ot(" %s CycloneFlushIrq\n",globl);\r
1122 ot(" %s CyclonePack\n",globl);\r
1123 ot(" %s CycloneUnpack\n",globl);\r
1124 ot(" %s CycloneVer\n",globl);\r
a9a5a6e0 1125#if (CYCLONE_FOR_GENESIS == 2)\r
0e11c502 1126 ot(" %s CycloneSetRealTAS\n",globl);\r
1127 ot(" %s CycloneDoInterrupt\n",globl);\r
1128 ot(" %s CycloneDoTrace\n",globl);\r
1129 ot(" %s CycloneJumpTab\n",globl);\r
7336a99a 1130#endif\r
0e11c502 1131 ot("\n");\r
1132 ot(ms?"CycloneVer dcd 0x":"CycloneVer: .long 0x");\r
1133 ot("%.4x\n",CycloneVer);\r
cc68a136 1134 ot("\n");\r
1135\r
1136 PrintFramework();\r
b637c56a 1137 arm_op_count = 0;\r
cc68a136 1138 PrintOpcodes();\r
b637c56a 1139 printf("~%i ARM instructions used for opcode handlers\n", arm_op_count);\r
cc68a136 1140 PrintJumpTable();\r
1141\r
1142 if (ms) ot(" END\n");\r
1143\r
7336a99a 1144 ot("\n\n;@ vim:filetype=armasm\n");\r
1145\r
cc68a136 1146 fclose(AsmFile); AsmFile=NULL;\r
1147\r
1148#if 0\r
1149 printf("Assembling...\n");\r
1150 // Assemble the file\r
1151 if (ms) system("armasm Cyclone.asm");\r
1152 else system("as -o Cyclone.o Cyclone.s");\r
1153 printf("Done!\n\n");\r
1154#endif\r
1155\r
1156 free(CyJump);\r
1157 return 0;\r
1158}\r
1159\r
1160int main()\r
1161{\r
1162 printf("\n Dave's Cyclone 68000 Emulator v%x.%.3x - Core Creator\n\n",CycloneVer>>12,CycloneVer&0xfff);\r
1163\r
1164 // Make GAS or ARMASM version\r
1165 CycloneMake();\r
1166 return 0;\r
1167}\r
1168\r
fast MegaDrive/MegaCD/32X emulator