| cc68a136 |
1 | \r |
| 2 | #include "app.h"\r |
| 3 | \r |
| 4 | static FILE *AsmFile=NULL;\r |
| 5 | \r |
| 449ecf92 |
6 | static int CycloneVer=0x0099; // Version number of library\r |
| cc68a136 |
7 | int *CyJump=NULL; // Jump table\r |
| 8 | int ms=USE_MS_SYNTAX; // If non-zero, output in Microsoft ARMASM format\r |
| d95259bd |
9 | const char * const Narm[4]={ "b", "h","",""}; // Normal ARM Extensions for operand sizes 0,1,2\r |
| 10 | const char * const Sarm[4]={"sb","sh","",""}; // Sign-extend ARM Extensions for operand sizes 0,1,2\r |
| cc68a136 |
11 | int Cycles; // Current cycles for opcode\r |
| cfb3dfa0 |
12 | int pc_dirty; // something changed PC during processing\r |
| ee5e024c |
13 | int arm_op_count;\r |
| cc68a136 |
14 | \r |
| d4789c7c |
15 | // opcodes often used by games\r |
| 16 | static const unsigned short hot_opcodes[] = {\r |
| 17 | 0x6701, // beq $3\r |
| 18 | 0x6601, // bne $3\r |
| 19 | 0x51c8, // dbra Dn, $2\r |
| 20 | 0x4a38, // tst.b $0.w\r |
| 21 | 0xd040, // add.w Dn, Dn\r |
| 22 | 0x4a79, // tst.w $0.l\r |
| 23 | 0x0240, // andi.w #$0, D0\r |
| 24 | 0x2038, // move.l $0.w, D0\r |
| 25 | 0xb0b8, // cmp.l $0.w, D0\r |
| 26 | 0x6001, // bra $3\r |
| 27 | 0x30c0, // move.w D0, (A0)+\r |
| 28 | 0x3028, // move.w ($0,A0), D0\r |
| 29 | 0x0c40, // cmpi.w #$0, D0\r |
| 30 | 0x0c79, // cmpi.w #$0, $0.l\r |
| 31 | 0x4e75, // rts\r |
| 32 | 0x4e71, // nop\r |
| 33 | 0x3000, // move.w D0, D0\r |
| 34 | 0x0839, // btst #$0, $0.l\r |
| 35 | 0x7000, // moveq #$0, D0\r |
| 36 | 0x3040, // movea.w D0, A0\r |
| 37 | 0x0838, // btst #$0, $0.w\r |
| 38 | 0x4a39, // tst.b $0.l\r |
| 39 | 0x33d8, // move.w (A0)+, $0.l\r |
| 40 | 0x6700, // beq $2\r |
| 41 | 0xb038, // cmp.b $0.w, D0\r |
| 42 | 0x3039, // move.w $0.l, D0\r |
| 43 | 0x4840, // swap D0\r |
| 44 | 0x6101, // bsr $3\r |
| 45 | 0x6100, // bsr $2\r |
| 46 | 0x5e40, // addq.w #7, D0\r |
| 47 | 0x1039, // move.b $0.l, D0\r |
| 48 | 0x20c0, // move.l D0, (A0)+\r |
| 49 | 0x1018, // move.b (A0)+, D0\r |
| 50 | 0x30d0, // move.w (A0), (A0)+\r |
| 51 | 0x3080, // move.w D0, (A0)\r |
| 52 | 0x3018, // move.w (A0)+, D0\r |
| 53 | 0xc040, // and.w D0, D0\r |
| 54 | 0x3180, // move.w D0, (A0,D0.w)\r |
| 55 | 0x1198, // move.b (A0)+, (A0,D0.w)\r |
| 56 | 0x6501, // bcs $3\r |
| 57 | 0x6500, // bcs $2\r |
| 58 | 0x6401, // bcc $3\r |
| 59 | 0x6a01, // bpl $3\r |
| 60 | 0x41f0, // lea (A0,D0.w), A0\r |
| 61 | 0x4a28, // tst.b ($0,A0)\r |
| 62 | 0x0828, // btst #$0, ($0,A0)\r |
| 63 | 0x0640, // addi.w #$0, D0\r |
| 64 | 0x10c0, // move.b D0, (A0)+\r |
| 65 | 0x10d8, // move.b (A0)+, (A0)+\r |
| 66 | };\r |
| 67 | #define hot_opcode_count (int)(sizeof(hot_opcodes) / sizeof(hot_opcodes[0]))\r |
| 68 | \r |
| 69 | static int is_op_hot(int op)\r |
| 70 | {\r |
| 71 | int i;\r |
| 72 | for (i = 0; i < hot_opcode_count; i++)\r |
| 73 | if (op == hot_opcodes[i])\r |
| 74 | return 1;\r |
| 75 | return 0;\r |
| 76 | }\r |
| cc68a136 |
77 | \r |
| 78 | void ot(const char *format, ...)\r |
| 79 | {\r |
| 80 | va_list valist=NULL;\r |
| 81 | int i, len;\r |
| 82 | \r |
| 83 | // notaz: stop me from leaving newlines in the middle of format string\r |
| 84 | // and generating bad code\r |
| 85 | for(i=0, len=strlen(format); i < len && format[i] != '\n'; i++);\r |
| 86 | if(i < len-1 && format[len-1] != '\n') printf("\nWARNING: possible improper newline placement:\n%s\n", format);\r |
| 87 | \r |
| b637c56a |
88 | if (format[0] == ' ' && format[1] == ' ' && format[2] != ' ' && format[2] != '.')\r |
| 89 | arm_op_count++;\r |
| 90 | \r |
| cc68a136 |
91 | va_start(valist,format);\r |
| 92 | if (AsmFile) vfprintf(AsmFile,format,valist);\r |
| 93 | va_end(valist);\r |
| 94 | }\r |
| 95 | \r |
| 96 | void ltorg()\r |
| 97 | {\r |
| 98 | if (ms) ot(" LTORG\n");\r |
| 99 | else ot(" .ltorg\n");\r |
| 100 | }\r |
| 101 | \r |
| a9a5a6e0 |
102 | #if (CYCLONE_FOR_GENESIS == 2)\r |
| c008977e |
103 | // r12=ptr to tas in table, trashes r0,r1\r |
| 104 | static void ChangeTAS(int norm)\r |
| 105 | {\r |
| 106 | ot(" ldr r0,=Op4ad0%s\n",norm?"_":"");\r |
| 107 | ot(" mov r1,#8\n");\r |
| 108 | ot("setrtas_loop%i0%s ;@ 4ad0-4ad7\n",norm,ms?"":":");\r |
| 109 | ot(" subs r1,r1,#1\n");\r |
| 110 | ot(" str r0,[r12],#4\n");\r |
| 111 | ot(" bne setrtas_loop%i0\n",norm);\r |
| 112 | ot(" ldr r0,=Op4ad8%s\n",norm?"_":"");\r |
| 113 | ot(" mov r1,#7\n");\r |
| 114 | ot("setrtas_loop%i1%s ;@ 4ad8-4ade\n",norm,ms?"":":");\r |
| 115 | ot(" subs r1,r1,#1\n");\r |
| 116 | ot(" str r0,[r12],#4\n");\r |
| 117 | ot(" bne setrtas_loop%i1\n",norm);\r |
| 118 | ot(" ldr r0,=Op4adf%s\n",norm?"_":"");\r |
| 119 | ot(" str r0,[r12],#4\n");\r |
| 120 | ot(" ldr r0,=Op4ae0%s\n",norm?"_":"");\r |
| 121 | ot(" mov r1,#7\n");\r |
| 122 | ot("setrtas_loop%i2%s ;@ 4ae0-4ae6\n",norm,ms?"":":");\r |
| 123 | ot(" subs r1,r1,#1\n");\r |
| 124 | ot(" str r0,[r12],#4\n");\r |
| 125 | ot(" bne setrtas_loop%i2\n",norm);\r |
| 126 | ot(" ldr r0,=Op4ae7%s\n",norm?"_":"");\r |
| 127 | ot(" str r0,[r12],#4\n");\r |
| 128 | ot(" ldr r0,=Op4ae8%s\n",norm?"_":"");\r |
| 129 | ot(" mov r1,#8\n");\r |
| 130 | ot("setrtas_loop%i3%s ;@ 4ae8-4aef\n",norm,ms?"":":");\r |
| 131 | ot(" subs r1,r1,#1\n");\r |
| 132 | ot(" str r0,[r12],#4\n");\r |
| 133 | ot(" bne setrtas_loop%i3\n",norm);\r |
| 134 | ot(" ldr r0,=Op4af0%s\n",norm?"_":"");\r |
| 135 | ot(" mov r1,#8\n");\r |
| 136 | ot("setrtas_loop%i4%s ;@ 4af0-4af7\n",norm,ms?"":":");\r |
| 137 | ot(" subs r1,r1,#1\n");\r |
| 138 | ot(" str r0,[r12],#4\n");\r |
| 139 | ot(" bne setrtas_loop%i4\n",norm);\r |
| 140 | ot(" ldr r0,=Op4af8%s\n",norm?"_":"");\r |
| 141 | ot(" str r0,[r12],#4\n");\r |
| 142 | ot(" ldr r0,=Op4af9%s\n",norm?"_":"");\r |
| 143 | ot(" str r0,[r12],#4\n");\r |
| 144 | }\r |
| 145 | #endif\r |
| 146 | \r |
| 0e11c502 |
147 | #if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO\r |
| d95259bd |
148 | static void AddressErrorWrapper(char rw, const char *dataprg, int iw)\r |
| cc68a136 |
149 | {\r |
| 0e11c502 |
150 | ot("ExceptionAddressError_%c_%s%s\n", rw, dataprg, ms?"":":");\r |
| 151 | ot(" ldr r1,[r7,#0x44]\n");\r |
| 449ecf92 |
152 | ot(" mov r6,#0x%02x\n", iw);\r |
| 0e11c502 |
153 | ot(" mov r11,r0\n");\r |
| 154 | ot(" tst r1,#0x20\n");\r |
| 449ecf92 |
155 | ot(" orrne r6,r6,#4\n");\r |
| 0e11c502 |
156 | ot(" b ExceptionAddressError\n");\r |
| cc68a136 |
157 | ot("\n");\r |
| cc68a136 |
158 | }\r |
| 0e11c502 |
159 | #endif\r |
| cc68a136 |
160 | \r |
| cfb3dfa0 |
161 | void FlushPC(void)\r |
| 162 | {\r |
| 163 | #if MEMHANDLERS_NEED_PC\r |
| 164 | if (pc_dirty)\r |
| 165 | ot(" str r4,[r7,#0x40] ;@ Save PC\n");\r |
| 166 | #endif\r |
| 167 | pc_dirty = 0;\r |
| 168 | }\r |
| 169 | \r |
| cc68a136 |
170 | static void PrintFramework()\r |
| 171 | {\r |
| 0e11c502 |
172 | int state_flags_to_check = 1; // stopped\r |
| 173 | #if EMULATE_TRACE\r |
| 174 | state_flags_to_check |= 2; // tracing\r |
| 175 | #endif\r |
| 176 | #if EMULATE_HALT\r |
| 177 | state_flags_to_check |= 0x10; // halted\r |
| 178 | #endif\r |
| 179 | \r |
| cc68a136 |
180 | ot(";@ --------------------------- Framework --------------------------\n");\r |
| 181 | if (ms) ot("CycloneRun\n");\r |
| 182 | else ot("CycloneRun:\n");\r |
| 183 | \r |
| 449ecf92 |
184 | ot(" stmdb sp!,{r4-r8,r10,r11,lr}\n");\r |
| cc68a136 |
185 | \r |
| 186 | ot(" mov r7,r0 ;@ r7 = Pointer to Cpu Context\n");\r |
| 187 | ot(" ;@ r0-3 = Temporary registers\n");\r |
| 449ecf92 |
188 | ot(" ldrb r10,[r7,#0x46] ;@ r10 = Flags (NZCV)\n");\r |
| 7336a99a |
189 | ot(" ldr r6,=CycloneJumpTab ;@ r6 = Opcode Jump table\n");\r |
| cc68a136 |
190 | ot(" ldr r5,[r7,#0x5c] ;@ r5 = Cycles\n");\r |
| 191 | ot(" ldr r4,[r7,#0x40] ;@ r4 = Current PC + Memory Base\n");\r |
| 192 | ot(" ;@ r8 = Current Opcode\n");\r |
| 66fdc0f0 |
193 | ot(" ldr r1,[r7,#0x44] ;@ Get SR high T_S__III and irq level\n");\r |
| 449ecf92 |
194 | ot(" mov r10,r10,lsl #28;@ r10 = Flags 0xf0000000, cpsr format\n");\r |
| 195 | ot(" ;@ r11 = Source value / Memory Base\n");\r |
| 196 | ot(" str r6,[r7,#0x54] ;@ make a copy to avoid literal pools\n");\r |
| cc68a136 |
197 | ot("\n");\r |
| 0e11c502 |
198 | #if (CYCLONE_FOR_GENESIS == 2) || EMULATE_TRACE\r |
| 199 | ot(" mov r2,#0\n");\r |
| 200 | ot(" str r2,[r7,#0x98] ;@ clear custom CycloneEnd\n");\r |
| 201 | #endif\r |
| cc68a136 |
202 | ot(";@ CheckInterrupt:\n");\r |
| 66fdc0f0 |
203 | ot(" movs r0,r1,lsr #24 ;@ Get IRQ level\n"); // same as ldrb r0,[r7,#0x47]\r |
| cc68a136 |
204 | ot(" beq NoInts0\n");\r |
| 205 | ot(" cmp r0,#6 ;@ irq>6 ?\n");\r |
| cc68a136 |
206 | ot(" andle r1,r1,#7 ;@ Get interrupt mask\n");\r |
| 207 | ot(" cmple r0,r1 ;@ irq<=6: Is irq<=mask ?\n");\r |
| ee5e024c |
208 | ot(" bgt CycloneDoInterrupt\n");\r |
| cc68a136 |
209 | ot("NoInts0%s\n", ms?"":":");\r |
| 210 | ot("\n");\r |
| 0e11c502 |
211 | ot(";@ Check if our processor is in special state\n");\r |
| 212 | ot(";@ and jump to opcode handler if not\n");\r |
| 213 | ot(" ldr r0,[r7,#0x58] ;@ state_flags\n");\r |
| cc68a136 |
214 | ot(" ldrh r8,[r4],#2 ;@ Fetch first opcode\n");\r |
| 0e11c502 |
215 | ot(" tst r0,#0x%02x ;@ special state?\n", state_flags_to_check);\r |
| 216 | ot(" ldreq pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r |
| 217 | ot("\n");\r |
| 218 | ot("CycloneSpecial%s\n", ms?"":":");\r |
| 219 | #if EMULATE_TRACE\r |
| 220 | ot(" tst r0,#2 ;@ tracing?\n");\r |
| 221 | ot(" bne CycloneDoTrace\n");\r |
| 222 | #endif\r |
| 223 | ot(";@ stopped or halted\n");\r |
| 224 | ot(" mov r5,#0\n");\r |
| 225 | ot(" str r5,[r7,#0x5C] ;@ eat all cycles\n");\r |
| 449ecf92 |
226 | ot(" ldmia sp!,{r4-r8,r10,r11,pc} ;@ we are stopped, do nothing!\n");\r |
| cc68a136 |
227 | ot("\n");\r |
| 228 | ot("\n");\r |
| 229 | \r |
| 230 | ot(";@ We come back here after execution\n");\r |
| 231 | ot("CycloneEnd%s\n", ms?"":":");\r |
| 232 | ot(" sub r4,r4,#2\n");\r |
| 233 | ot("CycloneEndNoBack%s\n", ms?"":":");\r |
| 0e11c502 |
234 | #if (CYCLONE_FOR_GENESIS == 2) || EMULATE_TRACE\r |
| 235 | ot(" ldr r1,[r7,#0x98]\n");\r |
| 449ecf92 |
236 | ot(" mov r10,r10,lsr #28\n");\r |
| 7336a99a |
237 | ot(" tst r1,r1\n");\r |
| 238 | ot(" bxne r1 ;@ jump to alternative CycloneEnd\n");\r |
| 239 | #else\r |
| 449ecf92 |
240 | ot(" mov r10,r10,lsr #28\n");\r |
| 7336a99a |
241 | #endif\r |
| cc68a136 |
242 | ot(" str r4,[r7,#0x40] ;@ Save Current PC + Memory Base\n");\r |
| 243 | ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");\r |
| 449ecf92 |
244 | ot(" strb r10,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r |
| 245 | ot(" ldmia sp!,{r4-r8,r10,r11,pc}\n");\r |
| 0e11c502 |
246 | ltorg();\r |
| cc68a136 |
247 | ot("\n");\r |
| cc68a136 |
248 | ot("\n");\r |
| 249 | \r |
| 0e11c502 |
250 | ot("CycloneInit%s\n", ms?"":":");\r |
| cc68a136 |
251 | #if COMPRESS_JUMPTABLE\r |
| 0e11c502 |
252 | ot(";@ decompress jump table\n");\r |
| 253 | ot(" ldr r12,=CycloneJumpTab\n");\r |
| 254 | ot(" add r0,r12,#0xe000*4 ;@ ctrl code pointer\n");\r |
| 255 | ot(" ldr r1,[r0,#-4]\n");\r |
| 256 | ot(" tst r1,r1\n");\r |
| 257 | ot(" movne pc,lr ;@ already uncompressed\n");\r |
| 258 | ot(" add r3,r12,#0xa000*4 ;@ handler table pointer, r12=dest\n");\r |
| 259 | ot("unc_loop%s\n", ms?"":":");\r |
| 260 | ot(" ldrh r1,[r0],#2\n");\r |
| 261 | ot(" and r2,r1,#0xf\n");\r |
| 262 | ot(" bic r1,r1,#0xf\n");\r |
| 263 | ot(" ldr r1,[r3,r1,lsr #2] ;@ r1=handler\n");\r |
| 264 | ot(" cmp r2,#0xf\n");\r |
| 265 | ot(" addeq r2,r2,#1 ;@ 0xf is really 0x10\n");\r |
| 266 | ot(" tst r2,r2\n");\r |
| 267 | ot(" ldreqh r2,[r0],#2 ;@ counter is in next word\n");\r |
| 268 | ot(" tst r2,r2\n");\r |
| 269 | ot(" beq unc_finish ;@ done decompressing\n");\r |
| 270 | ot(" tst r1,r1\n");\r |
| 271 | ot(" addeq r12,r12,r2,lsl #2 ;@ 0 handler means we should skip those bytes\n");\r |
| 272 | ot(" beq unc_loop\n");\r |
| 273 | ot("unc_loop_in%s\n", ms?"":":");\r |
| 274 | ot(" subs r2,r2,#1\n");\r |
| 275 | ot(" str r1,[r12],#4\n");\r |
| 276 | ot(" bgt unc_loop_in\n");\r |
| 277 | ot(" b unc_loop\n");\r |
| 278 | ot("unc_finish%s\n", ms?"":":");\r |
| 279 | ot(" ldr r12,=CycloneJumpTab\n");\r |
| 280 | ot(" ;@ set a-line and f-line handlers\n");\r |
| 281 | ot(" add r0,r12,#0xa000*4\n");\r |
| 282 | ot(" ldr r1,[r0,#4] ;@ a-line handler\n");\r |
| 283 | ot(" ldr r3,[r0,#8] ;@ f-line handler\n");\r |
| 284 | ot(" mov r2,#0x1000\n");\r |
| 285 | ot("unc_fill3%s\n", ms?"":":");\r |
| 286 | ot(" subs r2,r2,#1\n");\r |
| 287 | ot(" str r1,[r0],#4\n");\r |
| 288 | ot(" bgt unc_fill3\n");\r |
| 289 | ot(" add r0,r12,#0xf000*4\n");\r |
| 290 | ot(" mov r2,#0x1000\n");\r |
| 291 | ot("unc_fill4%s\n", ms?"":":");\r |
| 292 | ot(" subs r2,r2,#1\n");\r |
| 293 | ot(" str r3,[r0],#4\n");\r |
| 294 | ot(" bgt unc_fill4\n");\r |
| 295 | ot(" bx lr\n");\r |
| 296 | ltorg();\r |
| cc68a136 |
297 | #else\r |
| 0e11c502 |
298 | ot(";@ do nothing\n");\r |
| 299 | ot(" bx lr\n");\r |
| cc68a136 |
300 | #endif\r |
| 0e11c502 |
301 | ot("\n");\r |
| 302 | \r |
| 303 | // --------------\r |
| 85a36a57 |
304 | // 68k: XNZVC, ARM: NZCV\r |
| 0e11c502 |
305 | ot("CycloneSetSr%s\n", ms?"":":");\r |
| cc68a136 |
306 | ot(" mov r2,r1,lsr #8\n");\r |
| 0e11c502 |
307 | // ot(" ldrb r3,[r0,#0x44] ;@ get SR high\n");\r |
| 308 | // ot(" eor r3,r3,r2\n");\r |
| 309 | // ot(" tst r3,#0x20\n");\r |
| 310 | #if EMULATE_TRACE\r |
| 311 | ot(" and r2,r2,#0xa7 ;@ only defined bits\n");\r |
| 312 | #else\r |
| 313 | ot(" and r2,r2,#0x27 ;@ only defined bits\n");\r |
| 314 | #endif\r |
| cc68a136 |
315 | ot(" strb r2,[r0,#0x44] ;@ set SR high\n");\r |
| 85a36a57 |
316 | ot(" mov r2,r1,lsl #25\n");\r |
| 317 | ot(" str r2,[r0,#0x4c] ;@ the X flag\n");\r |
| cc68a136 |
318 | ot(" bic r2,r1,#0xf3\n");\r |
| 319 | ot(" tst r1,#1\n");\r |
| 320 | ot(" orrne r2,r2,#2\n");\r |
| 321 | ot(" tst r1,#2\n");\r |
| 322 | ot(" orrne r2,r2,#1\n");\r |
| 323 | ot(" strb r2,[r0,#0x46] ;@ flags\n");\r |
| 324 | ot(" bx lr\n");\r |
| 325 | ot("\n");\r |
| 326 | \r |
| 0e11c502 |
327 | // --------------\r |
| 328 | ot("CycloneGetSr%s\n", ms?"":":");\r |
| cc68a136 |
329 | ot(" ldrb r1,[r0,#0x46] ;@ flags\n");\r |
| 330 | ot(" bic r2,r1,#0xf3\n");\r |
| 331 | ot(" tst r1,#1\n");\r |
| 332 | ot(" orrne r2,r2,#2\n");\r |
| 333 | ot(" tst r1,#2\n");\r |
| 334 | ot(" orrne r2,r2,#1\n");\r |
| 85a36a57 |
335 | ot(" ldr r1,[r0,#0x4c] ;@ the X flag\n");\r |
| 336 | ot(" tst r1,#0x20000000\n");\r |
| cc68a136 |
337 | ot(" orrne r2,r2,#0x10\n");\r |
| 338 | ot(" ldrb r1,[r0,#0x44] ;@ the SR high\n");\r |
| 339 | ot(" orr r0,r2,r1,lsl #8\n");\r |
| 340 | ot(" bx lr\n");\r |
| 341 | ot("\n");\r |
| 342 | \r |
| 0e11c502 |
343 | // --------------\r |
| 344 | ot("CyclonePack%s\n", ms?"":":");\r |
| 345 | ot(" stmfd sp!,{r4,r5,lr}\n");\r |
| 346 | ot(" mov r4,r0\n");\r |
| 347 | ot(" mov r5,r1\n");\r |
| 348 | ot(" mov r3,#16\n");\r |
| 349 | ot(";@ 0x00-0x3f: DA registers\n");\r |
| 350 | ot("c_pack_loop%s\n",ms?"":":");\r |
| 351 | ot(" ldr r1,[r0],#4\n");\r |
| 352 | ot(" subs r3,r3,#1\n");\r |
| 353 | ot(" str r1,[r5],#4\n");\r |
| 354 | ot(" bne c_pack_loop\n");\r |
| 355 | ot(";@ 0x40: PC\n");\r |
| 356 | ot(" ldr r0,[r4,#0x40] ;@ PC + Memory Base\n");\r |
| 357 | ot(" ldr r1,[r4,#0x60] ;@ Memory base\n");\r |
| 358 | ot(" sub r0,r0,r1\n");\r |
| 359 | ot(" str r0,[r5],#4\n");\r |
| 360 | ot(";@ 0x44: SR\n");\r |
| 361 | ot(" mov r0,r4\n");\r |
| 362 | ot(" bl CycloneGetSr\n");\r |
| 363 | ot(" strh r0,[r5],#2\n");\r |
| 364 | ot(";@ 0x46: IRQ level\n");\r |
| 365 | ot(" ldrb r0,[r4,#0x47]\n");\r |
| 366 | ot(" strb r0,[r5],#2\n");\r |
| 367 | ot(";@ 0x48: other SP\n");\r |
| 368 | ot(" ldr r0,[r4,#0x48]\n");\r |
| 369 | ot(" str r0,[r5],#4\n");\r |
| 370 | ot(";@ 0x4c: CPU state flags\n");\r |
| 371 | ot(" ldr r0,[r4,#0x58]\n");\r |
| 372 | ot(" str r0,[r5],#4\n");\r |
| 373 | ot(" ldmfd sp!,{r4,r5,pc}\n");\r |
| 374 | ot("\n");\r |
| 375 | \r |
| 376 | // --------------\r |
| 377 | ot("CycloneUnpack%s\n", ms?"":":");\r |
| 378 | ot(" stmfd sp!,{r4,r5,lr}\n");\r |
| 379 | ot(" mov r4,r0\n");\r |
| 380 | ot(" mov r5,r1\n");\r |
| 381 | ot(" mov r3,#16\n");\r |
| 382 | ot(";@ 0x00-0x3f: DA registers\n");\r |
| 383 | ot("c_unpack_loop%s\n",ms?"":":");\r |
| 384 | ot(" ldr r1,[r5],#4\n");\r |
| 385 | ot(" subs r3,r3,#1\n");\r |
| 386 | ot(" str r1,[r0],#4\n");\r |
| 387 | ot(" bne c_unpack_loop\n");\r |
| 388 | ot(";@ 0x40: PC\n");\r |
| 389 | ot(" ldr r0,[r5],#4 ;@ PC\n");\r |
| 390 | #if USE_CHECKPC_CALLBACK\r |
| 391 | ot(" mov r1,#0\n");\r |
| 392 | ot(" str r1,[r4,#0x60] ;@ Memory base\n");\r |
| 393 | ot(" mov lr,pc\n");\r |
| 394 | ot(" ldr pc,[r4,#0x64] ;@ Call checkpc()\n");\r |
| 395 | #else\r |
| 396 | ot(" ldr r1,[r4,#0x60] ;@ Memory base\n");\r |
| 397 | ot(" add r0,r0,r1 ;@ r0 = Memory Base + New PC\n");\r |
| 398 | #endif\r |
| 399 | ot(" str r0,[r4,#0x40] ;@ PC + Memory Base\n");\r |
| 400 | ot(";@ 0x44: SR\n");\r |
| 401 | ot(" ldrh r1,[r5],#2\n");\r |
| 402 | ot(" mov r0,r4\n");\r |
| 403 | ot(" bl CycloneSetSr\n");\r |
| 404 | ot(";@ 0x46: IRQ level\n");\r |
| 405 | ot(" ldrb r0,[r5],#2\n");\r |
| 406 | ot(" strb r0,[r4,#0x47]\n");\r |
| 407 | ot(";@ 0x48: other SP\n");\r |
| 408 | ot(" ldr r0,[r5],#4\n");\r |
| 409 | ot(" str r0,[r4,#0x48]\n");\r |
| 410 | ot(";@ 0x4c: CPU state flags\n");\r |
| 411 | ot(" ldr r0,[r5],#4\n");\r |
| 412 | ot(" str r0,[r4,#0x58]\n");\r |
| 413 | ot(" ldmfd sp!,{r4,r5,pc}\n");\r |
| 414 | ot("\n");\r |
| 415 | \r |
| 416 | // --------------\r |
| 417 | ot("CycloneFlushIrq%s\n", ms?"":":");\r |
| 418 | ot(" ldr r1,[r0,#0x44] ;@ Get SR high T_S__III and irq level\n");\r |
| 419 | ot(" mov r2,r1,lsr #24 ;@ Get IRQ level\n"); // same as ldrb r0,[r7,#0x47]\r |
| 420 | ot(" cmp r2,#6 ;@ irq>6 ?\n");\r |
| 421 | ot(" andle r1,r1,#7 ;@ Get interrupt mask\n");\r |
| 422 | ot(" cmple r2,r1 ;@ irq<=6: Is irq<=mask ?\n");\r |
| 423 | ot(" movle r0,#0\n");\r |
| 424 | ot(" bxle lr ;@ no ints\n");\r |
| 425 | ot("\n");\r |
| 449ecf92 |
426 | ot(" stmdb sp!,{r4,r5,r7,r8,r10,r11,lr}\n");\r |
| 0e11c502 |
427 | ot(" mov r7,r0\n");\r |
| 428 | ot(" mov r0,r2\n");\r |
| 449ecf92 |
429 | ot(" ldrb r10,[r7,#0x46] ;@ r10 = Flags (NZCV)\n");\r |
| 0e11c502 |
430 | ot(" mov r5,#0\n");\r |
| 449ecf92 |
431 | ot(" ldr r4,[r7,#0x40] ;@ r4 = Current PC + Memory Base\n");\r |
| 432 | ot(" mov r10,r10,lsl #28 ;@ r10 = Flags 0xf0000000, cpsr format\n");\r |
| 0e11c502 |
433 | ot(" adr r2,CycloneFlushIrqEnd\n");\r |
| 434 | ot(" str r2,[r7,#0x98] ;@ set custom CycloneEnd\n");\r |
| 435 | ot(" b CycloneDoInterrupt\n");\r |
| 436 | ot("\n");\r |
| 437 | ot("CycloneFlushIrqEnd%s\n", ms?"":":");\r |
| 438 | ot(" rsb r0,r5,#0\n");\r |
| 449ecf92 |
439 | ot(" str r4,[r7,#0x40] ;@ Save Current PC + Memory Base\n");\r |
| 440 | ot(" strb r10,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r |
| 441 | ot(" ldmia sp!,{r4,r5,r7,r8,r10,r11,lr}\n");\r |
| 0e11c502 |
442 | ot(" bx lr\n");\r |
| 443 | ot("\n");\r |
| 444 | ot("\n");\r |
| 445 | \r |
| 446 | // --------------\r |
| 447 | ot("CycloneSetRealTAS%s\n", ms?"":":");\r |
| a9a5a6e0 |
448 | #if (CYCLONE_FOR_GENESIS == 2)\r |
| c008977e |
449 | ot(" ldr r12,=CycloneJumpTab\n");\r |
| 450 | ot(" tst r0,r0\n");\r |
| 451 | ot(" add r12,r12,#0x4a00*4\n");\r |
| 452 | ot(" add r12,r12,#0x00d0*4\n");\r |
| 453 | ot(" beq setrtas_off\n");\r |
| 454 | ChangeTAS(1);\r |
| 455 | ot(" bx lr\n");\r |
| 456 | ot("setrtas_off%s\n",ms?"":":");\r |
| 457 | ChangeTAS(0);\r |
| 458 | ot(" bx lr\n");\r |
| 459 | ltorg();\r |
| c008977e |
460 | #else\r |
| 461 | ot(" bx lr\n");\r |
| c008977e |
462 | #endif\r |
| 0e11c502 |
463 | ot("\n");\r |
| c008977e |
464 | \r |
| 0e11c502 |
465 | // --------------\r |
| 466 | ot(";@ DoInterrupt - r0=IRQ level\n");\r |
| ee5e024c |
467 | ot("CycloneDoInterruptGoBack%s\n", ms?"":":");\r |
| 468 | ot(" sub r4,r4,#2\n");\r |
| 7336a99a |
469 | ot("CycloneDoInterrupt%s\n", ms?"":":");\r |
| 0e11c502 |
470 | ot(" bic r8,r8,#0xff000000\n");\r |
| 471 | ot(" orr r8,r8,r0,lsl #29 ;@ abuse r8\n");\r |
| 472 | \r |
| 473 | // Steps are from "M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL", p. 6-4\r |
| 474 | // but their order is based on http://pasti.fxatari.com/68kdocs/68kPrefetch.html\r |
| 475 | // 1. Make a temporary copy of the status register and set the status register for exception processing.\r |
| 476 | ot(" ldr r2,[r7,#0x58] ;@ state flags\n");\r |
| 477 | ot(" and r0,r0,#7\n");\r |
| 478 | ot(" orr r3,r0,#0x20 ;@ Supervisor mode + IRQ level\n");\r |
| 479 | ot(" bic r2,r2,#3 ;@ clear stopped and trace states\n");\r |
| 480 | #if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO\r |
| 481 | ot(" orr r2,r2,#4 ;@ set activity bit: 'not processing instruction'\n");\r |
| 482 | #endif\r |
| cc68a136 |
483 | ot(" str r2,[r7,#0x58]\n");\r |
| 449ecf92 |
484 | ot(" ldrb r6,[r7,#0x44] ;@ Get old SR high, abuse r6\n");\r |
| 0e11c502 |
485 | ot(" strb r3,[r7,#0x44] ;@ Put new SR high\n");\r |
| 486 | ot("\n");\r |
| 487 | \r |
| 488 | // 3. Save the current processor context.\r |
| 489 | ot(" ldr r1,[r7,#0x60] ;@ Get Memory base\n");\r |
| 490 | ot(" ldr r11,[r7,#0x3c] ;@ Get A7\n");\r |
| 449ecf92 |
491 | ot(" tst r6,#0x20\n");\r |
| 0e11c502 |
492 | ot(";@ get our SP:\n");\r |
| 493 | ot(" ldreq r2,[r7,#0x48] ;@ ...or OSP as our stack pointer\n");\r |
| 494 | ot(" streq r11,[r7,#0x48]\n");\r |
| 495 | ot(" moveq r11,r2\n");\r |
| 496 | ot(";@ Push old PC onto stack\n");\r |
| 497 | ot(" sub r0,r11,#4 ;@ Predecremented A7\n");\r |
| 498 | ot(" sub r1,r4,r1 ;@ r1 = Old PC\n");\r |
| 499 | MemHandler(1,2);\r |
| 500 | ot(";@ Push old SR:\n");\r |
| 501 | ot(" ldr r0,[r7,#0x4c] ;@ X bit\n");\r |
| 449ecf92 |
502 | ot(" mov r1,r10,lsr #28 ;@ ____NZCV\n");\r |
| 0e11c502 |
503 | ot(" eor r2,r1,r1,ror #1 ;@ Bit 0=C^V\n");\r |
| 504 | ot(" tst r2,#1 ;@ 1 if C!=V\n");\r |
| 505 | ot(" eorne r1,r1,#3 ;@ ____NZVC\n");\r |
| 506 | ot(" and r0,r0,#0x20000000\n");\r |
| 507 | ot(" orr r1,r1,r0,lsr #25 ;@ ___XNZVC\n");\r |
| 449ecf92 |
508 | ot(" orr r1,r1,r6,lsl #8 ;@ Include old SR high\n");\r |
| 0e11c502 |
509 | ot(" sub r0,r11,#6 ;@ Predecrement A7\n");\r |
| 510 | ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r |
| 511 | MemHandler(1,1,0,0); // already checked for address error by prev MemHandler\r |
| cc68a136 |
512 | ot("\n");\r |
| 0e11c502 |
513 | \r |
| 514 | // 2. Obtain the exception vector.\r |
| 515 | ot(" mov r11,r8,lsr #29\n");\r |
| 516 | ot(" mov r0,r11\n");\r |
| cc68a136 |
517 | #if USE_INT_ACK_CALLBACK\r |
| 0e11c502 |
518 | ot(";@ call IrqCallback if it is defined\n");\r |
| cc68a136 |
519 | #if INT_ACK_NEEDS_STUFF\r |
| 520 | ot(" str r4,[r7,#0x40] ;@ Save PC\n");\r |
| 449ecf92 |
521 | ot(" mov r1,r10,lsr #28\n");\r |
| cc68a136 |
522 | ot(" strb r1,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r |
| 523 | ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");\r |
| 524 | #endif\r |
| 0e11c502 |
525 | ot(" ldr r3,[r7,#0x8c] ;@ IrqCallback\n");\r |
| 526 | ot(" add lr,pc,#4*3\n");\r |
| 527 | ot(" tst r3,r3\n");\r |
| 528 | ot(" streqb r3,[r7,#0x47] ;@ just clear IRQ if there is no callback\n");\r |
| 529 | ot(" mvneq r0,#0 ;@ and simulate -1 return\n");\r |
| 530 | ot(" bxne r3\n");\r |
| 531 | #if INT_ACK_CHANGES_CYCLES\r |
| cc68a136 |
532 | ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");\r |
| cc68a136 |
533 | #endif\r |
| 0e11c502 |
534 | ot(";@ get IRQ vector address:\n");\r |
| 535 | ot(" cmn r0,#1 ;@ returned -1?\n");\r |
| 536 | ot(" addeq r0,r11,#0x18 ;@ use autovector then\n");\r |
| 537 | ot(" cmn r0,#2 ;@ returned -2?\n"); // should be safe as above add should never result in -2\r |
| 538 | ot(" moveq r0,#0x18 ;@ use spurious interrupt then\n");\r |
| ee5e024c |
539 | #else // !USE_INT_ACK_CALLBACK\r |
| cc68a136 |
540 | ot(";@ Clear irq:\n");\r |
| 0e11c502 |
541 | ot(" mov r2,#0\n");\r |
| ee5e024c |
542 | ot(" strb r2,[r7,#0x47]\n");\r |
| 0e11c502 |
543 | ot(" add r0,r0,#0x18 ;@ use autovector\n");\r |
| 544 | #endif\r |
| 545 | ot(" mov r0,r0,lsl #2 ;@ get vector address\n");\r |
| 546 | ot("\n");\r |
| 449ecf92 |
547 | ot(" ldr r11,[r7,#0x60] ;@ Get Memory base\n");\r |
| 0e11c502 |
548 | ot(";@ Read IRQ Vector:\n");\r |
| 549 | MemHandler(0,2,0,0);\r |
| 550 | ot(" tst r0,r0 ;@ uninitialized int vector?\n");\r |
| 551 | ot(" moveq r0,#0x3c\n");\r |
| 552 | ot(" moveq lr,pc\n");\r |
| 553 | ot(" ldreq pc,[r7,#0x70] ;@ Call read32(r0) handler\n");\r |
| 554 | #if USE_CHECKPC_CALLBACK\r |
| 555 | ot(" add lr,pc,#4\n");\r |
| 449ecf92 |
556 | ot(" add r0,r0,r11 ;@ r0 = Memory Base + New PC\n");\r |
| 0e11c502 |
557 | ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r |
| 558 | #if EMULATE_ADDRESS_ERRORS_JUMP\r |
| 559 | ot(" mov r4,r0\n");\r |
| 560 | #else\r |
| 561 | ot(" bic r4,r0,#1\n");\r |
| 562 | #endif\r |
| 563 | #else\r |
| 449ecf92 |
564 | ot(" add r4,r0,r11 ;@ r4 = Memory Base + New PC\n");\r |
| 0e11c502 |
565 | #if EMULATE_ADDRESS_ERRORS_JUMP\r |
| 566 | ot(" bic r4,r4,#1\n");\r |
| 567 | #endif\r |
| 568 | #endif\r |
| 569 | ot("\n");\r |
| 570 | \r |
| 571 | // 4. Obtain a new context and resume instruction processing.\r |
| 572 | // note: the obtain part was already done in previous steps\r |
| 573 | #if EMULATE_ADDRESS_ERRORS_JUMP\r |
| 574 | ot(" tst r4,#1\n");\r |
| 575 | ot(" bne ExceptionAddressError_r_prg_r4\n");\r |
| cc68a136 |
576 | #endif\r |
| 449ecf92 |
577 | ot(" ldr r6,[r7,#0x54]\n");\r |
| ee5e024c |
578 | ot(" ldrh r8,[r4],#2 ;@ Fetch next opcode\n");\r |
| 579 | ot(" subs r5,r5,#44 ;@ Subtract cycles\n");\r |
| 580 | ot(" ldrge pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r |
| 581 | ot(" b CycloneEnd\n");\r |
| cc68a136 |
582 | ot("\n");\r |
| 583 | \r |
| 0e11c502 |
584 | // --------------\r |
| 585 | // trashes all temp regs\r |
| cc68a136 |
586 | ot("Exception%s\n", ms?"":":");\r |
| 0e11c502 |
587 | ot(" ;@ Cause an Exception - Vector number in r0\n");\r |
| 588 | ot(" mov r11,lr ;@ Preserve ARM return address\n");\r |
| 589 | ot(" bic r8,r8,#0xff000000\n");\r |
| 590 | ot(" orr r8,r8,r0,lsl #24 ;@ abuse r8\n");\r |
| 591 | \r |
| 592 | // 1. Make a temporary copy of the status register and set the status register for exception processing.\r |
| 449ecf92 |
593 | ot(" ldr r6,[r7,#0x44] ;@ Get old SR high, abuse r6\n");\r |
| 0e11c502 |
594 | ot(" ldr r2,[r7,#0x58] ;@ state flags\n");\r |
| 449ecf92 |
595 | ot(" and r3,r6,#0x27 ;@ clear trace and unused flags\n");\r |
| 0e11c502 |
596 | ot(" orr r3,r3,#0x20 ;@ set supervisor mode\n");\r |
| 597 | ot(" bic r2,r2,#3 ;@ clear stopped and trace states\n");\r |
| 598 | ot(" str r2,[r7,#0x58]\n");\r |
| 599 | ot(" strb r3,[r7,#0x44] ;@ Put new SR high\n");\r |
| 600 | ot("\n");\r |
| 601 | \r |
| 602 | // 3. Save the current processor context.\r |
| 603 | ot(" ldr r0,[r7,#0x3c] ;@ Get A7\n");\r |
| 449ecf92 |
604 | ot(" tst r6,#0x20\n");\r |
| 0e11c502 |
605 | ot(";@ get our SP:\n");\r |
| 606 | ot(" ldreq r2,[r7,#0x48] ;@ ...or OSP as our stack pointer\n");\r |
| 607 | ot(" streq r0,[r7,#0x48]\n");\r |
| 608 | ot(" moveq r0,r2\n");\r |
| 609 | ot(";@ Push old PC onto stack\n");\r |
| 610 | ot(" ldr r1,[r7,#0x60] ;@ Get Memory base\n");\r |
| 611 | ot(" sub r0,r0,#4 ;@ Predecremented A7\n");\r |
| 612 | ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r |
| 613 | ot(" sub r1,r4,r1 ;@ r1 = Old PC\n");\r |
| 614 | MemHandler(1,2);\r |
| 615 | ot(";@ Push old SR:\n");\r |
| 616 | ot(" ldr r0,[r7,#0x4c] ;@ X bit\n");\r |
| 449ecf92 |
617 | ot(" mov r1,r10,lsr #28 ;@ ____NZCV\n");\r |
| 0e11c502 |
618 | ot(" eor r2,r1,r1,ror #1 ;@ Bit 0=C^V\n");\r |
| 619 | ot(" tst r2,#1 ;@ 1 if C!=V\n");\r |
| 620 | ot(" eorne r1,r1,#3 ;@ ____NZVC\n");\r |
| 621 | ot(" and r0,r0,#0x20000000\n");\r |
| 622 | ot(" orr r1,r1,r0,lsr #25 ;@ ___XNZVC\n");\r |
| 623 | ot(" ldr r0,[r7,#0x3c] ;@ A7\n");\r |
| 449ecf92 |
624 | ot(" orr r1,r1,r6,lsl #8 ;@ Include SR high\n");\r |
| 0e11c502 |
625 | ot(" sub r0,r0,#2 ;@ Predecrement A7\n");\r |
| 626 | ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r |
| 627 | MemHandler(1,1,0,0);\r |
| 628 | ot("\n");\r |
| 629 | \r |
| 630 | // 2. Obtain the exception vector\r |
| 631 | ot(";@ Read Exception Vector:\n");\r |
| 632 | ot(" mov r0,r8,lsr #24\n");\r |
| 633 | ot(" mov r0,r0,lsl #2\n");\r |
| 634 | MemHandler(0,2,0,0);\r |
| 635 | ot(" ldr r3,[r7,#0x60] ;@ Get Memory base\n");\r |
| 636 | #if USE_CHECKPC_CALLBACK\r |
| 637 | ot(" add lr,pc,#4\n");\r |
| 638 | ot(" add r0,r0,r3 ;@ r0 = Memory Base + New PC\n");\r |
| 639 | ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r |
| 640 | #if EMULATE_ADDRESS_ERRORS_JUMP\r |
| 641 | ot(" mov r4,r0\n");\r |
| 642 | #else\r |
| 643 | ot(" bic r4,r0,#1\n");\r |
| 644 | #endif\r |
| 645 | #else\r |
| 646 | ot(" add r4,r0,r3 ;@ r4 = Memory Base + New PC\n");\r |
| 647 | #if EMULATE_ADDRESS_ERRORS_JUMP\r |
| 648 | ot(" bic r4,r4,#1\n");\r |
| 649 | #endif\r |
| 650 | #endif\r |
| 651 | ot("\n");\r |
| 652 | \r |
| 653 | // 4. Resume execution.\r |
| 654 | #if EMULATE_ADDRESS_ERRORS_JUMP\r |
| 655 | ot(" tst r4,#1\n");\r |
| 656 | ot(" bne ExceptionAddressError_r_prg_r4\n");\r |
| 657 | #endif\r |
| 449ecf92 |
658 | ot(" ldr r6,[r7,#0x54]\n");\r |
| 0e11c502 |
659 | ot(" bx r11 ;@ Return\n");\r |
| 660 | ot("\n");\r |
| 661 | \r |
| 662 | // --------------\r |
| 663 | #if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO\r |
| 664 | // first some wrappers: I see no point inlining this code,\r |
| 665 | // as it will be executed in really rare cases.\r |
| 666 | AddressErrorWrapper('r', "data", 0x11);\r |
| 667 | AddressErrorWrapper('r', "prg", 0x12);\r |
| 668 | AddressErrorWrapper('w', "data", 0x01);\r |
| 669 | // there are no program writes\r |
| 670 | // cpu space is only for bus errors?\r |
| 671 | ot("ExceptionAddressError_r_prg_r4%s\n", ms?"":":");\r |
| 672 | ot(" ldr r1,[r7,#0x44]\n");\r |
| 673 | ot(" ldr r3,[r7,#0x60] ;@ Get Memory base\n");\r |
| 449ecf92 |
674 | ot(" mov r6,#0x12\n");\r |
| 0e11c502 |
675 | ot(" sub r11,r4,r3\n");\r |
| 676 | ot(" tst r1,#0x20\n");\r |
| 449ecf92 |
677 | ot(" orrne r6,r6,#4\n");\r |
| 0e11c502 |
678 | ot("\n");\r |
| 679 | \r |
| 680 | ot("ExceptionAddressError%s\n", ms?"":":");\r |
| 449ecf92 |
681 | ot(";@ r6 - info word (without instruction/not bit), r11 - faulting address\n");\r |
| 0e11c502 |
682 | \r |
| 683 | // 1. Make a temporary copy of the status register and set the status register for exception processing.\r |
| 684 | ot(" ldrb r0,[r7,#0x44] ;@ Get old SR high\n");\r |
| 685 | ot(" ldr r2,[r7,#0x58] ;@ state flags\n");\r |
| 686 | ot(" and r3,r0,#0x27 ;@ clear trace and unused flags\n");\r |
| 687 | ot(" orr r3,r3,#0x20 ;@ set supervisor mode\n");\r |
| 688 | ot(" strb r3,[r7,#0x44] ;@ Put new SR high\n");\r |
| 689 | ot(" bic r2,r2,#3 ;@ clear stopped and trace states\n");\r |
| 690 | ot(" tst r2,#4\n");\r |
| 449ecf92 |
691 | ot(" orrne r6,r6,#8 ;@ complete info word\n");\r |
| 0e11c502 |
692 | ot(" orr r2,r2,#4 ;@ set activity bit: 'not processing instruction'\n");\r |
| 693 | #if EMULATE_HALT\r |
| 694 | ot(" tst r2,#8\n");\r |
| 695 | ot(" orrne r2,r2,#0x10 ;@ HALT\n");\r |
| 696 | ot(" orr r2,r2,#8 ;@ processing address error\n");\r |
| 697 | ot(" str r2,[r7,#0x58]\n");\r |
| 698 | ot(" movne r5,#0\n");\r |
| 699 | ot(" bne CycloneEndNoBack ;@ bye bye\n");\r |
| 700 | #else\r |
| 701 | ot(" str r2,[r7,#0x58]\n");\r |
| 702 | #endif\r |
| 449ecf92 |
703 | ot(" and r10,r10,#0xf0000000\n");\r |
| 704 | ot(" orr r10,r10,r0,lsl #4 ;@ some preparations for SR push\n");\r |
| 0e11c502 |
705 | ot("\n");\r |
| 706 | \r |
| 707 | // 3. Save the current processor context + additional information.\r |
| 708 | ot(" ldr r0,[r7,#0x3c] ;@ Get A7\n");\r |
| 449ecf92 |
709 | ot(" tst r10,#0x200\n");\r |
| 0e11c502 |
710 | ot(";@ get our SP:\n");\r |
| 711 | ot(" ldreq r2,[r7,#0x48] ;@ ...or OSP as our stack pointer\n");\r |
| 712 | ot(" streq r0,[r7,#0x48]\n");\r |
| 713 | ot(" moveq r0,r2\n");\r |
| 714 | // PC\r |
| 715 | ot(";@ Push old PC onto stack\n");\r |
| 716 | ot(" ldr r1,[r7,#0x60] ;@ Get Memory base\n");\r |
| 717 | ot(" sub r0,r0,#4 ;@ Predecremented A7\n");\r |
| 718 | ot(" sub r1,r4,r1 ;@ r1 = Old PC\n");\r |
| 719 | ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r |
| 720 | MemHandler(1,2,0,EMULATE_HALT);\r |
| 721 | // SR\r |
| 722 | ot(";@ Push old SR:\n");\r |
| 723 | ot(" ldr r0,[r7,#0x4c] ;@ X bit\n");\r |
| 449ecf92 |
724 | ot(" mov r1,r10,ror #28 ;@ ____NZCV\n");\r |
| 0e11c502 |
725 | ot(" eor r2,r1,r1,ror #1 ;@ Bit 0=C^V\n");\r |
| 726 | ot(" tst r2,#1 ;@ 1 if C!=V\n");\r |
| 727 | ot(" eorne r1,r1,#3 ;@ ____NZVC\n");\r |
| 728 | ot(" and r0,r0,#0x20000000\n");\r |
| 729 | ot(" orr r1,r1,r0,lsr #25 ;@ ___XNZVC\n");\r |
| 730 | ot(" ldr r0,[r7,#0x3c] ;@ A7\n");\r |
| 449ecf92 |
731 | ot(" and r10,r10,#0xf0000000\n");\r |
| 0e11c502 |
732 | ot(" sub r0,r0,#2 ;@ Predecrement A7\n");\r |
| 733 | ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r |
| 734 | MemHandler(1,1,0,0);\r |
| 735 | // IR (instruction register)\r |
| 736 | ot(";@ Push IR:\n");\r |
| 737 | ot(" ldr r0,[r7,#0x3c] ;@ A7\n");\r |
| 738 | ot(" mov r1,r8\n");\r |
| 739 | ot(" sub r0,r0,#2 ;@ Predecrement A7\n");\r |
| 740 | ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r |
| 741 | MemHandler(1,1,0,0);\r |
| 742 | // access address\r |
| 743 | ot(";@ Push address:\n");\r |
| 744 | ot(" ldr r0,[r7,#0x3c] ;@ A7\n");\r |
| 745 | ot(" mov r1,r11\n");\r |
| 746 | ot(" sub r0,r0,#4 ;@ Predecrement A7\n");\r |
| 747 | ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r |
| 748 | MemHandler(1,2,0,0);\r |
| 749 | // information word\r |
| 750 | ot(";@ Push info word:\n");\r |
| 751 | ot(" ldr r0,[r7,#0x3c] ;@ A7\n");\r |
| 449ecf92 |
752 | ot(" mov r1,r6\n");\r |
| 0e11c502 |
753 | ot(" sub r0,r0,#2 ;@ Predecrement A7\n");\r |
| 754 | ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r |
| 755 | MemHandler(1,1,0,0);\r |
| 756 | ot("\n");\r |
| 757 | \r |
| 758 | // 2. Obtain the exception vector\r |
| 759 | ot(";@ Read Exception Vector:\n");\r |
| 760 | ot(" mov r0,#0x0c\n");\r |
| 761 | MemHandler(0,2,0,0);\r |
| 762 | ot(" ldr r3,[r7,#0x60] ;@ Get Memory base\n");\r |
| 763 | #if USE_CHECKPC_CALLBACK\r |
| 764 | ot(" add lr,pc,#4\n");\r |
| 765 | ot(" add r0,r0,r3 ;@ r0 = Memory Base + New PC\n");\r |
| 766 | ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r |
| 767 | ot(" mov r4,r0\n");\r |
| 768 | #else\r |
| 769 | ot(" add r4,r0,r3 ;@ r4 = Memory Base + New PC\n");\r |
| 770 | #endif\r |
| 771 | ot("\n");\r |
| 772 | \r |
| 773 | #if EMULATE_ADDRESS_ERRORS_JUMP && EMULATE_HALT\r |
| 774 | ot(" tst r4,#1\n");\r |
| 775 | ot(" bne ExceptionAddressError_r_prg_r4\n");\r |
| 776 | #else\r |
| 777 | ot(" bic r4,r4,#1\n");\r |
| 778 | #endif\r |
| 779 | \r |
| 780 | // 4. Resume execution.\r |
| 449ecf92 |
781 | ot(" ldr r6,[r7,#0x54]\n");\r |
| 0e11c502 |
782 | ot(" ldrh r8,[r4],#2 ;@ Fetch next opcode\n");\r |
| 783 | ot(" subs r5,r5,#50 ;@ Subtract cycles\n");\r |
| 784 | ot(" ldrge pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r |
| 785 | ot(" b CycloneEnd\n");\r |
| 786 | ot("\n");\r |
| 787 | #endif\r |
| 788 | \r |
| 789 | // --------------\r |
| 790 | #if EMULATE_TRACE\r |
| 791 | // expects srh and irq level in r1, next opcode already fetched to r8\r |
| 792 | ot("CycloneDoTraceWithChecks%s\n", ms?"":":");\r |
| 793 | ot(" ldr r0,[r7,#0x58]\n");\r |
| 794 | ot(" cmp r5,#0\n");\r |
| 795 | ot(" orr r0,r0,#2 ;@ go to trace mode\n");\r |
| 796 | ot(" str r0,[r7,#0x58]\n");\r |
| 797 | ot(" blt CycloneEnd\n"); // should take care of situation where we come here when already tracing\r |
| 798 | ot(";@ CheckInterrupt:\n");\r |
| 799 | ot(" movs r0,r1,lsr #24 ;@ Get IRQ level\n");\r |
| 800 | ot(" beq CycloneDoTrace\n");\r |
| 801 | ot(" cmp r0,#6 ;@ irq>6 ?\n");\r |
| 802 | ot(" andle r1,r1,#7 ;@ Get interrupt mask\n");\r |
| 803 | ot(" cmple r0,r1 ;@ irq<=6: Is irq<=mask ?\n");\r |
| 804 | ot(" bgt CycloneDoInterruptGoBack\n");\r |
| 805 | ot("\n");\r |
| 806 | \r |
| 807 | // expects next opcode to be already fetched to r8\r |
| 808 | ot("CycloneDoTrace%s\n", ms?"":":");\r |
| 809 | ot(" str r5,[r7,#0x9c] ;@ save cycles\n");\r |
| 810 | ot(" ldr r1,[r7,#0x98]\n");\r |
| 811 | ot(" mov r5,#0\n");\r |
| 812 | ot(" str r1,[r7,#0xa0]\n");\r |
| 813 | ot(" adr r0,TraceEnd\n");\r |
| 814 | ot(" str r0,[r7,#0x98] ;@ store TraceEnd as CycloneEnd hadler\n");\r |
| 815 | ot(" ldr pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r |
| 816 | ot("\n");\r |
| 817 | \r |
| 818 | ot("TraceEnd%s\n", ms?"":":");\r |
| 819 | ot(" ldr r2,[r7,#0x58]\n");\r |
| 820 | ot(" ldr r0,[r7,#0x9c] ;@ restore cycles\n");\r |
| 821 | ot(" ldr r1,[r7,#0xa0] ;@ old CycloneEnd handler\n");\r |
| 449ecf92 |
822 | ot(" mov r10,r10,lsl #28\n");\r |
| 0e11c502 |
823 | ot(" add r5,r0,r5\n");\r |
| 824 | ot(" str r1,[r7,#0x98]\n");\r |
| 825 | ot(";@ still tracing?\n"); // exception might have happend\r |
| 826 | ot(" tst r2,#2\n");\r |
| 827 | ot(" beq TraceDisabled\n");\r |
| 828 | ot(";@ trace exception\n");\r |
| 829 | #if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO\r |
| 830 | ot(" ldr r1,[r7,#0x58]\n");\r |
| 831 | ot(" mov r0,#9\n");\r |
| 832 | ot(" orr r1,r1,#4 ;@ set activity bit: 'not processing instruction'\n");\r |
| 833 | ot(" str r1,[r7,#0x58]\n");\r |
| 834 | #else\r |
| 835 | ot(" mov r0,#9\n");\r |
| 836 | #endif\r |
| 837 | ot(" bl Exception\n");\r |
| 838 | ot(" ldrh r8,[r4],#2 ;@ Fetch next opcode\n");\r |
| 839 | ot(" subs r5,r5,#34 ;@ Subtract cycles\n");\r |
| 840 | ot(" ldrge pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r |
| 841 | ot(" b CycloneEnd\n");\r |
| cc68a136 |
842 | ot("\n");\r |
| 0e11c502 |
843 | ot("TraceDisabled%s\n", ms?"":":");\r |
| 844 | ot(" ldrh r8,[r4],#2 ;@ Fetch next opcode\n");\r |
| 845 | ot(" cmp r5,#0\n");\r |
| 846 | ot(" ldrge pc,[r6,r8,asl #2] ;@ Jump to opcode handler\n");\r |
| 847 | ot(" b CycloneEnd\n");\r |
| 848 | ot("\n");\r |
| 849 | #endif\r |
| cc68a136 |
850 | }\r |
| 851 | \r |
| 852 | // ---------------------------------------------------------------------------\r |
| 853 | // Call Read(r0), Write(r0,r1) or Fetch(r0)\r |
| 854 | // Trashes r0-r3,r12,lr\r |
| 0e11c502 |
855 | int MemHandler(int type,int size,int addrreg,int need_addrerr_check)\r |
| cc68a136 |
856 | {\r |
| 857 | int func=0;\r |
| 858 | func=0x68+type*0xc+(size<<2); // Find correct offset\r |
| 859 | \r |
| cc68a136 |
860 | #if MEMHANDLERS_NEED_FLAGS\r |
| 449ecf92 |
861 | ot(" mov r3,r10,lsr #28\n");\r |
| cc68a136 |
862 | ot(" strb r3,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r |
| 863 | #endif\r |
| cfb3dfa0 |
864 | FlushPC();\r |
| cc68a136 |
865 | \r |
| a6785576 |
866 | #if (MEMHANDLERS_ADDR_MASK & 0xff000000)\r |
| cfb3dfa0 |
867 | ot(" bic r0,r%i,#0x%08x\n", addrreg, MEMHANDLERS_ADDR_MASK & 0xff000000);\r |
| 868 | addrreg=0;\r |
| a6785576 |
869 | #endif\r |
| 870 | #if (MEMHANDLERS_ADDR_MASK & 0x00ff0000)\r |
| cfb3dfa0 |
871 | ot(" bic r0,r%i,#0x%08x\n", addrreg, MEMHANDLERS_ADDR_MASK & 0x00ff0000);\r |
| 872 | addrreg=0;\r |
| a6785576 |
873 | #endif\r |
| 874 | #if (MEMHANDLERS_ADDR_MASK & 0x0000ff00)\r |
| cfb3dfa0 |
875 | ot(" bic r0,r%i,#0x%08x\n", addrreg, MEMHANDLERS_ADDR_MASK & 0x0000ff00);\r |
| 876 | addrreg=0;\r |
| a6785576 |
877 | #endif\r |
| 878 | #if (MEMHANDLERS_ADDR_MASK & 0x000000ff)\r |
| cfb3dfa0 |
879 | ot(" bic r0,r%i,#0x%08x\n", addrreg, MEMHANDLERS_ADDR_MASK & 0x000000ff);\r |
| 880 | addrreg=0;\r |
| a6785576 |
881 | #endif\r |
| 0e11c502 |
882 | \r |
| 883 | #if EMULATE_ADDRESS_ERRORS_IO\r |
| 884 | if (size > 0 && need_addrerr_check)\r |
| 885 | {\r |
| 886 | ot(" add lr,pc,#4*%i\n", addrreg==0?2:3); // helps to prevent interlocks\r |
| 887 | if (addrreg != 0) ot(" mov r0,r%i\n", addrreg);\r |
| 888 | ot(" tst r0,#1 ;@ address error?\n");\r |
| 889 | switch (type) {\r |
| 890 | case 0: ot(" bne ExceptionAddressError_r_data\n"); break;\r |
| 891 | case 1: ot(" bne ExceptionAddressError_w_data\n"); break;\r |
| 892 | case 2: ot(" bne ExceptionAddressError_r_prg\n"); break;\r |
| 893 | }\r |
| 894 | }\r |
| 895 | else\r |
| 896 | #endif\r |
| cfb3dfa0 |
897 | if (addrreg != 0)\r |
| 85a36a57 |
898 | {\r |
| 0e11c502 |
899 | ot(" add lr,pc,#4\n");\r |
| cfb3dfa0 |
900 | ot(" mov r0,r%i\n", addrreg);\r |
| 85a36a57 |
901 | }\r |
| 902 | else\r |
| 903 | ot(" mov lr,pc\n");\r |
| cc68a136 |
904 | ot(" ldr pc,[r7,#0x%x] ;@ Call ",func);\r |
| 905 | \r |
| 906 | // Document what we are calling:\r |
| 907 | if (type==0) ot("read");\r |
| 908 | if (type==1) ot("write");\r |
| 909 | if (type==2) ot("fetch");\r |
| 910 | \r |
| 911 | if (type==1) ot("%d(r0,r1)",8<<size);\r |
| 912 | else ot("%d(r0)", 8<<size);\r |
| 913 | ot(" handler\n");\r |
| 914 | \r |
| cc68a136 |
915 | #if MEMHANDLERS_CHANGE_FLAGS\r |
| 449ecf92 |
916 | ot(" ldrb r10,[r7,#0x46] ;@ r10 = Load Flags (NZCV)\n");\r |
| 917 | ot(" mov r10,r10,lsl #28\n");\r |
| cc68a136 |
918 | #endif\r |
| 919 | #if MEMHANDLERS_CHANGE_PC\r |
| 920 | ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");\r |
| 921 | #endif\r |
| 922 | \r |
| 923 | return 0;\r |
| 924 | }\r |
| 925 | \r |
| 926 | static void PrintOpcodes()\r |
| 927 | {\r |
| 928 | int op=0;\r |
| b637c56a |
929 | \r |
| cc68a136 |
930 | printf("Creating Opcodes: [");\r |
| 931 | \r |
| 932 | ot(";@ ---------------------------- Opcodes ---------------------------\n");\r |
| 933 | \r |
| 934 | // Emit null opcode:\r |
| 935 | ot("Op____%s ;@ Called if an opcode is not recognised\n", ms?"":":");\r |
| 0e11c502 |
936 | #if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO\r |
| 937 | ot(" ldr r1,[r7,#0x58]\n");\r |
| cc68a136 |
938 | ot(" sub r4,r4,#2\n");\r |
| 0e11c502 |
939 | ot(" orr r1,r1,#4 ;@ set activity bit: 'not processing instruction'\n");\r |
| 940 | ot(" str r1,[r7,#0x58]\n");\r |
| 941 | #else\r |
| 942 | ot(" sub r4,r4,#2\n");\r |
| 943 | #endif\r |
| cc68a136 |
944 | #if USE_UNRECOGNIZED_CALLBACK\r |
| 945 | ot(" str r4,[r7,#0x40] ;@ Save PC\n");\r |
| 449ecf92 |
946 | ot(" mov r1,r10,lsr #28\n");\r |
| cc68a136 |
947 | ot(" strb r1,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r |
| 948 | ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");\r |
| 949 | ot(" ldr r11,[r7,#0x94] ;@ UnrecognizedCallback\n");\r |
| 950 | ot(" tst r11,r11\n");\r |
| 951 | ot(" movne lr,pc\n");\r |
| 952 | ot(" movne pc,r11 ;@ call UnrecognizedCallback if it is defined\n");\r |
| 449ecf92 |
953 | ot(" ldrb r10,[r7,#0x46] ;@ r10 = Load Flags (NZCV)\n");\r |
| cc68a136 |
954 | ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");\r |
| 955 | ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");\r |
| 449ecf92 |
956 | ot(" mov r10,r10,lsl #28\n");\r |
| cc68a136 |
957 | ot(" tst r0,r0\n");\r |
| 0e11c502 |
958 | ot(" moveq r0,#4\n");\r |
| cc68a136 |
959 | ot(" bleq Exception\n");\r |
| 960 | #else\r |
| 0e11c502 |
961 | ot(" mov r0,#4\n");\r |
| cc68a136 |
962 | ot(" bl Exception\n");\r |
| 963 | #endif\r |
| 85a36a57 |
964 | ot("\n");\r |
| cc68a136 |
965 | Cycles=34;\r |
| 966 | OpEnd();\r |
| 967 | \r |
| 968 | // Unrecognised a-line and f-line opcodes throw an exception:\r |
| 969 | ot("Op__al%s ;@ Unrecognised a-line opcode\n", ms?"":":");\r |
| 970 | ot(" sub r4,r4,#2\n");\r |
| 971 | #if USE_AFLINE_CALLBACK\r |
| 972 | ot(" str r4,[r7,#0x40] ;@ Save PC\n");\r |
| 449ecf92 |
973 | ot(" mov r1,r10,lsr #28\n");\r |
| cc68a136 |
974 | ot(" strb r1,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r |
| 975 | ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");\r |
| 976 | ot(" ldr r11,[r7,#0x94] ;@ UnrecognizedCallback\n");\r |
| 977 | ot(" tst r11,r11\n");\r |
| 978 | ot(" movne lr,pc\n");\r |
| 979 | ot(" movne pc,r11 ;@ call UnrecognizedCallback if it is defined\n");\r |
| 449ecf92 |
980 | ot(" ldrb r10,[r7,#0x46] ;@ r10 = Load Flags (NZCV)\n");\r |
| cc68a136 |
981 | ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");\r |
| 982 | ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");\r |
| 449ecf92 |
983 | ot(" mov r10,r10,lsl #28\n");\r |
| cc68a136 |
984 | ot(" tst r0,r0\n");\r |
| 0e11c502 |
985 | ot(" moveq r0,#0x0a\n");\r |
| cc68a136 |
986 | ot(" bleq Exception\n");\r |
| 987 | #else\r |
| 0e11c502 |
988 | ot(" mov r0,#0x0a\n");\r |
| cc68a136 |
989 | ot(" bl Exception\n");\r |
| 990 | #endif\r |
| 85a36a57 |
991 | ot("\n");\r |
| cc68a136 |
992 | Cycles=4;\r |
| 993 | OpEnd();\r |
| 994 | \r |
| 995 | ot("Op__fl%s ;@ Unrecognised f-line opcode\n", ms?"":":");\r |
| 996 | ot(" sub r4,r4,#2\n");\r |
| 997 | #if USE_AFLINE_CALLBACK\r |
| 998 | ot(" str r4,[r7,#0x40] ;@ Save PC\n");\r |
| 449ecf92 |
999 | ot(" mov r1,r10,lsr #28\n");\r |
| cc68a136 |
1000 | ot(" strb r1,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r |
| 1001 | ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");\r |
| 1002 | ot(" ldr r11,[r7,#0x94] ;@ UnrecognizedCallback\n");\r |
| 1003 | ot(" tst r11,r11\n");\r |
| 1004 | ot(" movne lr,pc\n");\r |
| 1005 | ot(" movne pc,r11 ;@ call UnrecognizedCallback if it is defined\n");\r |
| 449ecf92 |
1006 | ot(" ldrb r10,[r7,#0x46] ;@ r10 = Load Flags (NZCV)\n");\r |
| cc68a136 |
1007 | ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");\r |
| 1008 | ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");\r |
| 449ecf92 |
1009 | ot(" mov r10,r10,lsl #28\n");\r |
| cc68a136 |
1010 | ot(" tst r0,r0\n");\r |
| 0e11c502 |
1011 | ot(" moveq r0,#0x0b\n");\r |
| cc68a136 |
1012 | ot(" bleq Exception\n");\r |
| 1013 | #else\r |
| 0e11c502 |
1014 | ot(" mov r0,#0x0b\n");\r |
| cc68a136 |
1015 | ot(" bl Exception\n");\r |
| 1016 | #endif\r |
| 85a36a57 |
1017 | ot("\n");\r |
| cc68a136 |
1018 | Cycles=4;\r |
| 1019 | OpEnd();\r |
| 1020 | \r |
| 1021 | \r |
| d4789c7c |
1022 | for (op=0;op<hot_opcode_count;op++)\r |
| 1023 | OpAny(hot_opcodes[op]);\r |
| 1024 | \r |
| cc68a136 |
1025 | for (op=0;op<0x10000;op++)\r |
| 1026 | {\r |
| 1027 | if ((op&0xfff)==0) { printf("%x",op>>12); fflush(stdout); } // Update progress\r |
| 1028 | \r |
| d4789c7c |
1029 | if (!is_op_hot(op))\r |
| 1030 | OpAny(op);\r |
| cc68a136 |
1031 | }\r |
| 1032 | \r |
| 1033 | ot("\n");\r |
| 1034 | \r |
| 1035 | printf("]\n");\r |
| 1036 | }\r |
| 1037 | \r |
| 1038 | // helper\r |
| 1039 | static void ott(const char *str, int par, const char *nl, int nlp, int counter, int size)\r |
| 1040 | {\r |
| 1041 | switch(size) {\r |
| 1042 | case 0: if((counter&7)==0) ot(ms?" dcb ":" .byte "); break;\r |
| 1043 | case 1: if((counter&7)==0) ot(ms?" dcw ":" .hword "); break;\r |
| 1044 | case 2: if((counter&7)==0) ot(ms?" dcd ":" .long "); break;\r |
| 1045 | }\r |
| 1046 | ot(str, par);\r |
| 1047 | if((counter&7)==7) ot(nl,nlp); else ot(",");\r |
| 1048 | }\r |
| 1049 | \r |
| 1050 | static void PrintJumpTable()\r |
| 1051 | {\r |
| 1052 | int i=0,op=0,len=0;\r |
| 1053 | \r |
| 1054 | ot(";@ -------------------------- Jump Table --------------------------\n");\r |
| 1055 | \r |
| c008977e |
1056 | // space for decompressed table\r |
| 1057 | ot(ms?" area |.data|, data\n":" .data\n .align 4\n\n");\r |
| 1058 | \r |
| cc68a136 |
1059 | #if COMPRESS_JUMPTABLE\r |
| 1060 | int handlers=0,reps=0,*indexes,ip,u,out;\r |
| 1061 | // use some weird compression on the jump table\r |
| a6785576 |
1062 | indexes=(int *)malloc(0x10000*4);\r |
| 1063 | if(!indexes) { printf("ERROR: out of memory\n"); exit(1); }\r |
| 1064 | len=0x10000;\r |
| cc68a136 |
1065 | \r |
| a6785576 |
1066 | ot("CycloneJumpTab%s\n", ms?"":":");\r |
| 1067 | if(ms) {\r |
| 1068 | for(i = 0; i < 0xa000/8; i++)\r |
| 1069 | ot(" dcd 0,0,0,0,0,0,0,0\n");\r |
| 1070 | } else\r |
| 1071 | ot(" .rept 0x%x\n .long 0,0,0,0,0,0,0,0\n .endr\n", 0xa000/8);\r |
| cc68a136 |
1072 | \r |
| 1073 | // hanlers live in "a-line" part of the table\r |
| a6785576 |
1074 | // first output nop,a-line,f-line handlers\r |
| 1075 | ot(ms?" dcd Op____,Op__al,Op__fl,":" .long Op____,Op__al,Op__fl,");\r |
| 1076 | handlers=3;\r |
| cc68a136 |
1077 | \r |
| a6785576 |
1078 | for(i=0;i<len;i++)\r |
| cc68a136 |
1079 | {\r |
| 1080 | op=CyJump[i];\r |
| 1081 | \r |
| a6785576 |
1082 | for(u=i-1; u>=0; u--) if(op == CyJump[u]) break; // already done with this op?\r |
| 1083 | if(u==-1 && op >= 0) {\r |
| 1084 | ott("Op%.4x",op," ;@ %.4x\n",i,handlers,2);\r |
| 1085 | indexes[op] = handlers;\r |
| 1086 | handlers++;\r |
| cc68a136 |
1087 | }\r |
| a6785576 |
1088 | }\r |
| 1089 | if(handlers&7) {\r |
| 1090 | fseek(AsmFile, -1, SEEK_CUR); // remove last comma\r |
| 1091 | for(i = 8-(handlers&7); i > 0; i--)\r |
| 1092 | ot(",000000");\r |
| 1093 | ot("\n");\r |
| 1094 | }\r |
| 1095 | if(ms) {\r |
| 1096 | for(i = (0x4000-handlers)/8; i > 0; i--)\r |
| 1097 | ot(" dcd 0,0,0,0,0,0,0,0\n");\r |
| 1098 | } else {\r |
| 1099 | ot(ms?"":" .rept 0x%x\n .long 0,0,0,0,0,0,0,0\n .endr\n", (0x4000-handlers)/8);\r |
| 1100 | }\r |
| cc68a136 |
1101 | printf("total distinct hanlers: %i\n",handlers);\r |
| a6785576 |
1102 | // output data\r |
| 1103 | for(i=0,ip=0; i < 0xf000; i++, ip++) {\r |
| cc68a136 |
1104 | op=CyJump[i];\r |
| a6785576 |
1105 | if(op == -2) {\r |
| 1106 | // it must skip a-line area, because we keep our data there\r |
| 1107 | ott("0x%.4x", handlers<<4, "\n",0,ip++,1);\r |
| 1108 | ott("0x%.4x", 0x1000, "\n",0,ip,1);\r |
| 1109 | i+=0xfff;\r |
| 1110 | continue;\r |
| 1111 | }\r |
| 1112 | for(reps=1; i < 0xf000; i++, reps++) if(op != CyJump[i+1]) break;\r |
| 1113 | if(op>=0) out=indexes[op]<<4; else out=0; // unrecognised\r |
| 1114 | if(reps <= 0xe || reps==0x10) {\r |
| 1115 | if(reps!=0x10) out|=reps; else out|=0xf; // 0xf means 0x10 (0xf appeared to be unused anyway)\r |
| 1116 | ott("0x%.4x", out, "\n",0,ip,1);\r |
| cc68a136 |
1117 | } else {\r |
| a6785576 |
1118 | ott("0x%.4x", out, "\n",0,ip++,1);\r |
| 1119 | ott("0x%.4x", reps,"\n",0,ip,1);\r |
| 1120 | }\r |
| cc68a136 |
1121 | }\r |
| a6785576 |
1122 | if(ip&1) ott("0x%.4x", 0, "\n",0,ip++,1);\r |
| 1123 | if(ip&7) fseek(AsmFile, -1, SEEK_CUR); // remove last comma\r |
| a6785576 |
1124 | if(ip&7) {\r |
| 1125 | for(i = 8-(ip&7); i > 0; i--)\r |
| 1126 | ot(",0x0000");\r |
| a6785576 |
1127 | }\r |
| 547045e3 |
1128 | ot("\n");\r |
| a6785576 |
1129 | if(ms) {\r |
| 1130 | for(i = (0x2000-ip/2)/8+1; i > 0; i--)\r |
| 1131 | ot(" dcd 0,0,0,0,0,0,0,0\n");\r |
| 1132 | } else {\r |
| 1133 | ot(" .rept 0x%x\n .long 0,0,0,0,0,0,0,0\n .endr\n", (0x2000-ip/2)/8+1);\r |
| 1134 | }\r |
| 1135 | ot("\n");\r |
| 1136 | free(indexes);\r |
| cc68a136 |
1137 | #else\r |
| a6785576 |
1138 | ot("CycloneJumpTab%s\n", ms?"":":");\r |
| cc68a136 |
1139 | len=0xfffe; // Hmmm, armasm 2.50.8684 messes up with a 0x10000 long jump table\r |
| 1140 | // notaz: same thing with GNU as 2.9-psion-98r2 (reloc overflow)\r |
| 1141 | // this is due to COFF objects using only 2 bytes for reloc count\r |
| 1142 | \r |
| 1143 | for (i=0;i<len;i++)\r |
| 1144 | {\r |
| 1145 | op=CyJump[i];\r |
| 1146 | \r |
| 1147 | if(op>=0) ott("Op%.4x",op," ;@ %.4x\n",i-7,i,2);\r |
| 1148 | else if(op==-2) ott("Op__al",0, " ;@ %.4x\n",i-7,i,2);\r |
| 1149 | else if(op==-3) ott("Op__fl",0, " ;@ %.4x\n",i-7,i,2);\r |
| 1150 | else ott("Op____",0, " ;@ %.4x\n",i-7,i,2);\r |
| 1151 | }\r |
| a6785576 |
1152 | if(i&7) fseek(AsmFile, -1, SEEK_CUR); // remove last comma\r |
| cc68a136 |
1153 | \r |
| 1154 | ot("\n");\r |
| 1155 | ot(";@ notaz: we don't want to crash if we run into those 2 missing opcodes\n");\r |
| 1156 | ot(";@ so we leave this pattern to patch it later\n");\r |
| 1157 | ot("%s 0x78563412\n", ms?" dcd":" .long");\r |
| 1158 | ot("%s 0x56341290\n", ms?" dcd":" .long");\r |
| 1159 | #endif\r |
| 1160 | }\r |
| 1161 | \r |
| 1162 | static int CycloneMake()\r |
| 1163 | {\r |
| 1164 | int i;\r |
| d95259bd |
1165 | const char *name="Cyclone.s";\r |
| 0e11c502 |
1166 | const char *globl=ms?"export":".global";\r |
| cc68a136 |
1167 | \r |
| 1168 | // Open the assembly file\r |
| 1169 | if (ms) name="Cyclone.asm";\r |
| 1170 | AsmFile=fopen(name,"wt"); if (AsmFile==NULL) return 1;\r |
| 1171 | \r |
| 1172 | printf("Making %s...\n",name);\r |
| 1173 | \r |
| 1174 | ot("\n;@ Dave's Cyclone 68000 Emulator v%x.%.3x - Assembler Output\n\n",CycloneVer>>12,CycloneVer&0xfff);\r |
| 1175 | \r |
| 1176 | ot(";@ (c) Copyright 2003 Dave, All rights reserved.\n");\r |
| 547045e3 |
1177 | ot(";@ some code (c) Copyright 2005-2007 notaz, All rights reserved.\n");\r |
| cc68a136 |
1178 | ot(";@ Cyclone 68000 is free for non-commercial use.\n\n");\r |
| 1179 | ot(";@ For commercial use, separate licencing terms must be obtained.\n\n");\r |
| 1180 | \r |
| 1181 | CyJump=(int *)malloc(0x40000); if (CyJump==NULL) return 1;\r |
| 1182 | memset(CyJump,0xff,0x40000); // Init to -1\r |
| 1183 | for(i=0xa000; i<0xb000; i++) CyJump[i] = -2; // a-line emulation\r |
| 1184 | for(i=0xf000; i<0x10000; i++) CyJump[i] = -3; // f-line emulation\r |
| 1185 | \r |
| 0e11c502 |
1186 | ot(ms?" area |.text|, code\n":" .text\n .align 4\n\n");\r |
| 1187 | ot(" %s CycloneInit\n",globl);\r |
| 1188 | ot(" %s CycloneRun\n",globl);\r |
| 1189 | ot(" %s CycloneSetSr\n",globl);\r |
| 1190 | ot(" %s CycloneGetSr\n",globl);\r |
| 1191 | ot(" %s CycloneFlushIrq\n",globl);\r |
| 1192 | ot(" %s CyclonePack\n",globl);\r |
| 1193 | ot(" %s CycloneUnpack\n",globl);\r |
| 1194 | ot(" %s CycloneVer\n",globl);\r |
| a9a5a6e0 |
1195 | #if (CYCLONE_FOR_GENESIS == 2)\r |
| 0e11c502 |
1196 | ot(" %s CycloneSetRealTAS\n",globl);\r |
| 1197 | ot(" %s CycloneDoInterrupt\n",globl);\r |
| 1198 | ot(" %s CycloneDoTrace\n",globl);\r |
| 1199 | ot(" %s CycloneJumpTab\n",globl);\r |
| d95259bd |
1200 | ot(" %s Op____\n",globl);\r |
| 1201 | ot(" %s Op6001\n",globl);\r |
| 1202 | ot(" %s Op6601\n",globl);\r |
| 1203 | ot(" %s Op6701\n",globl);\r |
| 7336a99a |
1204 | #endif\r |
| 0e11c502 |
1205 | ot("\n");\r |
| 1206 | ot(ms?"CycloneVer dcd 0x":"CycloneVer: .long 0x");\r |
| 1207 | ot("%.4x\n",CycloneVer);\r |
| cc68a136 |
1208 | ot("\n");\r |
| 1209 | \r |
| 1210 | PrintFramework();\r |
| b637c56a |
1211 | arm_op_count = 0;\r |
| cc68a136 |
1212 | PrintOpcodes();\r |
| b637c56a |
1213 | printf("~%i ARM instructions used for opcode handlers\n", arm_op_count);\r |
| cc68a136 |
1214 | PrintJumpTable();\r |
| 1215 | \r |
| 1216 | if (ms) ot(" END\n");\r |
| 1217 | \r |
| 7336a99a |
1218 | ot("\n\n;@ vim:filetype=armasm\n");\r |
| 1219 | \r |
| cc68a136 |
1220 | fclose(AsmFile); AsmFile=NULL;\r |
| 1221 | \r |
| 1222 | #if 0\r |
| 1223 | printf("Assembling...\n");\r |
| 1224 | // Assemble the file\r |
| 1225 | if (ms) system("armasm Cyclone.asm");\r |
| 1226 | else system("as -o Cyclone.o Cyclone.s");\r |
| 1227 | printf("Done!\n\n");\r |
| 1228 | #endif\r |
| 1229 | \r |
| 1230 | free(CyJump);\r |
| 1231 | return 0;\r |
| 1232 | }\r |
| 1233 | \r |
| 1234 | int main()\r |
| 1235 | {\r |
| 1236 | printf("\n Dave's Cyclone 68000 Emulator v%x.%.3x - Core Creator\n\n",CycloneVer>>12,CycloneVer&0xfff);\r |
| 1237 | \r |
| 1238 | // Make GAS or ARMASM version\r |
| 1239 | CycloneMake();\r |
| 1240 | return 0;\r |
| 1241 | }\r |
| 1242 | \r |
notaz.gp2x.de / picodrive.git / blame