cc68a136 |
1 | \r |
2 | #include "app.h"\r |
3 | \r |
0e11c502 |
4 | // in/out address in r0, trashes all temp regs\r |
5 | static void CheckPc(void)\r |
cc68a136 |
6 | {\r |
cfb3dfa0 |
7 | #if USE_CHECKPC_CALLBACK\r |
0e11c502 |
8 | ot(";@ Check Memory Base+pc\n");\r |
cfb3dfa0 |
9 | ot(" mov lr,pc\n");\r |
cc68a136 |
10 | ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r |
cc68a136 |
11 | ot("\n");\r |
0e11c502 |
12 | #endif\r |
cc68a136 |
13 | }\r |
cc68a136 |
14 | \r |
15 | // Push 32-bit value in r1 - trashes r0-r3,r12,lr\r |
16 | void OpPush32()\r |
17 | {\r |
18 | ot(";@ Push r1 onto stack\n");\r |
19 | ot(" ldr r0,[r7,#0x3c]\n");\r |
20 | ot(" sub r0,r0,#4 ;@ Predecrement A7\n");\r |
21 | ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r |
22 | MemHandler(1,2);\r |
23 | ot("\n");\r |
24 | }\r |
25 | \r |
26 | // Push SR - trashes r0-r3,r12,lr\r |
27 | void OpPushSr(int high)\r |
28 | {\r |
29 | ot(";@ Push SR:\n");\r |
30 | OpFlagsToReg(high);\r |
31 | ot(" ldr r0,[r7,#0x3c]\n");\r |
32 | ot(" sub r0,r0,#2 ;@ Predecrement A7\n");\r |
33 | ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r |
34 | MemHandler(1,1);\r |
35 | ot("\n");\r |
36 | }\r |
37 | \r |
38 | // Pop SR - trashes r0-r3\r |
39 | static void PopSr(int high)\r |
40 | {\r |
41 | ot(";@ Pop SR:\n");\r |
42 | ot(" ldr r0,[r7,#0x3c]\n");\r |
43 | ot(" add r1,r0,#2 ;@ Postincrement A7\n");\r |
44 | ot(" str r1,[r7,#0x3c] ;@ Save A7\n");\r |
45 | MemHandler(0,1);\r |
46 | ot("\n");\r |
47 | OpRegToFlags(high);\r |
48 | }\r |
49 | \r |
50 | // Pop PC - assumes r10=Memory Base - trashes r0-r3\r |
51 | static void PopPc()\r |
52 | {\r |
53 | ot(";@ Pop PC:\n");\r |
54 | ot(" ldr r0,[r7,#0x3c]\n");\r |
55 | ot(" add r1,r0,#4 ;@ Postincrement A7\n");\r |
56 | ot(" str r1,[r7,#0x3c] ;@ Save A7\n");\r |
57 | MemHandler(0,2);\r |
cfb3dfa0 |
58 | ot(" add r0,r0,r10 ;@ Memory Base+PC\n");\r |
cc68a136 |
59 | ot("\n");\r |
0e11c502 |
60 | CheckPc();\r |
61 | #if EMULATE_ADDRESS_ERRORS_JUMP\r |
62 | ot(" mov r4,r0\n");\r |
63 | #else\r |
64 | ot(" bic r4,r0,#1\n");\r |
65 | #endif\r |
cc68a136 |
66 | }\r |
67 | \r |
68 | int OpTrap(int op)\r |
69 | {\r |
70 | int use=0;\r |
71 | \r |
72 | use=op&~0xf;\r |
73 | if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r |
74 | \r |
a6785576 |
75 | OpStart(op,0x10);\r |
cc68a136 |
76 | ot(" and r0,r8,#0xf ;@ Get trap number\n");\r |
0e11c502 |
77 | ot(" orr r0,r0,#0x20 ;@ 32+n\n");\r |
cc68a136 |
78 | ot(" bl Exception\n");\r |
79 | ot("\n");\r |
80 | \r |
cfb3dfa0 |
81 | Cycles=38; OpEnd(0x10);\r |
cc68a136 |
82 | \r |
83 | return 0;\r |
84 | }\r |
85 | \r |
86 | // --------------------- Opcodes 0x4e50+ ---------------------\r |
87 | int OpLink(int op)\r |
88 | {\r |
89 | int use=0,reg;\r |
90 | \r |
91 | use=op&~7;\r |
92 | reg=op&7;\r |
93 | if (reg==7) use=op;\r |
94 | if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r |
95 | \r |
a6785576 |
96 | OpStart(op,0x10);\r |
cc68a136 |
97 | \r |
98 | if(reg!=7) {\r |
99 | ot(";@ Get An\n");\r |
100 | EaCalc(10, 7, 8, 2, 1);\r |
101 | EaRead(10, 1, 8, 2, 7, 1);\r |
102 | }\r |
103 | \r |
104 | ot(" ldr r0,[r7,#0x3c] ;@ Get A7\n");\r |
105 | ot(" sub r0,r0,#4 ;@ A7-=4\n");\r |
106 | ot(" mov r11,r0\n");\r |
107 | if(reg==7) ot(" mov r1,r0\n");\r |
108 | ot("\n");\r |
109 | \r |
110 | ot(";@ Write An to Stack\n");\r |
111 | MemHandler(1,2);\r |
112 | \r |
113 | ot(";@ Save to An\n");\r |
114 | if(reg!=7)\r |
115 | EaWrite(10,11, 8, 2, 7, 1);\r |
116 | \r |
117 | ot(";@ Get offset:\n");\r |
118 | EaCalc(0,0,0x3c,1);\r |
119 | EaRead(0,0,0x3c,1,0);\r |
120 | \r |
121 | ot(" add r11,r11,r0 ;@ Add offset to A7\n");\r |
122 | ot(" str r11,[r7,#0x3c]\n");\r |
123 | ot("\n");\r |
124 | \r |
125 | Cycles=16;\r |
cfb3dfa0 |
126 | OpEnd(0x10);\r |
cc68a136 |
127 | return 0;\r |
128 | }\r |
129 | \r |
130 | // --------------------- Opcodes 0x4e58+ ---------------------\r |
131 | int OpUnlk(int op)\r |
132 | {\r |
133 | int use=0;\r |
134 | \r |
135 | use=op&~7;\r |
136 | if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r |
137 | \r |
a6785576 |
138 | OpStart(op,0x10);\r |
cc68a136 |
139 | \r |
140 | ot(";@ Get An\n");\r |
85a36a57 |
141 | EaCalc(10, 0xf, 8, 2, 1);\r |
142 | EaRead(10, 0, 8, 2, 0xf, 1);\r |
cc68a136 |
143 | \r |
144 | ot(" add r11,r0,#4 ;@ A7+=4\n");\r |
145 | ot("\n");\r |
146 | ot(";@ Pop An from stack:\n");\r |
147 | MemHandler(0,2);\r |
148 | ot("\n");\r |
149 | ot(" str r11,[r7,#0x3c] ;@ Save A7\n");\r |
150 | ot("\n");\r |
151 | ot(";@ An = value from stack:\n");\r |
152 | EaWrite(10, 0, 8, 2, 7, 1);\r |
85a36a57 |
153 | \r |
cc68a136 |
154 | Cycles=12;\r |
cfb3dfa0 |
155 | OpEnd(0x10);\r |
cc68a136 |
156 | return 0;\r |
157 | }\r |
158 | \r |
159 | // --------------------- Opcodes 0x4e70+ ---------------------\r |
03c5768c |
160 | // 01001110 01110ttt\r |
cc68a136 |
161 | int Op4E70(int op)\r |
162 | {\r |
163 | int type=0;\r |
164 | \r |
03c5768c |
165 | type=op&7; // reset/nop/stop/rte/rtd/rts/trapv/rtr\r |
cc68a136 |
166 | \r |
167 | switch (type)\r |
168 | {\r |
169 | case 1: // nop\r |
170 | OpStart(op);\r |
171 | Cycles=4;\r |
172 | OpEnd();\r |
173 | return 0;\r |
174 | \r |
a6785576 |
175 | case 3: // rte\r |
ee5e024c |
176 | OpStart(op,0x10,0,0,1); Cycles=20;\r |
cc68a136 |
177 | PopSr(1);\r |
178 | ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");\r |
179 | PopPc();\r |
0e11c502 |
180 | ot(" ldr r1,[r7,#0x44] ;@ reload SR high\n");\r |
181 | SuperChange(op,1);\r |
182 | #if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO || EMULATE_HALT\r |
183 | ot(" ldr r1,[r7,#0x58]\n");\r |
184 | ot(" bic r1,r1,#0x0c ;@ clear 'not processing instruction' and 'doing addr error' bits\n");\r |
185 | ot(" str r1,[r7,#0x58]\n");\r |
186 | #endif\r |
187 | #if EMULATE_ADDRESS_ERRORS_JUMP\r |
188 | ot(" tst r4,#1 ;@ address error?\n");\r |
189 | ot(" bne ExceptionAddressError_r_prg_r4\n");\r |
190 | #endif\r |
191 | opend_check_interrupt = 1;\r |
192 | opend_check_trace = 1;\r |
193 | OpEnd(0x10,0);\r |
cc68a136 |
194 | return 0;\r |
195 | \r |
196 | case 5: // rts\r |
a6785576 |
197 | OpStart(op,0x10); Cycles=16;\r |
cc68a136 |
198 | ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");\r |
199 | PopPc();\r |
0e11c502 |
200 | #if EMULATE_ADDRESS_ERRORS_JUMP\r |
201 | ot(" tst r4,#1 ;@ address error?\n");\r |
202 | ot(" bne ExceptionAddressError_r_prg_r4\n");\r |
203 | #endif\r |
cfb3dfa0 |
204 | OpEnd(0x10);\r |
cc68a136 |
205 | return 0;\r |
206 | \r |
207 | case 6: // trapv\r |
ee5e024c |
208 | OpStart(op,0x10,0,1); Cycles=4;\r |
cc68a136 |
209 | ot(" tst r9,#0x10000000\n");\r |
1c88b865 |
210 | ot(" subne r5,r5,#%i\n",34);\r |
0e11c502 |
211 | ot(" movne r0,#7 ;@ TRAPV exception\n");\r |
cc68a136 |
212 | ot(" blne Exception\n");\r |
0e11c502 |
213 | opend_op_changes_cycles = 1;\r |
214 | OpEnd(0x10,0);\r |
cc68a136 |
215 | return 0;\r |
216 | \r |
217 | case 7: // rtr\r |
a6785576 |
218 | OpStart(op,0x10); Cycles=20;\r |
cc68a136 |
219 | PopSr(0);\r |
220 | ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");\r |
221 | PopPc();\r |
0e11c502 |
222 | #if EMULATE_ADDRESS_ERRORS_JUMP\r |
223 | ot(" tst r4,#1 ;@ address error?\n");\r |
224 | ot(" bne ExceptionAddressError_r_prg_r4\n");\r |
225 | #endif\r |
cfb3dfa0 |
226 | OpEnd(0x10);\r |
cc68a136 |
227 | return 0;\r |
228 | \r |
229 | default:\r |
230 | return 1;\r |
231 | }\r |
232 | }\r |
233 | \r |
234 | // --------------------- Opcodes 0x4e80+ ---------------------\r |
235 | // Emit a Jsr/Jmp opcode, 01001110 1meeeeee\r |
236 | int OpJsr(int op)\r |
237 | {\r |
238 | int use=0;\r |
239 | int sea=0;\r |
240 | \r |
241 | sea=op&0x003f;\r |
242 | \r |
243 | // See if we can do this opcode:\r |
244 | if (EaCanRead(sea,-1)==0) return 1;\r |
245 | \r |
85a36a57 |
246 | use=OpBase(op,0);\r |
cc68a136 |
247 | if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r |
248 | \r |
cfb3dfa0 |
249 | OpStart(op,(op&0x40)?0:0x10);\r |
cc68a136 |
250 | \r |
251 | ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");\r |
252 | ot("\n");\r |
cfb3dfa0 |
253 | EaCalc(11,0x003f,sea,0);\r |
cc68a136 |
254 | \r |
0e11c502 |
255 | ot(";@ Jump - Get new PC from r11\n");\r |
256 | ot(" add r0,r11,r10 ;@ Memory Base + New PC\n");\r |
257 | ot("\n");\r |
258 | CheckPc();\r |
ee5e024c |
259 | if (!(op&0x40))\r |
cc68a136 |
260 | {\r |
0e11c502 |
261 | ot(" ldr r2,[r7,#0x3c]\n");\r |
547045e3 |
262 | ot(" sub r1,r4,r10 ;@ r1 = Old PC\n");\r |
0e11c502 |
263 | }\r |
264 | #if EMULATE_ADDRESS_ERRORS_JUMP\r |
265 | // jsr prefetches next instruction before pushing old PC,\r |
266 | // according to http://pasti.fxatari.com/68kdocs/68kPrefetch.html\r |
267 | ot(" mov r4,r0\n");\r |
268 | ot(" tst r4,#1 ;@ address error?\n");\r |
269 | ot(" bne ExceptionAddressError_r_prg_r4\n");\r |
270 | #else\r |
271 | ot(" bic r4,r0,#1\n");\r |
272 | #endif\r |
273 | \r |
274 | if (!(op&0x40))\r |
275 | {\r |
276 | ot(";@ Push old PC onto stack\n");\r |
277 | ot(" sub r0,r2,#4 ;@ Predecrement A7\n");\r |
cc68a136 |
278 | ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r |
279 | MemHandler(1,2);\r |
cc68a136 |
280 | }\r |
cc68a136 |
281 | \r |
282 | Cycles=(op&0x40) ? 4 : 12;\r |
283 | Cycles+=Ea_add_ns((op&0x40) ? g_jmp_cycle_table : g_jsr_cycle_table, sea);\r |
284 | \r |
cfb3dfa0 |
285 | OpEnd((op&0x40)?0:0x10);\r |
cc68a136 |
286 | \r |
287 | return 0;\r |
288 | }\r |
289 | \r |
290 | // --------------------- Opcodes 0x50c8+ ---------------------\r |
291 | \r |
292 | // ARM version of 68000 condition codes:\r |
293 | static char *Cond[16]=\r |
294 | {\r |
295 | "", "", "hi","ls","cc","cs","ne","eq",\r |
296 | "vc","vs","pl","mi","ge","lt","gt","le"\r |
297 | };\r |
298 | \r |
299 | // Emit a Dbra opcode, 0101cccc 11001nnn vv\r |
300 | int OpDbra(int op)\r |
301 | {\r |
302 | int use=0;\r |
303 | int cc=0;\r |
304 | \r |
305 | use=op&~7; // Use same handler\r |
306 | cc=(op>>8)&15;\r |
307 | \r |
308 | if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r |
309 | OpStart(op);\r |
310 | \r |
3a5e6cf8 |
311 | switch (cc)\r |
cc68a136 |
312 | {\r |
3a5e6cf8 |
313 | case 0: // T\r |
314 | case 1: // F\r |
315 | break;\r |
316 | case 2: // hi\r |
317 | ot(" tst r9,#0x60000000 ;@ hi: !C && !Z\n");\r |
85a36a57 |
318 | ot(" beq DbraTrue\n\n");\r |
3a5e6cf8 |
319 | break;\r |
320 | case 3: // ls\r |
321 | ot(" tst r9,#0x60000000 ;@ ls: C || Z\n");\r |
85a36a57 |
322 | ot(" bne DbraTrue\n\n");\r |
3a5e6cf8 |
323 | break;\r |
324 | default:\r |
325 | ot(";@ Is the condition true?\n");\r |
326 | ot(" msr cpsr_flg,r9 ;@ ARM flags = 68000 flags\n");\r |
327 | ot(";@ If so, don't dbra\n");\r |
85a36a57 |
328 | ot(" b%s DbraTrue\n\n",Cond[cc]);\r |
3a5e6cf8 |
329 | break;\r |
cc68a136 |
330 | }\r |
331 | \r |
3a5e6cf8 |
332 | if (cc!=0)\r |
333 | {\r |
334 | ot(";@ Decrement Dn.w\n");\r |
335 | ot(" and r1,r8,#0x0007\n");\r |
336 | ot(" mov r1,r1,lsl #2\n");\r |
337 | ot(" ldrsh r0,[r7,r1]\n");\r |
338 | ot(" sub r0,r0,#1\n");\r |
339 | ot(" strh r0,[r7,r1]\n");\r |
340 | ot("\n");\r |
cc68a136 |
341 | \r |
3a5e6cf8 |
342 | ot(";@ Check if Dn.w is -1\n");\r |
343 | ot(" cmn r0,#1\n");\r |
03c5768c |
344 | \r |
0e11c502 |
345 | #if (USE_CHECKPC_CALLBACK && USE_CHECKPC_DBRA) || EMULATE_ADDRESS_ERRORS_JUMP\r |
03c5768c |
346 | ot(" beq DbraMin1\n");\r |
3a5e6cf8 |
347 | ot("\n");\r |
cc68a136 |
348 | \r |
03c5768c |
349 | ot(";@ Get Branch offset:\n");\r |
350 | ot(" ldrsh r0,[r4]\n");\r |
0e11c502 |
351 | ot(" add r0,r4,r0 ;@ r0 = New PC\n");\r |
352 | CheckPc();\r |
353 | #if EMULATE_ADDRESS_ERRORS_JUMP\r |
354 | ot(" mov r4,r0\n");\r |
355 | ot(" tst r4,#1 ;@ address error?\n");\r |
356 | ot(" bne ExceptionAddressError_r_prg_r4\n");\r |
357 | #else\r |
358 | ot(" bic r4,r0,#1\n");\r |
359 | #endif\r |
03c5768c |
360 | #else\r |
361 | ot("\n");\r |
3a5e6cf8 |
362 | ot(";@ Get Branch offset:\n");\r |
363 | ot(" ldrnesh r0,[r4]\n");\r |
364 | ot(" addeq r4,r4,#2 ;@ Skip branch offset\n");\r |
365 | ot(" subeq r5,r5,#4 ;@ additional cycles\n");\r |
366 | ot(" addne r4,r4,r0 ;@ r4 = New PC\n");\r |
1c88b865 |
367 | ot(" bic r4,r4,#1\n"); // we do not emulate address errors\r |
3a5e6cf8 |
368 | ot("\n");\r |
03c5768c |
369 | #endif\r |
3a5e6cf8 |
370 | Cycles=12-2;\r |
371 | OpEnd();\r |
372 | }\r |
cc68a136 |
373 | \r |
85a36a57 |
374 | //if (cc==0||cc>=2)\r |
375 | if (op==0x50c8)\r |
3a5e6cf8 |
376 | {\r |
377 | ot(";@ condition true:\n");\r |
85a36a57 |
378 | ot("DbraTrue%s\n", ms?"":":");\r |
3a5e6cf8 |
379 | ot(" add r4,r4,#2 ;@ Skip branch offset\n");\r |
380 | ot("\n");\r |
381 | Cycles=12;\r |
382 | OpEnd();\r |
383 | }\r |
cc68a136 |
384 | \r |
0e11c502 |
385 | #if (USE_CHECKPC_CALLBACK && USE_CHECKPC_DBRA) || EMULATE_ADDRESS_ERRORS_JUMP\r |
03c5768c |
386 | if (op==0x51c8)\r |
387 | {\r |
388 | ot(";@ Dn.w is -1:\n");\r |
389 | ot("DbraMin1%s\n", ms?"":":");\r |
390 | ot(" add r4,r4,#2 ;@ Skip branch offset\n");\r |
391 | ot("\n");\r |
392 | Cycles=12+2;\r |
393 | OpEnd();\r |
394 | }\r |
395 | #endif\r |
396 | \r |
cc68a136 |
397 | return 0;\r |
398 | }\r |
399 | \r |
400 | // --------------------- Opcodes 0x6000+ ---------------------\r |
401 | // Emit a Branch opcode 0110cccc nn (cccc=condition)\r |
402 | int OpBranch(int op)\r |
403 | {\r |
03c5768c |
404 | int size=0,use=0,checkpc=0;\r |
cc68a136 |
405 | int offset=0;\r |
406 | int cc=0;\r |
85a36a57 |
407 | char *asr_r11="";\r |
cc68a136 |
408 | \r |
409 | offset=(char)(op&0xff);\r |
410 | cc=(op>>8)&15;\r |
411 | \r |
412 | // Special offsets:\r |
413 | if (offset==0) size=1;\r |
414 | if (offset==-1) size=2;\r |
415 | \r |
1c88b865 |
416 | if (size==2) size=0; // 000 model does not support long displacement\r |
cc68a136 |
417 | if (size) use=op; // 16-bit or 32-bit\r |
418 | else use=(op&0xff00)+1; // Use same opcode for all 8-bit branches\r |
419 | \r |
420 | if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r |
a6785576 |
421 | OpStart(op,size?0x10:0);\r |
cc68a136 |
422 | Cycles=10; // Assume branch taken\r |
423 | \r |
cc68a136 |
424 | if (cc==1) ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");\r |
425 | \r |
85a36a57 |
426 | switch (cc)\r |
cc68a136 |
427 | {\r |
85a36a57 |
428 | case 0: // T\r |
429 | case 1: // F\r |
430 | break;\r |
431 | case 2: // hi\r |
432 | ot(" tst r9,#0x60000000 ;@ hi: !C && !Z\n");\r |
433 | ot(" bne BccDontBranch%i\n\n",8<<size);\r |
434 | break;\r |
435 | case 3: // ls\r |
436 | ot(" tst r9,#0x60000000 ;@ ls: C || Z\n");\r |
437 | ot(" beq BccDontBranch%i\n\n",8<<size);\r |
438 | break;\r |
439 | default:\r |
440 | ot(";@ Is the condition true?\n");\r |
441 | ot(" msr cpsr_flg,r9 ;@ ARM flags = 68000 flags\n");\r |
442 | ot(" b%s BccDontBranch%i\n\n",Cond[cc^1],8<<size);\r |
443 | break;\r |
cc68a136 |
444 | }\r |
cfb3dfa0 |
445 | \r |
85a36a57 |
446 | if (size) \r |
447 | {\r |
448 | if (size<2)\r |
449 | {\r |
450 | ot(" ldrsh r11,[r4] ;@ Fetch Branch offset\n");\r |
451 | }\r |
452 | else\r |
453 | {\r |
454 | ot(" ldrh r2,[r4] ;@ Fetch Branch offset\n");\r |
455 | ot(" ldrh r11,[r4,#2]\n");\r |
456 | ot(" orr r11,r11,r2,lsl #16\n");\r |
457 | }\r |
458 | }\r |
459 | else\r |
460 | {\r |
461 | ot(" mov r11,r8,asl #24 ;@ Shift 8-bit signed offset up...\n\n");\r |
462 | asr_r11=",asr #24";\r |
463 | }\r |
cc68a136 |
464 | \r |
465 | ot(";@ Branch taken - Add on r0 to PC\n");\r |
466 | \r |
467 | if (cc==1)\r |
468 | {\r |
469 | ot(";@ Bsr - remember old PC\n");\r |
547045e3 |
470 | ot(" ldr r2,[r7,#0x3c]\n");\r |
cc68a136 |
471 | ot(" sub r1,r4,r10 ;@ r1 = Old PC\n");\r |
85a36a57 |
472 | if (size) ot(" add r1,r1,#%d\n",1<<size);\r |
cc68a136 |
473 | ot("\n");\r |
cc68a136 |
474 | ot(";@ Push r1 onto stack\n");\r |
475 | ot(" sub r0,r2,#4 ;@ Predecrement A7\n");\r |
476 | ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r |
477 | MemHandler(1,2);\r |
478 | ot("\n");\r |
479 | Cycles=18; // always 18\r |
03c5768c |
480 | }\r |
481 | \r |
1c88b865 |
482 | ot(" add r0,r4,r11%s ;@ r4 = New PC\n",asr_r11);\r |
483 | \r |
03c5768c |
484 | #if USE_CHECKPC_CALLBACK && USE_CHECKPC_OFFSETBITS_8\r |
485 | if (offset!=0 && offset!=-1) checkpc=1;\r |
486 | #endif\r |
487 | #if USE_CHECKPC_CALLBACK && USE_CHECKPC_OFFSETBITS_16\r |
488 | if (offset==0) checkpc=1;\r |
489 | #endif\r |
490 | #if USE_CHECKPC_CALLBACK\r |
491 | if (offset==-1) checkpc=1;\r |
492 | #endif\r |
0e11c502 |
493 | if (checkpc) CheckPc();\r |
494 | #if EMULATE_ADDRESS_ERRORS_JUMP\r |
495 | ot(" mov r4,r0\n");\r |
496 | ot(" tst r4,#1 ;@ address error?\n");\r |
497 | ot(" bne ExceptionAddressError_r_prg_r4\n");\r |
498 | #else\r |
499 | ot(" bic r4,r0,#1\n");\r |
500 | #endif\r |
501 | ot("\n");\r |
cc68a136 |
502 | \r |
cfb3dfa0 |
503 | OpEnd(size?0x10:0);\r |
cc68a136 |
504 | \r |
85a36a57 |
505 | // since all "DontBranch" code is same for every size, output only once\r |
506 | if (cc>=2&&(op&0xff00)==0x6200)\r |
cc68a136 |
507 | {\r |
85a36a57 |
508 | ot("BccDontBranch%i%s\n", 8<<size, ms?"":":");\r |
03c5768c |
509 | if (size) ot(" add r4,r4,#%d\n",1<<size);\r |
85a36a57 |
510 | Cycles+=(size==1) ? 2 : -2; // Branch not taken\r |
511 | OpEnd(0);\r |
cc68a136 |
512 | }\r |
513 | \r |
514 | return 0;\r |
515 | }\r |
516 | \r |