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cyclone_debug improvements pt. 2
[picodrive.git] / cpu / Cyclone / OpBranch.cpp
CommitLineData
cc68a136 1\r
2#include "app.h"\r
3\r
cfb3dfa0 4static void CheckPc(int reg)\r
cc68a136 5{\r
cfb3dfa0 6#if USE_CHECKPC_CALLBACK\r
cc68a136 7 ot(";@ Check Memory Base+pc (r4)\n");\r
cfb3dfa0 8 if (reg != 0)\r
9 ot(" mov r0,r%i\n", reg);\r
10 ot(" mov lr,pc\n");\r
cc68a136 11 ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r
12 ot(" mov r4,r0\n");\r
cfb3dfa0 13#else\r
14 if (reg != 4)\r
15 ot(" mov r4,r%i\n", reg);\r
16#endif\r
cc68a136 17 ot("\n");\r
18}\r
cc68a136 19\r
20// Push 32-bit value in r1 - trashes r0-r3,r12,lr\r
21void OpPush32()\r
22{\r
23 ot(";@ Push r1 onto stack\n");\r
24 ot(" ldr r0,[r7,#0x3c]\n");\r
25 ot(" sub r0,r0,#4 ;@ Predecrement A7\n");\r
26 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
27 MemHandler(1,2);\r
28 ot("\n");\r
29}\r
30\r
31// Push SR - trashes r0-r3,r12,lr\r
32void OpPushSr(int high)\r
33{\r
34 ot(";@ Push SR:\n");\r
35 OpFlagsToReg(high);\r
36 ot(" ldr r0,[r7,#0x3c]\n");\r
37 ot(" sub r0,r0,#2 ;@ Predecrement A7\n");\r
38 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
39 MemHandler(1,1);\r
40 ot("\n");\r
41}\r
42\r
43// Pop SR - trashes r0-r3\r
44static void PopSr(int high)\r
45{\r
46 ot(";@ Pop SR:\n");\r
47 ot(" ldr r0,[r7,#0x3c]\n");\r
48 ot(" add r1,r0,#2 ;@ Postincrement A7\n");\r
49 ot(" str r1,[r7,#0x3c] ;@ Save A7\n");\r
50 MemHandler(0,1);\r
51 ot("\n");\r
52 OpRegToFlags(high);\r
53}\r
54\r
55// Pop PC - assumes r10=Memory Base - trashes r0-r3\r
56static void PopPc()\r
57{\r
58 ot(";@ Pop PC:\n");\r
59 ot(" ldr r0,[r7,#0x3c]\n");\r
60 ot(" add r1,r0,#4 ;@ Postincrement A7\n");\r
61 ot(" str r1,[r7,#0x3c] ;@ Save A7\n");\r
62 MemHandler(0,2);\r
cfb3dfa0 63 ot(" add r0,r0,r10 ;@ Memory Base+PC\n");\r
cc68a136 64 ot("\n");\r
cfb3dfa0 65 CheckPc(0);\r
cc68a136 66}\r
67\r
68int OpTrap(int op)\r
69{\r
70 int use=0;\r
71\r
72 use=op&~0xf;\r
73 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
74\r
a6785576 75 OpStart(op,0x10);\r
cc68a136 76 ot(" and r0,r8,#0xf ;@ Get trap number\n");\r
77 ot(" orr r0,r0,#0x20\n");\r
78 ot(" mov r0,r0,asl #2\n");\r
79 ot(" bl Exception\n");\r
80 ot("\n");\r
81\r
cfb3dfa0 82 Cycles=38; OpEnd(0x10);\r
cc68a136 83\r
84 return 0;\r
85}\r
86\r
87// --------------------- Opcodes 0x4e50+ ---------------------\r
88int OpLink(int op)\r
89{\r
90 int use=0,reg;\r
91\r
92 use=op&~7;\r
93 reg=op&7;\r
94 if (reg==7) use=op;\r
95 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
96\r
a6785576 97 OpStart(op,0x10);\r
cc68a136 98\r
99 if(reg!=7) {\r
100 ot(";@ Get An\n");\r
101 EaCalc(10, 7, 8, 2, 1);\r
102 EaRead(10, 1, 8, 2, 7, 1);\r
103 }\r
104\r
105 ot(" ldr r0,[r7,#0x3c] ;@ Get A7\n");\r
106 ot(" sub r0,r0,#4 ;@ A7-=4\n");\r
107 ot(" mov r11,r0\n");\r
108 if(reg==7) ot(" mov r1,r0\n");\r
109 ot("\n");\r
110 \r
111 ot(";@ Write An to Stack\n");\r
112 MemHandler(1,2);\r
113\r
114 ot(";@ Save to An\n");\r
115 if(reg!=7)\r
116 EaWrite(10,11, 8, 2, 7, 1);\r
117\r
118 ot(";@ Get offset:\n");\r
119 EaCalc(0,0,0x3c,1);\r
120 EaRead(0,0,0x3c,1,0);\r
121\r
122 ot(" add r11,r11,r0 ;@ Add offset to A7\n");\r
123 ot(" str r11,[r7,#0x3c]\n");\r
124 ot("\n");\r
125\r
126 Cycles=16;\r
cfb3dfa0 127 OpEnd(0x10);\r
cc68a136 128 return 0;\r
129}\r
130\r
131// --------------------- Opcodes 0x4e58+ ---------------------\r
132int OpUnlk(int op)\r
133{\r
134 int use=0;\r
135\r
136 use=op&~7;\r
137 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
138\r
a6785576 139 OpStart(op,0x10);\r
cc68a136 140\r
141 ot(";@ Get An\n");\r
85a36a57 142 EaCalc(10, 0xf, 8, 2, 1);\r
143 EaRead(10, 0, 8, 2, 0xf, 1);\r
cc68a136 144\r
145 ot(" add r11,r0,#4 ;@ A7+=4\n");\r
146 ot("\n");\r
147 ot(";@ Pop An from stack:\n");\r
148 MemHandler(0,2);\r
149 ot("\n");\r
150 ot(" str r11,[r7,#0x3c] ;@ Save A7\n");\r
151 ot("\n");\r
152 ot(";@ An = value from stack:\n");\r
153 EaWrite(10, 0, 8, 2, 7, 1);\r
85a36a57 154\r
cc68a136 155 Cycles=12;\r
cfb3dfa0 156 OpEnd(0x10);\r
cc68a136 157 return 0;\r
158}\r
159\r
160// --------------------- Opcodes 0x4e70+ ---------------------\r
03c5768c 161// 01001110 01110ttt\r
cc68a136 162int Op4E70(int op)\r
163{\r
164 int type=0;\r
165\r
03c5768c 166 type=op&7; // reset/nop/stop/rte/rtd/rts/trapv/rtr\r
cc68a136 167\r
168 switch (type)\r
169 {\r
170 case 1: // nop\r
171 OpStart(op);\r
172 Cycles=4;\r
173 OpEnd();\r
174 return 0;\r
175\r
a6785576 176 case 3: // rte\r
177 OpStart(op,0x10); Cycles=20;\r
178 SuperCheck(op);\r
cc68a136 179 PopSr(1);\r
180 ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");\r
181 PopPc();\r
a6785576 182 SuperChange(op);\r
cc68a136 183 CheckInterrupt(op);\r
cfb3dfa0 184 OpEnd(0x10);\r
cc68a136 185 return 0;\r
186\r
187 case 5: // rts\r
a6785576 188 OpStart(op,0x10); Cycles=16;\r
cc68a136 189 ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");\r
190 PopPc();\r
cfb3dfa0 191 OpEnd(0x10);\r
cc68a136 192 return 0;\r
193\r
194 case 6: // trapv\r
a6785576 195 OpStart(op,0x10); Cycles=4;\r
cc68a136 196 ot(" tst r9,#0x10000000\n");\r
197 ot(" subne r5,r5,#%i\n",30);\r
198 ot(" movne r0,#0x1c ;@ TRAPV exception\n");\r
199 ot(" blne Exception\n");\r
cfb3dfa0 200 OpEnd(0x10);\r
cc68a136 201 return 0;\r
202\r
203 case 7: // rtr\r
a6785576 204 OpStart(op,0x10); Cycles=20;\r
cc68a136 205 PopSr(0);\r
206 ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");\r
207 PopPc();\r
cfb3dfa0 208 OpEnd(0x10);\r
cc68a136 209 return 0;\r
210\r
211 default:\r
212 return 1;\r
213 }\r
214}\r
215\r
216// --------------------- Opcodes 0x4e80+ ---------------------\r
217// Emit a Jsr/Jmp opcode, 01001110 1meeeeee\r
218int OpJsr(int op)\r
219{\r
220 int use=0;\r
221 int sea=0;\r
222\r
223 sea=op&0x003f;\r
224\r
225 // See if we can do this opcode:\r
226 if (EaCanRead(sea,-1)==0) return 1;\r
227\r
85a36a57 228 use=OpBase(op,0);\r
cc68a136 229 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
230\r
cfb3dfa0 231 OpStart(op,(op&0x40)?0:0x10);\r
cc68a136 232\r
233 ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");\r
234 ot("\n");\r
cfb3dfa0 235 EaCalc(11,0x003f,sea,0);\r
cc68a136 236\r
237 ot(";@ Jump - Get new PC from r0\n");\r
238 if (op&0x40)\r
239 {\r
03c5768c 240 // Jmp - Get new PC from r11\r
cfb3dfa0 241 ot(" add r0,r11,r10 ;@ Memory Base + New PC\n");\r
cc68a136 242 ot("\n");\r
243 }\r
244 else\r
245 {\r
246 ot(";@ Jsr - Push old PC first\n");\r
247 ot(" sub r1,r4,r10 ;@ r1 = Old PC\n");\r
cc68a136 248 ot(" mov r1,r1,lsl #8\n");\r
249 ot(" ldr r0,[r7,#0x3c]\n");\r
250 ot(" mov r1,r1,asr #8\n");\r
251 ot(";@ Push r1 onto stack\n");\r
252 ot(" sub r0,r0,#4 ;@ Predecrement A7\n");\r
253 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
254 MemHandler(1,2);\r
cfb3dfa0 255 ot(" add r0,r11,r10 ;@ Memory Base + New PC\n");\r
cc68a136 256 ot("\n");\r
257 }\r
258\r
cfb3dfa0 259 CheckPc(0);\r
cc68a136 260\r
261 Cycles=(op&0x40) ? 4 : 12;\r
262 Cycles+=Ea_add_ns((op&0x40) ? g_jmp_cycle_table : g_jsr_cycle_table, sea);\r
263\r
cfb3dfa0 264 OpEnd((op&0x40)?0:0x10);\r
cc68a136 265\r
266 return 0;\r
267}\r
268\r
269// --------------------- Opcodes 0x50c8+ ---------------------\r
270\r
271// ARM version of 68000 condition codes:\r
272static char *Cond[16]=\r
273{\r
274 "", "", "hi","ls","cc","cs","ne","eq",\r
275 "vc","vs","pl","mi","ge","lt","gt","le"\r
276};\r
277\r
278// Emit a Dbra opcode, 0101cccc 11001nnn vv\r
279int OpDbra(int op)\r
280{\r
281 int use=0;\r
282 int cc=0;\r
283\r
284 use=op&~7; // Use same handler\r
285 cc=(op>>8)&15;\r
286 \r
287 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
288 OpStart(op);\r
289\r
3a5e6cf8 290 switch (cc)\r
cc68a136 291 {\r
3a5e6cf8 292 case 0: // T\r
293 case 1: // F\r
294 break;\r
295 case 2: // hi\r
296 ot(" tst r9,#0x60000000 ;@ hi: !C && !Z\n");\r
85a36a57 297 ot(" beq DbraTrue\n\n");\r
3a5e6cf8 298 break;\r
299 case 3: // ls\r
300 ot(" tst r9,#0x60000000 ;@ ls: C || Z\n");\r
85a36a57 301 ot(" bne DbraTrue\n\n");\r
3a5e6cf8 302 break;\r
303 default:\r
304 ot(";@ Is the condition true?\n");\r
305 ot(" msr cpsr_flg,r9 ;@ ARM flags = 68000 flags\n");\r
306 ot(";@ If so, don't dbra\n");\r
85a36a57 307 ot(" b%s DbraTrue\n\n",Cond[cc]);\r
3a5e6cf8 308 break;\r
cc68a136 309 }\r
310\r
3a5e6cf8 311 if (cc!=0)\r
312 {\r
313 ot(";@ Decrement Dn.w\n");\r
314 ot(" and r1,r8,#0x0007\n");\r
315 ot(" mov r1,r1,lsl #2\n");\r
316 ot(" ldrsh r0,[r7,r1]\n");\r
317 ot(" sub r0,r0,#1\n");\r
318 ot(" strh r0,[r7,r1]\n");\r
319 ot("\n");\r
cc68a136 320\r
3a5e6cf8 321 ot(";@ Check if Dn.w is -1\n");\r
322 ot(" cmn r0,#1\n");\r
03c5768c 323\r
324#if USE_CHECKPC_CALLBACK && USE_CHECKPC_DBRA\r
325 ot(" beq DbraMin1\n");\r
3a5e6cf8 326 ot("\n");\r
cc68a136 327\r
03c5768c 328 ot(";@ Get Branch offset:\n");\r
329 ot(" ldrsh r0,[r4]\n");\r
330 ot(" add r0,r4,r0 ;@ r4 = New PC\n");\r
331 CheckPc(0);\r
332#else\r
333 ot("\n");\r
3a5e6cf8 334 ot(";@ Get Branch offset:\n");\r
335 ot(" ldrnesh r0,[r4]\n");\r
336 ot(" addeq r4,r4,#2 ;@ Skip branch offset\n");\r
337 ot(" subeq r5,r5,#4 ;@ additional cycles\n");\r
338 ot(" addne r4,r4,r0 ;@ r4 = New PC\n");\r
339 ot("\n");\r
03c5768c 340#endif\r
3a5e6cf8 341 Cycles=12-2;\r
342 OpEnd();\r
343 }\r
cc68a136 344 \r
85a36a57 345 //if (cc==0||cc>=2)\r
346 if (op==0x50c8)\r
3a5e6cf8 347 {\r
348 ot(";@ condition true:\n");\r
85a36a57 349 ot("DbraTrue%s\n", ms?"":":");\r
3a5e6cf8 350 ot(" add r4,r4,#2 ;@ Skip branch offset\n");\r
351 ot("\n");\r
352 Cycles=12;\r
353 OpEnd();\r
354 }\r
cc68a136 355\r
03c5768c 356#if USE_CHECKPC_CALLBACK && USE_CHECKPC_DBRA\r
357 if (op==0x51c8)\r
358 {\r
359 ot(";@ Dn.w is -1:\n");\r
360 ot("DbraMin1%s\n", ms?"":":");\r
361 ot(" add r4,r4,#2 ;@ Skip branch offset\n");\r
362 ot("\n");\r
363 Cycles=12+2;\r
364 OpEnd();\r
365 }\r
366#endif\r
367\r
cc68a136 368 return 0;\r
369}\r
370\r
371// --------------------- Opcodes 0x6000+ ---------------------\r
372// Emit a Branch opcode 0110cccc nn (cccc=condition)\r
373int OpBranch(int op)\r
374{\r
03c5768c 375 int size=0,use=0,checkpc=0;\r
cc68a136 376 int offset=0;\r
377 int cc=0;\r
85a36a57 378 char *asr_r11="";\r
cc68a136 379\r
380 offset=(char)(op&0xff);\r
381 cc=(op>>8)&15;\r
382\r
383 // Special offsets:\r
384 if (offset==0) size=1;\r
385 if (offset==-1) size=2;\r
386\r
387 if (size) use=op; // 16-bit or 32-bit\r
388 else use=(op&0xff00)+1; // Use same opcode for all 8-bit branches\r
389\r
390 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
a6785576 391 OpStart(op,size?0x10:0);\r
cc68a136 392 Cycles=10; // Assume branch taken\r
393\r
cc68a136 394 if (cc==1) ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");\r
395\r
85a36a57 396 switch (cc)\r
cc68a136 397 {\r
85a36a57 398 case 0: // T\r
399 case 1: // F\r
400 break;\r
401 case 2: // hi\r
402 ot(" tst r9,#0x60000000 ;@ hi: !C && !Z\n");\r
403 ot(" bne BccDontBranch%i\n\n",8<<size);\r
404 break;\r
405 case 3: // ls\r
406 ot(" tst r9,#0x60000000 ;@ ls: C || Z\n");\r
407 ot(" beq BccDontBranch%i\n\n",8<<size);\r
408 break;\r
409 default:\r
410 ot(";@ Is the condition true?\n");\r
411 ot(" msr cpsr_flg,r9 ;@ ARM flags = 68000 flags\n");\r
412 ot(" b%s BccDontBranch%i\n\n",Cond[cc^1],8<<size);\r
413 break;\r
cc68a136 414 }\r
cfb3dfa0 415\r
85a36a57 416 if (size) \r
417 {\r
418 if (size<2)\r
419 {\r
420 ot(" ldrsh r11,[r4] ;@ Fetch Branch offset\n");\r
421 }\r
422 else\r
423 {\r
424 ot(" ldrh r2,[r4] ;@ Fetch Branch offset\n");\r
425 ot(" ldrh r11,[r4,#2]\n");\r
426 ot(" orr r11,r11,r2,lsl #16\n");\r
427 }\r
428 }\r
429 else\r
430 {\r
431 ot(" mov r11,r8,asl #24 ;@ Shift 8-bit signed offset up...\n\n");\r
432 asr_r11=",asr #24";\r
433 }\r
cc68a136 434\r
435 ot(";@ Branch taken - Add on r0 to PC\n");\r
436\r
437 if (cc==1)\r
438 {\r
439 ot(";@ Bsr - remember old PC\n");\r
440 ot(" sub r1,r4,r10 ;@ r1 = Old PC\n");\r
85a36a57 441 if (size) ot(" add r1,r1,#%d\n",1<<size);\r
cc68a136 442 ot(" mov r1,r1, lsl #8\n");\r
85a36a57 443 ot(" ldr r2,[r7,#0x3c]\n");\r
cc68a136 444 ot(" mov r1,r1, asr #8\n");\r
445 ot("\n");\r
cc68a136 446 ot(";@ Push r1 onto stack\n");\r
447 ot(" sub r0,r2,#4 ;@ Predecrement A7\n");\r
448 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
449 MemHandler(1,2);\r
450 ot("\n");\r
451 Cycles=18; // always 18\r
03c5768c 452 }\r
453\r
454#if USE_CHECKPC_CALLBACK && USE_CHECKPC_OFFSETBITS_8\r
455 if (offset!=0 && offset!=-1) checkpc=1;\r
456#endif\r
457#if USE_CHECKPC_CALLBACK && USE_CHECKPC_OFFSETBITS_16\r
458 if (offset==0) checkpc=1;\r
459#endif\r
460#if USE_CHECKPC_CALLBACK\r
461 if (offset==-1) checkpc=1;\r
462#endif\r
463 if (checkpc)\r
464 {\r
465 ot(" add r0,r4,r11%s ;@ r4 = New PC\n",asr_r11);\r
466 CheckPc(0);\r
cc68a136 467 }\r
468 else\r
469 {\r
03c5768c 470 ot(" add r4,r4,r11%s ;@ r4 = New PC\n",asr_r11);\r
471 ot("\n");\r
cc68a136 472 }\r
473\r
cfb3dfa0 474 OpEnd(size?0x10:0);\r
cc68a136 475\r
85a36a57 476 // since all "DontBranch" code is same for every size, output only once\r
477 if (cc>=2&&(op&0xff00)==0x6200)\r
cc68a136 478 {\r
85a36a57 479 ot("BccDontBranch%i%s\n", 8<<size, ms?"":":");\r
03c5768c 480 if (size) ot(" add r4,r4,#%d\n",1<<size);\r
85a36a57 481 Cycles+=(size==1) ? 2 : -2; // Branch not taken\r
482 OpEnd(0);\r
cc68a136 483 }\r
484\r
485 return 0;\r
486}\r
487\r
fast MegaDrive/MegaCD/32X emulator