NOT setting upper bits on PUSH PC, minor adjustments

[picodrive.git] / cpu / Cyclone / OpBranch.cpp

\r
#include "app.h"\r
\r
static void CheckPc(int reg)\r
{\r
#if USE_CHECKPC_CALLBACK\r
  ot(";@ Check Memory Base+pc (r4)\n");\r
  if (reg != 0)\r
    ot("  mov r0,r%i\n", reg);\r
  ot("  mov lr,pc\n");\r
  ot("  ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r
  ot("  mov r4,r0\n");\r
#else\r
  ot("  bic r4,r%d,#1\n",reg); // we do not emulate address errors\r
#endif\r
  ot("\n");\r
}\r
\r
// Push 32-bit value in r1 - trashes r0-r3,r12,lr\r
void OpPush32()\r
{\r
  ot(";@ Push r1 onto stack\n");\r
  ot("  ldr r0,[r7,#0x3c]\n");\r
  ot("  sub r0,r0,#4 ;@ Predecrement A7\n");\r
  ot("  str r0,[r7,#0x3c] ;@ Save A7\n");\r
  MemHandler(1,2);\r
  ot("\n");\r
}\r
\r
// Push SR - trashes r0-r3,r12,lr\r
void OpPushSr(int high)\r
{\r
  ot(";@ Push SR:\n");\r
  OpFlagsToReg(high);\r
  ot("  ldr r0,[r7,#0x3c]\n");\r
  ot("  sub r0,r0,#2 ;@ Predecrement A7\n");\r
  ot("  str r0,[r7,#0x3c] ;@ Save A7\n");\r
  MemHandler(1,1);\r
  ot("\n");\r
}\r
\r
// Pop SR - trashes r0-r3\r
static void PopSr(int high)\r
{\r
  ot(";@ Pop SR:\n");\r
  ot("  ldr r0,[r7,#0x3c]\n");\r
  ot("  add r1,r0,#2 ;@ Postincrement A7\n");\r
  ot("  str r1,[r7,#0x3c] ;@ Save A7\n");\r
  MemHandler(0,1);\r
  ot("\n");\r
  OpRegToFlags(high);\r
}\r
\r
// Pop PC - assumes r10=Memory Base - trashes r0-r3\r
static void PopPc()\r
{\r
  ot(";@ Pop PC:\n");\r
  ot("  ldr r0,[r7,#0x3c]\n");\r
  ot("  add r1,r0,#4 ;@ Postincrement A7\n");\r
  ot("  str r1,[r7,#0x3c] ;@ Save A7\n");\r
  MemHandler(0,2);\r
  ot("  add r0,r0,r10 ;@ Memory Base+PC\n");\r
  ot("\n");\r
  CheckPc(0);\r
}\r
\r
int OpTrap(int op)\r
{\r
  int use=0;\r
\r
  use=op&~0xf;\r
  if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
  OpStart(op,0x10);\r
  ot("  and r0,r8,#0xf ;@ Get trap number\n");\r
  ot("  orr r0,r0,#0x20\n");\r
  ot("  mov r0,r0,asl #2\n");\r
  ot("  bl Exception\n");\r
  ot("\n");\r
\r
  Cycles=38; OpEnd(0x10);\r
\r
  return 0;\r
}\r
\r
// --------------------- Opcodes 0x4e50+ ---------------------\r
int OpLink(int op)\r
{\r
  int use=0,reg;\r
\r
  use=op&~7;\r
  reg=op&7;\r
  if (reg==7) use=op;\r
  if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
  OpStart(op,0x10);\r
\r
  if(reg!=7) {\r
    ot(";@ Get An\n");\r
    EaCalc(10, 7, 8, 2, 1);\r
    EaRead(10, 1, 8, 2, 7, 1);\r
  }\r
\r
  ot("  ldr r0,[r7,#0x3c] ;@ Get A7\n");\r
  ot("  sub r0,r0,#4 ;@ A7-=4\n");\r
  ot("  mov r11,r0\n");\r
  if(reg==7) ot("  mov r1,r0\n");\r
  ot("\n");\r
  \r
  ot(";@ Write An to Stack\n");\r
  MemHandler(1,2);\r
\r
  ot(";@ Save to An\n");\r
  if(reg!=7)\r
    EaWrite(10,11, 8, 2, 7, 1);\r
\r
  ot(";@ Get offset:\n");\r
  EaCalc(0,0,0x3c,1);\r
  EaRead(0,0,0x3c,1,0);\r
\r
  ot("  add r11,r11,r0 ;@ Add offset to A7\n");\r
  ot("  str r11,[r7,#0x3c]\n");\r
  ot("\n");\r
\r
  Cycles=16;\r
  OpEnd(0x10);\r
  return 0;\r
}\r
\r
// --------------------- Opcodes 0x4e58+ ---------------------\r
int OpUnlk(int op)\r
{\r
  int use=0;\r
\r
  use=op&~7;\r
  if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
  OpStart(op,0x10);\r
\r
  ot(";@ Get An\n");\r
  EaCalc(10, 0xf, 8, 2,   1);\r
  EaRead(10,   0, 8, 2, 0xf, 1);\r
\r
  ot("  add r11,r0,#4 ;@ A7+=4\n");\r
  ot("\n");\r
  ot(";@ Pop An from stack:\n");\r
  MemHandler(0,2);\r
  ot("\n");\r
  ot("  str r11,[r7,#0x3c] ;@ Save A7\n");\r
  ot("\n");\r
  ot(";@ An = value from stack:\n");\r
  EaWrite(10, 0, 8, 2, 7, 1);\r
\r
  Cycles=12;\r
  OpEnd(0x10);\r
  return 0;\r
}\r
\r
// --------------------- Opcodes 0x4e70+ ---------------------\r
// 01001110 01110ttt\r
int Op4E70(int op)\r
{\r
  int type=0;\r
\r
  type=op&7; // reset/nop/stop/rte/rtd/rts/trapv/rtr\r
\r
  switch (type)\r
  {\r
    case 1:  // nop\r
    OpStart(op);\r
    Cycles=4;\r
    OpEnd();\r
    return 0;\r
\r
    case 3: // rte\r
    OpStart(op,0x10); Cycles=20;\r
    SuperCheck(op);\r
    PopSr(1);\r
    ot("  ldr r10,[r7,#0x60] ;@ Get Memory base\n");\r
    PopPc();\r
    SuperChange(op);\r
    CheckInterrupt(op);\r
    OpEnd(0x10);\r
    return 0;\r
\r
    case 5: // rts\r
    OpStart(op,0x10); Cycles=16;\r
    ot("  ldr r10,[r7,#0x60] ;@ Get Memory base\n");\r
    PopPc();\r
    OpEnd(0x10);\r
    return 0;\r
\r
    case 6: // trapv\r
    OpStart(op,0x10); Cycles=4;\r
    ot("  tst r9,#0x10000000\n");\r
    ot("  subne r5,r5,#%i\n",34);\r
    ot("  movne r0,#0x1c ;@ TRAPV exception\n");\r
    ot("  blne Exception\n");\r
    OpEnd(0x10);\r
    return 0;\r
\r
    case 7: // rtr\r
    OpStart(op,0x10); Cycles=20;\r
    PopSr(0);\r
    ot("  ldr r10,[r7,#0x60] ;@ Get Memory base\n");\r
    PopPc();\r
    OpEnd(0x10);\r
    return 0;\r
\r
    default:\r
    return 1;\r
  }\r
}\r
\r
// --------------------- Opcodes 0x4e80+ ---------------------\r
// Emit a Jsr/Jmp opcode, 01001110 1meeeeee\r
int OpJsr(int op)\r
{\r
  int use=0;\r
  int sea=0;\r
\r
  sea=op&0x003f;\r
\r
  // See if we can do this opcode:\r
  if (EaCanRead(sea,-1)==0) return 1;\r
\r
  use=OpBase(op,0);\r
  if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
  OpStart(op,(op&0x40)?0:0x10);\r
\r
  ot("  ldr r10,[r7,#0x60] ;@ Get Memory base\n");\r
  ot("\n");\r
  EaCalc(11,0x003f,sea,0);\r
\r
  ot(";@ Jump - Get new PC from r0\n");\r
  if (op&0x40)\r
  {\r
    // Jmp - Get new PC from r11\r
    ot("  add r0,r11,r10 ;@ Memory Base + New PC\n");\r
    ot("\n");\r
  }\r
  else\r
  {\r
    ot(";@ Jsr - Push old PC first\n");\r
    ot("  ldr r0,[r7,#0x3c]\n");\r
    ot("  sub r1,r4,r10 ;@ r1 = Old PC\n");\r
//    ot("  mov r1,r1,lsl #8\n");\r
//    ot("  mov r1,r1,asr #8\n");\r
    ot(";@ Push r1 onto stack\n");\r
    ot("  sub r0,r0,#4 ;@ Predecrement A7\n");\r
    ot("  str r0,[r7,#0x3c] ;@ Save A7\n");\r
    MemHandler(1,2);\r
    ot("  add r0,r11,r10 ;@ Memory Base + New PC\n");\r
    ot("\n");\r
  }\r
\r
  CheckPc(0);\r
\r
  Cycles=(op&0x40) ? 4 : 12;\r
  Cycles+=Ea_add_ns((op&0x40) ? g_jmp_cycle_table : g_jsr_cycle_table, sea);\r
\r
  OpEnd((op&0x40)?0:0x10);\r
\r
  return 0;\r
}\r
\r
// --------------------- Opcodes 0x50c8+ ---------------------\r
\r
// ARM version of 68000 condition codes:\r
static char *Cond[16]=\r
{\r
  "",  "",  "hi","ls","cc","cs","ne","eq",\r
  "vc","vs","pl","mi","ge","lt","gt","le"\r
};\r
\r
// Emit a Dbra opcode, 0101cccc 11001nnn vv\r
int OpDbra(int op)\r
{\r
  int use=0;\r
  int cc=0;\r
\r
  use=op&~7; // Use same handler\r
  cc=(op>>8)&15;\r
  \r
  if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
  OpStart(op);\r
\r
  switch (cc)\r
  {\r
    case 0: // T\r
    case 1: // F\r
      break;\r
    case 2: // hi\r
      ot("  tst r9,#0x60000000 ;@ hi: !C && !Z\n");\r
      ot("  beq DbraTrue\n\n");\r
      break;\r
    case 3: // ls\r
      ot("  tst r9,#0x60000000 ;@ ls: C || Z\n");\r
      ot("  bne DbraTrue\n\n");\r
      break;\r
    default:\r
      ot(";@ Is the condition true?\n");\r
      ot("  msr cpsr_flg,r9 ;@ ARM flags = 68000 flags\n");\r
      ot(";@ If so, don't dbra\n");\r
      ot("  b%s DbraTrue\n\n",Cond[cc]);\r
      break;\r
  }\r
\r
  if (cc!=0)\r
  {\r
    ot(";@ Decrement Dn.w\n");\r
    ot("  and r1,r8,#0x0007\n");\r
    ot("  mov r1,r1,lsl #2\n");\r
    ot("  ldrsh r0,[r7,r1]\n");\r
    ot("  sub r0,r0,#1\n");\r
    ot("  strh r0,[r7,r1]\n");\r
    ot("\n");\r
\r
    ot(";@ Check if Dn.w is -1\n");\r
    ot("  cmn r0,#1\n");\r
\r
#if USE_CHECKPC_CALLBACK && USE_CHECKPC_DBRA\r
    ot("  beq DbraMin1\n");\r
    ot("\n");\r
\r
    ot(";@ Get Branch offset:\n");\r
    ot("  ldrsh r0,[r4]\n");\r
    ot("  add r0,r4,r0 ;@ r4 = New PC\n");\r
    CheckPc(0);\r
#else\r
    ot("\n");\r
    ot(";@ Get Branch offset:\n");\r
    ot("  ldrnesh r0,[r4]\n");\r
    ot("  addeq r4,r4,#2 ;@ Skip branch offset\n");\r
    ot("  subeq r5,r5,#4 ;@ additional cycles\n");\r
    ot("  addne r4,r4,r0 ;@ r4 = New PC\n");\r
    ot("  bic r4,r4,#1\n"); // we do not emulate address errors\r
    ot("\n");\r
#endif\r
    Cycles=12-2;\r
    OpEnd();\r
  }\r
  \r
  //if (cc==0||cc>=2)\r
  if (op==0x50c8)\r
  {\r
    ot(";@ condition true:\n");\r
    ot("DbraTrue%s\n", ms?"":":");\r
    ot("  add r4,r4,#2 ;@ Skip branch offset\n");\r
    ot("\n");\r
    Cycles=12;\r
    OpEnd();\r
  }\r
\r
#if USE_CHECKPC_CALLBACK && USE_CHECKPC_DBRA\r
  if (op==0x51c8)\r
  {\r
    ot(";@ Dn.w is -1:\n");\r
    ot("DbraMin1%s\n", ms?"":":");\r
    ot("  add r4,r4,#2 ;@ Skip branch offset\n");\r
    ot("\n");\r
    Cycles=12+2;\r
    OpEnd();\r
  }\r
#endif\r
\r
  return 0;\r
}\r
\r
// --------------------- Opcodes 0x6000+ ---------------------\r
// Emit a Branch opcode 0110cccc nn  (cccc=condition)\r
int OpBranch(int op)\r
{\r
  int size=0,use=0,checkpc=0;\r
  int offset=0;\r
  int cc=0;\r
  char *asr_r11="";\r
\r
  offset=(char)(op&0xff);\r
  cc=(op>>8)&15;\r
\r
  // Special offsets:\r
  if (offset==0)  size=1;\r
  if (offset==-1) size=2;\r
\r
  if (size==2) size=0; // 000 model does not support long displacement\r
  if (size) use=op; // 16-bit or 32-bit\r
  else use=(op&0xff00)+1; // Use same opcode for all 8-bit branches\r
\r
  if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
  OpStart(op,size?0x10:0);\r
  Cycles=10; // Assume branch taken\r
\r
  if (cc==1) ot("  ldr r10,[r7,#0x60] ;@ Get Memory base\n");\r
\r
  switch (cc)\r
  {\r
    case 0: // T\r
    case 1: // F\r
      break;\r
    case 2: // hi\r
      ot("  tst r9,#0x60000000 ;@ hi: !C && !Z\n");\r
      ot("  bne BccDontBranch%i\n\n",8<<size);\r
      break;\r
    case 3: // ls\r
      ot("  tst r9,#0x60000000 ;@ ls: C || Z\n");\r
      ot("  beq BccDontBranch%i\n\n",8<<size);\r
      break;\r
    default:\r
      ot(";@ Is the condition true?\n");\r
      ot("  msr cpsr_flg,r9 ;@ ARM flags = 68000 flags\n");\r
      ot("  b%s BccDontBranch%i\n\n",Cond[cc^1],8<<size);\r
      break;\r
  }\r
\r
  if (size) \r
  {\r
    if (size<2)\r
    {\r
      ot("  ldrsh r11,[r4] ;@ Fetch Branch offset\n");\r
    }\r
    else\r
    {\r
      ot("  ldrh r2,[r4] ;@ Fetch Branch offset\n");\r
      ot("  ldrh r11,[r4,#2]\n");\r
      ot("  orr r11,r11,r2,lsl #16\n");\r
    }\r
  }\r
  else\r
  {\r
    ot("  mov r11,r8,asl #24 ;@ Shift 8-bit signed offset up...\n\n");\r
    asr_r11=",asr #24";\r
  }\r
\r
  ot(";@ Branch taken - Add on r0 to PC\n");\r
\r
  if (cc==1)\r
  {\r
    ot(";@ Bsr - remember old PC\n");\r
    ot("  ldr r2,[r7,#0x3c]\n");\r
    ot("  sub r1,r4,r10 ;@ r1 = Old PC\n");\r
    if (size) ot("  add r1,r1,#%d\n",1<<size);\r
//    ot("  mov r1,r1, lsl #8\n");\r
//    ot("  mov r1,r1, asr #8\n");\r
    ot("\n");\r
    ot(";@ Push r1 onto stack\n");\r
    ot("  sub r0,r2,#4 ;@ Predecrement A7\n");\r
    ot("  str r0,[r7,#0x3c] ;@ Save A7\n");\r
    MemHandler(1,2);\r
    ot("\n");\r
    Cycles=18; // always 18\r
  }\r
\r
  ot("  add r0,r4,r11%s ;@ r4 = New PC\n",asr_r11);\r
\r
#if USE_CHECKPC_CALLBACK && USE_CHECKPC_OFFSETBITS_8\r
  if (offset!=0 && offset!=-1) checkpc=1;\r
#endif\r
#if USE_CHECKPC_CALLBACK && USE_CHECKPC_OFFSETBITS_16\r
  if (offset==0)  checkpc=1;\r
#endif\r
#if USE_CHECKPC_CALLBACK\r
  if (offset==-1) checkpc=1;\r
#endif\r
  if (checkpc)\r
  {\r
    CheckPc(0);\r
  }\r
  else\r
  {\r
    ot("  bic r4,r0,#1\n"); // we do not emulate address errors\r
    ot("\n");\r
  }\r
\r
  OpEnd(size?0x10:0);\r
\r
  // since all "DontBranch" code is same for every size, output only once\r
  if (cc>=2&&(op&0xff00)==0x6200)\r
  {\r
    ot("BccDontBranch%i%s\n", 8<<size, ms?"":":");\r
    if (size) ot("  add r4,r4,#%d\n",1<<size);\r
    Cycles+=(size==1) ? 2 : -2; // Branch not taken\r
    OpEnd(0);\r
  }\r
\r
  return 0;\r
}\r
\r