code review and optimizations
[picodrive.git] / cpu / Cyclone / OpBranch.cpp
CommitLineData
cc68a136 1\r
2#include "app.h"\r
3\r
cfb3dfa0 4static void CheckPc(int reg)\r
cc68a136 5{\r
cfb3dfa0 6#if USE_CHECKPC_CALLBACK\r
cc68a136 7 ot(";@ Check Memory Base+pc (r4)\n");\r
cfb3dfa0 8 if (reg != 0)\r
9 ot(" mov r0,r%i\n", reg);\r
10 ot(" mov lr,pc\n");\r
cc68a136 11 ot(" ldr pc,[r7,#0x64] ;@ Call checkpc()\n");\r
12 ot(" mov r4,r0\n");\r
cfb3dfa0 13#else\r
14 if (reg != 4)\r
15 ot(" mov r4,r%i\n", reg);\r
16#endif\r
cc68a136 17 ot("\n");\r
18}\r
cc68a136 19\r
20// Push 32-bit value in r1 - trashes r0-r3,r12,lr\r
21void OpPush32()\r
22{\r
23 ot(";@ Push r1 onto stack\n");\r
24 ot(" ldr r0,[r7,#0x3c]\n");\r
25 ot(" sub r0,r0,#4 ;@ Predecrement A7\n");\r
26 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
27 MemHandler(1,2);\r
28 ot("\n");\r
29}\r
30\r
31// Push SR - trashes r0-r3,r12,lr\r
32void OpPushSr(int high)\r
33{\r
34 ot(";@ Push SR:\n");\r
35 OpFlagsToReg(high);\r
36 ot(" ldr r0,[r7,#0x3c]\n");\r
37 ot(" sub r0,r0,#2 ;@ Predecrement A7\n");\r
38 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
39 MemHandler(1,1);\r
40 ot("\n");\r
41}\r
42\r
43// Pop SR - trashes r0-r3\r
44static void PopSr(int high)\r
45{\r
46 ot(";@ Pop SR:\n");\r
47 ot(" ldr r0,[r7,#0x3c]\n");\r
48 ot(" add r1,r0,#2 ;@ Postincrement A7\n");\r
49 ot(" str r1,[r7,#0x3c] ;@ Save A7\n");\r
50 MemHandler(0,1);\r
51 ot("\n");\r
52 OpRegToFlags(high);\r
53}\r
54\r
55// Pop PC - assumes r10=Memory Base - trashes r0-r3\r
56static void PopPc()\r
57{\r
58 ot(";@ Pop PC:\n");\r
59 ot(" ldr r0,[r7,#0x3c]\n");\r
60 ot(" add r1,r0,#4 ;@ Postincrement A7\n");\r
61 ot(" str r1,[r7,#0x3c] ;@ Save A7\n");\r
62 MemHandler(0,2);\r
cfb3dfa0 63 ot(" add r0,r0,r10 ;@ Memory Base+PC\n");\r
cc68a136 64 ot("\n");\r
cfb3dfa0 65 CheckPc(0);\r
cc68a136 66}\r
67\r
68int OpTrap(int op)\r
69{\r
70 int use=0;\r
71\r
72 use=op&~0xf;\r
73 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
74\r
a6785576 75 OpStart(op,0x10);\r
cc68a136 76 ot(" and r0,r8,#0xf ;@ Get trap number\n");\r
77 ot(" orr r0,r0,#0x20\n");\r
78 ot(" mov r0,r0,asl #2\n");\r
79 ot(" bl Exception\n");\r
80 ot("\n");\r
81\r
cfb3dfa0 82 Cycles=38; OpEnd(0x10);\r
cc68a136 83\r
84 return 0;\r
85}\r
86\r
87// --------------------- Opcodes 0x4e50+ ---------------------\r
88int OpLink(int op)\r
89{\r
90 int use=0,reg;\r
91\r
92 use=op&~7;\r
93 reg=op&7;\r
94 if (reg==7) use=op;\r
95 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
96\r
a6785576 97 OpStart(op,0x10);\r
cc68a136 98\r
99 if(reg!=7) {\r
100 ot(";@ Get An\n");\r
101 EaCalc(10, 7, 8, 2, 1);\r
102 EaRead(10, 1, 8, 2, 7, 1);\r
103 }\r
104\r
105 ot(" ldr r0,[r7,#0x3c] ;@ Get A7\n");\r
106 ot(" sub r0,r0,#4 ;@ A7-=4\n");\r
107 ot(" mov r11,r0\n");\r
108 if(reg==7) ot(" mov r1,r0\n");\r
109 ot("\n");\r
110 \r
111 ot(";@ Write An to Stack\n");\r
112 MemHandler(1,2);\r
113\r
114 ot(";@ Save to An\n");\r
115 if(reg!=7)\r
116 EaWrite(10,11, 8, 2, 7, 1);\r
117\r
118 ot(";@ Get offset:\n");\r
119 EaCalc(0,0,0x3c,1);\r
120 EaRead(0,0,0x3c,1,0);\r
121\r
122 ot(" add r11,r11,r0 ;@ Add offset to A7\n");\r
123 ot(" str r11,[r7,#0x3c]\n");\r
124 ot("\n");\r
125\r
126 Cycles=16;\r
cfb3dfa0 127 OpEnd(0x10);\r
cc68a136 128 return 0;\r
129}\r
130\r
131// --------------------- Opcodes 0x4e58+ ---------------------\r
132int OpUnlk(int op)\r
133{\r
134 int use=0;\r
135\r
136 use=op&~7;\r
137 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
138\r
a6785576 139 OpStart(op,0x10);\r
cc68a136 140\r
141 ot(";@ Get An\n");\r
85a36a57 142 EaCalc(10, 0xf, 8, 2, 1);\r
143 EaRead(10, 0, 8, 2, 0xf, 1);\r
cc68a136 144\r
145 ot(" add r11,r0,#4 ;@ A7+=4\n");\r
146 ot("\n");\r
147 ot(";@ Pop An from stack:\n");\r
148 MemHandler(0,2);\r
149 ot("\n");\r
150 ot(" str r11,[r7,#0x3c] ;@ Save A7\n");\r
151 ot("\n");\r
152 ot(";@ An = value from stack:\n");\r
153 EaWrite(10, 0, 8, 2, 7, 1);\r
85a36a57 154\r
cc68a136 155 Cycles=12;\r
cfb3dfa0 156 OpEnd(0x10);\r
cc68a136 157 return 0;\r
158}\r
159\r
160// --------------------- Opcodes 0x4e70+ ---------------------\r
161int Op4E70(int op)\r
162{\r
163 int type=0;\r
164\r
165 type=op&7; // 01001110 01110ttt, reset/nop/stop/rte/rtd/rts/trapv/rtr\r
166\r
167 switch (type)\r
168 {\r
169 case 1: // nop\r
170 OpStart(op);\r
171 Cycles=4;\r
172 OpEnd();\r
173 return 0;\r
174\r
a6785576 175 case 3: // rte\r
176 OpStart(op,0x10); Cycles=20;\r
177 SuperCheck(op);\r
cc68a136 178 PopSr(1);\r
179 ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");\r
180 PopPc();\r
a6785576 181 SuperChange(op);\r
cc68a136 182 CheckInterrupt(op);\r
cfb3dfa0 183 OpEnd(0x10);\r
cc68a136 184 return 0;\r
185\r
186 case 5: // rts\r
a6785576 187 OpStart(op,0x10); Cycles=16;\r
cc68a136 188 ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");\r
189 PopPc();\r
cfb3dfa0 190 OpEnd(0x10);\r
cc68a136 191 return 0;\r
192\r
193 case 6: // trapv\r
a6785576 194 OpStart(op,0x10); Cycles=4;\r
cc68a136 195 ot(" tst r9,#0x10000000\n");\r
196 ot(" subne r5,r5,#%i\n",30);\r
197 ot(" movne r0,#0x1c ;@ TRAPV exception\n");\r
198 ot(" blne Exception\n");\r
cfb3dfa0 199 OpEnd(0x10);\r
cc68a136 200 return 0;\r
201\r
202 case 7: // rtr\r
a6785576 203 OpStart(op,0x10); Cycles=20;\r
cc68a136 204 PopSr(0);\r
205 ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");\r
206 PopPc();\r
cfb3dfa0 207 OpEnd(0x10);\r
cc68a136 208 return 0;\r
209\r
210 default:\r
211 return 1;\r
212 }\r
213}\r
214\r
215// --------------------- Opcodes 0x4e80+ ---------------------\r
216// Emit a Jsr/Jmp opcode, 01001110 1meeeeee\r
217int OpJsr(int op)\r
218{\r
219 int use=0;\r
220 int sea=0;\r
221\r
222 sea=op&0x003f;\r
223\r
224 // See if we can do this opcode:\r
225 if (EaCanRead(sea,-1)==0) return 1;\r
226\r
85a36a57 227 use=OpBase(op,0);\r
cc68a136 228 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
229\r
cfb3dfa0 230 OpStart(op,(op&0x40)?0:0x10);\r
cc68a136 231\r
232 ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");\r
233 ot("\n");\r
cfb3dfa0 234 EaCalc(11,0x003f,sea,0);\r
cc68a136 235\r
236 ot(";@ Jump - Get new PC from r0\n");\r
237 if (op&0x40)\r
238 {\r
239 // Jmp - Get new PC from r0\r
cfb3dfa0 240 ot(" add r0,r11,r10 ;@ Memory Base + New PC\n");\r
cc68a136 241 ot("\n");\r
242 }\r
243 else\r
244 {\r
245 ot(";@ Jsr - Push old PC first\n");\r
246 ot(" sub r1,r4,r10 ;@ r1 = Old PC\n");\r
cc68a136 247 ot(" mov r1,r1,lsl #8\n");\r
248 ot(" ldr r0,[r7,#0x3c]\n");\r
249 ot(" mov r1,r1,asr #8\n");\r
250 ot(";@ Push r1 onto stack\n");\r
251 ot(" sub r0,r0,#4 ;@ Predecrement A7\n");\r
252 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
253 MemHandler(1,2);\r
cfb3dfa0 254 ot(" add r0,r11,r10 ;@ Memory Base + New PC\n");\r
cc68a136 255 ot("\n");\r
256 }\r
257\r
cfb3dfa0 258 CheckPc(0);\r
cc68a136 259\r
260 Cycles=(op&0x40) ? 4 : 12;\r
261 Cycles+=Ea_add_ns((op&0x40) ? g_jmp_cycle_table : g_jsr_cycle_table, sea);\r
262\r
cfb3dfa0 263 OpEnd((op&0x40)?0:0x10);\r
cc68a136 264\r
265 return 0;\r
266}\r
267\r
268// --------------------- Opcodes 0x50c8+ ---------------------\r
269\r
270// ARM version of 68000 condition codes:\r
271static char *Cond[16]=\r
272{\r
273 "", "", "hi","ls","cc","cs","ne","eq",\r
274 "vc","vs","pl","mi","ge","lt","gt","le"\r
275};\r
276\r
277// Emit a Dbra opcode, 0101cccc 11001nnn vv\r
278int OpDbra(int op)\r
279{\r
280 int use=0;\r
281 int cc=0;\r
282\r
283 use=op&~7; // Use same handler\r
284 cc=(op>>8)&15;\r
285 \r
286 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
287 OpStart(op);\r
288\r
3a5e6cf8 289 switch (cc)\r
cc68a136 290 {\r
3a5e6cf8 291 case 0: // T\r
292 case 1: // F\r
293 break;\r
294 case 2: // hi\r
295 ot(" tst r9,#0x60000000 ;@ hi: !C && !Z\n");\r
85a36a57 296 ot(" beq DbraTrue\n\n");\r
3a5e6cf8 297 break;\r
298 case 3: // ls\r
299 ot(" tst r9,#0x60000000 ;@ ls: C || Z\n");\r
85a36a57 300 ot(" bne DbraTrue\n\n");\r
3a5e6cf8 301 break;\r
302 default:\r
303 ot(";@ Is the condition true?\n");\r
304 ot(" msr cpsr_flg,r9 ;@ ARM flags = 68000 flags\n");\r
305 ot(";@ If so, don't dbra\n");\r
85a36a57 306 ot(" b%s DbraTrue\n\n",Cond[cc]);\r
3a5e6cf8 307 break;\r
cc68a136 308 }\r
309\r
3a5e6cf8 310 if (cc!=0)\r
311 {\r
312 ot(";@ Decrement Dn.w\n");\r
313 ot(" and r1,r8,#0x0007\n");\r
314 ot(" mov r1,r1,lsl #2\n");\r
315 ot(" ldrsh r0,[r7,r1]\n");\r
316 ot(" sub r0,r0,#1\n");\r
317 ot(" strh r0,[r7,r1]\n");\r
318 ot("\n");\r
cc68a136 319\r
3a5e6cf8 320 ot(";@ Check if Dn.w is -1\n");\r
321 ot(" cmn r0,#1\n");\r
322 ot("\n");\r
cc68a136 323\r
3a5e6cf8 324 ot(";@ Get Branch offset:\n");\r
325 ot(" ldrnesh r0,[r4]\n");\r
326 ot(" addeq r4,r4,#2 ;@ Skip branch offset\n");\r
327 ot(" subeq r5,r5,#4 ;@ additional cycles\n");\r
328 ot(" addne r4,r4,r0 ;@ r4 = New PC\n");\r
329 ot("\n");\r
330 Cycles=12-2;\r
331 OpEnd();\r
332 }\r
cc68a136 333 \r
85a36a57 334 //if (cc==0||cc>=2)\r
335 if (op==0x50c8)\r
3a5e6cf8 336 {\r
337 ot(";@ condition true:\n");\r
85a36a57 338 ot("DbraTrue%s\n", ms?"":":");\r
3a5e6cf8 339 ot(" add r4,r4,#2 ;@ Skip branch offset\n");\r
340 ot("\n");\r
341 Cycles=12;\r
342 OpEnd();\r
343 }\r
cc68a136 344\r
345 return 0;\r
346}\r
347\r
348// --------------------- Opcodes 0x6000+ ---------------------\r
349// Emit a Branch opcode 0110cccc nn (cccc=condition)\r
350int OpBranch(int op)\r
351{\r
352 int size=0,use=0;\r
353 int offset=0;\r
354 int cc=0;\r
85a36a57 355 char *asr_r11="";\r
cc68a136 356\r
357 offset=(char)(op&0xff);\r
358 cc=(op>>8)&15;\r
359\r
360 // Special offsets:\r
361 if (offset==0) size=1;\r
362 if (offset==-1) size=2;\r
363\r
364 if (size) use=op; // 16-bit or 32-bit\r
365 else use=(op&0xff00)+1; // Use same opcode for all 8-bit branches\r
366\r
367 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
a6785576 368 OpStart(op,size?0x10:0);\r
cc68a136 369 Cycles=10; // Assume branch taken\r
370\r
cc68a136 371 if (cc==1) ot(" ldr r10,[r7,#0x60] ;@ Get Memory base\n");\r
372\r
85a36a57 373 switch (cc)\r
cc68a136 374 {\r
85a36a57 375 case 0: // T\r
376 case 1: // F\r
377 break;\r
378 case 2: // hi\r
379 ot(" tst r9,#0x60000000 ;@ hi: !C && !Z\n");\r
380 ot(" bne BccDontBranch%i\n\n",8<<size);\r
381 break;\r
382 case 3: // ls\r
383 ot(" tst r9,#0x60000000 ;@ ls: C || Z\n");\r
384 ot(" beq BccDontBranch%i\n\n",8<<size);\r
385 break;\r
386 default:\r
387 ot(";@ Is the condition true?\n");\r
388 ot(" msr cpsr_flg,r9 ;@ ARM flags = 68000 flags\n");\r
389 ot(" b%s BccDontBranch%i\n\n",Cond[cc^1],8<<size);\r
390 break;\r
cc68a136 391 }\r
cfb3dfa0 392\r
85a36a57 393 if (size) \r
394 {\r
395 if (size<2)\r
396 {\r
397 ot(" ldrsh r11,[r4] ;@ Fetch Branch offset\n");\r
398 }\r
399 else\r
400 {\r
401 ot(" ldrh r2,[r4] ;@ Fetch Branch offset\n");\r
402 ot(" ldrh r11,[r4,#2]\n");\r
403 ot(" orr r11,r11,r2,lsl #16\n");\r
404 }\r
405 }\r
406 else\r
407 {\r
408 ot(" mov r11,r8,asl #24 ;@ Shift 8-bit signed offset up...\n\n");\r
409 asr_r11=",asr #24";\r
410 }\r
cc68a136 411\r
412 ot(";@ Branch taken - Add on r0 to PC\n");\r
413\r
414 if (cc==1)\r
415 {\r
416 ot(";@ Bsr - remember old PC\n");\r
417 ot(" sub r1,r4,r10 ;@ r1 = Old PC\n");\r
85a36a57 418 if (size) ot(" add r1,r1,#%d\n",1<<size);\r
cc68a136 419 ot(" mov r1,r1, lsl #8\n");\r
85a36a57 420 ot(" ldr r2,[r7,#0x3c]\n");\r
cc68a136 421 ot(" mov r1,r1, asr #8\n");\r
422 ot("\n");\r
cc68a136 423 ot(";@ Push r1 onto stack\n");\r
424 ot(" sub r0,r2,#4 ;@ Predecrement A7\n");\r
425 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
426 MemHandler(1,2);\r
427 ot("\n");\r
428 Cycles=18; // always 18\r
cfb3dfa0 429 if (offset==0 || offset==-1)\r
430 {\r
431 ot(";@ Branch is quite far, so may be a good idea to check Memory Base+pc\n");\r
85a36a57 432 ot(" add r0,r4,r11%s ;@ r4 = New PC\n",asr_r11);\r
433 CheckPc(0);\r
cfb3dfa0 434 }\r
85a36a57 435 else\r
436 ot(" add r4,r4,r11%s ;@ r4 = New PC\n",asr_r11);\r
cc68a136 437 }\r
438 else\r
439 {\r
cfb3dfa0 440 if (offset==0 || offset==-1)\r
441 {\r
85a36a57 442 ot(" add r0,r4,r11%s ;@ r4 = New PC\n",asr_r11);\r
cfb3dfa0 443 ot(";@ Branch is quite far, so may be a good idea to check Memory Base+pc\n");\r
444 CheckPc(0);\r
445 }\r
446 else\r
447 {\r
85a36a57 448 ot(" add r4,r4,r11%s ;@ r4 = New PC\n",asr_r11);\r
cfb3dfa0 449 ot("\n");\r
450 }\r
cc68a136 451 }\r
452\r
cfb3dfa0 453 OpEnd(size?0x10:0);\r
cc68a136 454\r
85a36a57 455 // since all "DontBranch" code is same for every size, output only once\r
456 if (cc>=2&&(op&0xff00)==0x6200)\r
cc68a136 457 {\r
85a36a57 458 ot("BccDontBranch%i%s\n", 8<<size, ms?"":":");\r
459 if (size) ot(" add r4,r4,#%d\n",8<<size);\r
460 Cycles+=(size==1) ? 2 : -2; // Branch not taken\r
461 OpEnd(0);\r
cc68a136 462 }\r
463\r
464 return 0;\r
465}\r
466\r