windows Pico stuff wip
[picodrive.git] / cpu / Cyclone / OpLogic.cpp
CommitLineData
cc68a136 1#include "app.h"\r
2\r
3// --------------------- Opcodes 0x0100+ ---------------------\r
4// Emit a Btst (Register) opcode 0000nnn1 ttaaaaaa\r
5int OpBtstReg(int op)\r
6{\r
7 int use=0;\r
8 int type=0,sea=0,tea=0;\r
9 int size=0;\r
10\r
11 type=(op>>6)&3; // Btst/Bchg/Bclr/Bset\r
12 // Get source and target EA\r
13 sea=(op>>9)&7;\r
14 tea=op&0x003f;\r
15 if (tea<0x10) size=2; // For registers, 32-bits\r
16\r
17 if ((tea&0x38)==0x08) return 1; // movep\r
18\r
19 // See if we can do this opcode:\r
20 if (EaCanRead(tea,0)==0) return 1;\r
21 if (type>0)\r
22 {\r
23 if (EaCanWrite(tea)==0) return 1;\r
24 }\r
25\r
85a36a57 26 use=OpBase(op,size);\r
cc68a136 27 use&=~0x0e00; // Use same handler for all registers\r
28 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
29\r
a6785576 30 OpStart(op,tea);\r
cc68a136 31\r
32 if(type==1||type==3) {\r
33 Cycles=8;\r
34 } else {\r
35 Cycles=type?8:4;\r
36 if(size>=2) Cycles+=2;\r
37 }\r
38\r
449ecf92 39 EaCalcReadNoSE(-1,11,sea,0,0x0e00);\r
b637c56a 40\r
449ecf92 41 EaCalcReadNoSE((type>0)?8:-1,0,tea,size,0x003f);\r
b637c56a 42\r
8527dc45 43 if (tea>=0x10)\r
449ecf92 44 ot(" and r11,r11,#7 ;@ mem - do mod 8\n"); // size always 0\r
45 else ot(" and r11,r11,#31 ;@ reg - do mod 32\n"); // size always 2\r
cc68a136 46 ot("\n");\r
47\r
cc68a136 48 ot(" mov r1,#1\n");\r
449ecf92 49 ot(" tst r0,r1,lsl r11 ;@ Do arithmetic\n");\r
50 ot(" bicne r10,r10,#0x40000000\n");\r
51 ot(" orreq r10,r10,#0x40000000 ;@ Get Z flag\n");\r
cc68a136 52 ot("\n");\r
53\r
54 if (type>0)\r
55 {\r
449ecf92 56 if (type==1) ot(" eor r1,r0,r1,lsl r11 ;@ Toggle bit\n");\r
57 if (type==2) ot(" bic r1,r0,r1,lsl r11 ;@ Clear bit\n");\r
58 if (type==3) ot(" orr r1,r0,r1,lsl r11 ;@ Set bit\n");\r
cc68a136 59 ot("\n");\r
449ecf92 60 EaWrite(8,1,tea,size,0x003f,0,0);\r
cc68a136 61 }\r
cfb3dfa0 62 OpEnd(tea);\r
cc68a136 63\r
64 return 0;\r
65}\r
66\r
67// --------------------- Opcodes 0x0800+ ---------------------\r
68// Emit a Btst/Bchg/Bclr/Bset (Immediate) opcode 00001000 ttaaaaaa nn\r
69int OpBtstImm(int op)\r
70{\r
71 int type=0,sea=0,tea=0;\r
72 int use=0;\r
73 int size=0;\r
74\r
75 type=(op>>6)&3;\r
76 // Get source and target EA\r
77 sea= 0x003c;\r
78 tea=op&0x003f;\r
79 if (tea<0x10) size=2; // For registers, 32-bits\r
80\r
81 // See if we can do this opcode:\r
82 if (EaCanRead(tea,0)==0||EaAn(tea)||tea==0x3c) return 1;\r
83 if (type>0)\r
84 {\r
85 if (EaCanWrite(tea)==0) return 1;\r
86 }\r
87\r
85a36a57 88 use=OpBase(op,size);\r
cc68a136 89 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
90\r
cfb3dfa0 91 OpStart(op,sea,tea);\r
cc68a136 92\r
cc68a136 93 ot("\n");\r
85a36a57 94 EaCalcReadNoSE(-1,0,sea,0,0);\r
449ecf92 95 ot(" mov r11,#1\n");\r
96 ot(" bic r10,r10,#0x40000000 ;@ Blank Z flag\n");\r
8527dc45 97 if (tea>=0x10)\r
b637c56a 98 ot(" and r0,r0,#7 ;@ mem - do mod 8\n"); // size always 0\r
99 else ot(" and r0,r0,#0x1F ;@ reg - do mod 32\n"); // size always 2\r
449ecf92 100 ot(" mov r11,r11,lsl r0 ;@ Make bit mask\n");\r
cc68a136 101 ot("\n");\r
102\r
103 if(type==1||type==3) {\r
104 Cycles=12;\r
105 } else {\r
106 Cycles=type?12:8;\r
107 if(size>=2) Cycles+=2;\r
108 }\r
109\r
449ecf92 110 EaCalcReadNoSE((type>0)?8:-1,0,tea,size,0x003f);\r
111 ot(" tst r0,r11 ;@ Do arithmetic\n");\r
112 ot(" orreq r10,r10,#0x40000000 ;@ Get Z flag\n");\r
cc68a136 113 ot("\n");\r
114\r
115 if (type>0)\r
116 {\r
449ecf92 117 if (type==1) ot(" eor r1,r0,r11 ;@ Toggle bit\n");\r
118 if (type==2) ot(" bic r1,r0,r11 ;@ Clear bit\n");\r
119 if (type==3) ot(" orr r1,r0,r11 ;@ Set bit\n");\r
cc68a136 120 ot("\n");\r
449ecf92 121 EaWrite(8, 1,tea,size,0x003f,0,0);\r
cc68a136 122 }\r
123\r
cfb3dfa0 124 OpEnd(sea,tea);\r
cc68a136 125\r
126 return 0;\r
127}\r
128\r
129// --------------------- Opcodes 0x4000+ ---------------------\r
130int OpNeg(int op)\r
131{\r
132 // 01000tt0 xxeeeeee (tt=negx/clr/neg/not, xx=size, eeeeee=EA)\r
133 int type=0,size=0,ea=0,use=0;\r
134\r
135 type=(op>>9)&3;\r
136 ea =op&0x003f;\r
137 size=(op>>6)&3; if (size>=3) return 1;\r
138\r
139 // See if we can do this opcode:\r
140 if (EaCanRead (ea,size)==0||EaAn(ea)) return 1;\r
141 if (EaCanWrite(ea )==0) return 1;\r
142\r
85a36a57 143 use=OpBase(op,size);\r
cc68a136 144 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
145\r
d5715559 146 OpStart(op,ea); Cycles=size<2?4:6;\r
147 if(ea >= 0x10) Cycles*=2;\r
cc68a136 148\r
449ecf92 149 EaCalc (11,0x003f,ea,size,0,0);\r
cc68a136 150\r
449ecf92 151 if (type!=1) EaRead (11,0,ea,size,0x003f,0,0); // Don't need to read for 'clr' (or do we, for a dummy read?)\r
cc68a136 152 if (type==1) ot("\n");\r
153\r
154 if (type==0)\r
155 {\r
156 ot(";@ Negx:\n");\r
157 GetXBit(1);\r
b637c56a 158 if(size!=2) ot(" mov r0,r0,asl #%i\n",size?16:24);\r
cc68a136 159 ot(" rscs r1,r0,#0 ;@ do arithmetic\n");\r
449ecf92 160 ot(" orr r3,r10,#0xb0000000 ;@ for old Z\n");\r
cc68a136 161 OpGetFlags(1,1,0);\r
162 if(size!=2) {\r
a6785576 163 ot(" movs r1,r1,asr #%i\n",size?16:24);\r
449ecf92 164 ot(" orreq r10,r10,#0x40000000 ;@ possily missed Z\n");\r
a6785576 165 }\r
449ecf92 166 ot(" andeq r10,r10,r3 ;@ fix Z\n");\r
cc68a136 167 ot("\n");\r
168 }\r
169\r
170 if (type==1)\r
171 {\r
172 ot(";@ Clear:\n");\r
173 ot(" mov r1,#0\n");\r
449ecf92 174 ot(" mov r10,#0x40000000 ;@ NZCV=0100\n");\r
cc68a136 175 ot("\n");\r
176 }\r
177\r
178 if (type==2)\r
179 {\r
180 ot(";@ Neg:\n");\r
b637c56a 181 if(size!=2) ot(" mov r0,r0,asl #%i\n",size?16:24);\r
cc68a136 182 ot(" rsbs r1,r0,#0\n");\r
183 OpGetFlags(1,1);\r
184 if(size!=2) ot(" mov r1,r1,asr #%i\n",size?16:24);\r
185 ot("\n");\r
186 }\r
187\r
188 if (type==3)\r
189 {\r
190 ot(";@ Not:\n");\r
b637c56a 191 if(size!=2) {\r
192 ot(" mov r0,r0,asl #%i\n",size?16:24);\r
193 ot(" mvn r1,r0,asr #%i\n",size?16:24);\r
194 }\r
195 else\r
196 ot(" mvn r1,r0\n");\r
cc68a136 197 ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");\r
198 OpGetFlags(0,0);\r
199 ot("\n");\r
200 }\r
201\r
0e11c502 202 if (type==1) eawrite_check_addrerr=1;\r
449ecf92 203 EaWrite(11, 1,ea,size,0x003f,0,0);\r
cc68a136 204\r
cfb3dfa0 205 OpEnd(ea);\r
cc68a136 206\r
207 return 0;\r
208}\r
209\r
210// --------------------- Opcodes 0x4840+ ---------------------\r
211// Swap, 01001000 01000nnn swap Dn\r
212int OpSwap(int op)\r
213{\r
214 int ea=0,use=0;\r
215\r
216 ea=op&7;\r
217 use=op&~0x0007; // Use same opcode for all An\r
218\r
219 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
220\r
221 OpStart(op); Cycles=4;\r
222\r
449ecf92 223 EaCalc (11,0x0007,ea,2,1);\r
224 EaRead (11, 0,ea,2,0x0007,1);\r
cc68a136 225\r
226 ot(" mov r1,r0,ror #16\n");\r
227 ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");\r
228 OpGetFlags(0,0);\r
229\r
449ecf92 230 EaWrite(11, 1,8,2,0x0007,1);\r
cc68a136 231\r
232 OpEnd();\r
233\r
234 return 0;\r
235}\r
236\r
237// --------------------- Opcodes 0x4a00+ ---------------------\r
238// Emit a Tst opcode, 01001010 xxeeeeee\r
239int OpTst(int op)\r
240{\r
241 int sea=0;\r
242 int size=0,use=0;\r
243\r
244 sea=op&0x003f;\r
245 size=(op>>6)&3; if (size>=3) return 1;\r
246\r
247 // See if we can do this opcode:\r
248 if (EaCanWrite(sea)==0||EaAn(sea)) return 1;\r
249\r
85a36a57 250 use=OpBase(op,size);\r
cc68a136 251 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
252\r
a6785576 253 OpStart(op,sea); Cycles=4;\r
cc68a136 254\r
255 EaCalc ( 0,0x003f,sea,size,1);\r
256 EaRead ( 0, 0,sea,size,0x003f,1);\r
257\r
258 ot(" adds r0,r0,#0 ;@ Defines NZ, clears CV\n");\r
449ecf92 259 ot(" mrs r10,cpsr ;@ r10=flags\n");\r
cc68a136 260 ot("\n");\r
261\r
cfb3dfa0 262 OpEnd(sea);\r
cc68a136 263 return 0;\r
264}\r
265\r
266// --------------------- Opcodes 0x4880+ ---------------------\r
267// Emit an Ext opcode, 01001000 1x000nnn\r
268int OpExt(int op)\r
269{\r
270 int ea=0;\r
271 int size=0,use=0;\r
272 int shift=0;\r
273\r
274 ea=op&0x0007;\r
275 size=(op>>6)&1;\r
276 shift=32-(8<<size);\r
277\r
85a36a57 278 use=OpBase(op,size);\r
cc68a136 279 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
280\r
281 OpStart(op); Cycles=4;\r
282\r
449ecf92 283 EaCalc (11,0x0007,ea,size+1,0,0);\r
284 EaRead (11, 0,ea,size+1,0x0007,0,0);\r
cc68a136 285\r
286 ot(" mov r0,r0,asl #%d\n",shift);\r
287 ot(" adds r0,r0,#0 ;@ Defines NZ, clears CV\n");\r
449ecf92 288 ot(" mrs r10,cpsr ;@ r10=flags\n");\r
cc68a136 289 ot(" mov r1,r0,asr #%d\n",shift);\r
290 ot("\n");\r
291\r
449ecf92 292 EaWrite(11, 1,ea,size+1,0x0007,0,0);\r
cc68a136 293\r
294 OpEnd();\r
295 return 0;\r
296}\r
297\r
298// --------------------- Opcodes 0x50c0+ ---------------------\r
299// Emit a Set cc opcode, 0101cccc 11eeeeee\r
300int OpSet(int op)\r
301{\r
302 int cc=0,ea=0;\r
ee5e024c 303 int size=0,use=0,changed_cycles=0;\r
cc68a136 304 char *cond[16]=\r
305 {\r
306 "al","", "hi","ls","cc","cs","ne","eq",\r
307 "vc","vs","pl","mi","ge","lt","gt","le"\r
308 };\r
309\r
310 cc=(op>>8)&15;\r
311 ea=op&0x003f;\r
312\r
313 if ((ea&0x38)==0x08) return 1; // dbra, not scc\r
314 \r
315 // See if we can do this opcode:\r
316 if (EaCanWrite(ea)==0) return 1;\r
317\r
85a36a57 318 use=OpBase(op,size);\r
cc68a136 319 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
320\r
ee5e024c 321 changed_cycles=ea<8 && cc>=2;\r
322 OpStart(op,ea,0,changed_cycles); Cycles=8;\r
cc68a136 323 if (ea<8) Cycles=4;\r
324\r
b637c56a 325 if (cc)\r
326 ot(" mov r1,#0\n");\r
cc68a136 327\r
b637c56a 328 switch (cc)\r
cc68a136 329 {\r
b637c56a 330 case 0: // T\r
331 ot(" mvn r1,#0\n");\r
332 if (ea<8) Cycles+=2;\r
333 break;\r
334 case 1: // F\r
335 break;\r
336 case 2: // hi\r
449ecf92 337 ot(" tst r10,#0x60000000 ;@ hi: !C && !Z\n");\r
b637c56a 338 ot(" mvneq r1,r1\n");\r
339 if (ea<8) ot(" subeq r5,r5,#2 ;@ Extra cycles\n");\r
340 break;\r
341 case 3: // ls\r
449ecf92 342 ot(" tst r10,#0x60000000 ;@ ls: C || Z\n");\r
b637c56a 343 ot(" mvnne r1,r1\n");\r
344 if (ea<8) ot(" subne r5,r5,#2 ;@ Extra cycles\n");\r
345 break;\r
346 default:\r
347 ot(";@ Is the condition true?\n");\r
449ecf92 348 ot(" msr cpsr_flg,r10 ;@ ARM flags = 68000 flags\n");\r
b637c56a 349 ot(" mvn%s r1,r1\n",cond[cc]);\r
350 if (ea<8) ot(" sub%s r5,r5,#2 ;@ Extra cycles\n",cond[cc]);\r
351 break;\r
cc68a136 352 }\r
353\r
cc68a136 354 ot("\n");\r
355\r
0e11c502 356 eawrite_check_addrerr=1;\r
b637c56a 357 EaCalc (0,0x003f, ea,size,0,0);\r
358 EaWrite(0, 1, ea,size,0x003f,0,0);\r
cc68a136 359\r
0e11c502 360 opend_op_changes_cycles=changed_cycles;\r
361 OpEnd(ea,0);\r
cc68a136 362 return 0;\r
363}\r
364\r
365// Emit a Asr/Lsr/Roxr/Ror opcode\r
366static int EmitAsr(int op,int type,int dir,int count,int size,int usereg)\r
367{\r
368 char pct[8]=""; // count\r
369 int shift=32-(8<<size);\r
370\r
371 if (count>=1) sprintf(pct,"#%d",count); // Fixed count\r
372\r
373 if (usereg)\r
374 {\r
375 ot(";@ Use Dn for count:\n");\r
85a36a57 376 ot(" and r2,r8,#0x0e00\n");\r
cc68a136 377 ot(" ldr r2,[r7,r2,lsr #7]\n");\r
378 ot(" and r2,r2,#63\n");\r
379 ot("\n");\r
380 strcpy(pct,"r2");\r
381 }\r
382 else if (count<0)\r
383 {\r
384 ot(" mov r2,r8,lsr #9 ;@ Get 'n'\n");\r
385 ot(" and r2,r2,#7\n\n"); strcpy(pct,"r2");\r
386 }\r
387\r
388 // Take 2*n cycles:\r
389 if (count<0) ot(" sub r5,r5,r2,asl #1 ;@ Take 2*n cycles\n\n");\r
390 else Cycles+=count<<1;\r
391\r
392 if (type<2)\r
393 {\r
394 // Asr/Lsr\r
395 if (dir==0 && size<2)\r
396 {\r
397 ot(";@ For shift right, use loworder bits for the operation:\n");\r
398 ot(" mov r0,r0,%s #%d\n",type?"lsr":"asr",32-(8<<size));\r
399 ot("\n");\r
400 }\r
401\r
1c88b865 402 if (type==0 && dir) ot(" adds r3,r0,#0 ;@ save old value for V flag calculation, also clear V\n");\r
cc68a136 403\r
404 ot(";@ Shift register:\n");\r
405 if (type==0) ot(" movs r0,r0,%s %s\n",dir?"asl":"asr",pct);\r
406 if (type==1) ot(" movs r0,r0,%s %s\n",dir?"lsl":"lsr",pct);\r
407\r
cc68a136 408 OpGetFlags(0,0);\r
409 if (usereg) { // store X only if count is not 0\r
410 ot(" cmp %s,#0 ;@ shifting by 0?\n",pct);\r
449ecf92 411 ot(" biceq r10,r10,#0x20000000 ;@ if so, clear carry\n");\r
412 ot(" strne r10,[r7,#0x4c] ;@ else Save X bit\n");\r
cc68a136 413 } else {\r
414 // count will never be 0 if we use immediate\r
449ecf92 415 ot(" str r10,[r7,#0x4c] ;@ Save X bit\n");\r
cc68a136 416 }\r
03c5768c 417 ot("\n");\r
418\r
419 if (dir==0 && size<2)\r
420 {\r
421 ot(";@ restore after right shift:\n");\r
422 ot(" movs r0,r0,lsl #%d\n",32-(8<<size));\r
423 if (type)\r
449ecf92 424 ot(" orrmi r10,r10,#0x80000000 ;@ Potentially missed N flag\n");\r
03c5768c 425 ot("\n");\r
426 }\r
cc68a136 427\r
428 if (type==0 && dir) {\r
429 ot(";@ calculate V flag (set if sign bit changes at anytime):\n");\r
430 ot(" mov r1,#0x80000000\n");\r
431 ot(" ands r3,r3,r1,asr %s\n", pct);\r
432 ot(" cmpne r3,r1,asr %s\n", pct);\r
1c88b865 433 ot(" eoreq r1,r0,r3\n"); // above check doesn't catch (-1)<<(32+), so we need this\r
434 ot(" tsteq r1,#0x80000000\n");\r
449ecf92 435 ot(" orrne r10,r10,#0x10000000\n");\r
03c5768c 436 ot("\n");\r
cc68a136 437 }\r
cc68a136 438 }\r
439\r
440 // --------------------------------------\r
441 if (type==2)\r
442 {\r
443 int wide=8<<size;\r
444\r
445 // Roxr\r
449ecf92 446 if(count == 1)\r
447 {\r
cc68a136 448 if(dir==0) {\r
449 if(size!=2) {\r
a6785576 450 ot(" orr r0,r0,r0,lsr #%i\n", size?16:24);\r
451 ot(" bic r0,r0,#0x%x\n", 1<<(32-wide));\r
452 }\r
cc68a136 453 GetXBit(0);\r
454 ot(" movs r0,r0,rrx\n");\r
455 OpGetFlags(0,1);\r
456 } else {\r
85a36a57 457 ot(" ldr r3,[r7,#0x4c]\n");\r
cc68a136 458 ot(" movs r0,r0,lsl #1\n");\r
459 OpGetFlags(0,1);\r
85a36a57 460 ot(" tst r3,#0x20000000\n");\r
cc68a136 461 ot(" orrne r0,r0,#0x%x\n", 1<<(32-wide));\r
449ecf92 462 ot(" bicne r10,r10,#0x40000000 ;@ clear Z in case it got there\n");\r
cc68a136 463 }\r
449ecf92 464 ot(" bic r10,r10,#0x10000000 ;@ make suve V is clear\n");\r
cc68a136 465 return 0;\r
466 }\r
467\r
468 if (usereg)\r
469 {\r
03c5768c 470 if (size==2)\r
471 {\r
472 ot(" subs r2,r2,#33\n");\r
473 ot(" addmis r2,r2,#33 ;@ Now r2=0-%d\n",wide);\r
474 }\r
475 else\r
476 {\r
477 ot(";@ Reduce r2 until <0:\n");\r
478 ot("Reduce_%.4x%s\n",op,ms?"":":");\r
479 ot(" subs r2,r2,#%d\n",wide+1);\r
480 ot(" bpl Reduce_%.4x\n",op);\r
481 ot(" adds r2,r2,#%d ;@ Now r2=0-%d\n",wide+1,wide);\r
482 }\r
483 ot(" beq norotx_%.4x\n",op);\r
cc68a136 484 ot("\n");\r
485 }\r
486\r
487 if (usereg||count < 0)\r
488 {\r
489 if (dir) ot(" rsb r2,r2,#%d ;@ Reverse direction\n",wide+1);\r
490 }\r
491 else\r
492 {\r
493 if (dir) ot(" mov r2,#%d ;@ Reversed\n",wide+1-count);\r
494 else ot(" mov r2,#%d\n",count);\r
495 }\r
496\r
497 if (shift) ot(" mov r0,r0,lsr #%d ;@ Shift down\n",shift);\r
498\r
03c5768c 499 ot("\n");\r
500 ot(";@ First get X bit (middle):\n");\r
85a36a57 501 ot(" ldr r3,[r7,#0x4c]\n");\r
03c5768c 502 ot(" rsb r1,r2,#%d\n",wide);\r
85a36a57 503 ot(" and r3,r3,#0x20000000\n");\r
504 ot(" mov r3,r3,lsr #29\n");\r
03c5768c 505 ot(" mov r3,r3,lsl r1\n");\r
506\r
507 ot(";@ Rotate bits:\n");\r
508 ot(" orr r3,r3,r0,lsr r2 ;@ Orr right part\n");\r
509 ot(" rsbs r2,r2,#%d ;@ should also clear ARM V\n",wide+1);\r
510 ot(" orrs r0,r3,r0,lsl r2 ;@ Orr left part, set flags\n");\r
cc68a136 511 ot("\n");\r
512\r
513 if (shift) ot(" movs r0,r0,lsl #%d ;@ Shift up and get correct NC flags\n",shift);\r
514 OpGetFlags(0,!usereg);\r
cc68a136 515 if (usereg) { // store X only if count is not 0\r
449ecf92 516 ot(" str r10,[r7,#0x4c] ;@ if not 0, Save X bit\n");\r
cc68a136 517 ot(" b nozerox%.4x\n",op);\r
03c5768c 518 ot("norotx_%.4x%s\n",op,ms?"":":");\r
85a36a57 519 ot(" ldr r2,[r7,#0x4c]\n");\r
cc68a136 520 ot(" adds r0,r0,#0 ;@ Defines NZ, clears CV\n");\r
521 OpGetFlags(0,0);\r
85a36a57 522 ot(" and r2,r2,#0x20000000\n");\r
449ecf92 523 ot(" orr r10,r10,r2 ;@ C = old_X\n");\r
cc68a136 524 ot("nozerox%.4x%s\n",op,ms?"":":");\r
525 }\r
526\r
527 ot("\n");\r
528 }\r
529\r
530 // --------------------------------------\r
531 if (type==3)\r
532 {\r
533 // Ror\r
534 if (size<2)\r
535 {\r
536 ot(";@ Mirror value in whole 32 bits:\n");\r
537 if (size<=0) ot(" orr r0,r0,r0,lsr #8\n");\r
538 if (size<=1) ot(" orr r0,r0,r0,lsr #16\n");\r
539 ot("\n");\r
540 }\r
541\r
542 ot(";@ Rotate register:\n");\r
03c5768c 543 if (!dir) ot(" adds r0,r0,#0 ;@ first clear V and C\n"); // ARM does not clear C if rot count is 0\r
cc68a136 544 if (count<0)\r
545 {\r
03c5768c 546 if (dir) ot(" rsb %s,%s,#32\n",pct,pct);\r
cc68a136 547 ot(" movs r0,r0,ror %s\n",pct);\r
548 }\r
549 else\r
550 {\r
551 int ror=count;\r
552 if (dir) ror=32-ror;\r
553 if (ror&31) ot(" movs r0,r0,ror #%d\n",ror);\r
554 }\r
555\r
556 OpGetFlags(0,0);\r
cc68a136 557 if (dir)\r
558 {\r
449ecf92 559 ot(" bic r10,r10,#0x30000000 ;@ clear CV\n");\r
cc68a136 560 ot(";@ Get carry bit from bit 0:\n");\r
561 if (usereg)\r
562 {\r
563 ot(" cmp %s,#32 ;@ rotating by 0?\n",pct);\r
564 ot(" tstne r0,#1 ;@ no, check bit 0\n");\r
565 }\r
566 else\r
567 ot(" tst r0,#1\n");\r
449ecf92 568 ot(" orrne r10,r10,#0x20000000\n");\r
cc68a136 569 }\r
570 ot("\n");\r
571\r
572 }\r
573 // --------------------------------------\r
574 \r
575 return 0;\r
576}\r
577\r
578// Emit a Asr/Lsr/Roxr/Ror opcode - 1110cccd xxuttnnn\r
579// (ccc=count, d=direction(r,l) xx=size extension, u=use reg for count, tt=type, nnn=register Dn)\r
580int OpAsr(int op)\r
581{\r
582 int ea=0,use=0;\r
583 int count=0,dir=0;\r
584 int size=0,usereg=0,type=0;\r
585\r
cc68a136 586 count =(op>>9)&7;\r
587 dir =(op>>8)&1;\r
588 size =(op>>6)&3;\r
589 if (size>=3) return 1; // use OpAsrEa()\r
590 usereg=(op>>5)&1;\r
591 type =(op>>3)&3;\r
592\r
593 if (usereg==0) count=((count-1)&7)+1; // because ccc=000 means 8\r
594\r
595 // Use the same opcode for target registers:\r
596 use=op&~0x0007;\r
597\r
03c5768c 598 // As long as count is not 8, use the same opcode for all shift counts:\r
cc68a136 599 if (usereg==0 && count!=8 && !(count==1&&type==2)) { use|=0x0e00; count=-1; }\r
600 if (usereg) { use&=~0x0e00; count=-1; } // Use same opcode for all Dn\r
601\r
602 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
603\r
ee5e024c 604 OpStart(op,ea,0,count<0); Cycles=size<2?6:8;\r
cc68a136 605\r
449ecf92 606 EaCalc(11,0x0007, ea,size,1);\r
607 EaRead(11, 0, ea,size,0x0007,1);\r
cc68a136 608\r
609 EmitAsr(op,type,dir,count, size,usereg);\r
610\r
449ecf92 611 EaWrite(11, 0, ea,size,0x0007,1);\r
cc68a136 612\r
0e11c502 613 opend_op_changes_cycles = (count<0);\r
614 OpEnd(ea,0);\r
cc68a136 615\r
616 return 0;\r
617}\r
618\r
619// Asr/Lsr/Roxr/Ror etc EA - 11100ttd 11eeeeee \r
620int OpAsrEa(int op)\r
621{\r
622 int use=0,type=0,dir=0,ea=0,size=1;\r
623\r
624 type=(op>>9)&3;\r
625 dir =(op>>8)&1;\r
626 ea = op&0x3f;\r
627\r
628 if (ea<0x10) return 1;\r
629 // See if we can do this opcode:\r
630 if (EaCanRead(ea,0)==0) return 1;\r
631 if (EaCanWrite(ea)==0) return 1;\r
632\r
85a36a57 633 use=OpBase(op,size);\r
cc68a136 634 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
635\r
a6785576 636 OpStart(op,ea); Cycles=6; // EmitAsr() will add 2\r
cc68a136 637\r
449ecf92 638 EaCalc (11,0x003f,ea,size,1);\r
639 EaRead (11, 0,ea,size,0x003f,1);\r
cc68a136 640\r
641 EmitAsr(op,type,dir,1,size,0);\r
642\r
449ecf92 643 EaWrite(11, 0,ea,size,0x003f,1);\r
cc68a136 644\r
cfb3dfa0 645 OpEnd(ea);\r
cc68a136 646 return 0;\r
647}\r
648\r
c008977e 649int OpTas(int op, int gen_special)\r
cc68a136 650{\r
651 int ea=0;\r
652 int use=0;\r
653\r
654 ea=op&0x003f;\r
655\r
656 // See if we can do this opcode:\r
657 if (EaCanWrite(ea)==0 || EaAn(ea)) return 1;\r
658\r
85a36a57 659 use=OpBase(op,0);\r
cc68a136 660 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
661\r
a6785576 662 if (!gen_special) OpStart(op,ea);\r
c008977e 663 else\r
664 ot("Op%.4x_%s\n", op, ms?"":":");\r
665\r
666 Cycles=4;\r
cc68a136 667 if(ea>=8) Cycles+=10;\r
668\r
449ecf92 669 EaCalc (11,0x003f,ea,0,1);\r
670 EaRead (11, 1,ea,0,0x003f,1);\r
cc68a136 671\r
672 ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");\r
673 OpGetFlags(0,0);\r
674 ot("\n");\r
675\r
676#if CYCLONE_FOR_GENESIS\r
677 // the original Sega hardware ignores write-back phase (to memory only)\r
c008977e 678 if (ea < 0x10 || gen_special) {\r
cc68a136 679#endif\r
680 ot(" orr r1,r1,#0x80000000 ;@ set bit7\n");\r
681\r
449ecf92 682 EaWrite(11, 1,ea,0,0x003f,1);\r
cc68a136 683#if CYCLONE_FOR_GENESIS\r
684 }\r
685#endif\r
686\r
cfb3dfa0 687 OpEnd(ea);\r
c008977e 688\r
a9a5a6e0 689#if (CYCLONE_FOR_GENESIS == 2)\r
c008977e 690 if (!gen_special && ea >= 0x10) {\r
691 OpTas(op, 1);\r
692 }\r
693#endif\r
694\r
cc68a136 695 return 0;\r
696}\r
697\r