[picodrive.git] / cpu / Cyclone / OpLogic.cpp

#include "app.h"\r
\r
// --------------------- Opcodes 0x0100+ ---------------------\r
// Emit a Btst (Register) opcode 0000nnn1 ttaaaaaa\r
int OpBtstReg(int op)\r
{\r
  int use=0;\r
  int type=0,sea=0,tea=0;\r
  int size=0;\r
\r
  type=(op>>6)&3; // Btst/Bchg/Bclr/Bset\r
  // Get source and target EA\r
  sea=(op>>9)&7;\r
  tea=op&0x003f;\r
  if (tea<0x10) size=2; // For registers, 32-bits\r
\r
  if ((tea&0x38)==0x08) return 1; // movep\r
\r
  // See if we can do this opcode:\r
  if (EaCanRead(tea,0)==0) return 1;\r
  if (type>0)\r
  {\r
    if (EaCanWrite(tea)==0) return 1;\r
  }\r
\r
  use=OpBase(op,size);\r
  use&=~0x0e00; // Use same handler for all registers\r
  if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
  OpStart(op,tea);\r
\r
  if(type==1||type==3) {\r
    Cycles=8;\r
  } else {\r
    Cycles=type?8:4;\r
    if(size>=2) Cycles+=2;\r
  }\r
\r
  EaCalcReadNoSE(-1,11,sea,0,0x0e00);\r
\r
  EaCalcReadNoSE((type>0)?8:-1,0,tea,size,0x003f);\r
\r
  if (tea>=0x10)\r
       ot("  and r11,r11,#7  ;@ mem - do mod 8\n");  // size always 0\r
  else ot("  and r11,r11,#31 ;@ reg - do mod 32\n"); // size always 2\r
  ot("\n");\r
\r
  ot("  mov r1,#1\n");\r
  ot("  tst r0,r1,lsl r11 ;@ Do arithmetic\n");\r
  ot("  bicne r10,r10,#0x40000000\n");\r
  ot("  orreq r10,r10,#0x40000000 ;@ Get Z flag\n");\r
  ot("\n");\r
\r
  if (type>0)\r
  {\r
    if (type==1) ot("  eor r1,r0,r1,lsl r11 ;@ Toggle bit\n");\r
    if (type==2) ot("  bic r1,r0,r1,lsl r11 ;@ Clear bit\n");\r
    if (type==3) ot("  orr r1,r0,r1,lsl r11 ;@ Set bit\n");\r
    ot("\n");\r
    EaWrite(8,1,tea,size,0x003f,0,0);\r
  }\r
  OpEnd(tea);\r
\r
  return 0;\r
}\r
\r
// --------------------- Opcodes 0x0800+ ---------------------\r
// Emit a Btst/Bchg/Bclr/Bset (Immediate) opcode 00001000 ttaaaaaa nn\r
int OpBtstImm(int op)\r
{\r
  int type=0,sea=0,tea=0;\r
  int use=0;\r
  int size=0;\r
\r
  type=(op>>6)&3;\r
  // Get source and target EA\r
  sea=   0x003c;\r
  tea=op&0x003f;\r
  if (tea<0x10) size=2; // For registers, 32-bits\r
\r
  // See if we can do this opcode:\r
  if (EaCanRead(tea,0)==0||EaAn(tea)||tea==0x3c) return 1;\r
  if (type>0)\r
  {\r
    if (EaCanWrite(tea)==0) return 1;\r
  }\r
\r
  use=OpBase(op,size);\r
  if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
  OpStart(op,sea,tea);\r
\r
  ot("\n");\r
  EaCalcReadNoSE(-1,0,sea,0,0);\r
  ot("  mov r11,#1\n");\r
  ot("  bic r10,r10,#0x40000000 ;@ Blank Z flag\n");\r
  if (tea>=0x10)\r
       ot("  and r0,r0,#7    ;@ mem - do mod 8\n");  // size always 0\r
  else ot("  and r0,r0,#0x1F ;@ reg - do mod 32\n"); // size always 2\r
  ot("  mov r11,r11,lsl r0 ;@ Make bit mask\n");\r
  ot("\n");\r
\r
  if(type==1||type==3) {\r
    Cycles=12;\r
  } else {\r
    Cycles=type?12:8;\r
    if(size>=2) Cycles+=2;\r
  }\r
\r
  EaCalcReadNoSE((type>0)?8:-1,0,tea,size,0x003f);\r
  ot("  tst r0,r11 ;@ Do arithmetic\n");\r
  ot("  orreq r10,r10,#0x40000000 ;@ Get Z flag\n");\r
  ot("\n");\r
\r
  if (type>0)\r
  {\r
    if (type==1) ot("  eor r1,r0,r11 ;@ Toggle bit\n");\r
    if (type==2) ot("  bic r1,r0,r11 ;@ Clear bit\n");\r
    if (type==3) ot("  orr r1,r0,r11 ;@ Set bit\n");\r
    ot("\n");\r
    EaWrite(8,   1,tea,size,0x003f,0,0);\r
#if CYCLONE_FOR_GENESIS && !MEMHANDLERS_CHANGE_CYCLES\r
    // this is a bit hacky (device handlers might modify cycles)\r
    if (tea==0x38||tea==0x39)\r
      ot("  ldr r5,[r7,#0x5c] ;@ Load Cycles\n");\r
#endif\r
  }\r
\r
  OpEnd(sea,tea);\r
\r
  return 0;\r
}\r
\r
// --------------------- Opcodes 0x4000+ ---------------------\r
int OpNeg(int op)\r
{\r
  // 01000tt0 xxeeeeee (tt=negx/clr/neg/not, xx=size, eeeeee=EA)\r
  int type=0,size=0,ea=0,use=0;\r
\r
  type=(op>>9)&3;\r
  ea  =op&0x003f;\r
  size=(op>>6)&3; if (size>=3) return 1;\r
\r
  // See if we can do this opcode:\r
  if (EaCanRead (ea,size)==0||EaAn(ea)) return 1;\r
  if (EaCanWrite(ea     )==0) return 1;\r
\r
  use=OpBase(op,size);\r
  if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
  OpStart(op,ea); Cycles=size<2?4:6;\r
  if(ea >= 0x10)  Cycles*=2;\r
\r
  EaCalc (11,0x003f,ea,size,0,0);\r
\r
  if (type!=1) EaRead (11,0,ea,size,0x003f,0,0); // Don't need to read for 'clr' (or do we, for a dummy read?)\r
  if (type==1) ot("\n");\r
\r
  if (type==0)\r
  {\r
    ot(";@ Negx:\n");\r
    GetXBit(1);\r
    if(size!=2) ot("  mov r0,r0,asl #%i\n",size?16:24);\r
    ot("  rscs r1,r0,#0 ;@ do arithmetic\n");\r
    ot("  orr r3,r10,#0xb0000000 ;@ for old Z\n");\r
    OpGetFlags(1,1,0);\r
    if(size!=2) {\r
      ot("  movs r1,r1,asr #%i\n",size?16:24);\r
      ot("  orreq r10,r10,#0x40000000 ;@ possily missed Z\n");\r
    }\r
    ot("  andeq r10,r10,r3 ;@ fix Z\n");\r
    ot("\n");\r
  }\r
\r
  if (type==1)\r
  {\r
    ot(";@ Clear:\n");\r
    ot("  mov r1,#0\n");\r
    ot("  mov r10,#0x40000000 ;@ NZCV=0100\n");\r
    ot("\n");\r
  }\r
\r
  if (type==2)\r
  {\r
    ot(";@ Neg:\n");\r
    if(size!=2) ot("  mov r0,r0,asl #%i\n",size?16:24);\r
    ot("  rsbs r1,r0,#0\n");\r
    OpGetFlags(1,1);\r
    if(size!=2) ot("  mov r1,r1,asr #%i\n",size?16:24);\r
    ot("\n");\r
  }\r
\r
  if (type==3)\r
  {\r
    ot(";@ Not:\n");\r
    if(size!=2) {\r
      ot("  mov r0,r0,asl #%i\n",size?16:24);\r
      ot("  mvn r1,r0,asr #%i\n",size?16:24);\r
    }\r
    else\r
      ot("  mvn r1,r0\n");\r
    ot("  adds r1,r1,#0 ;@ Defines NZ, clears CV\n");\r
    OpGetFlags(0,0);\r
    ot("\n");\r
  }\r
\r
  if (type==1) eawrite_check_addrerr=1;\r
  EaWrite(11,     1,ea,size,0x003f,0,0);\r
\r
  OpEnd(ea);\r
\r
  return 0;\r
}\r
\r
// --------------------- Opcodes 0x4840+ ---------------------\r
// Swap, 01001000 01000nnn swap Dn\r
int OpSwap(int op)\r
{\r
  int ea=0,use=0;\r
\r
  ea=op&7;\r
  use=op&~0x0007; // Use same opcode for all An\r
\r
  if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
  OpStart(op); Cycles=4;\r
\r
  EaCalc (11,0x0007,ea,2,1);\r
  EaRead (11,     0,ea,2,0x0007,1);\r
\r
  ot("  mov r1,r0,ror #16\n");\r
  ot("  adds r1,r1,#0 ;@ Defines NZ, clears CV\n");\r
  OpGetFlags(0,0);\r
\r
  EaWrite(11,     1,8,2,0x0007,1);\r
\r
  OpEnd();\r
\r
  return 0;\r
}\r
\r
// --------------------- Opcodes 0x4a00+ ---------------------\r
// Emit a Tst opcode, 01001010 xxeeeeee\r
int OpTst(int op)\r
{\r
  int sea=0;\r
  int size=0,use=0;\r
\r
  sea=op&0x003f;\r
  size=(op>>6)&3; if (size>=3) return 1;\r
\r
  // See if we can do this opcode:\r
  if (EaCanWrite(sea)==0||EaAn(sea)) return 1;\r
\r
  use=OpBase(op,size);\r
  if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
  OpStart(op,sea); Cycles=4;\r
\r
  EaCalc ( 0,0x003f,sea,size,1);\r
  EaRead ( 0,     0,sea,size,0x003f,1);\r
\r
  ot("  adds r0,r0,#0 ;@ Defines NZ, clears CV\n");\r
  ot("  mrs r10,cpsr ;@ r10=flags\n");\r
  ot("\n");\r
\r
  OpEnd(sea);\r
  return 0;\r
}\r
\r
// --------------------- Opcodes 0x4880+ ---------------------\r
// Emit an Ext opcode, 01001000 1x000nnn\r
int OpExt(int op)\r
{\r
  int ea=0;\r
  int size=0,use=0;\r
  int shift=0;\r
\r
  ea=op&0x0007;\r
  size=(op>>6)&1;\r
  shift=32-(8<<size);\r
\r
  use=OpBase(op,size);\r
  if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
  OpStart(op); Cycles=4;\r
\r
  EaCalc (11,0x0007,ea,size+1,0,0);\r
  EaRead (11,     0,ea,size+1,0x0007,0,0);\r
\r
  ot("  mov r0,r0,asl #%d\n",shift);\r
  ot("  adds r0,r0,#0 ;@ Defines NZ, clears CV\n");\r
  ot("  mrs r10,cpsr ;@ r10=flags\n");\r
  ot("  mov r1,r0,asr #%d\n",shift);\r
  ot("\n");\r
\r
  EaWrite(11,     1,ea,size+1,0x0007,0,0);\r
\r
  OpEnd();\r
  return 0;\r
}\r
\r
// --------------------- Opcodes 0x50c0+ ---------------------\r
// Emit a Set cc opcode, 0101cccc 11eeeeee\r
int OpSet(int op)\r
{\r
  int cc=0,ea=0;\r
  int size=0,use=0,changed_cycles=0;\r
  static const char * const cond[16]=\r
  {\r
    "al","", "hi","ls","cc","cs","ne","eq",\r
    "vc","vs","pl","mi","ge","lt","gt","le"\r
  };\r
\r
  cc=(op>>8)&15;\r
  ea=op&0x003f;\r
\r
  if ((ea&0x38)==0x08) return 1; // dbra, not scc\r
  \r
  // See if we can do this opcode:\r
  if (EaCanWrite(ea)==0) return 1;\r
\r
  use=OpBase(op,size);\r
  if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
  changed_cycles=ea<8 && cc>=2;\r
  OpStart(op,ea,0,changed_cycles); Cycles=8;\r
  if (ea<8) Cycles=4;\r
\r
  if (cc)\r
    ot("  mov r1,#0\n");\r
\r
  switch (cc)\r
  {\r
    case 0: // T\r
      ot("  mvn r1,#0\n");\r
      if (ea<8) Cycles+=2;\r
      break;\r
    case 1: // F\r
      break;\r
    case 2: // hi\r
      ot("  tst r10,#0x60000000 ;@ hi: !C && !Z\n");\r
      ot("  mvneq r1,r1\n");\r
      if (ea<8) ot("  subeq r5,r5,#2 ;@ Extra cycles\n");\r
      break;\r
    case 3: // ls\r
      ot("  tst r10,#0x60000000 ;@ ls: C || Z\n");\r
      ot("  mvnne r1,r1\n");\r
      if (ea<8) ot("  subne r5,r5,#2 ;@ Extra cycles\n");\r
      break;\r
    default:\r
      ot(";@ Is the condition true?\n");\r
      ot("  msr cpsr_flg,r10 ;@ ARM flags = 68000 flags\n");\r
      ot("  mvn%s r1,r1\n",cond[cc]);\r
      if (ea<8) ot("  sub%s r5,r5,#2 ;@ Extra cycles\n",cond[cc]);\r
      break;\r
  }\r
\r
  ot("\n");\r
\r
  eawrite_check_addrerr=1;\r
  EaCalc (0,0x003f, ea,size,0,0);\r
  EaWrite(0,     1, ea,size,0x003f,0,0);\r
\r
  opend_op_changes_cycles=changed_cycles;\r
  OpEnd(ea,0);\r
  return 0;\r
}\r
\r
// Emit a Asr/Lsr/Roxr/Ror opcode\r
static int EmitAsr(int op,int type,int dir,int count,int size,int usereg)\r
{\r
  char pct[8]=""; // count\r
  int shift=32-(8<<size);\r
\r
  if (count>=1) sprintf(pct,"#%d",count); // Fixed count\r
\r
  if (usereg)\r
  {\r
    ot(";@ Use Dn for count:\n");\r
    ot("  and r2,r8,#0x0e00\n");\r
    ot("  ldr r2,[r7,r2,lsr #7]\n");\r
    ot("  and r2,r2,#63\n");\r
    ot("\n");\r
    strcpy(pct,"r2");\r
  }\r
  else if (count<0)\r
  {\r
    ot("  mov r2,r8,lsr #9 ;@ Get 'n'\n");\r
    ot("  and r2,r2,#7\n\n"); strcpy(pct,"r2");\r
  }\r
\r
  // Take 2*n cycles:\r
  if (count<0) ot("  sub r5,r5,r2,asl #1 ;@ Take 2*n cycles\n\n");\r
  else Cycles+=count<<1;\r
\r
  if (type<2)\r
  {\r
    // Asr/Lsr\r
    if (dir==0 && size<2)\r
    {\r
      ot(";@ For shift right, use loworder bits for the operation:\n");\r
      ot("  mov r0,r0,%s #%d\n",type?"lsr":"asr",32-(8<<size));\r
      ot("\n");\r
    }\r
\r
    if (type==0 && dir) ot("  adds r3,r0,#0 ;@ save old value for V flag calculation, also clear V\n");\r
\r
    ot(";@ Shift register:\n");\r
    if (type==0) ot("  movs r0,r0,%s %s\n",dir?"asl":"asr",pct);\r
    if (type==1) ot("  movs r0,r0,%s %s\n",dir?"lsl":"lsr",pct);\r
\r
    OpGetFlags(0,0);\r
    if (usereg) { // store X only if count is not 0\r
      ot("  cmp %s,#0 ;@ shifting by 0?\n",pct);\r
      ot("  biceq r10,r10,#0x20000000 ;@ if so, clear carry\n");\r
      ot("  strne r10,[r7,#0x4c] ;@ else Save X bit\n");\r
    } else {\r
      // count will never be 0 if we use immediate\r
      ot("  str r10,[r7,#0x4c] ;@ Save X bit\n");\r
    }\r
    ot("\n");\r
\r
    if (dir==0 && size<2)\r
    {\r
      ot(";@ restore after right shift:\n");\r
      ot("  movs r0,r0,lsl #%d\n",32-(8<<size));\r
      if (type)\r
        ot("  orrmi r10,r10,#0x80000000 ;@ Potentially missed N flag\n");\r
      ot("\n");\r
    }\r
\r
    if (type==0 && dir) {\r
      ot(";@ calculate V flag (set if sign bit changes at anytime):\n");\r
      ot("  mov r1,#0x80000000\n");\r
      ot("  ands r3,r3,r1,asr %s\n", pct);\r
      ot("  cmpne r3,r1,asr %s\n", pct);\r
      ot("  eoreq r1,r0,r3\n"); // above check doesn't catch (-1)<<(32+), so we need this\r
      ot("  tsteq r1,#0x80000000\n");\r
      ot("  orrne r10,r10,#0x10000000\n");\r
      ot("\n");\r
    }\r
  }\r
\r
  // --------------------------------------\r
  if (type==2)\r
  {\r
    int wide=8<<size;\r
\r
    // Roxr\r
    if(count == 1)\r
    {\r
      if(dir==0) {\r
        if(size!=2) {\r
          ot("  orr r0,r0,r0,lsr #%i\n", size?16:24);\r
          ot("  bic r0,r0,#0x%x\n", 1<<(32-wide));\r
        }\r
        GetXBit(0);\r
        ot("  movs r0,r0,rrx\n");\r
        OpGetFlags(0,1);\r
      } else {\r
        ot("  ldr r3,[r7,#0x4c]\n");\r
        ot("  movs r0,r0,lsl #1\n");\r
        OpGetFlags(0,1);\r
        ot("  tst r3,#0x20000000\n");\r
        ot("  orrne r0,r0,#0x%x\n", 1<<(32-wide));\r
        ot("  bicne r10,r10,#0x40000000 ;@ clear Z in case it got there\n");\r
      }\r
      ot("  bic r10,r10,#0x10000000 ;@ make suve V is clear\n");\r
      return 0;\r
    }\r
\r
    if (usereg)\r
    {\r
      if (size==2)\r
      {\r
        ot("  subs r2,r2,#33\n");\r
        ot("  addmis r2,r2,#33 ;@ Now r2=0-%d\n",wide);\r
      }\r
      else\r
      {\r
        ot(";@ Reduce r2 until <0:\n");\r
        ot("Reduce_%.4x%s\n",op,ms?"":":");\r
        ot("  subs r2,r2,#%d\n",wide+1);\r
        ot("  bpl Reduce_%.4x\n",op);\r
        ot("  adds r2,r2,#%d ;@ Now r2=0-%d\n",wide+1,wide);\r
      }\r
      ot("  beq norotx_%.4x\n",op);\r
      ot("\n");\r
    }\r
\r
    if (usereg||count < 0)\r
    {\r
      if (dir) ot("  rsb r2,r2,#%d ;@ Reverse direction\n",wide+1);\r
    }\r
    else\r
    {\r
      if (dir) ot("  mov r2,#%d ;@ Reversed\n",wide+1-count);\r
      else     ot("  mov r2,#%d\n",count);\r
    }\r
\r
    if (shift) ot("  mov r0,r0,lsr #%d ;@ Shift down\n",shift);\r
\r
    ot("\n");\r
    ot(";@ First get X bit (middle):\n");\r
    ot("  ldr r3,[r7,#0x4c]\n");\r
    ot("  rsb r1,r2,#%d\n",wide);\r
    ot("  and r3,r3,#0x20000000\n");\r
    ot("  mov r3,r3,lsr #29\n");\r
    ot("  mov r3,r3,lsl r1\n");\r
\r
    ot(";@ Rotate bits:\n");\r
    ot("  orr r3,r3,r0,lsr r2 ;@ Orr right part\n");\r
    ot("  rsbs r2,r2,#%d ;@ should also clear ARM V\n",wide+1);\r
    ot("  orrs r0,r3,r0,lsl r2 ;@ Orr left part, set flags\n");\r
    ot("\n");\r
\r
    if (shift) ot("  movs r0,r0,lsl #%d ;@ Shift up and get correct NC flags\n",shift);\r
    OpGetFlags(0,!usereg);\r
    if (usereg) { // store X only if count is not 0\r
      ot("  str r10,[r7,#0x4c] ;@ if not 0, Save X bit\n");\r
      ot("  b nozerox%.4x\n",op);\r
      ot("norotx_%.4x%s\n",op,ms?"":":");\r
      ot("  ldr r2,[r7,#0x4c]\n");\r
      ot("  adds r0,r0,#0 ;@ Defines NZ, clears CV\n");\r
      OpGetFlags(0,0);\r
      ot("  and r2,r2,#0x20000000\n");\r
      ot("  orr r10,r10,r2 ;@ C = old_X\n");\r
      ot("nozerox%.4x%s\n",op,ms?"":":");\r
    }\r
\r
    ot("\n");\r
  }\r
\r
  // --------------------------------------\r
  if (type==3)\r
  {\r
    // Ror\r
    if (size<2)\r
    {\r
      ot(";@ Mirror value in whole 32 bits:\n");\r
      if (size<=0) ot("  orr r0,r0,r0,lsr #8\n");\r
      if (size<=1) ot("  orr r0,r0,r0,lsr #16\n");\r
      ot("\n");\r
    }\r
\r
    ot(";@ Rotate register:\n");\r
    if (!dir) ot("  adds r0,r0,#0 ;@ first clear V and C\n"); // ARM does not clear C if rot count is 0\r
    if (count<0)\r
    {\r
      if (dir) ot("  rsb %s,%s,#32\n",pct,pct);\r
      ot("  movs r0,r0,ror %s\n",pct);\r
    }\r
    else\r
    {\r
      int ror=count;\r
      if (dir) ror=32-ror;\r
      if (ror&31) ot("  movs r0,r0,ror #%d\n",ror);\r
    }\r
\r
    OpGetFlags(0,0);\r
    if (dir)\r
    {\r
      ot("  bic r10,r10,#0x30000000 ;@ clear CV\n");\r
      ot(";@ Get carry bit from bit 0:\n");\r
      if (usereg)\r
      {\r
        ot("  cmp %s,#32 ;@ rotating by 0?\n",pct);\r
        ot("  tstne r0,#1 ;@ no, check bit 0\n");\r
      }\r
      else\r
        ot("  tst r0,#1\n");\r
      ot("  orrne r10,r10,#0x20000000\n");\r
    }\r
    ot("\n");\r
\r
  }\r
  // --------------------------------------\r
  \r
  return 0;\r
}\r
\r
// Emit a Asr/Lsr/Roxr/Ror opcode - 1110cccd xxuttnnn\r
// (ccc=count, d=direction(r,l) xx=size extension, u=use reg for count, tt=type, nnn=register Dn)\r
int OpAsr(int op)\r
{\r
  int ea=0,use=0;\r
  int count=0,dir=0;\r
  int size=0,usereg=0,type=0;\r
\r
  count =(op>>9)&7;\r
  dir   =(op>>8)&1;\r
  size  =(op>>6)&3;\r
  if (size>=3) return 1; // use OpAsrEa()\r
  usereg=(op>>5)&1;\r
  type  =(op>>3)&3;\r
\r
  if (usereg==0) count=((count-1)&7)+1; // because ccc=000 means 8\r
\r
  // Use the same opcode for target registers:\r
  use=op&~0x0007;\r
\r
  // As long as count is not 8, use the same opcode for all shift counts:\r
  if (usereg==0 && count!=8 && !(count==1&&type==2)) { use|=0x0e00; count=-1; }\r
  if (usereg) { use&=~0x0e00; count=-1; } // Use same opcode for all Dn\r
\r
  if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
  OpStart(op,ea,0,count<0); Cycles=size<2?6:8;\r
\r
  EaCalc(11,0x0007, ea,size,1);\r
  EaRead(11,     0, ea,size,0x0007,1);\r
\r
  EmitAsr(op,type,dir,count, size,usereg);\r
\r
  EaWrite(11,    0, ea,size,0x0007,1);\r
\r
  opend_op_changes_cycles = (count<0);\r
  OpEnd(ea,0);\r
\r
  return 0;\r
}\r
\r
// Asr/Lsr/Roxr/Ror etc EA - 11100ttd 11eeeeee \r
int OpAsrEa(int op)\r
{\r
  int use=0,type=0,dir=0,ea=0,size=1;\r
\r
  type=(op>>9)&3;\r
  dir =(op>>8)&1;\r
  ea  = op&0x3f;\r
\r
  if (ea<0x10) return 1;\r
  // See if we can do this opcode:\r
  if (EaCanRead(ea,0)==0) return 1;\r
  if (EaCanWrite(ea)==0) return 1;\r
\r
  use=OpBase(op,size);\r
  if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
  OpStart(op,ea); Cycles=6; // EmitAsr() will add 2\r
\r
  EaCalc (11,0x003f,ea,size,1);\r
  EaRead (11,     0,ea,size,0x003f,1);\r
\r
  EmitAsr(op,type,dir,1,size,0);\r
\r
  EaWrite(11,     0,ea,size,0x003f,1);\r
\r
  OpEnd(ea);\r
  return 0;\r
}\r
\r
int OpTas(int op, int gen_special)\r
{\r
  int ea=0;\r
  int use=0;\r
\r
  ea=op&0x003f;\r
\r
  // See if we can do this opcode:\r
  if (EaCanWrite(ea)==0 || EaAn(ea)) return 1;\r
\r
  use=OpBase(op,0);\r
  if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
\r
  if (!gen_special) OpStart(op,ea);\r
  else\r
    ot("Op%.4x_%s\n", op, ms?"":":");\r
\r
  Cycles=4;\r
  if(ea>=8) Cycles+=10;\r
\r
  EaCalc (11,0x003f,ea,0,1);\r
  EaRead (11,     1,ea,0,0x003f,1);\r
\r
  ot("  adds r1,r1,#0 ;@ Defines NZ, clears CV\n");\r
  OpGetFlags(0,0);\r
  ot("\n");\r
\r
#if CYCLONE_FOR_GENESIS\r
  // the original Sega hardware ignores write-back phase (to memory only)\r
  if (ea < 0x10 || gen_special) {\r
#endif\r
    ot("  orr r1,r1,#0x80000000 ;@ set bit7\n");\r
\r
    EaWrite(11,     1,ea,0,0x003f,1);\r
#if CYCLONE_FOR_GENESIS\r
  }\r
#endif\r
\r
  OpEnd(ea);\r
\r
#if (CYCLONE_FOR_GENESIS == 2)\r
  if (!gen_special && ea >= 0x10) {\r
    OpTas(op, 1);\r
  }\r
#endif\r
\r
  return 0;\r
}\r
\r
Commit	Line	Data
cc68a136	1	#include "app.h"\r
	2	\r
	3	// --------------------- Opcodes 0x0100+ ---------------------\r
	4	// Emit a Btst (Register) opcode 0000nnn1 ttaaaaaa\r
	5	int OpBtstReg(int op)\r
	6	{\r
	7	int use=0;\r
	8	int type=0,sea=0,tea=0;\r
	9	int size=0;\r
	10	\r
	11	type=(op>>6)&3; // Btst/Bchg/Bclr/Bset\r
	12	// Get source and target EA\r
	13	sea=(op>>9)&7;\r
	14	tea=op&0x003f;\r
	15	if (tea<0x10) size=2; // For registers, 32-bits\r
	16	\r
	17	if ((tea&0x38)==0x08) return 1; // movep\r
	18	\r
	19	// See if we can do this opcode:\r
	20	if (EaCanRead(tea,0)==0) return 1;\r
	21	if (type>0)\r
	22	{\r
	23	if (EaCanWrite(tea)==0) return 1;\r
	24	}\r
	25	\r
85a36a57	26	use=OpBase(op,size);\r
cc68a136	27	use&=~0x0e00; // Use same handler for all registers\r
	28	if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
	29	\r
a6785576	30	OpStart(op,tea);\r
cc68a136	31	\r
	32	if(type==1\|\|type==3) {\r
	33	Cycles=8;\r
	34	} else {\r
	35	Cycles=type?8:4;\r
	36	if(size>=2) Cycles+=2;\r
	37	}\r
	38	\r
449ecf92	39	EaCalcReadNoSE(-1,11,sea,0,0x0e00);\r
b637c56a	40	\r
449ecf92	41	EaCalcReadNoSE((type>0)?8:-1,0,tea,size,0x003f);\r
b637c56a	42	\r
8527dc45	43	if (tea>=0x10)\r
449ecf92	44	ot(" and r11,r11,#7 ;@ mem - do mod 8\n"); // size always 0\r
449ecf92	45	else ot(" and r11,r11,#31 ;@ reg - do mod 32\n"); // size always 2\r
cc68a136	46	ot("\n");\r
cc68a136	47	\r
cc68a136	48	ot(" mov r1,#1\n");\r
449ecf92	49	ot(" tst r0,r1,lsl r11 ;@ Do arithmetic\n");\r
	50	ot(" bicne r10,r10,#0x40000000\n");\r
	51	ot(" orreq r10,r10,#0x40000000 ;@ Get Z flag\n");\r
cc68a136	52	ot("\n");\r
	53	\r
	54	if (type>0)\r
	55	{\r
449ecf92	56	if (type==1) ot(" eor r1,r0,r1,lsl r11 ;@ Toggle bit\n");\r
	57	if (type==2) ot(" bic r1,r0,r1,lsl r11 ;@ Clear bit\n");\r
	58	if (type==3) ot(" orr r1,r0,r1,lsl r11 ;@ Set bit\n");\r
cc68a136	59	ot("\n");\r
449ecf92	60	EaWrite(8,1,tea,size,0x003f,0,0);\r
cc68a136	61	}\r
cfb3dfa0	62	OpEnd(tea);\r
cc68a136	63	\r
	64	return 0;\r
	65	}\r
	66	\r
	67	// --------------------- Opcodes 0x0800+ ---------------------\r
	68	// Emit a Btst/Bchg/Bclr/Bset (Immediate) opcode 00001000 ttaaaaaa nn\r
	69	int OpBtstImm(int op)\r
	70	{\r
	71	int type=0,sea=0,tea=0;\r
	72	int use=0;\r
	73	int size=0;\r
	74	\r
	75	type=(op>>6)&3;\r
	76	// Get source and target EA\r
	77	sea= 0x003c;\r
	78	tea=op&0x003f;\r
	79	if (tea<0x10) size=2; // For registers, 32-bits\r
	80	\r
	81	// See if we can do this opcode:\r
	82	if (EaCanRead(tea,0)==0\|\|EaAn(tea)\|\|tea==0x3c) return 1;\r
	83	if (type>0)\r
	84	{\r
	85	if (EaCanWrite(tea)==0) return 1;\r
	86	}\r
	87	\r
85a36a57	88	use=OpBase(op,size);\r
cc68a136	89	if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
cc68a136	90	\r
cfb3dfa0	91	OpStart(op,sea,tea);\r
cc68a136	92	\r
cc68a136	93	ot("\n");\r
85a36a57	94	EaCalcReadNoSE(-1,0,sea,0,0);\r
449ecf92	95	ot(" mov r11,#1\n");\r
449ecf92	96	ot(" bic r10,r10,#0x40000000 ;@ Blank Z flag\n");\r
8527dc45	97	if (tea>=0x10)\r
b637c56a	98	ot(" and r0,r0,#7 ;@ mem - do mod 8\n"); // size always 0\r
b637c56a	99	else ot(" and r0,r0,#0x1F ;@ reg - do mod 32\n"); // size always 2\r
449ecf92	100	ot(" mov r11,r11,lsl r0 ;@ Make bit mask\n");\r
cc68a136	101	ot("\n");\r
	102	\r
	103	if(type==1\|\|type==3) {\r
	104	Cycles=12;\r
	105	} else {\r
	106	Cycles=type?12:8;\r
	107	if(size>=2) Cycles+=2;\r
	108	}\r
	109	\r
449ecf92	110	EaCalcReadNoSE((type>0)?8:-1,0,tea,size,0x003f);\r
	111	ot(" tst r0,r11 ;@ Do arithmetic\n");\r
	112	ot(" orreq r10,r10,#0x40000000 ;@ Get Z flag\n");\r
cc68a136	113	ot("\n");\r
	114	\r
	115	if (type>0)\r
	116	{\r
449ecf92	117	if (type==1) ot(" eor r1,r0,r11 ;@ Toggle bit\n");\r
	118	if (type==2) ot(" bic r1,r0,r11 ;@ Clear bit\n");\r
	119	if (type==3) ot(" orr r1,r0,r11 ;@ Set bit\n");\r
cc68a136	120	ot("\n");\r
449ecf92	121	EaWrite(8, 1,tea,size,0x003f,0,0);\r
07ceafdb	122	#if CYCLONE_FOR_GENESIS && !MEMHANDLERS_CHANGE_CYCLES\r
	123	// this is a bit hacky (device handlers might modify cycles)\r
	124	if (tea==0x38\|\|tea==0x39)\r
	125	ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");\r
	126	#endif\r
cc68a136	127	}\r
cc68a136	128	\r
cfb3dfa0	129	OpEnd(sea,tea);\r
cc68a136	130	\r
	131	return 0;\r
	132	}\r
	133	\r
	134	// --------------------- Opcodes 0x4000+ ---------------------\r
	135	int OpNeg(int op)\r
	136	{\r
	137	// 01000tt0 xxeeeeee (tt=negx/clr/neg/not, xx=size, eeeeee=EA)\r
	138	int type=0,size=0,ea=0,use=0;\r
	139	\r
	140	type=(op>>9)&3;\r
	141	ea =op&0x003f;\r
	142	size=(op>>6)&3; if (size>=3) return 1;\r
	143	\r
	144	// See if we can do this opcode:\r
	145	if (EaCanRead (ea,size)==0\|\|EaAn(ea)) return 1;\r
	146	if (EaCanWrite(ea )==0) return 1;\r
	147	\r
85a36a57	148	use=OpBase(op,size);\r
cc68a136	149	if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
cc68a136	150	\r
d5715559	151	OpStart(op,ea); Cycles=size<2?4:6;\r
d5715559	152	if(ea >= 0x10) Cycles*=2;\r
cc68a136	153	\r
449ecf92	154	EaCalc (11,0x003f,ea,size,0,0);\r
cc68a136	155	\r
449ecf92	156	if (type!=1) EaRead (11,0,ea,size,0x003f,0,0); // Don't need to read for 'clr' (or do we, for a dummy read?)\r
cc68a136	157	if (type==1) ot("\n");\r
	158	\r
	159	if (type==0)\r
	160	{\r
	161	ot(";@ Negx:\n");\r
	162	GetXBit(1);\r
b637c56a	163	if(size!=2) ot(" mov r0,r0,asl #%i\n",size?16:24);\r
cc68a136	164	ot(" rscs r1,r0,#0 ;@ do arithmetic\n");\r
449ecf92	165	ot(" orr r3,r10,#0xb0000000 ;@ for old Z\n");\r
cc68a136	166	OpGetFlags(1,1,0);\r
cc68a136	167	if(size!=2) {\r
a6785576	168	ot(" movs r1,r1,asr #%i\n",size?16:24);\r
449ecf92	169	ot(" orreq r10,r10,#0x40000000 ;@ possily missed Z\n");\r
a6785576	170	}\r
449ecf92	171	ot(" andeq r10,r10,r3 ;@ fix Z\n");\r
cc68a136	172	ot("\n");\r
	173	}\r
	174	\r
	175	if (type==1)\r
	176	{\r
	177	ot(";@ Clear:\n");\r
	178	ot(" mov r1,#0\n");\r
449ecf92	179	ot(" mov r10,#0x40000000 ;@ NZCV=0100\n");\r
cc68a136	180	ot("\n");\r
	181	}\r
	182	\r
	183	if (type==2)\r
	184	{\r
	185	ot(";@ Neg:\n");\r
b637c56a	186	if(size!=2) ot(" mov r0,r0,asl #%i\n",size?16:24);\r
cc68a136	187	ot(" rsbs r1,r0,#0\n");\r
	188	OpGetFlags(1,1);\r
	189	if(size!=2) ot(" mov r1,r1,asr #%i\n",size?16:24);\r
	190	ot("\n");\r
	191	}\r
	192	\r
	193	if (type==3)\r
	194	{\r
	195	ot(";@ Not:\n");\r
b637c56a	196	if(size!=2) {\r
	197	ot(" mov r0,r0,asl #%i\n",size?16:24);\r
	198	ot(" mvn r1,r0,asr #%i\n",size?16:24);\r
	199	}\r
	200	else\r
	201	ot(" mvn r1,r0\n");\r
cc68a136	202	ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");\r
	203	OpGetFlags(0,0);\r
	204	ot("\n");\r
	205	}\r
	206	\r
0e11c502	207	if (type==1) eawrite_check_addrerr=1;\r
449ecf92	208	EaWrite(11, 1,ea,size,0x003f,0,0);\r
cc68a136	209	\r
cfb3dfa0	210	OpEnd(ea);\r
cc68a136	211	\r
	212	return 0;\r
	213	}\r
	214	\r
	215	// --------------------- Opcodes 0x4840+ ---------------------\r
	216	// Swap, 01001000 01000nnn swap Dn\r
	217	int OpSwap(int op)\r
	218	{\r
	219	int ea=0,use=0;\r
	220	\r
	221	ea=op&7;\r
	222	use=op&~0x0007; // Use same opcode for all An\r
	223	\r
	224	if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
	225	\r
	226	OpStart(op); Cycles=4;\r
	227	\r
449ecf92	228	EaCalc (11,0x0007,ea,2,1);\r
449ecf92	229	EaRead (11, 0,ea,2,0x0007,1);\r
cc68a136	230	\r
	231	ot(" mov r1,r0,ror #16\n");\r
	232	ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");\r
	233	OpGetFlags(0,0);\r
	234	\r
449ecf92	235	EaWrite(11, 1,8,2,0x0007,1);\r
cc68a136	236	\r
	237	OpEnd();\r
	238	\r
	239	return 0;\r
	240	}\r
	241	\r
	242	// --------------------- Opcodes 0x4a00+ ---------------------\r
	243	// Emit a Tst opcode, 01001010 xxeeeeee\r
	244	int OpTst(int op)\r
	245	{\r
	246	int sea=0;\r
	247	int size=0,use=0;\r
	248	\r
	249	sea=op&0x003f;\r
	250	size=(op>>6)&3; if (size>=3) return 1;\r
	251	\r
	252	// See if we can do this opcode:\r
	253	if (EaCanWrite(sea)==0\|\|EaAn(sea)) return 1;\r
	254	\r
85a36a57	255	use=OpBase(op,size);\r
cc68a136	256	if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
cc68a136	257	\r
a6785576	258	OpStart(op,sea); Cycles=4;\r
cc68a136	259	\r
	260	EaCalc ( 0,0x003f,sea,size,1);\r
	261	EaRead ( 0, 0,sea,size,0x003f,1);\r
	262	\r
	263	ot(" adds r0,r0,#0 ;@ Defines NZ, clears CV\n");\r
449ecf92	264	ot(" mrs r10,cpsr ;@ r10=flags\n");\r
cc68a136	265	ot("\n");\r
cc68a136	266	\r
cfb3dfa0	267	OpEnd(sea);\r
cc68a136	268	return 0;\r
	269	}\r
	270	\r
	271	// --------------------- Opcodes 0x4880+ ---------------------\r
	272	// Emit an Ext opcode, 01001000 1x000nnn\r
	273	int OpExt(int op)\r
	274	{\r
	275	int ea=0;\r
	276	int size=0,use=0;\r
	277	int shift=0;\r
	278	\r
	279	ea=op&0x0007;\r
	280	size=(op>>6)&1;\r
	281	shift=32-(8<<size);\r
	282	\r
85a36a57	283	use=OpBase(op,size);\r
cc68a136	284	if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
	285	\r
	286	OpStart(op); Cycles=4;\r
	287	\r
449ecf92	288	EaCalc (11,0x0007,ea,size+1,0,0);\r
449ecf92	289	EaRead (11, 0,ea,size+1,0x0007,0,0);\r
cc68a136	290	\r
	291	ot(" mov r0,r0,asl #%d\n",shift);\r
	292	ot(" adds r0,r0,#0 ;@ Defines NZ, clears CV\n");\r
449ecf92	293	ot(" mrs r10,cpsr ;@ r10=flags\n");\r
cc68a136	294	ot(" mov r1,r0,asr #%d\n",shift);\r
	295	ot("\n");\r
	296	\r
449ecf92	297	EaWrite(11, 1,ea,size+1,0x0007,0,0);\r
cc68a136	298	\r
	299	OpEnd();\r
	300	return 0;\r
	301	}\r
	302	\r
	303	// --------------------- Opcodes 0x50c0+ ---------------------\r
	304	// Emit a Set cc opcode, 0101cccc 11eeeeee\r
	305	int OpSet(int op)\r
	306	{\r
	307	int cc=0,ea=0;\r
ee5e024c	308	int size=0,use=0,changed_cycles=0;\r
d95259bd	309	static const char * const cond[16]=\r
cc68a136	310	{\r
	311	"al","", "hi","ls","cc","cs","ne","eq",\r
	312	"vc","vs","pl","mi","ge","lt","gt","le"\r
	313	};\r
	314	\r
	315	cc=(op>>8)&15;\r
	316	ea=op&0x003f;\r
	317	\r
	318	if ((ea&0x38)==0x08) return 1; // dbra, not scc\r
	319	\r
	320	// See if we can do this opcode:\r
	321	if (EaCanWrite(ea)==0) return 1;\r
	322	\r
85a36a57	323	use=OpBase(op,size);\r
cc68a136	324	if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
cc68a136	325	\r
ee5e024c	326	changed_cycles=ea<8 && cc>=2;\r
ee5e024c	327	OpStart(op,ea,0,changed_cycles); Cycles=8;\r
cc68a136	328	if (ea<8) Cycles=4;\r
cc68a136	329	\r
b637c56a	330	if (cc)\r
b637c56a	331	ot(" mov r1,#0\n");\r
cc68a136	332	\r
b637c56a	333	switch (cc)\r
cc68a136	334	{\r
b637c56a	335	case 0: // T\r
	336	ot(" mvn r1,#0\n");\r
	337	if (ea<8) Cycles+=2;\r
	338	break;\r
	339	case 1: // F\r
	340	break;\r
	341	case 2: // hi\r
449ecf92	342	ot(" tst r10,#0x60000000 ;@ hi: !C && !Z\n");\r
b637c56a	343	ot(" mvneq r1,r1\n");\r
	344	if (ea<8) ot(" subeq r5,r5,#2 ;@ Extra cycles\n");\r
	345	break;\r
	346	case 3: // ls\r
449ecf92	347	ot(" tst r10,#0x60000000 ;@ ls: C \|\| Z\n");\r
b637c56a	348	ot(" mvnne r1,r1\n");\r
	349	if (ea<8) ot(" subne r5,r5,#2 ;@ Extra cycles\n");\r
	350	break;\r
	351	default:\r
	352	ot(";@ Is the condition true?\n");\r
449ecf92	353	ot(" msr cpsr_flg,r10 ;@ ARM flags = 68000 flags\n");\r
b637c56a	354	ot(" mvn%s r1,r1\n",cond[cc]);\r
	355	if (ea<8) ot(" sub%s r5,r5,#2 ;@ Extra cycles\n",cond[cc]);\r
	356	break;\r
cc68a136	357	}\r
cc68a136	358	\r
cc68a136	359	ot("\n");\r
cc68a136	360	\r
0e11c502	361	eawrite_check_addrerr=1;\r
b637c56a	362	EaCalc (0,0x003f, ea,size,0,0);\r
b637c56a	363	EaWrite(0, 1, ea,size,0x003f,0,0);\r
cc68a136	364	\r
0e11c502	365	opend_op_changes_cycles=changed_cycles;\r
0e11c502	366	OpEnd(ea,0);\r
cc68a136	367	return 0;\r
	368	}\r
	369	\r
	370	// Emit a Asr/Lsr/Roxr/Ror opcode\r
	371	static int EmitAsr(int op,int type,int dir,int count,int size,int usereg)\r
	372	{\r
	373	char pct[8]=""; // count\r
	374	int shift=32-(8<<size);\r
	375	\r
	376	if (count>=1) sprintf(pct,"#%d",count); // Fixed count\r
	377	\r
	378	if (usereg)\r
	379	{\r
	380	ot(";@ Use Dn for count:\n");\r
85a36a57	381	ot(" and r2,r8,#0x0e00\n");\r
cc68a136	382	ot(" ldr r2,[r7,r2,lsr #7]\n");\r
	383	ot(" and r2,r2,#63\n");\r
	384	ot("\n");\r
	385	strcpy(pct,"r2");\r
	386	}\r
	387	else if (count<0)\r
	388	{\r
	389	ot(" mov r2,r8,lsr #9 ;@ Get 'n'\n");\r
	390	ot(" and r2,r2,#7\n\n"); strcpy(pct,"r2");\r
	391	}\r
	392	\r
	393	// Take 2*n cycles:\r
	394	if (count<0) ot(" sub r5,r5,r2,asl #1 ;@ Take 2*n cycles\n\n");\r
	395	else Cycles+=count<<1;\r
	396	\r
	397	if (type<2)\r
	398	{\r
	399	// Asr/Lsr\r
	400	if (dir==0 && size<2)\r
	401	{\r
	402	ot(";@ For shift right, use loworder bits for the operation:\n");\r
	403	ot(" mov r0,r0,%s #%d\n",type?"lsr":"asr",32-(8<<size));\r
	404	ot("\n");\r
	405	}\r
	406	\r
1c88b865	407	if (type==0 && dir) ot(" adds r3,r0,#0 ;@ save old value for V flag calculation, also clear V\n");\r
cc68a136	408	\r
	409	ot(";@ Shift register:\n");\r
	410	if (type==0) ot(" movs r0,r0,%s %s\n",dir?"asl":"asr",pct);\r
	411	if (type==1) ot(" movs r0,r0,%s %s\n",dir?"lsl":"lsr",pct);\r
	412	\r
cc68a136	413	OpGetFlags(0,0);\r
	414	if (usereg) { // store X only if count is not 0\r
	415	ot(" cmp %s,#0 ;@ shifting by 0?\n",pct);\r
449ecf92	416	ot(" biceq r10,r10,#0x20000000 ;@ if so, clear carry\n");\r
449ecf92	417	ot(" strne r10,[r7,#0x4c] ;@ else Save X bit\n");\r
cc68a136	418	} else {\r
cc68a136	419	// count will never be 0 if we use immediate\r
449ecf92	420	ot(" str r10,[r7,#0x4c] ;@ Save X bit\n");\r
cc68a136	421	}\r
03c5768c	422	ot("\n");\r
	423	\r
	424	if (dir==0 && size<2)\r
	425	{\r
	426	ot(";@ restore after right shift:\n");\r
	427	ot(" movs r0,r0,lsl #%d\n",32-(8<<size));\r
	428	if (type)\r
449ecf92	429	ot(" orrmi r10,r10,#0x80000000 ;@ Potentially missed N flag\n");\r
03c5768c	430	ot("\n");\r
03c5768c	431	}\r
cc68a136	432	\r
	433	if (type==0 && dir) {\r
	434	ot(";@ calculate V flag (set if sign bit changes at anytime):\n");\r
	435	ot(" mov r1,#0x80000000\n");\r
	436	ot(" ands r3,r3,r1,asr %s\n", pct);\r
	437	ot(" cmpne r3,r1,asr %s\n", pct);\r
1c88b865	438	ot(" eoreq r1,r0,r3\n"); // above check doesn't catch (-1)<<(32+), so we need this\r
1c88b865	439	ot(" tsteq r1,#0x80000000\n");\r
449ecf92	440	ot(" orrne r10,r10,#0x10000000\n");\r
03c5768c	441	ot("\n");\r
cc68a136	442	}\r
cc68a136	443	}\r
	444	\r
	445	// --------------------------------------\r
	446	if (type==2)\r
	447	{\r
	448	int wide=8<<size;\r
	449	\r
	450	// Roxr\r
449ecf92	451	if(count == 1)\r
449ecf92	452	{\r
cc68a136	453	if(dir==0) {\r
cc68a136	454	if(size!=2) {\r
a6785576	455	ot(" orr r0,r0,r0,lsr #%i\n", size?16:24);\r
	456	ot(" bic r0,r0,#0x%x\n", 1<<(32-wide));\r
	457	}\r
cc68a136	458	GetXBit(0);\r
	459	ot(" movs r0,r0,rrx\n");\r
	460	OpGetFlags(0,1);\r
	461	} else {\r
85a36a57	462	ot(" ldr r3,[r7,#0x4c]\n");\r
cc68a136	463	ot(" movs r0,r0,lsl #1\n");\r
cc68a136	464	OpGetFlags(0,1);\r
85a36a57	465	ot(" tst r3,#0x20000000\n");\r
cc68a136	466	ot(" orrne r0,r0,#0x%x\n", 1<<(32-wide));\r
449ecf92	467	ot(" bicne r10,r10,#0x40000000 ;@ clear Z in case it got there\n");\r
cc68a136	468	}\r
449ecf92	469	ot(" bic r10,r10,#0x10000000 ;@ make suve V is clear\n");\r
cc68a136	470	return 0;\r
	471	}\r
	472	\r
	473	if (usereg)\r
	474	{\r
03c5768c	475	if (size==2)\r
	476	{\r
	477	ot(" subs r2,r2,#33\n");\r
	478	ot(" addmis r2,r2,#33 ;@ Now r2=0-%d\n",wide);\r
	479	}\r
	480	else\r
	481	{\r
	482	ot(";@ Reduce r2 until <0:\n");\r
	483	ot("Reduce_%.4x%s\n",op,ms?"":":");\r
	484	ot(" subs r2,r2,#%d\n",wide+1);\r
	485	ot(" bpl Reduce_%.4x\n",op);\r
	486	ot(" adds r2,r2,#%d ;@ Now r2=0-%d\n",wide+1,wide);\r
	487	}\r
	488	ot(" beq norotx_%.4x\n",op);\r
cc68a136	489	ot("\n");\r
	490	}\r
	491	\r
	492	if (usereg\|\|count < 0)\r
	493	{\r
	494	if (dir) ot(" rsb r2,r2,#%d ;@ Reverse direction\n",wide+1);\r
	495	}\r
	496	else\r
	497	{\r
	498	if (dir) ot(" mov r2,#%d ;@ Reversed\n",wide+1-count);\r
	499	else ot(" mov r2,#%d\n",count);\r
	500	}\r
	501	\r
	502	if (shift) ot(" mov r0,r0,lsr #%d ;@ Shift down\n",shift);\r
	503	\r
03c5768c	504	ot("\n");\r
03c5768c	505	ot(";@ First get X bit (middle):\n");\r
85a36a57	506	ot(" ldr r3,[r7,#0x4c]\n");\r
03c5768c	507	ot(" rsb r1,r2,#%d\n",wide);\r
85a36a57	508	ot(" and r3,r3,#0x20000000\n");\r
85a36a57	509	ot(" mov r3,r3,lsr #29\n");\r
03c5768c	510	ot(" mov r3,r3,lsl r1\n");\r
	511	\r
	512	ot(";@ Rotate bits:\n");\r
	513	ot(" orr r3,r3,r0,lsr r2 ;@ Orr right part\n");\r
	514	ot(" rsbs r2,r2,#%d ;@ should also clear ARM V\n",wide+1);\r
	515	ot(" orrs r0,r3,r0,lsl r2 ;@ Orr left part, set flags\n");\r
cc68a136	516	ot("\n");\r
	517	\r
	518	if (shift) ot(" movs r0,r0,lsl #%d ;@ Shift up and get correct NC flags\n",shift);\r
	519	OpGetFlags(0,!usereg);\r
cc68a136	520	if (usereg) { // store X only if count is not 0\r
449ecf92	521	ot(" str r10,[r7,#0x4c] ;@ if not 0, Save X bit\n");\r
cc68a136	522	ot(" b nozerox%.4x\n",op);\r
03c5768c	523	ot("norotx_%.4x%s\n",op,ms?"":":");\r
85a36a57	524	ot(" ldr r2,[r7,#0x4c]\n");\r
cc68a136	525	ot(" adds r0,r0,#0 ;@ Defines NZ, clears CV\n");\r
cc68a136	526	OpGetFlags(0,0);\r
85a36a57	527	ot(" and r2,r2,#0x20000000\n");\r
449ecf92	528	ot(" orr r10,r10,r2 ;@ C = old_X\n");\r
cc68a136	529	ot("nozerox%.4x%s\n",op,ms?"":":");\r
	530	}\r
	531	\r
	532	ot("\n");\r
	533	}\r
	534	\r
	535	// --------------------------------------\r
	536	if (type==3)\r
	537	{\r
	538	// Ror\r
	539	if (size<2)\r
	540	{\r
	541	ot(";@ Mirror value in whole 32 bits:\n");\r
	542	if (size<=0) ot(" orr r0,r0,r0,lsr #8\n");\r
	543	if (size<=1) ot(" orr r0,r0,r0,lsr #16\n");\r
	544	ot("\n");\r
	545	}\r
	546	\r
	547	ot(";@ Rotate register:\n");\r
03c5768c	548	if (!dir) ot(" adds r0,r0,#0 ;@ first clear V and C\n"); // ARM does not clear C if rot count is 0\r
cc68a136	549	if (count<0)\r
cc68a136	550	{\r
03c5768c	551	if (dir) ot(" rsb %s,%s,#32\n",pct,pct);\r
cc68a136	552	ot(" movs r0,r0,ror %s\n",pct);\r
	553	}\r
	554	else\r
	555	{\r
	556	int ror=count;\r
	557	if (dir) ror=32-ror;\r
	558	if (ror&31) ot(" movs r0,r0,ror #%d\n",ror);\r
	559	}\r
	560	\r
	561	OpGetFlags(0,0);\r
cc68a136	562	if (dir)\r
cc68a136	563	{\r
449ecf92	564	ot(" bic r10,r10,#0x30000000 ;@ clear CV\n");\r
cc68a136	565	ot(";@ Get carry bit from bit 0:\n");\r
	566	if (usereg)\r
	567	{\r
	568	ot(" cmp %s,#32 ;@ rotating by 0?\n",pct);\r
	569	ot(" tstne r0,#1 ;@ no, check bit 0\n");\r
	570	}\r
	571	else\r
	572	ot(" tst r0,#1\n");\r
449ecf92	573	ot(" orrne r10,r10,#0x20000000\n");\r
cc68a136	574	}\r
	575	ot("\n");\r
	576	\r
	577	}\r
	578	// --------------------------------------\r
	579	\r
	580	return 0;\r
	581	}\r
	582	\r
	583	// Emit a Asr/Lsr/Roxr/Ror opcode - 1110cccd xxuttnnn\r
	584	// (ccc=count, d=direction(r,l) xx=size extension, u=use reg for count, tt=type, nnn=register Dn)\r
	585	int OpAsr(int op)\r
	586	{\r
	587	int ea=0,use=0;\r
	588	int count=0,dir=0;\r
	589	int size=0,usereg=0,type=0;\r
	590	\r
cc68a136	591	count =(op>>9)&7;\r
	592	dir =(op>>8)&1;\r
	593	size =(op>>6)&3;\r
	594	if (size>=3) return 1; // use OpAsrEa()\r
	595	usereg=(op>>5)&1;\r
	596	type =(op>>3)&3;\r
	597	\r
	598	if (usereg==0) count=((count-1)&7)+1; // because ccc=000 means 8\r
	599	\r
	600	// Use the same opcode for target registers:\r
	601	use=op&~0x0007;\r
	602	\r
03c5768c	603	// As long as count is not 8, use the same opcode for all shift counts:\r
cc68a136	604	if (usereg==0 && count!=8 && !(count==1&&type==2)) { use\|=0x0e00; count=-1; }\r
	605	if (usereg) { use&=~0x0e00; count=-1; } // Use same opcode for all Dn\r
	606	\r
	607	if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
	608	\r
ee5e024c	609	OpStart(op,ea,0,count<0); Cycles=size<2?6:8;\r
cc68a136	610	\r
449ecf92	611	EaCalc(11,0x0007, ea,size,1);\r
449ecf92	612	EaRead(11, 0, ea,size,0x0007,1);\r
cc68a136	613	\r
	614	EmitAsr(op,type,dir,count, size,usereg);\r
	615	\r
449ecf92	616	EaWrite(11, 0, ea,size,0x0007,1);\r
cc68a136	617	\r
0e11c502	618	opend_op_changes_cycles = (count<0);\r
0e11c502	619	OpEnd(ea,0);\r
cc68a136	620	\r
	621	return 0;\r
	622	}\r
	623	\r
	624	// Asr/Lsr/Roxr/Ror etc EA - 11100ttd 11eeeeee \r
	625	int OpAsrEa(int op)\r
	626	{\r
	627	int use=0,type=0,dir=0,ea=0,size=1;\r
	628	\r
	629	type=(op>>9)&3;\r
	630	dir =(op>>8)&1;\r
	631	ea = op&0x3f;\r
	632	\r
	633	if (ea<0x10) return 1;\r
	634	// See if we can do this opcode:\r
	635	if (EaCanRead(ea,0)==0) return 1;\r
	636	if (EaCanWrite(ea)==0) return 1;\r
	637	\r
85a36a57	638	use=OpBase(op,size);\r
cc68a136	639	if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
cc68a136	640	\r
a6785576	641	OpStart(op,ea); Cycles=6; // EmitAsr() will add 2\r
cc68a136	642	\r
449ecf92	643	EaCalc (11,0x003f,ea,size,1);\r
449ecf92	644	EaRead (11, 0,ea,size,0x003f,1);\r
cc68a136	645	\r
	646	EmitAsr(op,type,dir,1,size,0);\r
	647	\r
449ecf92	648	EaWrite(11, 0,ea,size,0x003f,1);\r
cc68a136	649	\r
cfb3dfa0	650	OpEnd(ea);\r
cc68a136	651	return 0;\r
	652	}\r
	653	\r
c008977e	654	int OpTas(int op, int gen_special)\r
cc68a136	655	{\r
	656	int ea=0;\r
	657	int use=0;\r
	658	\r
	659	ea=op&0x003f;\r
	660	\r
	661	// See if we can do this opcode:\r
	662	if (EaCanWrite(ea)==0 \|\| EaAn(ea)) return 1;\r
	663	\r
85a36a57	664	use=OpBase(op,0);\r
cc68a136	665	if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
cc68a136	666	\r
a6785576	667	if (!gen_special) OpStart(op,ea);\r
c008977e	668	else\r
	669	ot("Op%.4x_%s\n", op, ms?"":":");\r
	670	\r
	671	Cycles=4;\r
cc68a136	672	if(ea>=8) Cycles+=10;\r
cc68a136	673	\r
449ecf92	674	EaCalc (11,0x003f,ea,0,1);\r
449ecf92	675	EaRead (11, 1,ea,0,0x003f,1);\r
cc68a136	676	\r
	677	ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");\r
	678	OpGetFlags(0,0);\r
	679	ot("\n");\r
	680	\r
	681	#if CYCLONE_FOR_GENESIS\r
	682	// the original Sega hardware ignores write-back phase (to memory only)\r
c008977e	683	if (ea < 0x10 \|\| gen_special) {\r
cc68a136	684	#endif\r
	685	ot(" orr r1,r1,#0x80000000 ;@ set bit7\n");\r
	686	\r
449ecf92	687	EaWrite(11, 1,ea,0,0x003f,1);\r
cc68a136	688	#if CYCLONE_FOR_GENESIS\r
	689	}\r
	690	#endif\r
	691	\r
cfb3dfa0	692	OpEnd(ea);\r
c008977e	693	\r
a9a5a6e0	694	#if (CYCLONE_FOR_GENESIS == 2)\r
c008977e	695	if (!gen_special && ea >= 0x10) {\r
	696	OpTas(op, 1);\r
	697	}\r
	698	#endif\r
	699	\r
cc68a136	700	return 0;\r
	701	}\r
	702	\r