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0.0088 release
[picodrive.git] / cpu / Cyclone / OpLogic.cpp
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cc68a136 1#include "app.h"\r
2\r
3// --------------------- Opcodes 0x0100+ ---------------------\r
4// Emit a Btst (Register) opcode 0000nnn1 ttaaaaaa\r
5int OpBtstReg(int op)\r
6{\r
7 int use=0;\r
8 int type=0,sea=0,tea=0;\r
9 int size=0;\r
10\r
11 type=(op>>6)&3; // Btst/Bchg/Bclr/Bset\r
12 // Get source and target EA\r
13 sea=(op>>9)&7;\r
14 tea=op&0x003f;\r
15 if (tea<0x10) size=2; // For registers, 32-bits\r
16\r
17 if ((tea&0x38)==0x08) return 1; // movep\r
18\r
19 // See if we can do this opcode:\r
20 if (EaCanRead(tea,0)==0) return 1;\r
21 if (type>0)\r
22 {\r
23 if (EaCanWrite(tea)==0) return 1;\r
24 }\r
25\r
85a36a57 26 use=OpBase(op,size);\r
cc68a136 27 use&=~0x0e00; // Use same handler for all registers\r
28 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
29\r
a6785576 30 OpStart(op,tea);\r
cc68a136 31\r
32 if(type==1||type==3) {\r
33 Cycles=8;\r
34 } else {\r
35 Cycles=type?8:4;\r
36 if(size>=2) Cycles+=2;\r
37 }\r
38\r
85a36a57 39 EaCalcReadNoSE(-1,10,sea,0,0x0e00);\r
b637c56a 40\r
85a36a57 41 EaCalcReadNoSE((type>0)?11:-1,0,tea,size,0x003f);\r
b637c56a 42\r
cc68a136 43 if (tea>=0x10)\r
b637c56a 44 ot(" and r10,r10,#7 ;@ mem - do mod 8\n"); // size always 0\r
45 else ot(" and r10,r10,#31 ;@ reg - do mod 32\n"); // size always 2\r
cc68a136 46 ot("\n");\r
47\r
cc68a136 48 ot(" mov r1,#1\n");\r
49 ot(" tst r0,r1,lsl r10 ;@ Do arithmetic\n");\r
50 ot(" bicne r9,r9,#0x40000000\n");\r
51 ot(" orreq r9,r9,#0x40000000 ;@ Get Z flag\n");\r
52 ot("\n");\r
53\r
54 if (type>0)\r
55 {\r
56 if (type==1) ot(" eor r1,r0,r1,lsl r10 ;@ Toggle bit\n");\r
57 if (type==2) ot(" bic r1,r0,r1,lsl r10 ;@ Clear bit\n");\r
58 if (type==3) ot(" orr r1,r0,r1,lsl r10 ;@ Set bit\n");\r
59 ot("\n");\r
b637c56a 60 EaWrite(11, 1,tea,size,0x003f,0,0);\r
cc68a136 61 }\r
cfb3dfa0 62 OpEnd(tea);\r
cc68a136 63\r
64 return 0;\r
65}\r
66\r
67// --------------------- Opcodes 0x0800+ ---------------------\r
68// Emit a Btst/Bchg/Bclr/Bset (Immediate) opcode 00001000 ttaaaaaa nn\r
69int OpBtstImm(int op)\r
70{\r
71 int type=0,sea=0,tea=0;\r
72 int use=0;\r
73 int size=0;\r
74\r
75 type=(op>>6)&3;\r
76 // Get source and target EA\r
77 sea= 0x003c;\r
78 tea=op&0x003f;\r
79 if (tea<0x10) size=2; // For registers, 32-bits\r
80\r
81 // See if we can do this opcode:\r
82 if (EaCanRead(tea,0)==0||EaAn(tea)||tea==0x3c) return 1;\r
83 if (type>0)\r
84 {\r
85 if (EaCanWrite(tea)==0) return 1;\r
86 }\r
87\r
85a36a57 88 use=OpBase(op,size);\r
cc68a136 89 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
90\r
cfb3dfa0 91 OpStart(op,sea,tea);\r
cc68a136 92\r
cc68a136 93 ot("\n");\r
85a36a57 94 EaCalcReadNoSE(-1,0,sea,0,0);\r
b637c56a 95 ot(" mov r10,#1\n");\r
cc68a136 96 ot(" bic r9,r9,#0x40000000 ;@ Blank Z flag\n");\r
97 if (tea>=0x10)\r
b637c56a 98 ot(" and r0,r0,#7 ;@ mem - do mod 8\n"); // size always 0\r
99 else ot(" and r0,r0,#0x1F ;@ reg - do mod 32\n"); // size always 2\r
cc68a136 100 ot(" mov r10,r10,lsl r0 ;@ Make bit mask\n");\r
101 ot("\n");\r
102\r
103 if(type==1||type==3) {\r
104 Cycles=12;\r
105 } else {\r
106 Cycles=type?12:8;\r
107 if(size>=2) Cycles+=2;\r
108 }\r
109\r
85a36a57 110 EaCalcReadNoSE((type>0)?11:-1,0,tea,size,0x003f);\r
cc68a136 111 ot(" tst r0,r10 ;@ Do arithmetic\n");\r
112 ot(" orreq r9,r9,#0x40000000 ;@ Get Z flag\n");\r
113 ot("\n");\r
114\r
115 if (type>0)\r
116 {\r
117 if (type==1) ot(" eor r1,r0,r10 ;@ Toggle bit\n");\r
118 if (type==2) ot(" bic r1,r0,r10 ;@ Clear bit\n");\r
119 if (type==3) ot(" orr r1,r0,r10 ;@ Set bit\n");\r
120 ot("\n");\r
b637c56a 121 EaWrite(11, 1,tea,size,0x003f,0,0);\r
cc68a136 122 }\r
123\r
cfb3dfa0 124 OpEnd(sea,tea);\r
cc68a136 125\r
126 return 0;\r
127}\r
128\r
129// --------------------- Opcodes 0x4000+ ---------------------\r
130int OpNeg(int op)\r
131{\r
132 // 01000tt0 xxeeeeee (tt=negx/clr/neg/not, xx=size, eeeeee=EA)\r
133 int type=0,size=0,ea=0,use=0;\r
134\r
135 type=(op>>9)&3;\r
136 ea =op&0x003f;\r
137 size=(op>>6)&3; if (size>=3) return 1;\r
138\r
139 // See if we can do this opcode:\r
140 if (EaCanRead (ea,size)==0||EaAn(ea)) return 1;\r
141 if (EaCanWrite(ea )==0) return 1;\r
142\r
85a36a57 143 use=OpBase(op,size);\r
cc68a136 144 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
145\r
a6785576 146 OpStart(op,ea); Cycles=size<2?4:6;\r
cc68a136 147 if(ea >= 0x10) {\r
148 Cycles*=2;\r
a9a5a6e0 149#if CYCLONE_FOR_GENESIS\r
cc68a136 150 // This is same as in Starscream core, CLR uses only 6 cycles for memory EAs.\r
151 // May be this is similar case as with TAS opcode, but this time the dummy\r
152 // read is ignored somehow? Without this hack Fatal Rewind hangs even in Gens.\r
153 if(type==1&&size<2) Cycles-=2;\r
154#endif\r
155 }\r
156\r
b637c56a 157 EaCalc (10,0x003f,ea,size,0,0);\r
cc68a136 158\r
85a36a57 159 if (type!=1) EaRead (10,0,ea,size,0x003f,0,0); // Don't need to read for 'clr' (or do we, for a dummy read?)\r
cc68a136 160 if (type==1) ot("\n");\r
161\r
162 if (type==0)\r
163 {\r
164 ot(";@ Negx:\n");\r
165 GetXBit(1);\r
b637c56a 166 if(size!=2) ot(" mov r0,r0,asl #%i\n",size?16:24);\r
cc68a136 167 ot(" rscs r1,r0,#0 ;@ do arithmetic\n");\r
168 ot(" orr r3,r9,#0xb0000000 ;@ for old Z\n");\r
169 OpGetFlags(1,1,0);\r
170 if(size!=2) {\r
a6785576 171 ot(" movs r1,r1,asr #%i\n",size?16:24);\r
cc68a136 172 ot(" orreq r9,r9,#0x40000000 ;@ possily missed Z\n");\r
a6785576 173 }\r
174 ot(" andeq r9,r9,r3 ;@ fix Z\n");\r
cc68a136 175 ot("\n");\r
176 }\r
177\r
178 if (type==1)\r
179 {\r
180 ot(";@ Clear:\n");\r
181 ot(" mov r1,#0\n");\r
182 ot(" mov r9,#0x40000000 ;@ NZCV=0100\n");\r
183 ot("\n");\r
184 }\r
185\r
186 if (type==2)\r
187 {\r
188 ot(";@ Neg:\n");\r
b637c56a 189 if(size!=2) ot(" mov r0,r0,asl #%i\n",size?16:24);\r
cc68a136 190 ot(" rsbs r1,r0,#0\n");\r
191 OpGetFlags(1,1);\r
192 if(size!=2) ot(" mov r1,r1,asr #%i\n",size?16:24);\r
193 ot("\n");\r
194 }\r
195\r
196 if (type==3)\r
197 {\r
198 ot(";@ Not:\n");\r
b637c56a 199 if(size!=2) {\r
200 ot(" mov r0,r0,asl #%i\n",size?16:24);\r
201 ot(" mvn r1,r0,asr #%i\n",size?16:24);\r
202 }\r
203 else\r
204 ot(" mvn r1,r0\n");\r
cc68a136 205 ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");\r
206 OpGetFlags(0,0);\r
207 ot("\n");\r
208 }\r
209\r
0e11c502 210 if (type==1) eawrite_check_addrerr=1;\r
b637c56a 211 EaWrite(10, 1,ea,size,0x003f,0,0);\r
cc68a136 212\r
cfb3dfa0 213 OpEnd(ea);\r
cc68a136 214\r
215 return 0;\r
216}\r
217\r
218// --------------------- Opcodes 0x4840+ ---------------------\r
219// Swap, 01001000 01000nnn swap Dn\r
220int OpSwap(int op)\r
221{\r
222 int ea=0,use=0;\r
223\r
224 ea=op&7;\r
225 use=op&~0x0007; // Use same opcode for all An\r
226\r
227 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
228\r
229 OpStart(op); Cycles=4;\r
230\r
231 EaCalc (10,0x0007,ea,2,1);\r
232 EaRead (10, 0,ea,2,0x0007,1);\r
233\r
234 ot(" mov r1,r0,ror #16\n");\r
235 ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");\r
236 OpGetFlags(0,0);\r
237\r
238 EaWrite(10, 1,8,2,0x0007,1);\r
239\r
240 OpEnd();\r
241\r
242 return 0;\r
243}\r
244\r
245// --------------------- Opcodes 0x4a00+ ---------------------\r
246// Emit a Tst opcode, 01001010 xxeeeeee\r
247int OpTst(int op)\r
248{\r
249 int sea=0;\r
250 int size=0,use=0;\r
251\r
252 sea=op&0x003f;\r
253 size=(op>>6)&3; if (size>=3) return 1;\r
254\r
255 // See if we can do this opcode:\r
256 if (EaCanWrite(sea)==0||EaAn(sea)) return 1;\r
257\r
85a36a57 258 use=OpBase(op,size);\r
cc68a136 259 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
260\r
a6785576 261 OpStart(op,sea); Cycles=4;\r
cc68a136 262\r
263 EaCalc ( 0,0x003f,sea,size,1);\r
264 EaRead ( 0, 0,sea,size,0x003f,1);\r
265\r
266 ot(" adds r0,r0,#0 ;@ Defines NZ, clears CV\n");\r
267 ot(" mrs r9,cpsr ;@ r9=flags\n");\r
268 ot("\n");\r
269\r
cfb3dfa0 270 OpEnd(sea);\r
cc68a136 271 return 0;\r
272}\r
273\r
274// --------------------- Opcodes 0x4880+ ---------------------\r
275// Emit an Ext opcode, 01001000 1x000nnn\r
276int OpExt(int op)\r
277{\r
278 int ea=0;\r
279 int size=0,use=0;\r
280 int shift=0;\r
281\r
282 ea=op&0x0007;\r
283 size=(op>>6)&1;\r
284 shift=32-(8<<size);\r
285\r
85a36a57 286 use=OpBase(op,size);\r
cc68a136 287 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
288\r
289 OpStart(op); Cycles=4;\r
290\r
b637c56a 291 EaCalc (10,0x0007,ea,size+1,0,0);\r
292 EaRead (10, 0,ea,size+1,0x0007,0,0);\r
cc68a136 293\r
294 ot(" mov r0,r0,asl #%d\n",shift);\r
295 ot(" adds r0,r0,#0 ;@ Defines NZ, clears CV\n");\r
296 ot(" mrs r9,cpsr ;@ r9=flags\n");\r
297 ot(" mov r1,r0,asr #%d\n",shift);\r
298 ot("\n");\r
299\r
b637c56a 300 EaWrite(10, 1,ea,size+1,0x0007,0,0);\r
cc68a136 301\r
302 OpEnd();\r
303 return 0;\r
304}\r
305\r
306// --------------------- Opcodes 0x50c0+ ---------------------\r
307// Emit a Set cc opcode, 0101cccc 11eeeeee\r
308int OpSet(int op)\r
309{\r
310 int cc=0,ea=0;\r
ee5e024c 311 int size=0,use=0,changed_cycles=0;\r
cc68a136 312 char *cond[16]=\r
313 {\r
314 "al","", "hi","ls","cc","cs","ne","eq",\r
315 "vc","vs","pl","mi","ge","lt","gt","le"\r
316 };\r
317\r
318 cc=(op>>8)&15;\r
319 ea=op&0x003f;\r
320\r
321 if ((ea&0x38)==0x08) return 1; // dbra, not scc\r
322 \r
323 // See if we can do this opcode:\r
324 if (EaCanWrite(ea)==0) return 1;\r
325\r
85a36a57 326 use=OpBase(op,size);\r
cc68a136 327 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
328\r
ee5e024c 329 changed_cycles=ea<8 && cc>=2;\r
330 OpStart(op,ea,0,changed_cycles); Cycles=8;\r
cc68a136 331 if (ea<8) Cycles=4;\r
332\r
b637c56a 333 if (cc)\r
334 ot(" mov r1,#0\n");\r
cc68a136 335\r
b637c56a 336 switch (cc)\r
cc68a136 337 {\r
b637c56a 338 case 0: // T\r
339 ot(" mvn r1,#0\n");\r
340 if (ea<8) Cycles+=2;\r
341 break;\r
342 case 1: // F\r
343 break;\r
344 case 2: // hi\r
3a5e6cf8 345 ot(" tst r9,#0x60000000 ;@ hi: !C && !Z\n");\r
b637c56a 346 ot(" mvneq r1,r1\n");\r
347 if (ea<8) ot(" subeq r5,r5,#2 ;@ Extra cycles\n");\r
348 break;\r
349 case 3: // ls\r
350 ot(" tst r9,#0x60000000 ;@ ls: C || Z\n");\r
351 ot(" mvnne r1,r1\n");\r
352 if (ea<8) ot(" subne r5,r5,#2 ;@ Extra cycles\n");\r
353 break;\r
354 default:\r
355 ot(";@ Is the condition true?\n");\r
356 ot(" msr cpsr_flg,r9 ;@ ARM flags = 68000 flags\n");\r
357 ot(" mvn%s r1,r1\n",cond[cc]);\r
358 if (ea<8) ot(" sub%s r5,r5,#2 ;@ Extra cycles\n",cond[cc]);\r
359 break;\r
cc68a136 360 }\r
361\r
cc68a136 362 ot("\n");\r
363\r
0e11c502 364 eawrite_check_addrerr=1;\r
b637c56a 365 EaCalc (0,0x003f, ea,size,0,0);\r
366 EaWrite(0, 1, ea,size,0x003f,0,0);\r
cc68a136 367\r
0e11c502 368 opend_op_changes_cycles=changed_cycles;\r
369 OpEnd(ea,0);\r
cc68a136 370 return 0;\r
371}\r
372\r
373// Emit a Asr/Lsr/Roxr/Ror opcode\r
374static int EmitAsr(int op,int type,int dir,int count,int size,int usereg)\r
375{\r
376 char pct[8]=""; // count\r
377 int shift=32-(8<<size);\r
378\r
379 if (count>=1) sprintf(pct,"#%d",count); // Fixed count\r
380\r
381 if (usereg)\r
382 {\r
383 ot(";@ Use Dn for count:\n");\r
85a36a57 384 ot(" and r2,r8,#0x0e00\n");\r
cc68a136 385 ot(" ldr r2,[r7,r2,lsr #7]\n");\r
386 ot(" and r2,r2,#63\n");\r
387 ot("\n");\r
388 strcpy(pct,"r2");\r
389 }\r
390 else if (count<0)\r
391 {\r
392 ot(" mov r2,r8,lsr #9 ;@ Get 'n'\n");\r
393 ot(" and r2,r2,#7\n\n"); strcpy(pct,"r2");\r
394 }\r
395\r
396 // Take 2*n cycles:\r
397 if (count<0) ot(" sub r5,r5,r2,asl #1 ;@ Take 2*n cycles\n\n");\r
398 else Cycles+=count<<1;\r
399\r
400 if (type<2)\r
401 {\r
402 // Asr/Lsr\r
403 if (dir==0 && size<2)\r
404 {\r
405 ot(";@ For shift right, use loworder bits for the operation:\n");\r
406 ot(" mov r0,r0,%s #%d\n",type?"lsr":"asr",32-(8<<size));\r
407 ot("\n");\r
408 }\r
409\r
1c88b865 410 if (type==0 && dir) ot(" adds r3,r0,#0 ;@ save old value for V flag calculation, also clear V\n");\r
cc68a136 411\r
412 ot(";@ Shift register:\n");\r
413 if (type==0) ot(" movs r0,r0,%s %s\n",dir?"asl":"asr",pct);\r
414 if (type==1) ot(" movs r0,r0,%s %s\n",dir?"lsl":"lsr",pct);\r
415\r
cc68a136 416 OpGetFlags(0,0);\r
417 if (usereg) { // store X only if count is not 0\r
418 ot(" cmp %s,#0 ;@ shifting by 0?\n",pct);\r
419 ot(" biceq r9,r9,#0x20000000 ;@ if so, clear carry\n");\r
85a36a57 420 ot(" strne r9,[r7,#0x4c] ;@ else Save X bit\n");\r
cc68a136 421 } else {\r
422 // count will never be 0 if we use immediate\r
85a36a57 423 ot(" str r9,[r7,#0x4c] ;@ Save X bit\n");\r
cc68a136 424 }\r
03c5768c 425 ot("\n");\r
426\r
427 if (dir==0 && size<2)\r
428 {\r
429 ot(";@ restore after right shift:\n");\r
430 ot(" movs r0,r0,lsl #%d\n",32-(8<<size));\r
431 if (type)\r
432 ot(" orrmi r9,r9,#0x80000000 ;@ Potentially missed N flag\n");\r
433 ot("\n");\r
434 }\r
cc68a136 435\r
436 if (type==0 && dir) {\r
437 ot(";@ calculate V flag (set if sign bit changes at anytime):\n");\r
438 ot(" mov r1,#0x80000000\n");\r
439 ot(" ands r3,r3,r1,asr %s\n", pct);\r
440 ot(" cmpne r3,r1,asr %s\n", pct);\r
1c88b865 441 ot(" eoreq r1,r0,r3\n"); // above check doesn't catch (-1)<<(32+), so we need this\r
442 ot(" tsteq r1,#0x80000000\n");\r
cc68a136 443 ot(" orrne r9,r9,#0x10000000\n");\r
03c5768c 444 ot("\n");\r
cc68a136 445 }\r
cc68a136 446 }\r
447\r
448 // --------------------------------------\r
449 if (type==2)\r
450 {\r
451 int wide=8<<size;\r
452\r
453 // Roxr\r
454 if(count == 1) {\r
455 if(dir==0) {\r
456 if(size!=2) {\r
a6785576 457 ot(" orr r0,r0,r0,lsr #%i\n", size?16:24);\r
458 ot(" bic r0,r0,#0x%x\n", 1<<(32-wide));\r
459 }\r
cc68a136 460 GetXBit(0);\r
461 ot(" movs r0,r0,rrx\n");\r
462 OpGetFlags(0,1);\r
463 } else {\r
85a36a57 464 ot(" ldr r3,[r7,#0x4c]\n");\r
cc68a136 465 ot(" movs r0,r0,lsl #1\n");\r
466 OpGetFlags(0,1);\r
85a36a57 467 ot(" tst r3,#0x20000000\n");\r
cc68a136 468 ot(" orrne r0,r0,#0x%x\n", 1<<(32-wide));\r
469 ot(" bicne r9,r9,#0x40000000 ;@ clear Z in case it got there\n");\r
470 }\r
471 ot(" bic r9,r9,#0x10000000 ;@ make suve V is clear\n");\r
472 return 0;\r
473 }\r
474\r
475 if (usereg)\r
476 {\r
03c5768c 477 if (size==2)\r
478 {\r
479 ot(" subs r2,r2,#33\n");\r
480 ot(" addmis r2,r2,#33 ;@ Now r2=0-%d\n",wide);\r
481 }\r
482 else\r
483 {\r
484 ot(";@ Reduce r2 until <0:\n");\r
485 ot("Reduce_%.4x%s\n",op,ms?"":":");\r
486 ot(" subs r2,r2,#%d\n",wide+1);\r
487 ot(" bpl Reduce_%.4x\n",op);\r
488 ot(" adds r2,r2,#%d ;@ Now r2=0-%d\n",wide+1,wide);\r
489 }\r
490 ot(" beq norotx_%.4x\n",op);\r
cc68a136 491 ot("\n");\r
492 }\r
493\r
494 if (usereg||count < 0)\r
495 {\r
496 if (dir) ot(" rsb r2,r2,#%d ;@ Reverse direction\n",wide+1);\r
497 }\r
498 else\r
499 {\r
500 if (dir) ot(" mov r2,#%d ;@ Reversed\n",wide+1-count);\r
501 else ot(" mov r2,#%d\n",count);\r
502 }\r
503\r
504 if (shift) ot(" mov r0,r0,lsr #%d ;@ Shift down\n",shift);\r
505\r
03c5768c 506 ot("\n");\r
507 ot(";@ First get X bit (middle):\n");\r
85a36a57 508 ot(" ldr r3,[r7,#0x4c]\n");\r
03c5768c 509 ot(" rsb r1,r2,#%d\n",wide);\r
85a36a57 510 ot(" and r3,r3,#0x20000000\n");\r
511 ot(" mov r3,r3,lsr #29\n");\r
03c5768c 512 ot(" mov r3,r3,lsl r1\n");\r
513\r
514 ot(";@ Rotate bits:\n");\r
515 ot(" orr r3,r3,r0,lsr r2 ;@ Orr right part\n");\r
516 ot(" rsbs r2,r2,#%d ;@ should also clear ARM V\n",wide+1);\r
517 ot(" orrs r0,r3,r0,lsl r2 ;@ Orr left part, set flags\n");\r
cc68a136 518 ot("\n");\r
519\r
520 if (shift) ot(" movs r0,r0,lsl #%d ;@ Shift up and get correct NC flags\n",shift);\r
521 OpGetFlags(0,!usereg);\r
cc68a136 522 if (usereg) { // store X only if count is not 0\r
85a36a57 523 ot(" str r9,[r7,#0x4c] ;@ if not 0, Save X bit\n");\r
cc68a136 524 ot(" b nozerox%.4x\n",op);\r
03c5768c 525 ot("norotx_%.4x%s\n",op,ms?"":":");\r
85a36a57 526 ot(" ldr r2,[r7,#0x4c]\n");\r
cc68a136 527 ot(" adds r0,r0,#0 ;@ Defines NZ, clears CV\n");\r
528 OpGetFlags(0,0);\r
85a36a57 529 ot(" and r2,r2,#0x20000000\n");\r
530 ot(" orr r9,r9,r2 ;@ C = old_X\n");\r
cc68a136 531 ot("nozerox%.4x%s\n",op,ms?"":":");\r
532 }\r
533\r
534 ot("\n");\r
535 }\r
536\r
537 // --------------------------------------\r
538 if (type==3)\r
539 {\r
540 // Ror\r
541 if (size<2)\r
542 {\r
543 ot(";@ Mirror value in whole 32 bits:\n");\r
544 if (size<=0) ot(" orr r0,r0,r0,lsr #8\n");\r
545 if (size<=1) ot(" orr r0,r0,r0,lsr #16\n");\r
546 ot("\n");\r
547 }\r
548\r
549 ot(";@ Rotate register:\n");\r
03c5768c 550 if (!dir) ot(" adds r0,r0,#0 ;@ first clear V and C\n"); // ARM does not clear C if rot count is 0\r
cc68a136 551 if (count<0)\r
552 {\r
03c5768c 553 if (dir) ot(" rsb %s,%s,#32\n",pct,pct);\r
cc68a136 554 ot(" movs r0,r0,ror %s\n",pct);\r
555 }\r
556 else\r
557 {\r
558 int ror=count;\r
559 if (dir) ror=32-ror;\r
560 if (ror&31) ot(" movs r0,r0,ror #%d\n",ror);\r
561 }\r
562\r
563 OpGetFlags(0,0);\r
cc68a136 564 if (dir)\r
565 {\r
03c5768c 566 ot(" bic r9,r9,#0x30000000 ;@ clear CV\n");\r
cc68a136 567 ot(";@ Get carry bit from bit 0:\n");\r
568 if (usereg)\r
569 {\r
570 ot(" cmp %s,#32 ;@ rotating by 0?\n",pct);\r
571 ot(" tstne r0,#1 ;@ no, check bit 0\n");\r
572 }\r
573 else\r
574 ot(" tst r0,#1\n");\r
575 ot(" orrne r9,r9,#0x20000000\n");\r
cc68a136 576 }\r
577 ot("\n");\r
578\r
579 }\r
580 // --------------------------------------\r
581 \r
582 return 0;\r
583}\r
584\r
585// Emit a Asr/Lsr/Roxr/Ror opcode - 1110cccd xxuttnnn\r
586// (ccc=count, d=direction(r,l) xx=size extension, u=use reg for count, tt=type, nnn=register Dn)\r
587int OpAsr(int op)\r
588{\r
589 int ea=0,use=0;\r
590 int count=0,dir=0;\r
591 int size=0,usereg=0,type=0;\r
592\r
cc68a136 593 count =(op>>9)&7;\r
594 dir =(op>>8)&1;\r
595 size =(op>>6)&3;\r
596 if (size>=3) return 1; // use OpAsrEa()\r
597 usereg=(op>>5)&1;\r
598 type =(op>>3)&3;\r
599\r
600 if (usereg==0) count=((count-1)&7)+1; // because ccc=000 means 8\r
601\r
602 // Use the same opcode for target registers:\r
603 use=op&~0x0007;\r
604\r
03c5768c 605 // As long as count is not 8, use the same opcode for all shift counts:\r
cc68a136 606 if (usereg==0 && count!=8 && !(count==1&&type==2)) { use|=0x0e00; count=-1; }\r
607 if (usereg) { use&=~0x0e00; count=-1; } // Use same opcode for all Dn\r
608\r
609 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
610\r
ee5e024c 611 OpStart(op,ea,0,count<0); Cycles=size<2?6:8;\r
cc68a136 612\r
613 EaCalc(10,0x0007, ea,size,1);\r
614 EaRead(10, 0, ea,size,0x0007,1);\r
615\r
616 EmitAsr(op,type,dir,count, size,usereg);\r
617\r
618 EaWrite(10, 0, ea,size,0x0007,1);\r
619\r
0e11c502 620 opend_op_changes_cycles = (count<0);\r
621 OpEnd(ea,0);\r
cc68a136 622\r
623 return 0;\r
624}\r
625\r
626// Asr/Lsr/Roxr/Ror etc EA - 11100ttd 11eeeeee \r
627int OpAsrEa(int op)\r
628{\r
629 int use=0,type=0,dir=0,ea=0,size=1;\r
630\r
631 type=(op>>9)&3;\r
632 dir =(op>>8)&1;\r
633 ea = op&0x3f;\r
634\r
635 if (ea<0x10) return 1;\r
636 // See if we can do this opcode:\r
637 if (EaCanRead(ea,0)==0) return 1;\r
638 if (EaCanWrite(ea)==0) return 1;\r
639\r
85a36a57 640 use=OpBase(op,size);\r
cc68a136 641 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
642\r
a6785576 643 OpStart(op,ea); Cycles=6; // EmitAsr() will add 2\r
cc68a136 644\r
645 EaCalc (10,0x003f,ea,size,1);\r
646 EaRead (10, 0,ea,size,0x003f,1);\r
647\r
648 EmitAsr(op,type,dir,1,size,0);\r
649\r
650 EaWrite(10, 0,ea,size,0x003f,1);\r
651\r
cfb3dfa0 652 OpEnd(ea);\r
cc68a136 653 return 0;\r
654}\r
655\r
c008977e 656int OpTas(int op, int gen_special)\r
cc68a136 657{\r
658 int ea=0;\r
659 int use=0;\r
660\r
661 ea=op&0x003f;\r
662\r
663 // See if we can do this opcode:\r
664 if (EaCanWrite(ea)==0 || EaAn(ea)) return 1;\r
665\r
85a36a57 666 use=OpBase(op,0);\r
cc68a136 667 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
668\r
a6785576 669 if (!gen_special) OpStart(op,ea);\r
c008977e 670 else\r
671 ot("Op%.4x_%s\n", op, ms?"":":");\r
672\r
673 Cycles=4;\r
cc68a136 674 if(ea>=8) Cycles+=10;\r
675\r
676 EaCalc (10,0x003f,ea,0,1);\r
677 EaRead (10, 1,ea,0,0x003f,1);\r
678\r
679 ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");\r
680 OpGetFlags(0,0);\r
681 ot("\n");\r
682\r
683#if CYCLONE_FOR_GENESIS\r
684 // the original Sega hardware ignores write-back phase (to memory only)\r
c008977e 685 if (ea < 0x10 || gen_special) {\r
cc68a136 686#endif\r
687 ot(" orr r1,r1,#0x80000000 ;@ set bit7\n");\r
688\r
689 EaWrite(10, 1,ea,0,0x003f,1);\r
690#if CYCLONE_FOR_GENESIS\r
691 }\r
692#endif\r
693\r
cfb3dfa0 694 OpEnd(ea);\r
c008977e 695\r
a9a5a6e0 696#if (CYCLONE_FOR_GENESIS == 2)\r
c008977e 697 if (!gen_special && ea >= 0x10) {\r
698 OpTas(op, 1);\r
699 }\r
700#endif\r
701\r
cc68a136 702 return 0;\r
703}\r
704\r
fast MegaDrive/MegaCD/32X emulator