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adjustments for CPU core changes
[picodrive.git] / cpu / Cyclone / OpLogic.cpp
CommitLineData
cc68a136 1#include "app.h"\r
2\r
3// --------------------- Opcodes 0x0100+ ---------------------\r
4// Emit a Btst (Register) opcode 0000nnn1 ttaaaaaa\r
5int OpBtstReg(int op)\r
6{\r
7 int use=0;\r
8 int type=0,sea=0,tea=0;\r
9 int size=0;\r
10\r
11 type=(op>>6)&3; // Btst/Bchg/Bclr/Bset\r
12 // Get source and target EA\r
13 sea=(op>>9)&7;\r
14 tea=op&0x003f;\r
15 if (tea<0x10) size=2; // For registers, 32-bits\r
16\r
17 if ((tea&0x38)==0x08) return 1; // movep\r
18\r
19 // See if we can do this opcode:\r
20 if (EaCanRead(tea,0)==0) return 1;\r
21 if (type>0)\r
22 {\r
23 if (EaCanWrite(tea)==0) return 1;\r
24 }\r
25\r
85a36a57 26 use=OpBase(op,size);\r
cc68a136 27 use&=~0x0e00; // Use same handler for all registers\r
28 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
29\r
a6785576 30 OpStart(op,tea);\r
cc68a136 31\r
32 if(type==1||type==3) {\r
33 Cycles=8;\r
34 } else {\r
35 Cycles=type?8:4;\r
36 if(size>=2) Cycles+=2;\r
37 }\r
38\r
85a36a57 39 EaCalcReadNoSE(-1,10,sea,0,0x0e00);\r
b637c56a 40\r
85a36a57 41 EaCalcReadNoSE((type>0)?11:-1,0,tea,size,0x003f);\r
b637c56a 42\r
cc68a136 43 if (tea>=0x10)\r
b637c56a 44 ot(" and r10,r10,#7 ;@ mem - do mod 8\n"); // size always 0\r
45 else ot(" and r10,r10,#31 ;@ reg - do mod 32\n"); // size always 2\r
cc68a136 46 ot("\n");\r
47\r
cc68a136 48 ot(" mov r1,#1\n");\r
49 ot(" tst r0,r1,lsl r10 ;@ Do arithmetic\n");\r
50 ot(" bicne r9,r9,#0x40000000\n");\r
51 ot(" orreq r9,r9,#0x40000000 ;@ Get Z flag\n");\r
52 ot("\n");\r
53\r
54 if (type>0)\r
55 {\r
56 if (type==1) ot(" eor r1,r0,r1,lsl r10 ;@ Toggle bit\n");\r
57 if (type==2) ot(" bic r1,r0,r1,lsl r10 ;@ Clear bit\n");\r
58 if (type==3) ot(" orr r1,r0,r1,lsl r10 ;@ Set bit\n");\r
59 ot("\n");\r
b637c56a 60 EaWrite(11, 1,tea,size,0x003f,0,0);\r
cc68a136 61 }\r
cfb3dfa0 62 OpEnd(tea);\r
cc68a136 63\r
64 return 0;\r
65}\r
66\r
67// --------------------- Opcodes 0x0800+ ---------------------\r
68// Emit a Btst/Bchg/Bclr/Bset (Immediate) opcode 00001000 ttaaaaaa nn\r
69int OpBtstImm(int op)\r
70{\r
71 int type=0,sea=0,tea=0;\r
72 int use=0;\r
73 int size=0;\r
74\r
75 type=(op>>6)&3;\r
76 // Get source and target EA\r
77 sea= 0x003c;\r
78 tea=op&0x003f;\r
79 if (tea<0x10) size=2; // For registers, 32-bits\r
80\r
81 // See if we can do this opcode:\r
82 if (EaCanRead(tea,0)==0||EaAn(tea)||tea==0x3c) return 1;\r
83 if (type>0)\r
84 {\r
85 if (EaCanWrite(tea)==0) return 1;\r
86 }\r
87\r
85a36a57 88 use=OpBase(op,size);\r
cc68a136 89 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
90\r
cfb3dfa0 91 OpStart(op,sea,tea);\r
cc68a136 92\r
cc68a136 93 ot("\n");\r
85a36a57 94 EaCalcReadNoSE(-1,0,sea,0,0);\r
b637c56a 95 ot(" mov r10,#1\n");\r
cc68a136 96 ot(" bic r9,r9,#0x40000000 ;@ Blank Z flag\n");\r
97 if (tea>=0x10)\r
b637c56a 98 ot(" and r0,r0,#7 ;@ mem - do mod 8\n"); // size always 0\r
99 else ot(" and r0,r0,#0x1F ;@ reg - do mod 32\n"); // size always 2\r
cc68a136 100 ot(" mov r10,r10,lsl r0 ;@ Make bit mask\n");\r
101 ot("\n");\r
102\r
103 if(type==1||type==3) {\r
104 Cycles=12;\r
105 } else {\r
106 Cycles=type?12:8;\r
107 if(size>=2) Cycles+=2;\r
108 }\r
109\r
85a36a57 110 EaCalcReadNoSE((type>0)?11:-1,0,tea,size,0x003f);\r
cc68a136 111 ot(" tst r0,r10 ;@ Do arithmetic\n");\r
112 ot(" orreq r9,r9,#0x40000000 ;@ Get Z flag\n");\r
113 ot("\n");\r
114\r
115 if (type>0)\r
116 {\r
117 if (type==1) ot(" eor r1,r0,r10 ;@ Toggle bit\n");\r
118 if (type==2) ot(" bic r1,r0,r10 ;@ Clear bit\n");\r
119 if (type==3) ot(" orr r1,r0,r10 ;@ Set bit\n");\r
120 ot("\n");\r
b637c56a 121 EaWrite(11, 1,tea,size,0x003f,0,0);\r
cc68a136 122 }\r
123\r
cfb3dfa0 124 OpEnd(sea,tea);\r
cc68a136 125\r
126 return 0;\r
127}\r
128\r
129// --------------------- Opcodes 0x4000+ ---------------------\r
130int OpNeg(int op)\r
131{\r
132 // 01000tt0 xxeeeeee (tt=negx/clr/neg/not, xx=size, eeeeee=EA)\r
133 int type=0,size=0,ea=0,use=0;\r
134\r
135 type=(op>>9)&3;\r
136 ea =op&0x003f;\r
137 size=(op>>6)&3; if (size>=3) return 1;\r
138\r
139 // See if we can do this opcode:\r
140 if (EaCanRead (ea,size)==0||EaAn(ea)) return 1;\r
141 if (EaCanWrite(ea )==0) return 1;\r
142\r
85a36a57 143 use=OpBase(op,size);\r
cc68a136 144 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
145\r
a6785576 146 OpStart(op,ea); Cycles=size<2?4:6;\r
cc68a136 147 if(ea >= 0x10) {\r
148 Cycles*=2;\r
a9a5a6e0 149#if CYCLONE_FOR_GENESIS\r
cc68a136 150 // This is same as in Starscream core, CLR uses only 6 cycles for memory EAs.\r
151 // May be this is similar case as with TAS opcode, but this time the dummy\r
152 // read is ignored somehow? Without this hack Fatal Rewind hangs even in Gens.\r
153 if(type==1&&size<2) Cycles-=2;\r
154#endif\r
155 }\r
156\r
b637c56a 157 EaCalc (10,0x003f,ea,size,0,0);\r
cc68a136 158\r
85a36a57 159 if (type!=1) EaRead (10,0,ea,size,0x003f,0,0); // Don't need to read for 'clr' (or do we, for a dummy read?)\r
cc68a136 160 if (type==1) ot("\n");\r
161\r
162 if (type==0)\r
163 {\r
164 ot(";@ Negx:\n");\r
165 GetXBit(1);\r
b637c56a 166 if(size!=2) ot(" mov r0,r0,asl #%i\n",size?16:24);\r
cc68a136 167 ot(" rscs r1,r0,#0 ;@ do arithmetic\n");\r
168 ot(" orr r3,r9,#0xb0000000 ;@ for old Z\n");\r
169 OpGetFlags(1,1,0);\r
170 if(size!=2) {\r
a6785576 171 ot(" movs r1,r1,asr #%i\n",size?16:24);\r
cc68a136 172 ot(" orreq r9,r9,#0x40000000 ;@ possily missed Z\n");\r
a6785576 173 }\r
174 ot(" andeq r9,r9,r3 ;@ fix Z\n");\r
cc68a136 175 ot("\n");\r
176 }\r
177\r
178 if (type==1)\r
179 {\r
180 ot(";@ Clear:\n");\r
181 ot(" mov r1,#0\n");\r
182 ot(" mov r9,#0x40000000 ;@ NZCV=0100\n");\r
183 ot("\n");\r
184 }\r
185\r
186 if (type==2)\r
187 {\r
188 ot(";@ Neg:\n");\r
b637c56a 189 if(size!=2) ot(" mov r0,r0,asl #%i\n",size?16:24);\r
cc68a136 190 ot(" rsbs r1,r0,#0\n");\r
191 OpGetFlags(1,1);\r
192 if(size!=2) ot(" mov r1,r1,asr #%i\n",size?16:24);\r
193 ot("\n");\r
194 }\r
195\r
196 if (type==3)\r
197 {\r
198 ot(";@ Not:\n");\r
b637c56a 199 if(size!=2) {\r
200 ot(" mov r0,r0,asl #%i\n",size?16:24);\r
201 ot(" mvn r1,r0,asr #%i\n",size?16:24);\r
202 }\r
203 else\r
204 ot(" mvn r1,r0\n");\r
cc68a136 205 ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");\r
206 OpGetFlags(0,0);\r
207 ot("\n");\r
208 }\r
209\r
b637c56a 210 EaWrite(10, 1,ea,size,0x003f,0,0);\r
cc68a136 211\r
cfb3dfa0 212 OpEnd(ea);\r
cc68a136 213\r
214 return 0;\r
215}\r
216\r
217// --------------------- Opcodes 0x4840+ ---------------------\r
218// Swap, 01001000 01000nnn swap Dn\r
219int OpSwap(int op)\r
220{\r
221 int ea=0,use=0;\r
222\r
223 ea=op&7;\r
224 use=op&~0x0007; // Use same opcode for all An\r
225\r
226 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
227\r
228 OpStart(op); Cycles=4;\r
229\r
230 EaCalc (10,0x0007,ea,2,1);\r
231 EaRead (10, 0,ea,2,0x0007,1);\r
232\r
233 ot(" mov r1,r0,ror #16\n");\r
234 ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");\r
235 OpGetFlags(0,0);\r
236\r
237 EaWrite(10, 1,8,2,0x0007,1);\r
238\r
239 OpEnd();\r
240\r
241 return 0;\r
242}\r
243\r
244// --------------------- Opcodes 0x4a00+ ---------------------\r
245// Emit a Tst opcode, 01001010 xxeeeeee\r
246int OpTst(int op)\r
247{\r
248 int sea=0;\r
249 int size=0,use=0;\r
250\r
251 sea=op&0x003f;\r
252 size=(op>>6)&3; if (size>=3) return 1;\r
253\r
254 // See if we can do this opcode:\r
255 if (EaCanWrite(sea)==0||EaAn(sea)) return 1;\r
256\r
85a36a57 257 use=OpBase(op,size);\r
cc68a136 258 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
259\r
a6785576 260 OpStart(op,sea); Cycles=4;\r
cc68a136 261\r
262 EaCalc ( 0,0x003f,sea,size,1);\r
263 EaRead ( 0, 0,sea,size,0x003f,1);\r
264\r
265 ot(" adds r0,r0,#0 ;@ Defines NZ, clears CV\n");\r
266 ot(" mrs r9,cpsr ;@ r9=flags\n");\r
267 ot("\n");\r
268\r
cfb3dfa0 269 OpEnd(sea);\r
cc68a136 270 return 0;\r
271}\r
272\r
273// --------------------- Opcodes 0x4880+ ---------------------\r
274// Emit an Ext opcode, 01001000 1x000nnn\r
275int OpExt(int op)\r
276{\r
277 int ea=0;\r
278 int size=0,use=0;\r
279 int shift=0;\r
280\r
281 ea=op&0x0007;\r
282 size=(op>>6)&1;\r
283 shift=32-(8<<size);\r
284\r
85a36a57 285 use=OpBase(op,size);\r
cc68a136 286 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
287\r
288 OpStart(op); Cycles=4;\r
289\r
b637c56a 290 EaCalc (10,0x0007,ea,size+1,0,0);\r
291 EaRead (10, 0,ea,size+1,0x0007,0,0);\r
cc68a136 292\r
293 ot(" mov r0,r0,asl #%d\n",shift);\r
294 ot(" adds r0,r0,#0 ;@ Defines NZ, clears CV\n");\r
295 ot(" mrs r9,cpsr ;@ r9=flags\n");\r
296 ot(" mov r1,r0,asr #%d\n",shift);\r
297 ot("\n");\r
298\r
b637c56a 299 EaWrite(10, 1,ea,size+1,0x0007,0,0);\r
cc68a136 300\r
301 OpEnd();\r
302 return 0;\r
303}\r
304\r
305// --------------------- Opcodes 0x50c0+ ---------------------\r
306// Emit a Set cc opcode, 0101cccc 11eeeeee\r
307int OpSet(int op)\r
308{\r
309 int cc=0,ea=0;\r
310 int size=0,use=0;\r
311 char *cond[16]=\r
312 {\r
313 "al","", "hi","ls","cc","cs","ne","eq",\r
314 "vc","vs","pl","mi","ge","lt","gt","le"\r
315 };\r
316\r
317 cc=(op>>8)&15;\r
318 ea=op&0x003f;\r
319\r
320 if ((ea&0x38)==0x08) return 1; // dbra, not scc\r
321 \r
322 // See if we can do this opcode:\r
323 if (EaCanWrite(ea)==0) return 1;\r
324\r
85a36a57 325 use=OpBase(op,size);\r
cc68a136 326 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
327\r
a6785576 328 OpStart(op,ea); Cycles=8;\r
cc68a136 329 if (ea<8) Cycles=4;\r
330\r
b637c56a 331 if (cc)\r
332 ot(" mov r1,#0\n");\r
cc68a136 333\r
b637c56a 334 switch (cc)\r
cc68a136 335 {\r
b637c56a 336 case 0: // T\r
337 ot(" mvn r1,#0\n");\r
338 if (ea<8) Cycles+=2;\r
339 break;\r
340 case 1: // F\r
341 break;\r
342 case 2: // hi\r
3a5e6cf8 343 ot(" tst r9,#0x60000000 ;@ hi: !C && !Z\n");\r
b637c56a 344 ot(" mvneq r1,r1\n");\r
345 if (ea<8) ot(" subeq r5,r5,#2 ;@ Extra cycles\n");\r
346 break;\r
347 case 3: // ls\r
348 ot(" tst r9,#0x60000000 ;@ ls: C || Z\n");\r
349 ot(" mvnne r1,r1\n");\r
350 if (ea<8) ot(" subne r5,r5,#2 ;@ Extra cycles\n");\r
351 break;\r
352 default:\r
353 ot(";@ Is the condition true?\n");\r
354 ot(" msr cpsr_flg,r9 ;@ ARM flags = 68000 flags\n");\r
355 ot(" mvn%s r1,r1\n",cond[cc]);\r
356 if (ea<8) ot(" sub%s r5,r5,#2 ;@ Extra cycles\n",cond[cc]);\r
357 break;\r
cc68a136 358 }\r
359\r
cc68a136 360 ot("\n");\r
361\r
b637c56a 362 EaCalc (0,0x003f, ea,size,0,0);\r
363 EaWrite(0, 1, ea,size,0x003f,0,0);\r
cc68a136 364\r
cfb3dfa0 365 OpEnd(ea);\r
cc68a136 366 return 0;\r
367}\r
368\r
369// Emit a Asr/Lsr/Roxr/Ror opcode\r
370static int EmitAsr(int op,int type,int dir,int count,int size,int usereg)\r
371{\r
372 char pct[8]=""; // count\r
373 int shift=32-(8<<size);\r
374\r
375 if (count>=1) sprintf(pct,"#%d",count); // Fixed count\r
376\r
377 if (usereg)\r
378 {\r
379 ot(";@ Use Dn for count:\n");\r
85a36a57 380 ot(" and r2,r8,#0x0e00\n");\r
cc68a136 381 ot(" ldr r2,[r7,r2,lsr #7]\n");\r
382 ot(" and r2,r2,#63\n");\r
383 ot("\n");\r
384 strcpy(pct,"r2");\r
385 }\r
386 else if (count<0)\r
387 {\r
388 ot(" mov r2,r8,lsr #9 ;@ Get 'n'\n");\r
389 ot(" and r2,r2,#7\n\n"); strcpy(pct,"r2");\r
390 }\r
391\r
392 // Take 2*n cycles:\r
393 if (count<0) ot(" sub r5,r5,r2,asl #1 ;@ Take 2*n cycles\n\n");\r
394 else Cycles+=count<<1;\r
395\r
396 if (type<2)\r
397 {\r
398 // Asr/Lsr\r
399 if (dir==0 && size<2)\r
400 {\r
401 ot(";@ For shift right, use loworder bits for the operation:\n");\r
402 ot(" mov r0,r0,%s #%d\n",type?"lsr":"asr",32-(8<<size));\r
403 ot("\n");\r
404 }\r
405\r
1c88b865 406 if (type==0 && dir) ot(" adds r3,r0,#0 ;@ save old value for V flag calculation, also clear V\n");\r
cc68a136 407\r
408 ot(";@ Shift register:\n");\r
409 if (type==0) ot(" movs r0,r0,%s %s\n",dir?"asl":"asr",pct);\r
410 if (type==1) ot(" movs r0,r0,%s %s\n",dir?"lsl":"lsr",pct);\r
411\r
cc68a136 412 OpGetFlags(0,0);\r
413 if (usereg) { // store X only if count is not 0\r
414 ot(" cmp %s,#0 ;@ shifting by 0?\n",pct);\r
415 ot(" biceq r9,r9,#0x20000000 ;@ if so, clear carry\n");\r
85a36a57 416 ot(" strne r9,[r7,#0x4c] ;@ else Save X bit\n");\r
cc68a136 417 } else {\r
418 // count will never be 0 if we use immediate\r
85a36a57 419 ot(" str r9,[r7,#0x4c] ;@ Save X bit\n");\r
cc68a136 420 }\r
03c5768c 421 ot("\n");\r
422\r
423 if (dir==0 && size<2)\r
424 {\r
425 ot(";@ restore after right shift:\n");\r
426 ot(" movs r0,r0,lsl #%d\n",32-(8<<size));\r
427 if (type)\r
428 ot(" orrmi r9,r9,#0x80000000 ;@ Potentially missed N flag\n");\r
429 ot("\n");\r
430 }\r
cc68a136 431\r
432 if (type==0 && dir) {\r
433 ot(";@ calculate V flag (set if sign bit changes at anytime):\n");\r
434 ot(" mov r1,#0x80000000\n");\r
435 ot(" ands r3,r3,r1,asr %s\n", pct);\r
436 ot(" cmpne r3,r1,asr %s\n", pct);\r
1c88b865 437 ot(" eoreq r1,r0,r3\n"); // above check doesn't catch (-1)<<(32+), so we need this\r
438 ot(" tsteq r1,#0x80000000\n");\r
cc68a136 439 ot(" orrne r9,r9,#0x10000000\n");\r
03c5768c 440 ot("\n");\r
cc68a136 441 }\r
cc68a136 442 }\r
443\r
444 // --------------------------------------\r
445 if (type==2)\r
446 {\r
447 int wide=8<<size;\r
448\r
449 // Roxr\r
450 if(count == 1) {\r
451 if(dir==0) {\r
452 if(size!=2) {\r
a6785576 453 ot(" orr r0,r0,r0,lsr #%i\n", size?16:24);\r
454 ot(" bic r0,r0,#0x%x\n", 1<<(32-wide));\r
455 }\r
cc68a136 456 GetXBit(0);\r
457 ot(" movs r0,r0,rrx\n");\r
458 OpGetFlags(0,1);\r
459 } else {\r
85a36a57 460 ot(" ldr r3,[r7,#0x4c]\n");\r
cc68a136 461 ot(" movs r0,r0,lsl #1\n");\r
462 OpGetFlags(0,1);\r
85a36a57 463 ot(" tst r3,#0x20000000\n");\r
cc68a136 464 ot(" orrne r0,r0,#0x%x\n", 1<<(32-wide));\r
465 ot(" bicne r9,r9,#0x40000000 ;@ clear Z in case it got there\n");\r
466 }\r
467 ot(" bic r9,r9,#0x10000000 ;@ make suve V is clear\n");\r
468 return 0;\r
469 }\r
470\r
471 if (usereg)\r
472 {\r
03c5768c 473 if (size==2)\r
474 {\r
475 ot(" subs r2,r2,#33\n");\r
476 ot(" addmis r2,r2,#33 ;@ Now r2=0-%d\n",wide);\r
477 }\r
478 else\r
479 {\r
480 ot(";@ Reduce r2 until <0:\n");\r
481 ot("Reduce_%.4x%s\n",op,ms?"":":");\r
482 ot(" subs r2,r2,#%d\n",wide+1);\r
483 ot(" bpl Reduce_%.4x\n",op);\r
484 ot(" adds r2,r2,#%d ;@ Now r2=0-%d\n",wide+1,wide);\r
485 }\r
486 ot(" beq norotx_%.4x\n",op);\r
cc68a136 487 ot("\n");\r
488 }\r
489\r
490 if (usereg||count < 0)\r
491 {\r
492 if (dir) ot(" rsb r2,r2,#%d ;@ Reverse direction\n",wide+1);\r
493 }\r
494 else\r
495 {\r
496 if (dir) ot(" mov r2,#%d ;@ Reversed\n",wide+1-count);\r
497 else ot(" mov r2,#%d\n",count);\r
498 }\r
499\r
500 if (shift) ot(" mov r0,r0,lsr #%d ;@ Shift down\n",shift);\r
501\r
03c5768c 502 ot("\n");\r
503 ot(";@ First get X bit (middle):\n");\r
85a36a57 504 ot(" ldr r3,[r7,#0x4c]\n");\r
03c5768c 505 ot(" rsb r1,r2,#%d\n",wide);\r
85a36a57 506 ot(" and r3,r3,#0x20000000\n");\r
507 ot(" mov r3,r3,lsr #29\n");\r
03c5768c 508 ot(" mov r3,r3,lsl r1\n");\r
509\r
510 ot(";@ Rotate bits:\n");\r
511 ot(" orr r3,r3,r0,lsr r2 ;@ Orr right part\n");\r
512 ot(" rsbs r2,r2,#%d ;@ should also clear ARM V\n",wide+1);\r
513 ot(" orrs r0,r3,r0,lsl r2 ;@ Orr left part, set flags\n");\r
cc68a136 514 ot("\n");\r
515\r
516 if (shift) ot(" movs r0,r0,lsl #%d ;@ Shift up and get correct NC flags\n",shift);\r
517 OpGetFlags(0,!usereg);\r
cc68a136 518 if (usereg) { // store X only if count is not 0\r
85a36a57 519 ot(" str r9,[r7,#0x4c] ;@ if not 0, Save X bit\n");\r
cc68a136 520 ot(" b nozerox%.4x\n",op);\r
03c5768c 521 ot("norotx_%.4x%s\n",op,ms?"":":");\r
85a36a57 522 ot(" ldr r2,[r7,#0x4c]\n");\r
cc68a136 523 ot(" adds r0,r0,#0 ;@ Defines NZ, clears CV\n");\r
524 OpGetFlags(0,0);\r
85a36a57 525 ot(" and r2,r2,#0x20000000\n");\r
526 ot(" orr r9,r9,r2 ;@ C = old_X\n");\r
cc68a136 527 ot("nozerox%.4x%s\n",op,ms?"":":");\r
528 }\r
529\r
530 ot("\n");\r
531 }\r
532\r
533 // --------------------------------------\r
534 if (type==3)\r
535 {\r
536 // Ror\r
537 if (size<2)\r
538 {\r
539 ot(";@ Mirror value in whole 32 bits:\n");\r
540 if (size<=0) ot(" orr r0,r0,r0,lsr #8\n");\r
541 if (size<=1) ot(" orr r0,r0,r0,lsr #16\n");\r
542 ot("\n");\r
543 }\r
544\r
545 ot(";@ Rotate register:\n");\r
03c5768c 546 if (!dir) ot(" adds r0,r0,#0 ;@ first clear V and C\n"); // ARM does not clear C if rot count is 0\r
cc68a136 547 if (count<0)\r
548 {\r
03c5768c 549 if (dir) ot(" rsb %s,%s,#32\n",pct,pct);\r
cc68a136 550 ot(" movs r0,r0,ror %s\n",pct);\r
551 }\r
552 else\r
553 {\r
554 int ror=count;\r
555 if (dir) ror=32-ror;\r
556 if (ror&31) ot(" movs r0,r0,ror #%d\n",ror);\r
557 }\r
558\r
559 OpGetFlags(0,0);\r
cc68a136 560 if (dir)\r
561 {\r
03c5768c 562 ot(" bic r9,r9,#0x30000000 ;@ clear CV\n");\r
cc68a136 563 ot(";@ Get carry bit from bit 0:\n");\r
564 if (usereg)\r
565 {\r
566 ot(" cmp %s,#32 ;@ rotating by 0?\n",pct);\r
567 ot(" tstne r0,#1 ;@ no, check bit 0\n");\r
568 }\r
569 else\r
570 ot(" tst r0,#1\n");\r
571 ot(" orrne r9,r9,#0x20000000\n");\r
cc68a136 572 }\r
573 ot("\n");\r
574\r
575 }\r
576 // --------------------------------------\r
577 \r
578 return 0;\r
579}\r
580\r
581// Emit a Asr/Lsr/Roxr/Ror opcode - 1110cccd xxuttnnn\r
582// (ccc=count, d=direction(r,l) xx=size extension, u=use reg for count, tt=type, nnn=register Dn)\r
583int OpAsr(int op)\r
584{\r
585 int ea=0,use=0;\r
586 int count=0,dir=0;\r
587 int size=0,usereg=0,type=0;\r
588\r
589 ea=0;\r
590 count =(op>>9)&7;\r
591 dir =(op>>8)&1;\r
592 size =(op>>6)&3;\r
593 if (size>=3) return 1; // use OpAsrEa()\r
594 usereg=(op>>5)&1;\r
595 type =(op>>3)&3;\r
596\r
597 if (usereg==0) count=((count-1)&7)+1; // because ccc=000 means 8\r
598\r
599 // Use the same opcode for target registers:\r
600 use=op&~0x0007;\r
601\r
03c5768c 602 // As long as count is not 8, use the same opcode for all shift counts:\r
cc68a136 603 if (usereg==0 && count!=8 && !(count==1&&type==2)) { use|=0x0e00; count=-1; }\r
604 if (usereg) { use&=~0x0e00; count=-1; } // Use same opcode for all Dn\r
605\r
606 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
607\r
608 OpStart(op); Cycles=size<2?6:8;\r
609\r
610 EaCalc(10,0x0007, ea,size,1);\r
611 EaRead(10, 0, ea,size,0x0007,1);\r
612\r
613 EmitAsr(op,type,dir,count, size,usereg);\r
614\r
615 EaWrite(10, 0, ea,size,0x0007,1);\r
616\r
617 OpEnd();\r
618\r
619 return 0;\r
620}\r
621\r
622// Asr/Lsr/Roxr/Ror etc EA - 11100ttd 11eeeeee \r
623int OpAsrEa(int op)\r
624{\r
625 int use=0,type=0,dir=0,ea=0,size=1;\r
626\r
627 type=(op>>9)&3;\r
628 dir =(op>>8)&1;\r
629 ea = op&0x3f;\r
630\r
631 if (ea<0x10) return 1;\r
632 // See if we can do this opcode:\r
633 if (EaCanRead(ea,0)==0) return 1;\r
634 if (EaCanWrite(ea)==0) return 1;\r
635\r
85a36a57 636 use=OpBase(op,size);\r
cc68a136 637 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
638\r
a6785576 639 OpStart(op,ea); Cycles=6; // EmitAsr() will add 2\r
cc68a136 640\r
641 EaCalc (10,0x003f,ea,size,1);\r
642 EaRead (10, 0,ea,size,0x003f,1);\r
643\r
644 EmitAsr(op,type,dir,1,size,0);\r
645\r
646 EaWrite(10, 0,ea,size,0x003f,1);\r
647\r
cfb3dfa0 648 OpEnd(ea);\r
cc68a136 649 return 0;\r
650}\r
651\r
c008977e 652int OpTas(int op, int gen_special)\r
cc68a136 653{\r
654 int ea=0;\r
655 int use=0;\r
656\r
657 ea=op&0x003f;\r
658\r
659 // See if we can do this opcode:\r
660 if (EaCanWrite(ea)==0 || EaAn(ea)) return 1;\r
661\r
85a36a57 662 use=OpBase(op,0);\r
cc68a136 663 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
664\r
a6785576 665 if (!gen_special) OpStart(op,ea);\r
c008977e 666 else\r
667 ot("Op%.4x_%s\n", op, ms?"":":");\r
668\r
669 Cycles=4;\r
cc68a136 670 if(ea>=8) Cycles+=10;\r
671\r
672 EaCalc (10,0x003f,ea,0,1);\r
673 EaRead (10, 1,ea,0,0x003f,1);\r
674\r
675 ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");\r
676 OpGetFlags(0,0);\r
677 ot("\n");\r
678\r
679#if CYCLONE_FOR_GENESIS\r
680 // the original Sega hardware ignores write-back phase (to memory only)\r
c008977e 681 if (ea < 0x10 || gen_special) {\r
cc68a136 682#endif\r
683 ot(" orr r1,r1,#0x80000000 ;@ set bit7\n");\r
684\r
685 EaWrite(10, 1,ea,0,0x003f,1);\r
686#if CYCLONE_FOR_GENESIS\r
687 }\r
688#endif\r
689\r
cfb3dfa0 690 OpEnd(ea);\r
c008977e 691\r
a9a5a6e0 692#if (CYCLONE_FOR_GENESIS == 2)\r
c008977e 693 if (!gen_special && ea >= 0x10) {\r
694 OpTas(op, 1);\r
695 }\r
696#endif\r
697\r
cc68a136 698 return 0;\r
699}\r
700\r
fast MegaDrive/MegaCD/32X emulator