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some optimizations
[picodrive.git] / cpu / Cyclone / OpLogic.cpp
CommitLineData
cc68a136 1#include "app.h"\r
2\r
3// --------------------- Opcodes 0x0100+ ---------------------\r
4// Emit a Btst (Register) opcode 0000nnn1 ttaaaaaa\r
5int OpBtstReg(int op)\r
6{\r
7 int use=0;\r
8 int type=0,sea=0,tea=0;\r
9 int size=0;\r
10\r
11 type=(op>>6)&3; // Btst/Bchg/Bclr/Bset\r
12 // Get source and target EA\r
13 sea=(op>>9)&7;\r
14 tea=op&0x003f;\r
15 if (tea<0x10) size=2; // For registers, 32-bits\r
16\r
17 if ((tea&0x38)==0x08) return 1; // movep\r
18\r
19 // See if we can do this opcode:\r
20 if (EaCanRead(tea,0)==0) return 1;\r
21 if (type>0)\r
22 {\r
23 if (EaCanWrite(tea)==0) return 1;\r
24 }\r
25\r
26 use=OpBase(op);\r
27 use&=~0x0e00; // Use same handler for all registers\r
28 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
29\r
a6785576 30 OpStart(op,tea);\r
cc68a136 31\r
32 if(type==1||type==3) {\r
33 Cycles=8;\r
34 } else {\r
35 Cycles=type?8:4;\r
36 if(size>=2) Cycles+=2;\r
37 }\r
38\r
b637c56a 39 EaCalc (10,0x0e00,sea,0,0,0);\r
40 EaRead (10, 10,sea,0,0x0e00,0,0);\r
41\r
42 EaCalc ( 0,0x003f,tea,size,0,0);\r
43 if (type>0)\r
44 ot(" mov r11,r0\n");\r
45 EaRead ( 0, 0,tea,size,0x003f,0,0);\r
46\r
cc68a136 47 if (tea>=0x10)\r
b637c56a 48 ot(" and r10,r10,#7 ;@ mem - do mod 8\n"); // size always 0\r
49 else ot(" and r10,r10,#31 ;@ reg - do mod 32\n"); // size always 2\r
cc68a136 50 ot("\n");\r
51\r
cc68a136 52 ot(" mov r1,#1\n");\r
53 ot(" tst r0,r1,lsl r10 ;@ Do arithmetic\n");\r
54 ot(" bicne r9,r9,#0x40000000\n");\r
55 ot(" orreq r9,r9,#0x40000000 ;@ Get Z flag\n");\r
56 ot("\n");\r
57\r
58 if (type>0)\r
59 {\r
60 if (type==1) ot(" eor r1,r0,r1,lsl r10 ;@ Toggle bit\n");\r
61 if (type==2) ot(" bic r1,r0,r1,lsl r10 ;@ Clear bit\n");\r
62 if (type==3) ot(" orr r1,r0,r1,lsl r10 ;@ Set bit\n");\r
63 ot("\n");\r
b637c56a 64 EaWrite(11, 1,tea,size,0x003f,0,0);\r
cc68a136 65 }\r
cfb3dfa0 66 OpEnd(tea);\r
cc68a136 67\r
68 return 0;\r
69}\r
70\r
71// --------------------- Opcodes 0x0800+ ---------------------\r
72// Emit a Btst/Bchg/Bclr/Bset (Immediate) opcode 00001000 ttaaaaaa nn\r
73int OpBtstImm(int op)\r
74{\r
75 int type=0,sea=0,tea=0;\r
76 int use=0;\r
77 int size=0;\r
78\r
79 type=(op>>6)&3;\r
80 // Get source and target EA\r
81 sea= 0x003c;\r
82 tea=op&0x003f;\r
83 if (tea<0x10) size=2; // For registers, 32-bits\r
84\r
85 // See if we can do this opcode:\r
86 if (EaCanRead(tea,0)==0||EaAn(tea)||tea==0x3c) return 1;\r
87 if (type>0)\r
88 {\r
89 if (EaCanWrite(tea)==0) return 1;\r
90 }\r
91\r
92 use=OpBase(op);\r
93 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
94\r
cfb3dfa0 95 OpStart(op,sea,tea);\r
cc68a136 96\r
cc68a136 97 ot("\n");\r
b637c56a 98 EaCalc ( 0,0x0000,sea,0,0,0);\r
99 EaRead ( 0, 0,sea,0,0,0,0);\r
100 ot(" mov r10,#1\n");\r
cc68a136 101 ot(" bic r9,r9,#0x40000000 ;@ Blank Z flag\n");\r
102 if (tea>=0x10)\r
b637c56a 103 ot(" and r0,r0,#7 ;@ mem - do mod 8\n"); // size always 0\r
104 else ot(" and r0,r0,#0x1F ;@ reg - do mod 32\n"); // size always 2\r
cc68a136 105 ot(" mov r10,r10,lsl r0 ;@ Make bit mask\n");\r
106 ot("\n");\r
107\r
108 if(type==1||type==3) {\r
109 Cycles=12;\r
110 } else {\r
111 Cycles=type?12:8;\r
112 if(size>=2) Cycles+=2;\r
113 }\r
114\r
b637c56a 115 EaCalc (11,0x003f,tea,size,0,0);\r
116 EaRead (11, 0,tea,size,0x003f,0,0);\r
cc68a136 117 ot(" tst r0,r10 ;@ Do arithmetic\n");\r
118 ot(" orreq r9,r9,#0x40000000 ;@ Get Z flag\n");\r
119 ot("\n");\r
120\r
121 if (type>0)\r
122 {\r
123 if (type==1) ot(" eor r1,r0,r10 ;@ Toggle bit\n");\r
124 if (type==2) ot(" bic r1,r0,r10 ;@ Clear bit\n");\r
125 if (type==3) ot(" orr r1,r0,r10 ;@ Set bit\n");\r
126 ot("\n");\r
b637c56a 127 EaWrite(11, 1,tea,size,0x003f,0,0);\r
cc68a136 128 }\r
129\r
cfb3dfa0 130 OpEnd(sea,tea);\r
cc68a136 131\r
132 return 0;\r
133}\r
134\r
135// --------------------- Opcodes 0x4000+ ---------------------\r
136int OpNeg(int op)\r
137{\r
138 // 01000tt0 xxeeeeee (tt=negx/clr/neg/not, xx=size, eeeeee=EA)\r
139 int type=0,size=0,ea=0,use=0;\r
140\r
141 type=(op>>9)&3;\r
142 ea =op&0x003f;\r
143 size=(op>>6)&3; if (size>=3) return 1;\r
144\r
145 // See if we can do this opcode:\r
146 if (EaCanRead (ea,size)==0||EaAn(ea)) return 1;\r
147 if (EaCanWrite(ea )==0) return 1;\r
148\r
149 use=OpBase(op);\r
150 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
151\r
a6785576 152 OpStart(op,ea); Cycles=size<2?4:6;\r
cc68a136 153 if(ea >= 0x10) {\r
154 Cycles*=2;\r
a9a5a6e0 155#if CYCLONE_FOR_GENESIS\r
cc68a136 156 // This is same as in Starscream core, CLR uses only 6 cycles for memory EAs.\r
157 // May be this is similar case as with TAS opcode, but this time the dummy\r
158 // read is ignored somehow? Without this hack Fatal Rewind hangs even in Gens.\r
159 if(type==1&&size<2) Cycles-=2;\r
160#endif\r
161 }\r
162\r
b637c56a 163 EaCalc (10,0x003f,ea,size,0,0);\r
cc68a136 164\r
b637c56a 165 if (type!=1) EaRead (10,0,ea,size,0x003f,0,0); // Don't need to read for 'clr' (or do we, for dummy read?)\r
cc68a136 166 if (type==1) ot("\n");\r
167\r
168 if (type==0)\r
169 {\r
170 ot(";@ Negx:\n");\r
171 GetXBit(1);\r
b637c56a 172 if(size!=2) ot(" mov r0,r0,asl #%i\n",size?16:24);\r
cc68a136 173 ot(" rscs r1,r0,#0 ;@ do arithmetic\n");\r
174 ot(" orr r3,r9,#0xb0000000 ;@ for old Z\n");\r
175 OpGetFlags(1,1,0);\r
176 if(size!=2) {\r
a6785576 177 ot(" movs r1,r1,asr #%i\n",size?16:24);\r
cc68a136 178 ot(" orreq r9,r9,#0x40000000 ;@ possily missed Z\n");\r
a6785576 179 }\r
180 ot(" andeq r9,r9,r3 ;@ fix Z\n");\r
cc68a136 181 ot("\n");\r
182 }\r
183\r
184 if (type==1)\r
185 {\r
186 ot(";@ Clear:\n");\r
187 ot(" mov r1,#0\n");\r
188 ot(" mov r9,#0x40000000 ;@ NZCV=0100\n");\r
189 ot("\n");\r
190 }\r
191\r
192 if (type==2)\r
193 {\r
194 ot(";@ Neg:\n");\r
b637c56a 195 if(size!=2) ot(" mov r0,r0,asl #%i\n",size?16:24);\r
cc68a136 196 ot(" rsbs r1,r0,#0\n");\r
197 OpGetFlags(1,1);\r
198 if(size!=2) ot(" mov r1,r1,asr #%i\n",size?16:24);\r
199 ot("\n");\r
200 }\r
201\r
202 if (type==3)\r
203 {\r
204 ot(";@ Not:\n");\r
b637c56a 205 if(size!=2) {\r
206 ot(" mov r0,r0,asl #%i\n",size?16:24);\r
207 ot(" mvn r1,r0,asr #%i\n",size?16:24);\r
208 }\r
209 else\r
210 ot(" mvn r1,r0\n");\r
cc68a136 211 ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");\r
212 OpGetFlags(0,0);\r
213 ot("\n");\r
214 }\r
215\r
b637c56a 216 EaWrite(10, 1,ea,size,0x003f,0,0);\r
cc68a136 217\r
cfb3dfa0 218 OpEnd(ea);\r
cc68a136 219\r
220 return 0;\r
221}\r
222\r
223// --------------------- Opcodes 0x4840+ ---------------------\r
224// Swap, 01001000 01000nnn swap Dn\r
225int OpSwap(int op)\r
226{\r
227 int ea=0,use=0;\r
228\r
229 ea=op&7;\r
230 use=op&~0x0007; // Use same opcode for all An\r
231\r
232 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
233\r
234 OpStart(op); Cycles=4;\r
235\r
236 EaCalc (10,0x0007,ea,2,1);\r
237 EaRead (10, 0,ea,2,0x0007,1);\r
238\r
239 ot(" mov r1,r0,ror #16\n");\r
240 ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");\r
241 OpGetFlags(0,0);\r
242\r
243 EaWrite(10, 1,8,2,0x0007,1);\r
244\r
245 OpEnd();\r
246\r
247 return 0;\r
248}\r
249\r
250// --------------------- Opcodes 0x4a00+ ---------------------\r
251// Emit a Tst opcode, 01001010 xxeeeeee\r
252int OpTst(int op)\r
253{\r
254 int sea=0;\r
255 int size=0,use=0;\r
256\r
257 sea=op&0x003f;\r
258 size=(op>>6)&3; if (size>=3) return 1;\r
259\r
260 // See if we can do this opcode:\r
261 if (EaCanWrite(sea)==0||EaAn(sea)) return 1;\r
262\r
263 use=OpBase(op);\r
264 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
265\r
a6785576 266 OpStart(op,sea); Cycles=4;\r
cc68a136 267\r
268 EaCalc ( 0,0x003f,sea,size,1);\r
269 EaRead ( 0, 0,sea,size,0x003f,1);\r
270\r
271 ot(" adds r0,r0,#0 ;@ Defines NZ, clears CV\n");\r
272 ot(" mrs r9,cpsr ;@ r9=flags\n");\r
273 ot("\n");\r
274\r
cfb3dfa0 275 OpEnd(sea);\r
cc68a136 276 return 0;\r
277}\r
278\r
279// --------------------- Opcodes 0x4880+ ---------------------\r
280// Emit an Ext opcode, 01001000 1x000nnn\r
281int OpExt(int op)\r
282{\r
283 int ea=0;\r
284 int size=0,use=0;\r
285 int shift=0;\r
286\r
287 ea=op&0x0007;\r
288 size=(op>>6)&1;\r
289 shift=32-(8<<size);\r
290\r
291 use=OpBase(op);\r
292 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
293\r
294 OpStart(op); Cycles=4;\r
295\r
b637c56a 296 EaCalc (10,0x0007,ea,size+1,0,0);\r
297 EaRead (10, 0,ea,size+1,0x0007,0,0);\r
cc68a136 298\r
299 ot(" mov r0,r0,asl #%d\n",shift);\r
300 ot(" adds r0,r0,#0 ;@ Defines NZ, clears CV\n");\r
301 ot(" mrs r9,cpsr ;@ r9=flags\n");\r
302 ot(" mov r1,r0,asr #%d\n",shift);\r
303 ot("\n");\r
304\r
b637c56a 305 EaWrite(10, 1,ea,size+1,0x0007,0,0);\r
cc68a136 306\r
307 OpEnd();\r
308 return 0;\r
309}\r
310\r
311// --------------------- Opcodes 0x50c0+ ---------------------\r
312// Emit a Set cc opcode, 0101cccc 11eeeeee\r
313int OpSet(int op)\r
314{\r
315 int cc=0,ea=0;\r
316 int size=0,use=0;\r
317 char *cond[16]=\r
318 {\r
319 "al","", "hi","ls","cc","cs","ne","eq",\r
320 "vc","vs","pl","mi","ge","lt","gt","le"\r
321 };\r
322\r
323 cc=(op>>8)&15;\r
324 ea=op&0x003f;\r
325\r
326 if ((ea&0x38)==0x08) return 1; // dbra, not scc\r
327 \r
328 // See if we can do this opcode:\r
329 if (EaCanWrite(ea)==0) return 1;\r
330\r
331 use=OpBase(op);\r
332 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
333\r
a6785576 334 OpStart(op,ea); Cycles=8;\r
cc68a136 335 if (ea<8) Cycles=4;\r
336\r
b637c56a 337 if (cc)\r
338 ot(" mov r1,#0\n");\r
cc68a136 339\r
b637c56a 340 switch (cc)\r
cc68a136 341 {\r
b637c56a 342 case 0: // T\r
343 ot(" mvn r1,#0\n");\r
344 if (ea<8) Cycles+=2;\r
345 break;\r
346 case 1: // F\r
347 break;\r
348 case 2: // hi\r
349 ot(" ands r0,r9,#0x60000000 ;@ hi: !C && !Z\n");\r
350 ot(" mvneq r1,r1\n");\r
351 if (ea<8) ot(" subeq r5,r5,#2 ;@ Extra cycles\n");\r
352 break;\r
353 case 3: // ls\r
354 ot(" tst r9,#0x60000000 ;@ ls: C || Z\n");\r
355 ot(" mvnne r1,r1\n");\r
356 if (ea<8) ot(" subne r5,r5,#2 ;@ Extra cycles\n");\r
357 break;\r
358 default:\r
359 ot(";@ Is the condition true?\n");\r
360 ot(" msr cpsr_flg,r9 ;@ ARM flags = 68000 flags\n");\r
361 ot(" mvn%s r1,r1\n",cond[cc]);\r
362 if (ea<8) ot(" sub%s r5,r5,#2 ;@ Extra cycles\n",cond[cc]);\r
363 break;\r
cc68a136 364 }\r
365\r
cc68a136 366 ot("\n");\r
367\r
b637c56a 368 EaCalc (0,0x003f, ea,size,0,0);\r
369 EaWrite(0, 1, ea,size,0x003f,0,0);\r
cc68a136 370\r
cfb3dfa0 371 OpEnd(ea);\r
cc68a136 372 return 0;\r
373}\r
374\r
375// Emit a Asr/Lsr/Roxr/Ror opcode\r
376static int EmitAsr(int op,int type,int dir,int count,int size,int usereg)\r
377{\r
378 char pct[8]=""; // count\r
379 int shift=32-(8<<size);\r
380\r
381 if (count>=1) sprintf(pct,"#%d",count); // Fixed count\r
382\r
383 if (usereg)\r
384 {\r
385 ot(";@ Use Dn for count:\n");\r
386 ot(" and r2,r8,#7<<9\n");\r
387 ot(" ldr r2,[r7,r2,lsr #7]\n");\r
388 ot(" and r2,r2,#63\n");\r
389 ot("\n");\r
390 strcpy(pct,"r2");\r
391 }\r
392 else if (count<0)\r
393 {\r
394 ot(" mov r2,r8,lsr #9 ;@ Get 'n'\n");\r
395 ot(" and r2,r2,#7\n\n"); strcpy(pct,"r2");\r
396 }\r
397\r
398 // Take 2*n cycles:\r
399 if (count<0) ot(" sub r5,r5,r2,asl #1 ;@ Take 2*n cycles\n\n");\r
400 else Cycles+=count<<1;\r
401\r
402 if (type<2)\r
403 {\r
404 // Asr/Lsr\r
405 if (dir==0 && size<2)\r
406 {\r
407 ot(";@ For shift right, use loworder bits for the operation:\n");\r
408 ot(" mov r0,r0,%s #%d\n",type?"lsr":"asr",32-(8<<size));\r
409 ot("\n");\r
410 }\r
411\r
412 if (type==0 && dir) ot(" mov r3,r0 ;@ save old value for V flag calculation\n");\r
413\r
414 ot(";@ Shift register:\n");\r
415 if (type==0) ot(" movs r0,r0,%s %s\n",dir?"asl":"asr",pct);\r
416 if (type==1) ot(" movs r0,r0,%s %s\n",dir?"lsl":"lsr",pct);\r
417\r
418 if (dir==0 && size<2)\r
419 {\r
420 ot(";@ restore after right shift:\n");\r
421 ot(" mov r0,r0,lsl #%d\n",32-(8<<size));\r
422 ot("\n");\r
423 }\r
424\r
425 OpGetFlags(0,0);\r
426 if (usereg) { // store X only if count is not 0\r
427 ot(" cmp %s,#0 ;@ shifting by 0?\n",pct);\r
428 ot(" biceq r9,r9,#0x20000000 ;@ if so, clear carry\n");\r
429 ot(" movne r1,r9,lsr #28\n");\r
430 ot(" strneb r1,[r7,#0x45] ;@ else Save X bit\n");\r
431 } else {\r
432 // count will never be 0 if we use immediate\r
433 ot(" mov r1,r9,lsr #28\n");\r
434 ot(" strb r1,[r7,#0x45] ;@ Save X bit\n");\r
435 }\r
436\r
437 if (type==0 && dir) {\r
438 ot(";@ calculate V flag (set if sign bit changes at anytime):\n");\r
439 ot(" mov r1,#0x80000000\n");\r
440 ot(" ands r3,r3,r1,asr %s\n", pct);\r
441 ot(" cmpne r3,r1,asr %s\n", pct);\r
442 ot(" biceq r9,r9,#0x10000000\n");\r
443 ot(" orrne r9,r9,#0x10000000\n");\r
444 }\r
445\r
446 ot("\n");\r
447 }\r
448\r
449 // --------------------------------------\r
450 if (type==2)\r
451 {\r
452 int wide=8<<size;\r
453\r
454 // Roxr\r
455 if(count == 1) {\r
456 if(dir==0) {\r
457 if(size!=2) {\r
a6785576 458 ot(" orr r0,r0,r0,lsr #%i\n", size?16:24);\r
459 ot(" bic r0,r0,#0x%x\n", 1<<(32-wide));\r
460 }\r
cc68a136 461 GetXBit(0);\r
462 ot(" movs r0,r0,rrx\n");\r
463 OpGetFlags(0,1);\r
464 } else {\r
465 ot(" ldrb r3,[r7,#0x45]\n");\r
466 ot(" movs r0,r0,lsl #1\n");\r
467 OpGetFlags(0,1);\r
468 ot(" tst r3,#2\n");\r
469 ot(" orrne r0,r0,#0x%x\n", 1<<(32-wide));\r
470 ot(" bicne r9,r9,#0x40000000 ;@ clear Z in case it got there\n");\r
471 }\r
472 ot(" bic r9,r9,#0x10000000 ;@ make suve V is clear\n");\r
473 return 0;\r
474 }\r
475\r
476 if (usereg)\r
477 {\r
478 ot(";@ Reduce r2 until <0:\n");\r
479 ot("Reduce_%.4x%s\n",op,ms?"":":");\r
480 ot(" subs r2,r2,#%d\n",wide+1);\r
481 ot(" bpl Reduce_%.4x\n",op);\r
482 ot(" adds r2,r2,#%d ;@ Now r2=0-%d\n",wide+1,wide);\r
483 ot(" beq norotx%.4x\n",op);\r
484 ot("\n");\r
485 }\r
486\r
487 if (usereg||count < 0)\r
488 {\r
489 if (dir) ot(" rsb r2,r2,#%d ;@ Reverse direction\n",wide+1);\r
490 }\r
491 else\r
492 {\r
493 if (dir) ot(" mov r2,#%d ;@ Reversed\n",wide+1-count);\r
494 else ot(" mov r2,#%d\n",count);\r
495 }\r
496\r
497 if (shift) ot(" mov r0,r0,lsr #%d ;@ Shift down\n",shift);\r
498\r
499 ot(";@ Rotate bits:\n");\r
500 ot(" mov r3,r0,lsr r2 ;@ Get right part\n");\r
501 ot(" rsbs r2,r2,#%d ;@ should also clear ARM V\n",wide+1);\r
502 ot(" movs r0,r0,lsl r2 ;@ Get left part\n");\r
503 ot(" orr r0,r3,r0 ;@ r0=Rotated value\n");\r
504\r
505 ot(";@ Insert X bit into r2-1:\n");\r
506 ot(" ldrb r3,[r7,#0x45]\n");\r
507 ot(" sub r2,r2,#1\n");\r
508 ot(" and r3,r3,#2\n");\r
509 ot(" mov r3,r3,lsr #1\n");\r
510 ot(" orr r0,r0,r3,lsl r2\n");\r
511 ot("\n");\r
512\r
513 if (shift) ot(" movs r0,r0,lsl #%d ;@ Shift up and get correct NC flags\n",shift);\r
514 OpGetFlags(0,!usereg);\r
515 if (!shift) {\r
516 ot(" tst r0,r0\n");\r
517 ot(" bicne r9,r9,#0x40000000 ;@ make sure we didn't mess Z\n");\r
518 }\r
519 if (usereg) { // store X only if count is not 0\r
520 ot(" mov r2,r9,lsr #28\n");\r
521 ot(" strb r2,[r7,#0x45] ;@ if not 0, Save X bit\n");\r
522 ot(" b nozerox%.4x\n",op);\r
523 ot("norotx%.4x%s\n",op,ms?"":":");\r
524 ot(" ldrb r2,[r7,#0x45]\n");\r
525 ot(" adds r0,r0,#0 ;@ Defines NZ, clears CV\n");\r
526 OpGetFlags(0,0);\r
527 ot(" and r2,r2,#2\n");\r
528 ot(" orr r9,r9,r2,lsl #28 ;@ C = old_X\n");\r
529 ot("nozerox%.4x%s\n",op,ms?"":":");\r
530 }\r
531\r
532 ot("\n");\r
533 }\r
534\r
535 // --------------------------------------\r
536 if (type==3)\r
537 {\r
538 // Ror\r
539 if (size<2)\r
540 {\r
541 ot(";@ Mirror value in whole 32 bits:\n");\r
542 if (size<=0) ot(" orr r0,r0,r0,lsr #8\n");\r
543 if (size<=1) ot(" orr r0,r0,r0,lsr #16\n");\r
544 ot("\n");\r
545 }\r
546\r
547 ot(";@ Rotate register:\n");\r
548 if (count<0)\r
549 {\r
550 if (dir) ot(" rsbs %s,%s,#32\n",pct,pct);\r
551 ot(" movs r0,r0,ror %s\n",pct);\r
552 }\r
553 else\r
554 {\r
555 int ror=count;\r
556 if (dir) ror=32-ror;\r
557 if (ror&31) ot(" movs r0,r0,ror #%d\n",ror);\r
558 }\r
559\r
560 OpGetFlags(0,0);\r
561 if (!dir) ot(" bic r9,r9,#0x10000000 ;@ make suve V is clear\n");\r
562 if (dir)\r
563 {\r
564 ot(";@ Get carry bit from bit 0:\n");\r
565 if (usereg)\r
566 {\r
567 ot(" cmp %s,#32 ;@ rotating by 0?\n",pct);\r
568 ot(" tstne r0,#1 ;@ no, check bit 0\n");\r
569 }\r
570 else\r
571 ot(" tst r0,#1\n");\r
572 ot(" orrne r9,r9,#0x20000000\n");\r
573 ot(" biceq r9,r9,#0x20000000\n");\r
574 }\r
575 else if (usereg)\r
576 {\r
577 // if we rotate something by 0, ARM doesn't clear C\r
578 // so we need to detect that\r
579 ot(" cmp %s,#0\n",pct);\r
580 ot(" biceq r9,r9,#0x20000000\n");\r
581 }\r
582 ot("\n");\r
583\r
584 }\r
585 // --------------------------------------\r
586 \r
587 return 0;\r
588}\r
589\r
590// Emit a Asr/Lsr/Roxr/Ror opcode - 1110cccd xxuttnnn\r
591// (ccc=count, d=direction(r,l) xx=size extension, u=use reg for count, tt=type, nnn=register Dn)\r
592int OpAsr(int op)\r
593{\r
594 int ea=0,use=0;\r
595 int count=0,dir=0;\r
596 int size=0,usereg=0,type=0;\r
597\r
598 ea=0;\r
599 count =(op>>9)&7;\r
600 dir =(op>>8)&1;\r
601 size =(op>>6)&3;\r
602 if (size>=3) return 1; // use OpAsrEa()\r
603 usereg=(op>>5)&1;\r
604 type =(op>>3)&3;\r
605\r
606 if (usereg==0) count=((count-1)&7)+1; // because ccc=000 means 8\r
607\r
608 // Use the same opcode for target registers:\r
609 use=op&~0x0007;\r
610\r
611 // As long as count is not 8, use the same opcode for all shift counts::\r
612 if (usereg==0 && count!=8 && !(count==1&&type==2)) { use|=0x0e00; count=-1; }\r
613 if (usereg) { use&=~0x0e00; count=-1; } // Use same opcode for all Dn\r
614\r
615 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
616\r
617 OpStart(op); Cycles=size<2?6:8;\r
618\r
619 EaCalc(10,0x0007, ea,size,1);\r
620 EaRead(10, 0, ea,size,0x0007,1);\r
621\r
622 EmitAsr(op,type,dir,count, size,usereg);\r
623\r
624 EaWrite(10, 0, ea,size,0x0007,1);\r
625\r
626 OpEnd();\r
627\r
628 return 0;\r
629}\r
630\r
631// Asr/Lsr/Roxr/Ror etc EA - 11100ttd 11eeeeee \r
632int OpAsrEa(int op)\r
633{\r
634 int use=0,type=0,dir=0,ea=0,size=1;\r
635\r
636 type=(op>>9)&3;\r
637 dir =(op>>8)&1;\r
638 ea = op&0x3f;\r
639\r
640 if (ea<0x10) return 1;\r
641 // See if we can do this opcode:\r
642 if (EaCanRead(ea,0)==0) return 1;\r
643 if (EaCanWrite(ea)==0) return 1;\r
644\r
645 use=OpBase(op);\r
646 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
647\r
a6785576 648 OpStart(op,ea); Cycles=6; // EmitAsr() will add 2\r
cc68a136 649\r
650 EaCalc (10,0x003f,ea,size,1);\r
651 EaRead (10, 0,ea,size,0x003f,1);\r
652\r
653 EmitAsr(op,type,dir,1,size,0);\r
654\r
655 EaWrite(10, 0,ea,size,0x003f,1);\r
656\r
cfb3dfa0 657 OpEnd(ea);\r
cc68a136 658 return 0;\r
659}\r
660\r
c008977e 661int OpTas(int op, int gen_special)\r
cc68a136 662{\r
663 int ea=0;\r
664 int use=0;\r
665\r
666 ea=op&0x003f;\r
667\r
668 // See if we can do this opcode:\r
669 if (EaCanWrite(ea)==0 || EaAn(ea)) return 1;\r
670\r
671 use=OpBase(op);\r
672 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
673\r
a6785576 674 if (!gen_special) OpStart(op,ea);\r
c008977e 675 else\r
676 ot("Op%.4x_%s\n", op, ms?"":":");\r
677\r
678 Cycles=4;\r
cc68a136 679 if(ea>=8) Cycles+=10;\r
680\r
681 EaCalc (10,0x003f,ea,0,1);\r
682 EaRead (10, 1,ea,0,0x003f,1);\r
683\r
684 ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");\r
685 OpGetFlags(0,0);\r
686 ot("\n");\r
687\r
688#if CYCLONE_FOR_GENESIS\r
689 // the original Sega hardware ignores write-back phase (to memory only)\r
c008977e 690 if (ea < 0x10 || gen_special) {\r
cc68a136 691#endif\r
692 ot(" orr r1,r1,#0x80000000 ;@ set bit7\n");\r
693\r
694 EaWrite(10, 1,ea,0,0x003f,1);\r
695#if CYCLONE_FOR_GENESIS\r
696 }\r
697#endif\r
698\r
cfb3dfa0 699 OpEnd(ea);\r
c008977e 700\r
a9a5a6e0 701#if (CYCLONE_FOR_GENESIS == 2)\r
c008977e 702 if (!gen_special && ea >= 0x10) {\r
703 OpTas(op, 1);\r
704 }\r
705#endif\r
706\r
cc68a136 707 return 0;\r
708}\r
709\r
fast MegaDrive/MegaCD/32X emulator