cc68a136 |
1 | \r |
2 | #include "app.h"\r |
3 | \r |
4 | \r |
5 | // Pack our flags into r1, in SR/CCR register format\r |
6 | // trashes r0,r2\r |
7 | void OpFlagsToReg(int high)\r |
8 | {\r |
85a36a57 |
9 | ot(" ldr r0,[r7,#0x4c] ;@ X bit\n");\r |
449ecf92 |
10 | ot(" mov r1,r10,lsr #28 ;@ ____NZCV\n");\r |
cc68a136 |
11 | ot(" eor r2,r1,r1,ror #1 ;@ Bit 0=C^V\n");\r |
12 | ot(" tst r2,#1 ;@ 1 if C!=V\n");\r |
13 | ot(" eorne r1,r1,#3 ;@ ____NZVC\n");\r |
14 | ot("\n");\r |
15 | if (high) ot(" ldrb r2,[r7,#0x44] ;@ Include SR high\n");\r |
85a36a57 |
16 | ot(" and r0,r0,#0x20000000\n");\r |
17 | ot(" orr r1,r1,r0,lsr #25 ;@ ___XNZVC\n");\r |
cc68a136 |
18 | if (high) ot(" orr r1,r1,r2,lsl #8\n");\r |
19 | ot("\n");\r |
20 | }\r |
21 | \r |
22 | // Convert SR/CRR register in r0 to our flags\r |
23 | // trashes r0,r1\r |
0e11c502 |
24 | void OpRegToFlags(int high, int srh_reg)\r |
cc68a136 |
25 | {\r |
26 | ot(" eor r1,r0,r0,ror #1 ;@ Bit 0=C^V\n");\r |
85a36a57 |
27 | ot(" mov r2,r0,lsl #25\n");\r |
cc68a136 |
28 | ot(" tst r1,#1 ;@ 1 if C!=V\n");\r |
29 | ot(" eorne r0,r0,#3 ;@ ___XNZCV\n");\r |
85a36a57 |
30 | ot(" str r2,[r7,#0x4c] ;@ Store X bit\n");\r |
449ecf92 |
31 | ot(" mov r10,r0,lsl #28 ;@ r10=NZCV...\n");\r |
cc68a136 |
32 | \r |
33 | if (high)\r |
34 | {\r |
0e11c502 |
35 | int mask=EMULATE_TRACE?0xa7:0x27;\r |
36 | ot(" mov r%i,r0,ror #8\n",srh_reg);\r |
37 | ot(" and r%i,r%i,#0x%02x ;@ only take defined bits\n",srh_reg,srh_reg,mask);\r |
38 | ot(" strb r%i,[r7,#0x44] ;@ Store SR high\n",srh_reg);\r |
cc68a136 |
39 | }\r |
40 | ot("\n");\r |
41 | }\r |
42 | \r |
85a36a57 |
43 | void SuperEnd(void)\r |
cc68a136 |
44 | {\r |
85a36a57 |
45 | ot(";@ ----------\n");\r |
46 | ot(";@ tried execute privileged instruction in user mode\n");\r |
47 | ot("WrongPrivilegeMode%s\n",ms?"":":");\r |
0e11c502 |
48 | #if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO\r |
49 | ot(" ldr r1,[r7,#0x58]\n");\r |
85a36a57 |
50 | ot(" sub r4,r4,#2 ;@ last opcode wasn't executed - go back\n");\r |
0e11c502 |
51 | ot(" orr r1,r1,#4 ;@ set activity bit: 'not processing instruction'\n");\r |
52 | ot(" str r1,[r7,#0x58]\n");\r |
53 | #else\r |
54 | ot(" sub r4,r4,#2 ;@ last opcode wasn't executed - go back\n");\r |
55 | #endif\r |
56 | ot(" mov r0,#8 ;@ privilege violation\n");\r |
cc68a136 |
57 | ot(" bl Exception\n");\r |
58 | Cycles=34;\r |
ee5e024c |
59 | OpEnd(0);\r |
cc68a136 |
60 | }\r |
61 | \r |
62 | // does OSP and A7 swapping if needed\r |
63 | // new or old SR (not the one already in [r7,#0x44]) should be passed in r11\r |
0e11c502 |
64 | // uses srh from srh_reg (loads if < 0), trashes r0,r11\r |
65 | void SuperChange(int op,int srh_reg)\r |
cc68a136 |
66 | {\r |
67 | ot(";@ A7 <-> OSP?\n");\r |
0e11c502 |
68 | if (srh_reg < 0) {\r |
85a36a57 |
69 | ot(" ldr r0,[r7,#0x44] ;@ Get other SR high\n");\r |
0e11c502 |
70 | srh_reg=0;\r |
71 | }\r |
72 | ot(" eor r0,r%i,r11\n",srh_reg);\r |
85a36a57 |
73 | ot(" tst r0,#0x20\n");\r |
cc68a136 |
74 | ot(" beq no_sp_swap%.4x\n",op);\r |
75 | ot(" ;@ swap OSP and A7:\n");\r |
76 | ot(" ldr r11,[r7,#0x3C] ;@ Get A7\n");\r |
85a36a57 |
77 | ot(" ldr r0, [r7,#0x48] ;@ Get OSP\n");\r |
cc68a136 |
78 | ot(" str r11,[r7,#0x48]\n");\r |
85a36a57 |
79 | ot(" str r0, [r7,#0x3C]\n");\r |
cc68a136 |
80 | ot("no_sp_swap%.4x%s\n", op, ms?"":":");\r |
81 | }\r |
82 | \r |
83 | \r |
84 | \r |
85 | // --------------------- Opcodes 0x1000+ ---------------------\r |
86 | // Emit a Move opcode, 00xxdddd ddssssss\r |
87 | int OpMove(int op)\r |
88 | {\r |
89 | int sea=0,tea=0;\r |
90 | int size=0,use=0;\r |
91 | int movea=0;\r |
92 | \r |
93 | // Get source and target EA\r |
94 | sea = op&0x003f;\r |
95 | tea =(op&0x01c0)>>3;\r |
96 | tea|=(op&0x0e00)>>9;\r |
97 | \r |
98 | if (tea>=8 && tea<0x10) movea=1;\r |
99 | \r |
100 | // Find size extension\r |
101 | switch (op&0x3000)\r |
102 | {\r |
103 | default: return 1;\r |
104 | case 0x1000: size=0; break;\r |
105 | case 0x3000: size=1; break;\r |
106 | case 0x2000: size=2; break;\r |
107 | }\r |
108 | \r |
109 | if (size<1 && (movea || EaAn(sea))) return 1; // move.b An,* and movea.b * are invalid\r |
110 | \r |
111 | // See if we can do this opcode:\r |
112 | if (EaCanRead (sea,size)==0) return 1;\r |
113 | if (EaCanWrite(tea )==0) return 1;\r |
114 | \r |
85a36a57 |
115 | use=OpBase(op,size);\r |
cc68a136 |
116 | if (tea<0x38) use&=~0x0e00; // Use same handler for register ?0-7\r |
117 | \r |
85a36a57 |
118 | if (tea==0x1f || tea==0x27) use|=0x0e00; // Specific handler for (a7)+ and -(a7)\r |
cc68a136 |
119 | \r |
120 | if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r |
121 | \r |
cfb3dfa0 |
122 | OpStart(op,sea,tea); Cycles=4;\r |
cc68a136 |
123 | \r |
85a36a57 |
124 | if (movea==0)\r |
125 | {\r |
d4789c7c |
126 | EaCalcRead(-1,0,sea,size,0x003f);\r |
127 | ot(" adds r1,r0,#0 ;@ Defines NZ, clears CV\n");\r |
449ecf92 |
128 | ot(" mrs r10,cpsr ;@ r10=NZCV flags\n");\r |
cc68a136 |
129 | ot("\n");\r |
130 | }\r |
d4789c7c |
131 | else\r |
132 | {\r |
133 | EaCalcRead(-1,1,sea,size,0x003f);\r |
134 | size=2; // movea always expands to 32-bits\r |
135 | }\r |
cc68a136 |
136 | \r |
0e11c502 |
137 | eawrite_check_addrerr=1;\r |
cc68a136 |
138 | #if SPLIT_MOVEL_PD\r |
139 | if ((tea&0x38)==0x20 && size==2) { // -(An)\r |
449ecf92 |
140 | EaCalc (8,0x0e00,tea,size,0,0);\r |
cc68a136 |
141 | ot(" mov r11,r1\n");\r |
449ecf92 |
142 | ot(" add r0,r8,#2\n");\r |
03c5768c |
143 | EaWrite(0, 1,tea,1,0x0e00,0,0);\r |
449ecf92 |
144 | EaWrite(8, 11,tea,1,0x0e00,1);\r |
cc68a136 |
145 | }\r |
60305cdd |
146 | else\r |
cc68a136 |
147 | #endif\r |
60305cdd |
148 | {\r |
149 | EaCalc (0,0x0e00,tea,size,0,0);\r |
150 | EaWrite(0, 1,tea,size,0x0e00,0,0);\r |
151 | }\r |
cc68a136 |
152 | \r |
153 | #if CYCLONE_FOR_GENESIS && !MEMHANDLERS_CHANGE_CYCLES\r |
07ceafdb |
154 | // this is a bit hacky (device handlers might modify cycles)\r |
155 | if (tea==0x39||((0x10<=tea&&tea<0x30)&&size>=1))\r |
cc68a136 |
156 | ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");\r |
157 | #endif\r |
158 | \r |
159 | if((tea&0x38)==0x20) Cycles-=2; // less cycles when dest is -(An)\r |
160 | \r |
cfb3dfa0 |
161 | OpEnd(sea,tea);\r |
cc68a136 |
162 | return 0;\r |
163 | }\r |
164 | \r |
165 | // --------------------- Opcodes 0x41c0+ ---------------------\r |
166 | // Emit an Lea opcode, 0100nnn1 11aaaaaa\r |
167 | int OpLea(int op)\r |
168 | {\r |
169 | int use=0;\r |
170 | int sea=0,tea=0;\r |
171 | \r |
172 | sea= op&0x003f;\r |
173 | tea=(op&0x0e00)>>9; tea|=8;\r |
174 | \r |
175 | if (EaCanRead(sea,-1)==0) return 1; // See if we can do this opcode\r |
176 | \r |
85a36a57 |
177 | use=OpBase(op,0);\r |
cc68a136 |
178 | use&=~0x0e00; // Also use 1 handler for target ?0-7\r |
179 | if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r |
180 | \r |
cfb3dfa0 |
181 | OpStart(op,sea,tea);\r |
cc68a136 |
182 | \r |
0e11c502 |
183 | eawrite_check_addrerr=1;\r |
cc68a136 |
184 | EaCalc (1,0x003f,sea,0); // Lea\r |
03c5768c |
185 | EaCalc (0,0x0e00,tea,2);\r |
186 | EaWrite(0, 1,tea,2,0x0e00);\r |
cc68a136 |
187 | \r |
188 | Cycles=Ea_add_ns(g_lea_cycle_table,sea);\r |
189 | \r |
cfb3dfa0 |
190 | OpEnd(sea,tea);\r |
cc68a136 |
191 | \r |
192 | return 0;\r |
193 | }\r |
194 | \r |
195 | // --------------------- Opcodes 0x40c0+ ---------------------\r |
196 | // Move SR opcode, 01000tt0 11aaaaaa move SR\r |
197 | int OpMoveSr(int op)\r |
198 | {\r |
199 | int type=0,ea=0;\r |
200 | int use=0,size=1;\r |
201 | \r |
202 | type=(op>>9)&3; // from SR, from CCR, to CCR, to SR\r |
203 | ea=op&0x3f;\r |
204 | \r |
205 | if(EaAn(ea)) return 1; // can't use An regs\r |
206 | \r |
207 | switch(type)\r |
208 | {\r |
209 | case 0:\r |
210 | if (EaCanWrite(ea)==0) return 1; // See if we can do this opcode:\r |
211 | break;\r |
212 | \r |
213 | case 1:\r |
214 | return 1; // no such op in 68000\r |
215 | \r |
a6785576 |
216 | case 2: case 3:\r |
cc68a136 |
217 | if (EaCanRead(ea,size)==0) return 1; // See if we can do this opcode:\r |
218 | break;\r |
219 | }\r |
220 | \r |
85a36a57 |
221 | use=OpBase(op,size);\r |
cc68a136 |
222 | if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r |
223 | \r |
ee5e024c |
224 | // 68000 model allows reading whole SR in user mode (but newer models don't)\r |
225 | OpStart(op,ea,0,0,type==3);\r |
cc68a136 |
226 | Cycles=12;\r |
227 | if (type==0) Cycles=(ea>=8)?8:6;\r |
228 | \r |
cc68a136 |
229 | if (type==0 || type==1)\r |
230 | {\r |
0e11c502 |
231 | eawrite_check_addrerr=1;\r |
cc68a136 |
232 | OpFlagsToReg(type==0);\r |
b637c56a |
233 | EaCalc (0,0x003f,ea,size,0,0);\r |
234 | EaWrite(0, 1,ea,size,0x003f,0,0);\r |
cc68a136 |
235 | }\r |
236 | \r |
237 | if (type==2 || type==3)\r |
238 | {\r |
85a36a57 |
239 | EaCalcReadNoSE(-1,0,ea,size,0x003f);\r |
0e11c502 |
240 | OpRegToFlags(type==3,1);\r |
cc68a136 |
241 | if (type==3) {\r |
0e11c502 |
242 | SuperChange(op,1);\r |
243 | opend_check_interrupt = 1;\r |
244 | opend_check_trace = 1;\r |
245 | OpEnd(ea);\r |
246 | return 0;\r |
a6785576 |
247 | }\r |
cc68a136 |
248 | }\r |
249 | \r |
0e11c502 |
250 | OpEnd(ea);\r |
cc68a136 |
251 | \r |
cc68a136 |
252 | return 0;\r |
253 | }\r |
254 | \r |
255 | \r |
256 | // Ori/Andi/Eori $nnnn,sr 0000t0t0 01111100\r |
257 | int OpArithSr(int op)\r |
258 | {\r |
259 | int type=0,ea=0;\r |
260 | int use=0,size=0;\r |
0e11c502 |
261 | int sr_mask=EMULATE_TRACE?0xa7:0x27;\r |
cc68a136 |
262 | \r |
263 | type=(op>>9)&5; if (type==4) return 1;\r |
264 | size=(op>>6)&1; // ccr or sr?\r |
265 | ea=0x3c;\r |
266 | \r |
85a36a57 |
267 | use=OpBase(op,size);\r |
cc68a136 |
268 | if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r |
269 | \r |
ee5e024c |
270 | OpStart(op,ea,0,0,size!=0); Cycles=16;\r |
cc68a136 |
271 | \r |
0e11c502 |
272 | EaCalcRead(-1,0,ea,size,0x003f);\r |
cc68a136 |
273 | \r |
0e11c502 |
274 | ot(" eor r1,r0,r0,ror #1 ;@ Bit 0=C^V\n");\r |
275 | ot(" tst r1,#1 ;@ 1 if C!=V\n");\r |
276 | ot(" eorne r0,r0,#3 ;@ ___XNZCV\n");\r |
277 | ot(" ldr r2,[r7,#0x4c] ;@ Load old X bit\n");\r |
278 | \r |
279 | // note: old srh is already in r11 (done by OpStart)\r |
280 | if (type==0) {\r |
449ecf92 |
281 | ot(" orr r10,r10,r0,lsl #28\n");\r |
0e11c502 |
282 | ot(" orr r2,r2,r0,lsl #25 ;@ X bit\n");\r |
283 | if (size!=0) {\r |
284 | ot(" orr r1,r11,r0,lsr #8\n");\r |
285 | ot(" and r1,r1,#0x%02x ;@ mask-out unused bits\n",sr_mask);\r |
286 | }\r |
287 | }\r |
288 | if (type==1) {\r |
449ecf92 |
289 | ot(" and r10,r10,r0,lsl #28\n");\r |
0e11c502 |
290 | ot(" and r2,r2,r0,lsl #25 ;@ X bit\n");\r |
291 | if (size!=0)\r |
292 | ot(" and r1,r11,r0,lsr #8\n");\r |
293 | }\r |
294 | if (type==5) {\r |
449ecf92 |
295 | ot(" eor r10,r10,r0,lsl #28\n");\r |
0e11c502 |
296 | ot(" eor r2,r2,r0,lsl #25 ;@ X bit\n");\r |
297 | if (size!=0) {\r |
298 | ot(" eor r1,r11,r0,lsr #8\n");\r |
299 | ot(" and r1,r1,#0x%02x ;@ mask-out unused bits\n",sr_mask);\r |
300 | }\r |
cc68a136 |
301 | }\r |
302 | \r |
0e11c502 |
303 | ot(" str r2,[r7,#0x4c] ;@ Save X bit\n");\r |
304 | if (size!=0)\r |
305 | ot(" strb r1,[r7,#0x44]\n");\r |
306 | ot("\n");\r |
307 | \r |
308 | // we can't enter supervisor mode, nor unmask irqs just by using OR\r |
309 | if (size!=0 && type!=0) {\r |
310 | SuperChange(op,1);\r |
311 | ot("\n");\r |
312 | opend_check_interrupt = 1;\r |
313 | }\r |
314 | // also can't set trace bit with AND\r |
315 | if (size!=0 && type!=1)\r |
316 | opend_check_trace = 1;\r |
317 | \r |
318 | OpEnd(ea);\r |
cc68a136 |
319 | \r |
320 | return 0;\r |
321 | }\r |
322 | \r |
323 | // --------------------- Opcodes 0x4850+ ---------------------\r |
324 | // Emit an Pea opcode, 01001000 01aaaaaa\r |
325 | int OpPea(int op)\r |
326 | {\r |
327 | int use=0;\r |
328 | int ea=0;\r |
329 | \r |
330 | ea=op&0x003f; if (ea<0x10) return 1; // Swap opcode\r |
331 | if (EaCanRead(ea,-1)==0) return 1; // See if we can do this opcode:\r |
332 | \r |
85a36a57 |
333 | use=OpBase(op,0);\r |
cc68a136 |
334 | if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r |
335 | \r |
a6785576 |
336 | OpStart(op,ea);\r |
cc68a136 |
337 | \r |
449ecf92 |
338 | ot(" ldr r11,[r7,#0x3c]\n");\r |
cc68a136 |
339 | EaCalc (1,0x003f, ea,0);\r |
340 | ot("\n");\r |
449ecf92 |
341 | ot(" sub r0,r11,#4 ;@ Predecrement A7\n");\r |
cc68a136 |
342 | ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r |
343 | ot("\n");\r |
344 | MemHandler(1,2); // Write 32-bit\r |
345 | ot("\n");\r |
346 | \r |
347 | Cycles=6+Ea_add_ns(g_pea_cycle_table,ea);\r |
348 | \r |
cfb3dfa0 |
349 | OpEnd(ea);\r |
cc68a136 |
350 | \r |
351 | return 0;\r |
352 | }\r |
353 | \r |
354 | // --------------------- Opcodes 0x4880+ ---------------------\r |
355 | // Emit a Movem opcode, 01001d00 1xeeeeee regmask\r |
356 | int OpMovem(int op)\r |
357 | {\r |
358 | int size=0,ea=0,cea=0,dir=0;\r |
359 | int use=0,decr=0,change=0;\r |
360 | \r |
361 | size=((op>>6)&1)+1; // word, long\r |
362 | ea=op&0x003f;\r |
363 | dir=(op>>10)&1; // Direction (1==ea2reg)\r |
364 | \r |
365 | if (dir) {\r |
366 | if (ea<0x10 || ea>0x3b || (ea&0x38)==0x20) return 1; // Invalid EA\r |
367 | } else {\r |
368 | if (ea<0x10 || ea>0x39 || (ea&0x38)==0x18) return 1;\r |
369 | }\r |
370 | \r |
371 | if ((ea&0x38)==0x18 || (ea&0x38)==0x20) change=1;\r |
372 | if ((ea&0x38)==0x20) decr=1; // -(An), bitfield is decr\r |
373 | \r |
374 | cea=ea; if (change) cea=0x10;\r |
375 | \r |
85a36a57 |
376 | use=OpBase(op,size);\r |
cc68a136 |
377 | if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r |
378 | \r |
ee5e024c |
379 | OpStart(op,ea,0,1);\r |
cc68a136 |
380 | \r |
8527dc45 |
381 | ot(" ldrh r11,[r4],#2 ;@ r11=register mask\n");\r |
382 | ot("\n");\r |
383 | ot(";@ Get the address into r6:\n");\r |
384 | EaCalc(6,0x003f,cea,size);\r |
385 | \r |
449ecf92 |
386 | #if !MEMHANDLERS_NEED_PREV_PC\r |
387 | // must save PC, need a spare register\r |
388 | ot(" str r4,[r7,#0x40] ;@ Save PC\n");\r |
389 | #endif\r |
cc68a136 |
390 | \r |
449ecf92 |
391 | ot(";@ r4=Register Index*4:\n");\r |
392 | if (decr) ot(" mov r4,#0x40 ;@ order reversed for -(An)\n");\r |
393 | else ot(" mov r4,#-4\n");\r |
cc68a136 |
394 | \r |
cc68a136 |
395 | ot("\n");\r |
b637c56a |
396 | ot(" tst r11,r11\n"); // sanity check\r |
397 | ot(" beq NoRegs%.4x\n",op);\r |
cc68a136 |
398 | \r |
0e11c502 |
399 | #if EMULATE_ADDRESS_ERRORS_IO\r |
400 | ot("\n");\r |
401 | ot(" tst r6,#1 ;@ address error?\n");\r |
402 | ot(" movne r0,r6\n");\r |
403 | ot(" bne ExceptionAddressError_%c_data\n",dir?'r':'w');\r |
404 | #endif\r |
405 | \r |
b637c56a |
406 | ot("\n");\r |
407 | ot("Movemloop%.4x%s\n",op, ms?"":":");\r |
449ecf92 |
408 | ot(" add r4,r4,#%d ;@ r4=Next Register\n",decr?-4:4);\r |
b637c56a |
409 | ot(" movs r11,r11,lsr #1\n");\r |
410 | ot(" bcc Movemloop%.4x\n",op);\r |
411 | ot("\n");\r |
412 | \r |
413 | if (decr) ot(" sub r6,r6,#%d ;@ Pre-decrement address\n",1<<size);\r |
cc68a136 |
414 | \r |
415 | if (dir)\r |
416 | {\r |
417 | ot(" ;@ Copy memory to register:\n",1<<size);\r |
0e11c502 |
418 | earead_check_addrerr=0; // already checked\r |
b637c56a |
419 | EaRead (6,0,ea,size,0x003f);\r |
449ecf92 |
420 | ot(" str r0,[r7,r4] ;@ Save value into Dn/An\n");\r |
cc68a136 |
421 | }\r |
422 | else\r |
423 | {\r |
424 | ot(" ;@ Copy register to memory:\n",1<<size);\r |
449ecf92 |
425 | ot(" ldr r1,[r7,r4] ;@ Load value from Dn/An\n");\r |
e28a980f |
426 | #if SPLIT_MOVEL_PD\r |
427 | if (decr && size==2) { // -(An)\r |
428 | ot(" add r0,r6,#2\n");\r |
429 | EaWrite(0,1,ea,1,0x003f,0,0);\r |
449ecf92 |
430 | ot(" ldr r1,[r7,r4] ;@ Load value from Dn/An\n");\r |
e28a980f |
431 | ot(" mov r0,r6\n");\r |
432 | EaWrite(0,1,ea,1,0x003f,1);\r |
433 | }\r |
434 | else\r |
435 | #endif\r |
436 | {\r |
437 | EaWrite(6,1,ea,size,0x003f);\r |
438 | }\r |
cc68a136 |
439 | }\r |
440 | \r |
b637c56a |
441 | if (decr==0) ot(" add r6,r6,#%d ;@ Post-increment address\n",1<<size);\r |
cc68a136 |
442 | \r |
443 | ot(" sub r5,r5,#%d ;@ Take some cycles\n",2<<size);\r |
b637c56a |
444 | ot(" tst r11,r11\n");\r |
445 | ot(" bne Movemloop%.4x\n",op);\r |
cc68a136 |
446 | ot("\n");\r |
447 | \r |
448 | if (change)\r |
449 | {\r |
450 | ot(";@ Write back address:\n");\r |
451 | EaCalc (0,0x0007,8|(ea&7),2);\r |
b637c56a |
452 | EaWrite(0, 6,8|(ea&7),2,0x0007);\r |
cc68a136 |
453 | }\r |
454 | \r |
b637c56a |
455 | ot("NoRegs%.4x%s\n",op, ms?"":":");\r |
449ecf92 |
456 | ot(" ldr r4,[r7,#0x40]\n");\r |
457 | ot(" ldr r6,[r7,#0x54] ;@ restore Opcode Jump table\n");\r |
cc68a136 |
458 | ot("\n");\r |
459 | \r |
460 | if(dir) { // er\r |
461 | if (ea==0x3a) Cycles=16; // ($nn,PC)\r |
462 | else if (ea==0x3b) Cycles=18; // ($nn,pc,Rn)\r |
a6785576 |
463 | else Cycles=12;\r |
cc68a136 |
464 | } else {\r |
465 | Cycles=8;\r |
466 | }\r |
467 | \r |
468 | Cycles+=Ea_add_ns(g_movem_cycle_table,ea);\r |
469 | \r |
0e11c502 |
470 | opend_op_changes_cycles = 1;\r |
471 | OpEnd(ea);\r |
3a5e6cf8 |
472 | ot("\n");\r |
cc68a136 |
473 | \r |
474 | return 0;\r |
475 | }\r |
476 | \r |
477 | // --------------------- Opcodes 0x4e60+ ---------------------\r |
478 | // Emit a Move USP opcode, 01001110 0110dnnn move An to/from USP\r |
479 | int OpMoveUsp(int op)\r |
480 | {\r |
481 | int use=0,dir=0;\r |
482 | \r |
483 | dir=(op>>3)&1; // Direction\r |
484 | use=op&~0x0007; // Use same opcode for all An\r |
485 | \r |
486 | if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r |
487 | \r |
ee5e024c |
488 | OpStart(op,0,0,0,1); Cycles=4;\r |
cc68a136 |
489 | \r |
490 | if (dir)\r |
491 | {\r |
0e11c502 |
492 | eawrite_check_addrerr=1;\r |
cc68a136 |
493 | ot(" ldr r1,[r7,#0x48] ;@ Get from USP\n\n");\r |
85a36a57 |
494 | EaCalc (0,0x000f,8,2,1);\r |
495 | EaWrite(0, 1,8,2,0x000f,1);\r |
cc68a136 |
496 | }\r |
497 | else\r |
498 | {\r |
85a36a57 |
499 | EaCalc (0,0x000f,8,2,1);\r |
500 | EaRead (0, 0,8,2,0x000f,1);\r |
cc68a136 |
501 | ot(" str r0,[r7,#0x48] ;@ Put in USP\n\n");\r |
502 | }\r |
503 | \r |
504 | OpEnd();\r |
505 | \r |
cc68a136 |
506 | return 0;\r |
507 | }\r |
508 | \r |
509 | // --------------------- Opcodes 0x7000+ ---------------------\r |
510 | // Emit a Move Quick opcode, 0111nnn0 dddddddd moveq #dd,Dn\r |
511 | int OpMoveq(int op)\r |
512 | {\r |
513 | int use=0;\r |
514 | \r |
515 | use=op&0xf100; // Use same opcode for all values\r |
516 | if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r |
517 | \r |
518 | OpStart(op); Cycles=4;\r |
519 | \r |
520 | ot(" movs r0,r8,asl #24\n");\r |
521 | ot(" and r1,r8,#0x0e00\n");\r |
522 | ot(" mov r0,r0,asr #24 ;@ Sign extended Quick value\n");\r |
449ecf92 |
523 | ot(" mrs r10,cpsr ;@ r10=NZ flags\n");\r |
cc68a136 |
524 | ot(" str r0,[r7,r1,lsr #7] ;@ Store into Dn\n");\r |
525 | ot("\n");\r |
526 | \r |
527 | OpEnd();\r |
528 | \r |
529 | return 0;\r |
530 | }\r |
531 | \r |
532 | // --------------------- Opcodes 0xc140+ ---------------------\r |
533 | // Emit a Exchange opcode:\r |
534 | // 1100ttt1 01000sss exg ds,dt\r |
535 | // 1100ttt1 01001sss exg as,at\r |
536 | // 1100ttt1 10001sss exg as,dt\r |
537 | int OpExg(int op)\r |
538 | {\r |
539 | int use=0,type=0;\r |
540 | \r |
541 | type=op&0xf8;\r |
542 | \r |
543 | if (type!=0x40 && type!=0x48 && type!=0x88) return 1; // Not an exg opcode\r |
544 | \r |
545 | use=op&0xf1f8; // Use same opcode for all values\r |
546 | if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r |
547 | \r |
548 | OpStart(op); Cycles=6;\r |
549 | \r |
449ecf92 |
550 | ot(" and r2,r8,#0x0e00 ;@ Find T register\n");\r |
551 | ot(" and r3,r8,#0x000f ;@ Find S register\n");\r |
552 | if (type==0x48) ot(" orr r2,r2,#0x1000 ;@ T is an address register\n");\r |
cc68a136 |
553 | ot("\n");\r |
449ecf92 |
554 | ot(" ldr r0,[r7,r2,lsr #7] ;@ Get T\n");\r |
555 | ot(" ldr r1,[r7,r3,lsl #2] ;@ Get S\n");\r |
cc68a136 |
556 | ot("\n");\r |
449ecf92 |
557 | ot(" str r0,[r7,r3,lsl #2] ;@ T->S\n");\r |
558 | ot(" str r1,[r7,r2,lsr #7] ;@ S->T\n"); \r |
cc68a136 |
559 | ot("\n");\r |
560 | \r |
561 | OpEnd();\r |
562 | \r |
563 | return 0;\r |
564 | }\r |
565 | \r |
566 | // ------------------------- movep -------------------------------\r |
567 | // 0000ddd1 0z001sss\r |
568 | // 0000sss1 1z001ddd (to mem)\r |
569 | int OpMovep(int op)\r |
570 | {\r |
85a36a57 |
571 | int ea=0,rea=0;\r |
572 | int size=1,use=0,dir,aadd=0;\r |
cc68a136 |
573 | \r |
574 | use=op&0xf1f8;\r |
575 | if (op!=use) { OpUse(op,use); return 0; } // Use existing handler (for all dests, srcs)\r |
576 | \r |
577 | // Get EA\r |
578 | ea = (op&0x0007)|0x28;\r |
03c5768c |
579 | rea= (op&0x0e00)>>9;\r |
cc68a136 |
580 | dir = (op>>7)&1;\r |
581 | \r |
582 | // Find size extension\r |
583 | if(op&0x0040) size=2;\r |
584 | \r |
a6785576 |
585 | OpStart(op,ea);\r |
cc68a136 |
586 | \r |
449ecf92 |
587 | if(dir) // reg to mem\r |
588 | {\r |
03c5768c |
589 | EaCalcReadNoSE(-1,11,rea,size,0x0e00);\r |
85a36a57 |
590 | \r |
449ecf92 |
591 | EaCalc(8,0x000f,ea,size);\r |
a6785576 |
592 | if(size==2) { // if operand is long\r |
593 | ot(" mov r1,r11,lsr #24 ;@ first byte\n");\r |
449ecf92 |
594 | EaWrite(8,1,ea,0,0x000f); // store first byte\r |
595 | ot(" add r0,r8,#%i\n",(aadd+=2));\r |
a6785576 |
596 | ot(" mov r1,r11,lsr #16 ;@ second byte\n");\r |
85a36a57 |
597 | EaWrite(0,1,ea,0,0x000f); // store second byte\r |
449ecf92 |
598 | ot(" add r0,r8,#%i\n",(aadd+=2));\r |
85a36a57 |
599 | } else {\r |
449ecf92 |
600 | ot(" mov r0,r8\n");\r |
a6785576 |
601 | }\r |
602 | ot(" mov r1,r11,lsr #8 ;@ first or third byte\n");\r |
85a36a57 |
603 | EaWrite(0,1,ea,0,0x000f);\r |
449ecf92 |
604 | ot(" add r0,r8,#%i\n",(aadd+=2));\r |
a6785576 |
605 | ot(" and r1,r11,#0xff\n");\r |
85a36a57 |
606 | EaWrite(0,1,ea,0,0x000f);\r |
449ecf92 |
607 | }\r |
608 | else // mem to reg\r |
609 | {\r |
610 | EaCalc(6,0x000f,ea,size,1);\r |
611 | EaRead(6,11,ea,0,0x000f,1); // read first byte\r |
612 | ot(" add r0,r6,#2\n");\r |
85a36a57 |
613 | EaRead(0,1,ea,0,0x000f,1); // read second byte\r |
a6785576 |
614 | if(size==2) { // if operand is long\r |
cc68a136 |
615 | ot(" orr r11,r11,r1,lsr #8 ;@ second byte\n");\r |
449ecf92 |
616 | ot(" add r0,r6,#4\n");\r |
85a36a57 |
617 | EaRead(0,1,ea,0,0x000f,1);\r |
cc68a136 |
618 | ot(" orr r11,r11,r1,lsr #16 ;@ third byte\n");\r |
449ecf92 |
619 | ot(" add r0,r6,#6\n");\r |
85a36a57 |
620 | EaRead(0,1,ea,0,0x000f,1);\r |
621 | ot(" orr r1,r11,r1,lsr #24 ;@ fourth byte\n");\r |
a6785576 |
622 | } else {\r |
85a36a57 |
623 | ot(" orr r1,r11,r1,lsr #8 ;@ second byte\n");\r |
a6785576 |
624 | }\r |
625 | // store the result\r |
449ecf92 |
626 | EaCalc(0,0x0e00,rea,size,1);\r |
627 | EaWrite(0,1,rea,size,0x0e00,1);\r |
628 | ot(" ldr r6,[r7,#0x54]\n");\r |
cc68a136 |
629 | }\r |
630 | \r |
631 | Cycles=(size==2)?24:16;\r |
cfb3dfa0 |
632 | OpEnd(ea);\r |
cc68a136 |
633 | \r |
634 | return 0;\r |
635 | }\r |
636 | \r |
637 | // Emit a Stop/Reset opcodes, 01001110 011100t0 imm\r |
638 | int OpStopReset(int op)\r |
639 | {\r |
85a36a57 |
640 | int type=(op>>1)&1; // stop/reset\r |
cc68a136 |
641 | \r |
ee5e024c |
642 | OpStart(op,0,0,0,1);\r |
cc68a136 |
643 | \r |
644 | if(type) {\r |
645 | // copy immediate to SR, stop the CPU and eat all remaining cycles.\r |
646 | ot(" ldrh r0,[r4],#2 ;@ Fetch the immediate\n");\r |
cc68a136 |
647 | OpRegToFlags(1);\r |
85a36a57 |
648 | SuperChange(op,0);\r |
cc68a136 |
649 | \r |
a6785576 |
650 | ot("\n");\r |
cc68a136 |
651 | \r |
0e11c502 |
652 | ot(" ldr r0,[r7,#0x58]\n");\r |
653 | ot(" mov r5,#0 ;@ eat cycles\n");\r |
654 | ot(" orr r0,r0,#1 ;@ stopped\n");\r |
655 | ot(" str r0,[r7,#0x58]\n");\r |
a6785576 |
656 | ot("\n");\r |
cc68a136 |
657 | \r |
cc68a136 |
658 | Cycles = 4;\r |
a6785576 |
659 | ot("\n");\r |
cc68a136 |
660 | }\r |
661 | else\r |
662 | {\r |
663 | Cycles = 132;\r |
664 | #if USE_RESET_CALLBACK\r |
665 | ot(" str r4,[r7,#0x40] ;@ Save PC\n");\r |
449ecf92 |
666 | ot(" mov r1,r10,lsr #28\n");\r |
cc68a136 |
667 | ot(" strb r1,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r |
668 | ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");\r |
669 | ot(" ldr r11,[r7,#0x90] ;@ ResetCallback\n");\r |
670 | ot(" tst r11,r11\n");\r |
671 | ot(" movne lr,pc\n");\r |
85a36a57 |
672 | ot(" bxne r11 ;@ call ResetCallback if it is defined\n");\r |
449ecf92 |
673 | ot(" ldrb r10,[r7,#0x46] ;@ r10 = Load Flags (NZCV)\n");\r |
cc68a136 |
674 | ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");\r |
675 | ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");\r |
449ecf92 |
676 | ot(" mov r10,r10,lsl #28\n");\r |
85a36a57 |
677 | ot("\n");\r |
cc68a136 |
678 | #endif\r |
679 | }\r |
680 | \r |
681 | OpEnd();\r |
cc68a136 |
682 | \r |
683 | return 0;\r |
684 | }\r |
cfb3dfa0 |
685 | \r |