windows Pico stuff wip
[picodrive.git] / cpu / Cyclone / OpMove.cpp
CommitLineData
cc68a136 1\r
2#include "app.h"\r
3\r
4\r
5// Pack our flags into r1, in SR/CCR register format\r
6// trashes r0,r2\r
7void OpFlagsToReg(int high)\r
8{\r
85a36a57 9 ot(" ldr r0,[r7,#0x4c] ;@ X bit\n");\r
449ecf92 10 ot(" mov r1,r10,lsr #28 ;@ ____NZCV\n");\r
cc68a136 11 ot(" eor r2,r1,r1,ror #1 ;@ Bit 0=C^V\n");\r
12 ot(" tst r2,#1 ;@ 1 if C!=V\n");\r
13 ot(" eorne r1,r1,#3 ;@ ____NZVC\n");\r
14 ot("\n");\r
15 if (high) ot(" ldrb r2,[r7,#0x44] ;@ Include SR high\n");\r
85a36a57 16 ot(" and r0,r0,#0x20000000\n");\r
17 ot(" orr r1,r1,r0,lsr #25 ;@ ___XNZVC\n");\r
cc68a136 18 if (high) ot(" orr r1,r1,r2,lsl #8\n");\r
19 ot("\n");\r
20}\r
21\r
22// Convert SR/CRR register in r0 to our flags\r
23// trashes r0,r1\r
0e11c502 24void OpRegToFlags(int high, int srh_reg)\r
cc68a136 25{\r
26 ot(" eor r1,r0,r0,ror #1 ;@ Bit 0=C^V\n");\r
85a36a57 27 ot(" mov r2,r0,lsl #25\n");\r
cc68a136 28 ot(" tst r1,#1 ;@ 1 if C!=V\n");\r
29 ot(" eorne r0,r0,#3 ;@ ___XNZCV\n");\r
85a36a57 30 ot(" str r2,[r7,#0x4c] ;@ Store X bit\n");\r
449ecf92 31 ot(" mov r10,r0,lsl #28 ;@ r10=NZCV...\n");\r
cc68a136 32\r
33 if (high)\r
34 {\r
0e11c502 35 int mask=EMULATE_TRACE?0xa7:0x27;\r
36 ot(" mov r%i,r0,ror #8\n",srh_reg);\r
37 ot(" and r%i,r%i,#0x%02x ;@ only take defined bits\n",srh_reg,srh_reg,mask);\r
38 ot(" strb r%i,[r7,#0x44] ;@ Store SR high\n",srh_reg);\r
cc68a136 39 }\r
40 ot("\n");\r
41}\r
42\r
85a36a57 43void SuperEnd(void)\r
cc68a136 44{\r
85a36a57 45 ot(";@ ----------\n");\r
46 ot(";@ tried execute privileged instruction in user mode\n");\r
47 ot("WrongPrivilegeMode%s\n",ms?"":":");\r
0e11c502 48#if EMULATE_ADDRESS_ERRORS_JUMP || EMULATE_ADDRESS_ERRORS_IO\r
49 ot(" ldr r1,[r7,#0x58]\n");\r
85a36a57 50 ot(" sub r4,r4,#2 ;@ last opcode wasn't executed - go back\n");\r
0e11c502 51 ot(" orr r1,r1,#4 ;@ set activity bit: 'not processing instruction'\n");\r
52 ot(" str r1,[r7,#0x58]\n");\r
53#else\r
54 ot(" sub r4,r4,#2 ;@ last opcode wasn't executed - go back\n");\r
55#endif\r
56 ot(" mov r0,#8 ;@ privilege violation\n");\r
cc68a136 57 ot(" bl Exception\n");\r
58 Cycles=34;\r
ee5e024c 59 OpEnd(0);\r
cc68a136 60}\r
61\r
62// does OSP and A7 swapping if needed\r
63// new or old SR (not the one already in [r7,#0x44]) should be passed in r11\r
0e11c502 64// uses srh from srh_reg (loads if < 0), trashes r0,r11\r
65void SuperChange(int op,int srh_reg)\r
cc68a136 66{\r
67 ot(";@ A7 <-> OSP?\n");\r
0e11c502 68 if (srh_reg < 0) {\r
85a36a57 69 ot(" ldr r0,[r7,#0x44] ;@ Get other SR high\n");\r
0e11c502 70 srh_reg=0;\r
71 }\r
72 ot(" eor r0,r%i,r11\n",srh_reg);\r
85a36a57 73 ot(" tst r0,#0x20\n");\r
cc68a136 74 ot(" beq no_sp_swap%.4x\n",op);\r
75 ot(" ;@ swap OSP and A7:\n");\r
76 ot(" ldr r11,[r7,#0x3C] ;@ Get A7\n");\r
85a36a57 77 ot(" ldr r0, [r7,#0x48] ;@ Get OSP\n");\r
cc68a136 78 ot(" str r11,[r7,#0x48]\n");\r
85a36a57 79 ot(" str r0, [r7,#0x3C]\n");\r
cc68a136 80 ot("no_sp_swap%.4x%s\n", op, ms?"":":");\r
81}\r
82\r
83\r
84\r
85// --------------------- Opcodes 0x1000+ ---------------------\r
86// Emit a Move opcode, 00xxdddd ddssssss\r
87int OpMove(int op)\r
88{\r
89 int sea=0,tea=0;\r
90 int size=0,use=0;\r
91 int movea=0;\r
92\r
93 // Get source and target EA\r
94 sea = op&0x003f;\r
95 tea =(op&0x01c0)>>3;\r
96 tea|=(op&0x0e00)>>9;\r
97\r
98 if (tea>=8 && tea<0x10) movea=1;\r
99\r
100 // Find size extension\r
101 switch (op&0x3000)\r
102 {\r
103 default: return 1;\r
104 case 0x1000: size=0; break;\r
105 case 0x3000: size=1; break;\r
106 case 0x2000: size=2; break;\r
107 }\r
108\r
109 if (size<1 && (movea || EaAn(sea))) return 1; // move.b An,* and movea.b * are invalid\r
110\r
111 // See if we can do this opcode:\r
112 if (EaCanRead (sea,size)==0) return 1;\r
113 if (EaCanWrite(tea )==0) return 1;\r
114\r
85a36a57 115 use=OpBase(op,size);\r
cc68a136 116 if (tea<0x38) use&=~0x0e00; // Use same handler for register ?0-7\r
117 \r
85a36a57 118 if (tea==0x1f || tea==0x27) use|=0x0e00; // Specific handler for (a7)+ and -(a7)\r
cc68a136 119\r
120 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
121\r
cfb3dfa0 122 OpStart(op,sea,tea); Cycles=4;\r
cc68a136 123\r
85a36a57 124 EaCalcRead(-1,1,sea,size,0x003f);\r
cc68a136 125\r
85a36a57 126 if (movea==0)\r
127 {\r
cc68a136 128 ot(" adds r1,r1,#0 ;@ Defines NZ, clears CV\n");\r
449ecf92 129 ot(" mrs r10,cpsr ;@ r10=NZCV flags\n");\r
cc68a136 130 ot("\n");\r
131 }\r
132\r
133 if (movea) size=2; // movea always expands to 32-bits\r
134\r
0e11c502 135 eawrite_check_addrerr=1;\r
cc68a136 136#if SPLIT_MOVEL_PD\r
137 if ((tea&0x38)==0x20 && size==2) { // -(An)\r
449ecf92 138 EaCalc (8,0x0e00,tea,size,0,0);\r
cc68a136 139 ot(" mov r11,r1\n");\r
449ecf92 140 ot(" add r0,r8,#2\n");\r
03c5768c 141 EaWrite(0, 1,tea,1,0x0e00,0,0);\r
449ecf92 142 EaWrite(8, 11,tea,1,0x0e00,1);\r
cc68a136 143 }\r
60305cdd 144 else\r
cc68a136 145#endif\r
60305cdd 146 {\r
147 EaCalc (0,0x0e00,tea,size,0,0);\r
148 EaWrite(0, 1,tea,size,0x0e00,0,0);\r
149 }\r
cc68a136 150\r
151#if CYCLONE_FOR_GENESIS && !MEMHANDLERS_CHANGE_CYCLES\r
152 // this is a bit hacky\r
69996cb7 153 if ((tea==0x39||(tea>=0x10&&tea<0x30))&&size>=1)\r
cc68a136 154 ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");\r
155#endif\r
156\r
157 if((tea&0x38)==0x20) Cycles-=2; // less cycles when dest is -(An)\r
158\r
cfb3dfa0 159 OpEnd(sea,tea);\r
cc68a136 160 return 0;\r
161}\r
162\r
163// --------------------- Opcodes 0x41c0+ ---------------------\r
164// Emit an Lea opcode, 0100nnn1 11aaaaaa\r
165int OpLea(int op)\r
166{\r
167 int use=0;\r
168 int sea=0,tea=0;\r
169\r
170 sea= op&0x003f;\r
171 tea=(op&0x0e00)>>9; tea|=8;\r
172\r
173 if (EaCanRead(sea,-1)==0) return 1; // See if we can do this opcode\r
174\r
85a36a57 175 use=OpBase(op,0);\r
cc68a136 176 use&=~0x0e00; // Also use 1 handler for target ?0-7\r
177 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
178\r
cfb3dfa0 179 OpStart(op,sea,tea);\r
cc68a136 180\r
0e11c502 181 eawrite_check_addrerr=1;\r
cc68a136 182 EaCalc (1,0x003f,sea,0); // Lea\r
03c5768c 183 EaCalc (0,0x0e00,tea,2);\r
184 EaWrite(0, 1,tea,2,0x0e00);\r
cc68a136 185\r
186 Cycles=Ea_add_ns(g_lea_cycle_table,sea);\r
187\r
cfb3dfa0 188 OpEnd(sea,tea);\r
cc68a136 189\r
190 return 0;\r
191}\r
192\r
193// --------------------- Opcodes 0x40c0+ ---------------------\r
194// Move SR opcode, 01000tt0 11aaaaaa move SR\r
195int OpMoveSr(int op)\r
196{\r
197 int type=0,ea=0;\r
198 int use=0,size=1;\r
199\r
200 type=(op>>9)&3; // from SR, from CCR, to CCR, to SR\r
201 ea=op&0x3f;\r
202\r
203 if(EaAn(ea)) return 1; // can't use An regs\r
204\r
205 switch(type)\r
206 {\r
207 case 0:\r
208 if (EaCanWrite(ea)==0) return 1; // See if we can do this opcode:\r
209 break;\r
210\r
211 case 1:\r
212 return 1; // no such op in 68000\r
213\r
a6785576 214 case 2: case 3:\r
cc68a136 215 if (EaCanRead(ea,size)==0) return 1; // See if we can do this opcode:\r
216 break;\r
217 }\r
218\r
85a36a57 219 use=OpBase(op,size);\r
cc68a136 220 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
221\r
ee5e024c 222 // 68000 model allows reading whole SR in user mode (but newer models don't)\r
223 OpStart(op,ea,0,0,type==3);\r
cc68a136 224 Cycles=12;\r
225 if (type==0) Cycles=(ea>=8)?8:6;\r
226\r
cc68a136 227 if (type==0 || type==1)\r
228 {\r
0e11c502 229 eawrite_check_addrerr=1;\r
cc68a136 230 OpFlagsToReg(type==0);\r
b637c56a 231 EaCalc (0,0x003f,ea,size,0,0);\r
232 EaWrite(0, 1,ea,size,0x003f,0,0);\r
cc68a136 233 }\r
234\r
235 if (type==2 || type==3)\r
236 {\r
85a36a57 237 EaCalcReadNoSE(-1,0,ea,size,0x003f);\r
0e11c502 238 OpRegToFlags(type==3,1);\r
cc68a136 239 if (type==3) {\r
0e11c502 240 SuperChange(op,1);\r
241 opend_check_interrupt = 1;\r
242 opend_check_trace = 1;\r
243 OpEnd(ea);\r
244 return 0;\r
a6785576 245 }\r
cc68a136 246 }\r
247\r
0e11c502 248 OpEnd(ea);\r
cc68a136 249\r
cc68a136 250 return 0;\r
251}\r
252\r
253\r
254// Ori/Andi/Eori $nnnn,sr 0000t0t0 01111100\r
255int OpArithSr(int op)\r
256{\r
257 int type=0,ea=0;\r
258 int use=0,size=0;\r
0e11c502 259 int sr_mask=EMULATE_TRACE?0xa7:0x27;\r
cc68a136 260\r
261 type=(op>>9)&5; if (type==4) return 1;\r
262 size=(op>>6)&1; // ccr or sr?\r
263 ea=0x3c;\r
264\r
85a36a57 265 use=OpBase(op,size);\r
cc68a136 266 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
267\r
ee5e024c 268 OpStart(op,ea,0,0,size!=0); Cycles=16;\r
cc68a136 269\r
0e11c502 270 EaCalcRead(-1,0,ea,size,0x003f);\r
cc68a136 271\r
0e11c502 272 ot(" eor r1,r0,r0,ror #1 ;@ Bit 0=C^V\n");\r
273 ot(" tst r1,#1 ;@ 1 if C!=V\n");\r
274 ot(" eorne r0,r0,#3 ;@ ___XNZCV\n");\r
275 ot(" ldr r2,[r7,#0x4c] ;@ Load old X bit\n");\r
276\r
277 // note: old srh is already in r11 (done by OpStart)\r
278 if (type==0) {\r
449ecf92 279 ot(" orr r10,r10,r0,lsl #28\n");\r
0e11c502 280 ot(" orr r2,r2,r0,lsl #25 ;@ X bit\n");\r
281 if (size!=0) {\r
282 ot(" orr r1,r11,r0,lsr #8\n");\r
283 ot(" and r1,r1,#0x%02x ;@ mask-out unused bits\n",sr_mask);\r
284 }\r
285 }\r
286 if (type==1) {\r
449ecf92 287 ot(" and r10,r10,r0,lsl #28\n");\r
0e11c502 288 ot(" and r2,r2,r0,lsl #25 ;@ X bit\n");\r
289 if (size!=0)\r
290 ot(" and r1,r11,r0,lsr #8\n");\r
291 }\r
292 if (type==5) {\r
449ecf92 293 ot(" eor r10,r10,r0,lsl #28\n");\r
0e11c502 294 ot(" eor r2,r2,r0,lsl #25 ;@ X bit\n");\r
295 if (size!=0) {\r
296 ot(" eor r1,r11,r0,lsr #8\n");\r
297 ot(" and r1,r1,#0x%02x ;@ mask-out unused bits\n",sr_mask);\r
298 }\r
cc68a136 299 }\r
300\r
0e11c502 301 ot(" str r2,[r7,#0x4c] ;@ Save X bit\n");\r
302 if (size!=0)\r
303 ot(" strb r1,[r7,#0x44]\n");\r
304 ot("\n");\r
305\r
306 // we can't enter supervisor mode, nor unmask irqs just by using OR\r
307 if (size!=0 && type!=0) {\r
308 SuperChange(op,1);\r
309 ot("\n");\r
310 opend_check_interrupt = 1;\r
311 }\r
312 // also can't set trace bit with AND\r
313 if (size!=0 && type!=1)\r
314 opend_check_trace = 1;\r
315\r
316 OpEnd(ea);\r
cc68a136 317\r
318 return 0;\r
319}\r
320\r
321// --------------------- Opcodes 0x4850+ ---------------------\r
322// Emit an Pea opcode, 01001000 01aaaaaa\r
323int OpPea(int op)\r
324{\r
325 int use=0;\r
326 int ea=0;\r
327\r
328 ea=op&0x003f; if (ea<0x10) return 1; // Swap opcode\r
329 if (EaCanRead(ea,-1)==0) return 1; // See if we can do this opcode:\r
330\r
85a36a57 331 use=OpBase(op,0);\r
cc68a136 332 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
333\r
a6785576 334 OpStart(op,ea);\r
cc68a136 335\r
449ecf92 336 ot(" ldr r11,[r7,#0x3c]\n");\r
cc68a136 337 EaCalc (1,0x003f, ea,0);\r
338 ot("\n");\r
449ecf92 339 ot(" sub r0,r11,#4 ;@ Predecrement A7\n");\r
cc68a136 340 ot(" str r0,[r7,#0x3c] ;@ Save A7\n");\r
341 ot("\n");\r
342 MemHandler(1,2); // Write 32-bit\r
343 ot("\n");\r
344\r
345 Cycles=6+Ea_add_ns(g_pea_cycle_table,ea);\r
346\r
cfb3dfa0 347 OpEnd(ea);\r
cc68a136 348\r
349 return 0;\r
350}\r
351\r
352// --------------------- Opcodes 0x4880+ ---------------------\r
353// Emit a Movem opcode, 01001d00 1xeeeeee regmask\r
354int OpMovem(int op)\r
355{\r
356 int size=0,ea=0,cea=0,dir=0;\r
357 int use=0,decr=0,change=0;\r
358\r
359 size=((op>>6)&1)+1; // word, long\r
360 ea=op&0x003f;\r
361 dir=(op>>10)&1; // Direction (1==ea2reg)\r
362\r
363 if (dir) {\r
364 if (ea<0x10 || ea>0x3b || (ea&0x38)==0x20) return 1; // Invalid EA\r
365 } else {\r
366 if (ea<0x10 || ea>0x39 || (ea&0x38)==0x18) return 1;\r
367 }\r
368\r
369 if ((ea&0x38)==0x18 || (ea&0x38)==0x20) change=1;\r
370 if ((ea&0x38)==0x20) decr=1; // -(An), bitfield is decr\r
371\r
372 cea=ea; if (change) cea=0x10;\r
373\r
85a36a57 374 use=OpBase(op,size);\r
cc68a136 375 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
376\r
ee5e024c 377 OpStart(op,ea,0,1);\r
cc68a136 378\r
8527dc45 379 ot(" ldrh r11,[r4],#2 ;@ r11=register mask\n");\r
380 ot("\n");\r
381 ot(";@ Get the address into r6:\n");\r
382 EaCalc(6,0x003f,cea,size);\r
383\r
449ecf92 384#if !MEMHANDLERS_NEED_PREV_PC\r
385 // must save PC, need a spare register\r
386 ot(" str r4,[r7,#0x40] ;@ Save PC\n");\r
387#endif\r
cc68a136 388\r
449ecf92 389 ot(";@ r4=Register Index*4:\n");\r
390 if (decr) ot(" mov r4,#0x40 ;@ order reversed for -(An)\n");\r
391 else ot(" mov r4,#-4\n");\r
cc68a136 392 \r
cc68a136 393 ot("\n");\r
b637c56a 394 ot(" tst r11,r11\n"); // sanity check\r
395 ot(" beq NoRegs%.4x\n",op);\r
cc68a136 396\r
0e11c502 397#if EMULATE_ADDRESS_ERRORS_IO\r
398 ot("\n");\r
399 ot(" tst r6,#1 ;@ address error?\n");\r
400 ot(" movne r0,r6\n");\r
401 ot(" bne ExceptionAddressError_%c_data\n",dir?'r':'w');\r
402#endif\r
403\r
b637c56a 404 ot("\n");\r
405 ot("Movemloop%.4x%s\n",op, ms?"":":");\r
449ecf92 406 ot(" add r4,r4,#%d ;@ r4=Next Register\n",decr?-4:4);\r
b637c56a 407 ot(" movs r11,r11,lsr #1\n");\r
408 ot(" bcc Movemloop%.4x\n",op);\r
409 ot("\n");\r
410\r
411 if (decr) ot(" sub r6,r6,#%d ;@ Pre-decrement address\n",1<<size);\r
cc68a136 412\r
413 if (dir)\r
414 {\r
415 ot(" ;@ Copy memory to register:\n",1<<size);\r
0e11c502 416 earead_check_addrerr=0; // already checked\r
b637c56a 417 EaRead (6,0,ea,size,0x003f);\r
449ecf92 418 ot(" str r0,[r7,r4] ;@ Save value into Dn/An\n");\r
cc68a136 419 }\r
420 else\r
421 {\r
422 ot(" ;@ Copy register to memory:\n",1<<size);\r
449ecf92 423 ot(" ldr r1,[r7,r4] ;@ Load value from Dn/An\n");\r
e28a980f 424#if SPLIT_MOVEL_PD\r
425 if (decr && size==2) { // -(An)\r
426 ot(" add r0,r6,#2\n");\r
427 EaWrite(0,1,ea,1,0x003f,0,0);\r
449ecf92 428 ot(" ldr r1,[r7,r4] ;@ Load value from Dn/An\n");\r
e28a980f 429 ot(" mov r0,r6\n");\r
430 EaWrite(0,1,ea,1,0x003f,1);\r
431 }\r
432 else\r
433#endif\r
434 {\r
435 EaWrite(6,1,ea,size,0x003f);\r
436 }\r
cc68a136 437 }\r
438\r
b637c56a 439 if (decr==0) ot(" add r6,r6,#%d ;@ Post-increment address\n",1<<size);\r
cc68a136 440\r
441 ot(" sub r5,r5,#%d ;@ Take some cycles\n",2<<size);\r
b637c56a 442 ot(" tst r11,r11\n");\r
443 ot(" bne Movemloop%.4x\n",op);\r
cc68a136 444 ot("\n");\r
445\r
446 if (change)\r
447 {\r
448 ot(";@ Write back address:\n");\r
449 EaCalc (0,0x0007,8|(ea&7),2);\r
b637c56a 450 EaWrite(0, 6,8|(ea&7),2,0x0007);\r
cc68a136 451 }\r
452\r
b637c56a 453 ot("NoRegs%.4x%s\n",op, ms?"":":");\r
449ecf92 454 ot(" ldr r4,[r7,#0x40]\n");\r
455 ot(" ldr r6,[r7,#0x54] ;@ restore Opcode Jump table\n");\r
cc68a136 456 ot("\n");\r
457\r
458 if(dir) { // er\r
459 if (ea==0x3a) Cycles=16; // ($nn,PC)\r
460 else if (ea==0x3b) Cycles=18; // ($nn,pc,Rn)\r
a6785576 461 else Cycles=12;\r
cc68a136 462 } else {\r
463 Cycles=8;\r
464 }\r
465\r
466 Cycles+=Ea_add_ns(g_movem_cycle_table,ea);\r
467\r
0e11c502 468 opend_op_changes_cycles = 1;\r
469 OpEnd(ea);\r
3a5e6cf8 470 ot("\n");\r
cc68a136 471\r
472 return 0;\r
473}\r
474\r
475// --------------------- Opcodes 0x4e60+ ---------------------\r
476// Emit a Move USP opcode, 01001110 0110dnnn move An to/from USP\r
477int OpMoveUsp(int op)\r
478{\r
479 int use=0,dir=0;\r
480\r
481 dir=(op>>3)&1; // Direction\r
482 use=op&~0x0007; // Use same opcode for all An\r
483\r
484 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
485\r
ee5e024c 486 OpStart(op,0,0,0,1); Cycles=4;\r
cc68a136 487\r
488 if (dir)\r
489 {\r
0e11c502 490 eawrite_check_addrerr=1;\r
cc68a136 491 ot(" ldr r1,[r7,#0x48] ;@ Get from USP\n\n");\r
85a36a57 492 EaCalc (0,0x000f,8,2,1);\r
493 EaWrite(0, 1,8,2,0x000f,1);\r
cc68a136 494 }\r
495 else\r
496 {\r
85a36a57 497 EaCalc (0,0x000f,8,2,1);\r
498 EaRead (0, 0,8,2,0x000f,1);\r
cc68a136 499 ot(" str r0,[r7,#0x48] ;@ Put in USP\n\n");\r
500 }\r
501 \r
502 OpEnd();\r
503\r
cc68a136 504 return 0;\r
505}\r
506\r
507// --------------------- Opcodes 0x7000+ ---------------------\r
508// Emit a Move Quick opcode, 0111nnn0 dddddddd moveq #dd,Dn\r
509int OpMoveq(int op)\r
510{\r
511 int use=0;\r
512\r
513 use=op&0xf100; // Use same opcode for all values\r
514 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
515\r
516 OpStart(op); Cycles=4;\r
517\r
518 ot(" movs r0,r8,asl #24\n");\r
519 ot(" and r1,r8,#0x0e00\n");\r
520 ot(" mov r0,r0,asr #24 ;@ Sign extended Quick value\n");\r
449ecf92 521 ot(" mrs r10,cpsr ;@ r10=NZ flags\n");\r
cc68a136 522 ot(" str r0,[r7,r1,lsr #7] ;@ Store into Dn\n");\r
523 ot("\n");\r
524\r
525 OpEnd();\r
526\r
527 return 0;\r
528}\r
529\r
530// --------------------- Opcodes 0xc140+ ---------------------\r
531// Emit a Exchange opcode:\r
532// 1100ttt1 01000sss exg ds,dt\r
533// 1100ttt1 01001sss exg as,at\r
534// 1100ttt1 10001sss exg as,dt\r
535int OpExg(int op)\r
536{\r
537 int use=0,type=0;\r
538\r
539 type=op&0xf8;\r
540\r
541 if (type!=0x40 && type!=0x48 && type!=0x88) return 1; // Not an exg opcode\r
542\r
543 use=op&0xf1f8; // Use same opcode for all values\r
544 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler\r
545\r
546 OpStart(op); Cycles=6;\r
547\r
449ecf92 548 ot(" and r2,r8,#0x0e00 ;@ Find T register\n");\r
549 ot(" and r3,r8,#0x000f ;@ Find S register\n");\r
550 if (type==0x48) ot(" orr r2,r2,#0x1000 ;@ T is an address register\n");\r
cc68a136 551 ot("\n");\r
449ecf92 552 ot(" ldr r0,[r7,r2,lsr #7] ;@ Get T\n");\r
553 ot(" ldr r1,[r7,r3,lsl #2] ;@ Get S\n");\r
cc68a136 554 ot("\n");\r
449ecf92 555 ot(" str r0,[r7,r3,lsl #2] ;@ T->S\n");\r
556 ot(" str r1,[r7,r2,lsr #7] ;@ S->T\n"); \r
cc68a136 557 ot("\n");\r
558\r
559 OpEnd();\r
560 \r
561 return 0;\r
562}\r
563\r
564// ------------------------- movep -------------------------------\r
565// 0000ddd1 0z001sss\r
566// 0000sss1 1z001ddd (to mem)\r
567int OpMovep(int op)\r
568{\r
85a36a57 569 int ea=0,rea=0;\r
570 int size=1,use=0,dir,aadd=0;\r
cc68a136 571\r
572 use=op&0xf1f8;\r
573 if (op!=use) { OpUse(op,use); return 0; } // Use existing handler (for all dests, srcs)\r
574\r
575 // Get EA\r
576 ea = (op&0x0007)|0x28;\r
03c5768c 577 rea= (op&0x0e00)>>9;\r
cc68a136 578 dir = (op>>7)&1;\r
579\r
580 // Find size extension\r
581 if(op&0x0040) size=2;\r
582\r
a6785576 583 OpStart(op,ea);\r
cc68a136 584 \r
449ecf92 585 if(dir) // reg to mem\r
586 {\r
03c5768c 587 EaCalcReadNoSE(-1,11,rea,size,0x0e00);\r
85a36a57 588\r
449ecf92 589 EaCalc(8,0x000f,ea,size);\r
a6785576 590 if(size==2) { // if operand is long\r
591 ot(" mov r1,r11,lsr #24 ;@ first byte\n");\r
449ecf92 592 EaWrite(8,1,ea,0,0x000f); // store first byte\r
593 ot(" add r0,r8,#%i\n",(aadd+=2));\r
a6785576 594 ot(" mov r1,r11,lsr #16 ;@ second byte\n");\r
85a36a57 595 EaWrite(0,1,ea,0,0x000f); // store second byte\r
449ecf92 596 ot(" add r0,r8,#%i\n",(aadd+=2));\r
85a36a57 597 } else {\r
449ecf92 598 ot(" mov r0,r8\n");\r
a6785576 599 }\r
600 ot(" mov r1,r11,lsr #8 ;@ first or third byte\n");\r
85a36a57 601 EaWrite(0,1,ea,0,0x000f);\r
449ecf92 602 ot(" add r0,r8,#%i\n",(aadd+=2));\r
a6785576 603 ot(" and r1,r11,#0xff\n");\r
85a36a57 604 EaWrite(0,1,ea,0,0x000f);\r
449ecf92 605 }\r
606 else // mem to reg\r
607 {\r
608 EaCalc(6,0x000f,ea,size,1);\r
609 EaRead(6,11,ea,0,0x000f,1); // read first byte\r
610 ot(" add r0,r6,#2\n");\r
85a36a57 611 EaRead(0,1,ea,0,0x000f,1); // read second byte\r
a6785576 612 if(size==2) { // if operand is long\r
cc68a136 613 ot(" orr r11,r11,r1,lsr #8 ;@ second byte\n");\r
449ecf92 614 ot(" add r0,r6,#4\n");\r
85a36a57 615 EaRead(0,1,ea,0,0x000f,1);\r
cc68a136 616 ot(" orr r11,r11,r1,lsr #16 ;@ third byte\n");\r
449ecf92 617 ot(" add r0,r6,#6\n");\r
85a36a57 618 EaRead(0,1,ea,0,0x000f,1);\r
619 ot(" orr r1,r11,r1,lsr #24 ;@ fourth byte\n");\r
a6785576 620 } else {\r
85a36a57 621 ot(" orr r1,r11,r1,lsr #8 ;@ second byte\n");\r
a6785576 622 }\r
623 // store the result\r
449ecf92 624 EaCalc(0,0x0e00,rea,size,1);\r
625 EaWrite(0,1,rea,size,0x0e00,1);\r
626 ot(" ldr r6,[r7,#0x54]\n");\r
cc68a136 627 }\r
628\r
629 Cycles=(size==2)?24:16;\r
cfb3dfa0 630 OpEnd(ea);\r
cc68a136 631\r
632 return 0;\r
633}\r
634\r
635// Emit a Stop/Reset opcodes, 01001110 011100t0 imm\r
636int OpStopReset(int op)\r
637{\r
85a36a57 638 int type=(op>>1)&1; // stop/reset\r
cc68a136 639\r
ee5e024c 640 OpStart(op,0,0,0,1);\r
cc68a136 641\r
642 if(type) {\r
643 // copy immediate to SR, stop the CPU and eat all remaining cycles.\r
644 ot(" ldrh r0,[r4],#2 ;@ Fetch the immediate\n");\r
cc68a136 645 OpRegToFlags(1);\r
85a36a57 646 SuperChange(op,0);\r
cc68a136 647\r
a6785576 648 ot("\n");\r
cc68a136 649\r
0e11c502 650 ot(" ldr r0,[r7,#0x58]\n");\r
651 ot(" mov r5,#0 ;@ eat cycles\n");\r
652 ot(" orr r0,r0,#1 ;@ stopped\n");\r
653 ot(" str r0,[r7,#0x58]\n");\r
a6785576 654 ot("\n");\r
cc68a136 655\r
cc68a136 656 Cycles = 4;\r
a6785576 657 ot("\n");\r
cc68a136 658 }\r
659 else\r
660 {\r
661 Cycles = 132;\r
662#if USE_RESET_CALLBACK\r
663 ot(" str r4,[r7,#0x40] ;@ Save PC\n");\r
449ecf92 664 ot(" mov r1,r10,lsr #28\n");\r
cc68a136 665 ot(" strb r1,[r7,#0x46] ;@ Save Flags (NZCV)\n");\r
666 ot(" str r5,[r7,#0x5c] ;@ Save Cycles\n");\r
667 ot(" ldr r11,[r7,#0x90] ;@ ResetCallback\n");\r
668 ot(" tst r11,r11\n");\r
669 ot(" movne lr,pc\n");\r
85a36a57 670 ot(" bxne r11 ;@ call ResetCallback if it is defined\n");\r
449ecf92 671 ot(" ldrb r10,[r7,#0x46] ;@ r10 = Load Flags (NZCV)\n");\r
cc68a136 672 ot(" ldr r5,[r7,#0x5c] ;@ Load Cycles\n");\r
673 ot(" ldr r4,[r7,#0x40] ;@ Load PC\n");\r
449ecf92 674 ot(" mov r10,r10,lsl #28\n");\r
85a36a57 675 ot("\n");\r
cc68a136 676#endif\r
677 }\r
678\r
679 OpEnd();\r
cc68a136 680\r
681 return 0;\r
682}\r
cfb3dfa0 683\r