windows Pico stuff wip
[picodrive.git] / cpu / Cyclone / config.h
CommitLineData
cc68a136 1\r
2\r
3/**\r
4 * Cyclone 68000 configuration file\r
5**/\r
6\r
7\r
8/*\r
0e11c502 9 * If this option is enabled, Microsoft ARMASM compatible output is generated\r
10 * (output file - Cyclone.asm). Otherwise GNU as syntax is used (Cyclone.s).\r
cc68a136 11 */\r
0e11c502 12#define USE_MS_SYNTAX 0\r
cc68a136 13\r
14/*\r
15 * Enable this option if you are going to use Cyclone to emulate Genesis /\r
16 * Mega Drive system. As VDP chip in these systems had control of the bus,\r
17 * several instructions were acting differently, for example TAS did'n have\r
a6785576 18 * the write-back phase. That will be emulated, if this option is enabled.\r
cc68a136 19 */\r
0e11c502 20#define CYCLONE_FOR_GENESIS 0\r
cc68a136 21\r
22/*\r
23 * This option compresses Cyclone's jumptable. Because of this the executable\r
24 * will be smaller and load slightly faster and less relocations will be needed.\r
25 * This also fixes the crash problem with 0xfffe and 0xffff opcodes.\r
26 * Warning: if you enable this, you MUST call CycloneInit() before calling\r
27 * CycloneRun(), or else it will crash.\r
28 */\r
0e11c502 29#define COMPRESS_JUMPTABLE 1\r
cc68a136 30\r
a6785576 31/*\r
32 * Address mask for memory hadlers. The bits set will be masked out of address\r
33 * parameter, which is passed to r/w memory handlers.\r
34 * Using 0xff000000 means that only 24 least significant bits should be used.\r
35 * Set to 0 if you want to mask unused address bits in the memory handlers yourself.\r
36 */\r
0e11c502 37#define MEMHANDLERS_ADDR_MASK 0\r
a6785576 38\r
cc68a136 39/*\r
40 * Cyclone keeps the 4 least significant bits of SR, PC+membase and it's cycle\r
0e11c502 41 * counter in ARM registers instead of the context for performance reasons. If you for\r
cc68a136 42 * any reason need to access them in your memory handlers, enable the options below,\r
43 * otherwise disable them to improve performance.\r
0e11c502 44 *\r
cfb3dfa0 45 * MEMHANDLERS_NEED_PC updates .pc context field with PC value effective at the time\r
0e11c502 46 * when memhandler was called (opcode address + 2-10 bytes).\r
cfb3dfa0 47 * MEMHANDLERS_NEED_PREV_PC updates .prev_pc context field to currently executed\r
b637c56a 48 * opcode address + 2.\r
cfb3dfa0 49 * Note that .pc and .prev_pc values are always real pointers to memory, so you must\r
50 * subtract .membase to get M68k PC value.\r
0e11c502 51 *\r
a6785576 52 * Warning: updating PC in memhandlers is dangerous, as Cyclone may internally\r
53 * increment the PC before fetching the next instruction and continue executing\r
0e11c502 54 * at wrong location. It's better to wait until Cyclone CycloneRun() finishes.\r
55 *\r
56 * Warning: if you enable MEMHANDLERS_CHANGE_CYCLES, you must also enable\r
57 * MEMHANDLERS_NEED_CYCLES, or else Cyclone will keep reloading the same cycle\r
58 * count and this will screw timing (if not cause a deadlock).\r
cc68a136 59 */\r
0e11c502 60#define MEMHANDLERS_NEED_PC 0\r
61#define MEMHANDLERS_NEED_PREV_PC 0\r
62#define MEMHANDLERS_NEED_FLAGS 0\r
63#define MEMHANDLERS_NEED_CYCLES 0\r
64#define MEMHANDLERS_CHANGE_PC 0\r
65#define MEMHANDLERS_CHANGE_FLAGS 0\r
66#define MEMHANDLERS_CHANGE_CYCLES 0\r
cc68a136 67\r
68/*\r
0e11c502 69 * If enabled, Cyclone will call .IrqCallback routine from it's context whenever it\r
70 * acknowledges an IRQ. IRQ level (.irq) is not cleared automatically, do this in your\r
71 * handler if needed.\r
72 * This function must either return vector number to use for interrupt exception,\r
73 * CYCLONE_INT_ACK_AUTOVECTOR to use autovector (this is the most common case), or\r
74 * CYCLONE_INT_ACK_SPURIOUS (least common case).\r
75 * If disabled, it simply uses appropriate autovector, clears the IRQ level and\r
76 * continues execution.\r
cc68a136 77 */\r
0e11c502 78#define USE_INT_ACK_CALLBACK 0\r
cc68a136 79\r
80/*\r
0e11c502 81 * Enable this if you need old PC, flags or cycles;\r
82 * or you change cycles in your IrqCallback function.\r
cc68a136 83 */\r
0e11c502 84#define INT_ACK_NEEDS_STUFF 0\r
85#define INT_ACK_CHANGES_CYCLES 0\r
cc68a136 86\r
87/*\r
0e11c502 88 * If enabled, .ResetCallback is called from the context, whenever RESET opcode is\r
cc68a136 89 * encountered. All context members are valid and can be changed.\r
90 * If disabled, RESET opcode acts as an NOP.\r
91 */\r
0e11c502 92#define USE_RESET_CALLBACK 0\r
cc68a136 93\r
94/*\r
95 * If enabled, UnrecognizedCallback is called if an invalid opcode is\r
96 * encountered. All context members are valid and can be changed. The handler\r
97 * should return zero if you want Cyclone to gererate "Illegal Instruction"\r
a6785576 98 * exception after this, or nonzero if not. In the later case you should change\r
cc68a136 99 * the PC by yourself, or else Cyclone will keep executing that opcode all over\r
100 * again.\r
101 * If disabled, "Illegal Instruction" exception is generated and execution is\r
102 * continued.\r
103 */\r
0e11c502 104#define USE_UNRECOGNIZED_CALLBACK 0\r
cc68a136 105\r
106/*\r
107 * This option will also call UnrecognizedCallback for a-line and f-line\r
108 * (0xa*** and 0xf***) opcodes the same way as described above, only appropriate\r
109 * exceptions will be generated.\r
110 */\r
0e11c502 111#define USE_AFLINE_CALLBACK 0\r
cc68a136 112\r
113/*\r
114 * This makes Cyclone to call checkpc from it's context whenever it changes the PC\r
115 * by a large value. It takes and should return the PC value in PC+membase form.\r
116 * The flags and cycle counter are not valid in this function.\r
117 */\r
0e11c502 118#define USE_CHECKPC_CALLBACK 1\r
cc68a136 119\r
03c5768c 120/*\r
121 * This determines if checkpc() should be called after jumps when 8 and 16 bit\r
122 * displacement values were used.\r
123 */\r
0e11c502 124#define USE_CHECKPC_OFFSETBITS_16 1\r
125#define USE_CHECKPC_OFFSETBITS_8 0\r
03c5768c 126\r
127/*\r
128 * Call checkpc() after DBcc jumps (which use 16bit displacement). Cyclone prior to\r
129 * 0.0087 never did that.\r
130 */\r
0e11c502 131#define USE_CHECKPC_DBRA 0\r
03c5768c 132\r
cc68a136 133/*\r
134 * When this option is enabled Cyclone will do two word writes instead of one\r
e28a980f 135 * long write when handling MOVE.L or MOVEM.L with pre-decrementing destination,\r
136 * as described in Bart Trzynadlowski's doc (http://www.trzy.org/files/68knotes.txt).\r
cc68a136 137 * Enable this if you are emulating a 16 bit system.\r
138 */\r
0e11c502 139#define SPLIT_MOVEL_PD 1\r
140\r
141/*\r
142 * Enable emulation of trace mode. Shouldn't cause any performance decrease, so it\r
143 * should be safe to keep this ON.\r
144 */\r
145#define EMULATE_TRACE 1\r
146\r
147/*\r
148 * If enabled, address error exception will be generated if 68k code jumps to an\r
149 * odd address. Causes very small performance hit (2 ARM instructions for every\r
150 * emulated jump/return/exception in normal case).\r
151 * Note: checkpc() must not clear least significant bit of rebased address\r
152 * for this to work, as checks are performed after calling checkpc().\r
153 */\r
154#define EMULATE_ADDRESS_ERRORS_JUMP 1\r
155\r
156/*\r
157 * If enabled, address error exception will be generated if 68k code tries to\r
158 * access a word or longword at an odd address. The performance cost is also 2 ARM\r
159 * instructions per access (for address error checks).\r
160 */\r
161#define EMULATE_ADDRESS_ERRORS_IO 0\r
162\r
163/*\r
164 * If an address error happens during another address error processing,\r
165 * the processor halts until it is reset (catastrophic system failure, as the manual\r
166 * states). This option enables halt emulation.\r
167 * Note that this might be not desired if it is known that emulated system should\r
168 * never reach this state.\r
169 */\r
170#define EMULATE_HALT 0\r
171\r