| cc68a136 |
1 | \r |
| 2 | \r |
| 3 | /**\r |
| 4 | * Cyclone 68000 configuration file\r |
| 5 | **/\r |
| 6 | \r |
| 7 | \r |
| 8 | /*\r |
| 9 | * If this option is enabled, Microsoft ARMASM compatible output is generated.\r |
| 10 | * Otherwise GNU as syntax is used.\r |
| 11 | */\r |
| 12 | #define USE_MS_SYNTAX 0\r |
| 13 | \r |
| 14 | /*\r |
| 15 | * Enable this option if you are going to use Cyclone to emulate Genesis /\r |
| 16 | * Mega Drive system. As VDP chip in these systems had control of the bus,\r |
| 17 | * several instructions were acting differently, for example TAS did'n have\r |
| a6785576 |
18 | * the write-back phase. That will be emulated, if this option is enabled.\r |
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19 | * This option also alters timing slightly.\r |
| 20 | */\r |
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21 | #define CYCLONE_FOR_GENESIS 1\r |
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22 | \r |
| 23 | /*\r |
| 24 | * This option compresses Cyclone's jumptable. Because of this the executable\r |
| 25 | * will be smaller and load slightly faster and less relocations will be needed.\r |
| 26 | * This also fixes the crash problem with 0xfffe and 0xffff opcodes.\r |
| 27 | * Warning: if you enable this, you MUST call CycloneInit() before calling\r |
| 28 | * CycloneRun(), or else it will crash.\r |
| 29 | */\r |
| 30 | #define COMPRESS_JUMPTABLE 1\r |
| 31 | \r |
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32 | /*\r |
| 33 | * Address mask for memory hadlers. The bits set will be masked out of address\r |
| 34 | * parameter, which is passed to r/w memory handlers.\r |
| 35 | * Using 0xff000000 means that only 24 least significant bits should be used.\r |
| 36 | * Set to 0 if you want to mask unused address bits in the memory handlers yourself.\r |
| 37 | */\r |
| 38 | #define MEMHANDLERS_ADDR_MASK 0xff000000\r |
| 39 | \r |
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40 | /*\r |
| 41 | * Cyclone keeps the 4 least significant bits of SR, PC+membase and it's cycle\r |
| 42 | * count in ARM registers instead of the context for performance reasons. If you for\r |
| 43 | * any reason need to access them in your memory handlers, enable the options below,\r |
| 44 | * otherwise disable them to improve performance.\r |
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45 | * PC value will point to start of instruction currently executed.\r |
| 46 | * Warning: updating PC in memhandlers is dangerous, as Cyclone may internally\r |
| 47 | * increment the PC before fetching the next instruction and continue executing\r |
| 48 | * at wrong location.\r |
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49 | */\r |
| 50 | #define MEMHANDLERS_NEED_PC 0\r |
| 51 | #define MEMHANDLERS_NEED_FLAGS 0\r |
| 52 | #define MEMHANDLERS_NEED_CYCLES 1\r |
| 53 | #define MEMHANDLERS_CHANGE_PC 0\r |
| 54 | #define MEMHANDLERS_CHANGE_FLAGS 0\r |
| 55 | #define MEMHANDLERS_CHANGE_CYCLES 0\r |
| 56 | \r |
| 57 | /*\r |
| 58 | * If enabled, Cyclone will call IrqCallback routine from it's context whenever it\r |
| 59 | * acknowledges an IRQ. IRQ level is not cleared automatically, do this in your\r |
| 60 | * hadler if needed. PC, flags and cycles are valid in the context and can be read.\r |
| 61 | * If disabled, it simply clears the IRQ level and continues execution.\r |
| 62 | */\r |
| 63 | #define USE_INT_ACK_CALLBACK 1\r |
| 64 | \r |
| 65 | /*\r |
| 66 | * Enable this if you need/change PC, flags or cycles in your IrqCallback function.\r |
| 67 | */\r |
| 68 | #define INT_ACK_NEEDS_STUFF 0\r |
| 69 | #define INT_ACK_CHANGES_STUFF 0\r |
| 70 | \r |
| 71 | /*\r |
| 72 | * If enabled, ResetCallback is called from the context, whenever RESET opcode is\r |
| 73 | * encountered. All context members are valid and can be changed.\r |
| 74 | * If disabled, RESET opcode acts as an NOP.\r |
| 75 | */\r |
| 76 | #define USE_RESET_CALLBACK 1\r |
| 77 | \r |
| 78 | /*\r |
| 79 | * If enabled, UnrecognizedCallback is called if an invalid opcode is\r |
| 80 | * encountered. All context members are valid and can be changed. The handler\r |
| 81 | * should return zero if you want Cyclone to gererate "Illegal Instruction"\r |
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82 | * exception after this, or nonzero if not. In the later case you should change\r |
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83 | * the PC by yourself, or else Cyclone will keep executing that opcode all over\r |
| 84 | * again.\r |
| 85 | * If disabled, "Illegal Instruction" exception is generated and execution is\r |
| 86 | * continued.\r |
| 87 | */\r |
| 88 | #define USE_UNRECOGNIZED_CALLBACK 1\r |
| 89 | \r |
| 90 | /*\r |
| 91 | * This option will also call UnrecognizedCallback for a-line and f-line\r |
| 92 | * (0xa*** and 0xf***) opcodes the same way as described above, only appropriate\r |
| 93 | * exceptions will be generated.\r |
| 94 | */\r |
| 95 | #define USE_AFLINE_CALLBACK 1\r |
| 96 | \r |
| 97 | /*\r |
| 98 | * This makes Cyclone to call checkpc from it's context whenever it changes the PC\r |
| 99 | * by a large value. It takes and should return the PC value in PC+membase form.\r |
| 100 | * The flags and cycle counter are not valid in this function.\r |
| 101 | */\r |
| 102 | #define USE_CHECKPC_CALLBACK 1\r |
| 103 | \r |
| 104 | /*\r |
| 105 | * When this option is enabled Cyclone will do two word writes instead of one\r |
| 106 | * long write when handling MOVE.L with pre-decrementing destination, as described in\r |
| 107 | * Bart Trzynadlowski's doc (http://www.trzy.org/files/68knotes.txt).\r |
| 108 | * Enable this if you are emulating a 16 bit system.\r |
| 109 | */\r |
| 110 | #define SPLIT_MOVEL_PD 1\r |
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