0.0088 release

[picodrive.git] / cpu / Cyclone / config_uae4all.h

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/**\r
 * Cyclone 68000 configuration file\r
**/\r
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/*\r
 * If this option is enabled, Microsoft ARMASM compatible output is generated\r
 * (output file -  Cyclone.asm). Otherwise GNU as syntax is used (Cyclone.s).\r
 */\r
#define USE_MS_SYNTAX               0\r
\r
/*\r
 * Enable this option if you are going to use Cyclone to emulate Genesis /\r
 * Mega Drive system. As VDP chip in these systems had control of the bus,\r
 * several instructions were acting differently, for example TAS did'n have\r
 * the write-back phase. That will be emulated, if this option is enabled.\r
 * This option also alters timing slightly.\r
 */\r
#define CYCLONE_FOR_GENESIS         0\r
\r
/*\r
 * This option compresses Cyclone's jumptable. Because of this the executable\r
 * will be smaller and load slightly faster and less relocations will be needed.\r
 * This also fixes the crash problem with 0xfffe and 0xffff opcodes.\r
 * Warning: if you enable this, you MUST call CycloneInit() before calling\r
 * CycloneRun(), or else it will crash.\r
 */\r
#define COMPRESS_JUMPTABLE          1\r
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/*\r
 * Address mask for memory hadlers. The bits set will be masked out of address\r
 * parameter, which is passed to r/w memory handlers.\r
 * Using 0xff000000 means that only 24 least significant bits should be used.\r
 * Set to 0 if you want to mask unused address bits in the memory handlers yourself.\r
 */\r
#define MEMHANDLERS_ADDR_MASK       0\r
\r
/*\r
 * Cyclone keeps the 4 least significant bits of SR, PC+membase and it's cycle\r
 * counter in ARM registers instead of the context for performance reasons. If you for\r
 * any reason need to access them in your memory handlers, enable the options below,\r
 * otherwise disable them to improve performance.\r
 *\r
 * MEMHANDLERS_NEED_PC updates .pc context field with PC value effective at the time\r
 * when memhandler was called (opcode address + 2-10 bytes).\r
 * MEMHANDLERS_NEED_PREV_PC updates .prev_pc context field to currently executed\r
 * opcode address + 2.\r
 * Note that .pc and .prev_pc values are always real pointers to memory, so you must\r
 * subtract .membase to get M68k PC value.\r
 *\r
 * Warning: updating PC in memhandlers is dangerous, as Cyclone may internally\r
 * increment the PC before fetching the next instruction and continue executing\r
 * at wrong location. It's better to wait until Cyclone CycloneRun() finishes.\r
 *\r
 * Warning: if you enable MEMHANDLERS_CHANGE_CYCLES, you must also enable\r
 * MEMHANDLERS_NEED_CYCLES, or else Cyclone will keep reloading the same cycle\r
 * count and this will screw timing (if not cause a deadlock).\r
 */\r
#define MEMHANDLERS_NEED_PC         1\r
#define MEMHANDLERS_NEED_PREV_PC    0\r
#define MEMHANDLERS_NEED_FLAGS      0\r
#define MEMHANDLERS_NEED_CYCLES     1\r
#define MEMHANDLERS_CHANGE_PC       0\r
#define MEMHANDLERS_CHANGE_FLAGS    0\r
#define MEMHANDLERS_CHANGE_CYCLES   1\r
\r
/*\r
 * If enabled, Cyclone will call .IrqCallback routine from it's context whenever it\r
 * acknowledges an IRQ. IRQ level (.irq) is not cleared automatically, do this in your\r
 * handler if needed.\r
 * This function must either return vector number to use for interrupt exception,\r
 * CYCLONE_INT_ACK_AUTOVECTOR to use autovector (this is the most common case), or\r
 * CYCLONE_INT_ACK_SPURIOUS (least common case).\r
 * If disabled, it simply uses appropriate autovector, clears the IRQ level and\r
 * continues execution.\r
 */\r
#define USE_INT_ACK_CALLBACK        1\r
\r
/*\r
 * Enable this if you need old PC, flags or cycles;\r
 * or you change cycles in your IrqCallback function.\r
 */\r
#define INT_ACK_NEEDS_STUFF         0\r
#define INT_ACK_CHANGES_CYCLES      0\r
\r
/*\r
 * If enabled, .ResetCallback is called from the context, whenever RESET opcode is\r
 * encountered. All context members are valid and can be changed.\r
 * If disabled, RESET opcode acts as an NOP.\r
 */\r
#define USE_RESET_CALLBACK          0\r
\r
/*\r
 * If enabled, UnrecognizedCallback is called if an invalid opcode is\r
 * encountered. All context members are valid and can be changed. The handler\r
 * should return zero if you want Cyclone to gererate "Illegal Instruction"\r
 * exception after this, or nonzero if not. In the later case you should change\r
 * the PC by yourself, or else Cyclone will keep executing that opcode all over\r
 * again.\r
 * If disabled, "Illegal Instruction" exception is generated and execution is\r
 * continued.\r
 */\r
#define USE_UNRECOGNIZED_CALLBACK   1\r
\r
/*\r
 * This option will also call UnrecognizedCallback for a-line and f-line\r
 * (0xa*** and 0xf***) opcodes the same way as described above, only appropriate\r
 * exceptions will be generated.\r
 */\r
#define USE_AFLINE_CALLBACK         1\r
\r
/*\r
 * This makes Cyclone to call checkpc from it's context whenever it changes the PC\r
 * by a large value. It takes and should return the PC value in PC+membase form.\r
 * The flags and cycle counter are not valid in this function.\r
 */\r
#define USE_CHECKPC_CALLBACK        1\r
\r
/*\r
 * This determines if checkpc() should be called after jumps when 8 and 16 bit\r
 * displacement values were used.\r
 */\r
#define USE_CHECKPC_OFFSETBITS_16   1\r
#define USE_CHECKPC_OFFSETBITS_8    0\r
\r
/*\r
 * Call checkpc() after DBcc jumps (which use 16bit displacement). Cyclone prior to\r
 * 0.0087 never did that.\r
 */\r
#define USE_CHECKPC_DBRA            0\r
\r
/*\r
 * When this option is enabled Cyclone will do two word writes instead of one\r
 * long write when handling MOVE.L with pre-decrementing destination, as described in\r
 * Bart Trzynadlowski's doc (http://www.trzy.org/files/68knotes.txt).\r
 * Enable this if you are emulating a 16 bit system.\r
 */\r
#define SPLIT_MOVEL_PD              1\r
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/*\r
 * Enable emulation of trace mode. Shouldn't cause any performance decrease, so it\r
 * should be safe to keep this ON.\r
 */\r
#define EMULATE_TRACE               1\r
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/*\r
 * If enabled, address error exception will be generated if 68k code jumps to an\r
 * odd address. Causes very small performance hit (2 ARM instructions for every\r
 * emulated jump/return/exception in normal case).\r
 * Note: checkpc() must not clear least significant bit of rebased address\r
 * for this to work, as checks are performed after calling checkpc().\r
 */\r
#define EMULATE_ADDRESS_ERRORS_JUMP 1\r
\r
/*\r
 * If enabled, address error exception will be generated if 68k code tries to\r
 * access a word or longword at an odd address. The performance cost is also 2 ARM\r
 * instructions per access (for address error checks).\r
 */\r
#define EMULATE_ADDRESS_ERRORS_IO   1\r
\r
/*\r
 * If an address error happens during another address error processing,\r
 * the processor halts until it is reset (catastrophic system failure, as the manual\r
 * states). This option enables halt emulation.\r
 * Note that this might be not desired if it is known that emulated system should\r
 * never reach this state.\r
 */\r
#define EMULATE_HALT                0\r
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