0.0088 release
[picodrive.git] / cpu / Cyclone / config_uae4all.h
CommitLineData
0e11c502 1\r
2\r
3/**\r
4 * Cyclone 68000 configuration file\r
5**/\r
6\r
7\r
8/*\r
9 * If this option is enabled, Microsoft ARMASM compatible output is generated\r
10 * (output file - Cyclone.asm). Otherwise GNU as syntax is used (Cyclone.s).\r
11 */\r
12#define USE_MS_SYNTAX 0\r
13\r
14/*\r
15 * Enable this option if you are going to use Cyclone to emulate Genesis /\r
16 * Mega Drive system. As VDP chip in these systems had control of the bus,\r
17 * several instructions were acting differently, for example TAS did'n have\r
18 * the write-back phase. That will be emulated, if this option is enabled.\r
19 * This option also alters timing slightly.\r
20 */\r
21#define CYCLONE_FOR_GENESIS 0\r
22\r
23/*\r
24 * This option compresses Cyclone's jumptable. Because of this the executable\r
25 * will be smaller and load slightly faster and less relocations will be needed.\r
26 * This also fixes the crash problem with 0xfffe and 0xffff opcodes.\r
27 * Warning: if you enable this, you MUST call CycloneInit() before calling\r
28 * CycloneRun(), or else it will crash.\r
29 */\r
30#define COMPRESS_JUMPTABLE 1\r
31\r
32/*\r
33 * Address mask for memory hadlers. The bits set will be masked out of address\r
34 * parameter, which is passed to r/w memory handlers.\r
35 * Using 0xff000000 means that only 24 least significant bits should be used.\r
36 * Set to 0 if you want to mask unused address bits in the memory handlers yourself.\r
37 */\r
38#define MEMHANDLERS_ADDR_MASK 0\r
39\r
40/*\r
41 * Cyclone keeps the 4 least significant bits of SR, PC+membase and it's cycle\r
42 * counter in ARM registers instead of the context for performance reasons. If you for\r
43 * any reason need to access them in your memory handlers, enable the options below,\r
44 * otherwise disable them to improve performance.\r
45 *\r
46 * MEMHANDLERS_NEED_PC updates .pc context field with PC value effective at the time\r
47 * when memhandler was called (opcode address + 2-10 bytes).\r
48 * MEMHANDLERS_NEED_PREV_PC updates .prev_pc context field to currently executed\r
49 * opcode address + 2.\r
50 * Note that .pc and .prev_pc values are always real pointers to memory, so you must\r
51 * subtract .membase to get M68k PC value.\r
52 *\r
53 * Warning: updating PC in memhandlers is dangerous, as Cyclone may internally\r
54 * increment the PC before fetching the next instruction and continue executing\r
55 * at wrong location. It's better to wait until Cyclone CycloneRun() finishes.\r
56 *\r
57 * Warning: if you enable MEMHANDLERS_CHANGE_CYCLES, you must also enable\r
58 * MEMHANDLERS_NEED_CYCLES, or else Cyclone will keep reloading the same cycle\r
59 * count and this will screw timing (if not cause a deadlock).\r
60 */\r
61#define MEMHANDLERS_NEED_PC 1\r
62#define MEMHANDLERS_NEED_PREV_PC 0\r
63#define MEMHANDLERS_NEED_FLAGS 0\r
64#define MEMHANDLERS_NEED_CYCLES 1\r
65#define MEMHANDLERS_CHANGE_PC 0\r
66#define MEMHANDLERS_CHANGE_FLAGS 0\r
67#define MEMHANDLERS_CHANGE_CYCLES 1\r
68\r
69/*\r
70 * If enabled, Cyclone will call .IrqCallback routine from it's context whenever it\r
71 * acknowledges an IRQ. IRQ level (.irq) is not cleared automatically, do this in your\r
72 * handler if needed.\r
73 * This function must either return vector number to use for interrupt exception,\r
74 * CYCLONE_INT_ACK_AUTOVECTOR to use autovector (this is the most common case), or\r
75 * CYCLONE_INT_ACK_SPURIOUS (least common case).\r
76 * If disabled, it simply uses appropriate autovector, clears the IRQ level and\r
77 * continues execution.\r
78 */\r
79#define USE_INT_ACK_CALLBACK 1\r
80\r
81/*\r
82 * Enable this if you need old PC, flags or cycles;\r
83 * or you change cycles in your IrqCallback function.\r
84 */\r
85#define INT_ACK_NEEDS_STUFF 0\r
86#define INT_ACK_CHANGES_CYCLES 0\r
87\r
88/*\r
89 * If enabled, .ResetCallback is called from the context, whenever RESET opcode is\r
90 * encountered. All context members are valid and can be changed.\r
91 * If disabled, RESET opcode acts as an NOP.\r
92 */\r
93#define USE_RESET_CALLBACK 0\r
94\r
95/*\r
96 * If enabled, UnrecognizedCallback is called if an invalid opcode is\r
97 * encountered. All context members are valid and can be changed. The handler\r
98 * should return zero if you want Cyclone to gererate "Illegal Instruction"\r
99 * exception after this, or nonzero if not. In the later case you should change\r
100 * the PC by yourself, or else Cyclone will keep executing that opcode all over\r
101 * again.\r
102 * If disabled, "Illegal Instruction" exception is generated and execution is\r
103 * continued.\r
104 */\r
105#define USE_UNRECOGNIZED_CALLBACK 1\r
106\r
107/*\r
108 * This option will also call UnrecognizedCallback for a-line and f-line\r
109 * (0xa*** and 0xf***) opcodes the same way as described above, only appropriate\r
110 * exceptions will be generated.\r
111 */\r
112#define USE_AFLINE_CALLBACK 1\r
113\r
114/*\r
115 * This makes Cyclone to call checkpc from it's context whenever it changes the PC\r
116 * by a large value. It takes and should return the PC value in PC+membase form.\r
117 * The flags and cycle counter are not valid in this function.\r
118 */\r
119#define USE_CHECKPC_CALLBACK 1\r
120\r
121/*\r
122 * This determines if checkpc() should be called after jumps when 8 and 16 bit\r
123 * displacement values were used.\r
124 */\r
125#define USE_CHECKPC_OFFSETBITS_16 1\r
126#define USE_CHECKPC_OFFSETBITS_8 0\r
127\r
128/*\r
129 * Call checkpc() after DBcc jumps (which use 16bit displacement). Cyclone prior to\r
130 * 0.0087 never did that.\r
131 */\r
132#define USE_CHECKPC_DBRA 0\r
133\r
134/*\r
135 * When this option is enabled Cyclone will do two word writes instead of one\r
136 * long write when handling MOVE.L with pre-decrementing destination, as described in\r
137 * Bart Trzynadlowski's doc (http://www.trzy.org/files/68knotes.txt).\r
138 * Enable this if you are emulating a 16 bit system.\r
139 */\r
140#define SPLIT_MOVEL_PD 1\r
141\r
142/*\r
143 * Enable emulation of trace mode. Shouldn't cause any performance decrease, so it\r
144 * should be safe to keep this ON.\r
145 */\r
146#define EMULATE_TRACE 1\r
147\r
148/*\r
149 * If enabled, address error exception will be generated if 68k code jumps to an\r
150 * odd address. Causes very small performance hit (2 ARM instructions for every\r
151 * emulated jump/return/exception in normal case).\r
152 * Note: checkpc() must not clear least significant bit of rebased address\r
153 * for this to work, as checks are performed after calling checkpc().\r
154 */\r
155#define EMULATE_ADDRESS_ERRORS_JUMP 1\r
156\r
157/*\r
158 * If enabled, address error exception will be generated if 68k code tries to\r
159 * access a word or longword at an odd address. The performance cost is also 2 ARM\r
160 * instructions per access (for address error checks).\r
161 */\r
162#define EMULATE_ADDRESS_ERRORS_IO 1\r
163\r
164/*\r
165 * If an address error happens during another address error processing,\r
166 * the processor halts until it is reset (catastrophic system failure, as the manual\r
167 * states). This option enables halt emulation.\r
168 * Note that this might be not desired if it is known that emulated system should\r
169 * never reach this state.\r
170 */\r
171#define EMULATE_HALT 0\r
172\r