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[picodrive.git] / cpu / DrZ80 / drz80.s
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cc68a136 1;@ Reesy's Z80 Emulator Version 0.001\r
2\r
3;@ (c) Copyright 2004 Reesy, All rights reserved\r
4;@ DrZ80 is free for non-commercial use.\r
5\r
6;@ For commercial use, separate licencing terms must be obtained.\r
7\r
8 .data\r
9 .align 4\r
10\r
11 .global DrZ80Run\r
12 .global DrZ80Ver\r
13\r
14 .equiv INTERRUPT_MODE, 0 ;@0 = Use internal int handler, 1 = Use Mames int handler\r
15 .equiv FAST_Z80SP, 1 ;@0 = Use mem functions for stack pointer, 1 = Use direct mem pointer\r
16 .equiv UPDATE_CONTEXT, 0\r
17 .equiv DRZ80_FOR_PICODRIVE, 1\r
18\r
19.if INTERRUPT_MODE\r
20 .extern Interrupt\r
21.endif\r
22\r
23.if DRZ80_FOR_PICODRIVE\r
24 .extern YM2612Read_\r
25 .extern YM2612Read_940\r
26 .extern PicoRead8\r
27 .extern Pico\r
28 .extern z80_write\r
29.endif\r
30\r
31DrZ80Ver: .long 0x0001\r
32\r
33;@ --------------------------- Defines ----------------------------\r
34;@ Make sure that regs/pointers for z80pc to z80sp match up!\r
35\r
36 opcodes .req r3\r
37 z80_icount .req r4\r
38 cpucontext .req r5\r
39 z80pc .req r6\r
40 z80a .req r7\r
41 z80f .req r8\r
42 z80bc .req r9\r
43 z80de .req r10\r
44 z80hl .req r11\r
45 z80sp .req r12 \r
46 z80xx .req lr\r
47\r
48 .equ z80pc_pointer, 0 ;@ 0\r
49 .equ z80a_pointer, z80pc_pointer+4 ;@ 4\r
50 .equ z80f_pointer, z80a_pointer+4 ;@ 8\r
51 .equ z80bc_pointer, z80f_pointer+4 ;@ \r
52 .equ z80de_pointer, z80bc_pointer+4\r
53 .equ z80hl_pointer, z80de_pointer+4\r
54 .equ z80sp_pointer, z80hl_pointer+4\r
55 .equ z80pc_base, z80sp_pointer+4\r
56 .equ z80sp_base, z80pc_base+4\r
57 .equ z80ix, z80sp_base+4\r
58 .equ z80iy, z80ix+4\r
59 .equ z80i, z80iy+4\r
60 .equ z80a2, z80i+4\r
61 .equ z80f2, z80a2+4\r
62 .equ z80bc2, z80f2+4\r
63 .equ z80de2, z80bc2+4\r
64 .equ z80hl2, z80de2+4\r
65 .equ cycles_pointer, z80hl2+4 \r
66 .equ previouspc, cycles_pointer+4 \r
67 .equ z80irq, previouspc+4\r
68 .equ z80if, z80irq+1\r
69 .equ z80im, z80if+1\r
70 .equ z80r, z80im+1\r
71 .equ z80irqvector, z80r+1\r
72 .equ z80irqcallback, z80irqvector+4\r
73 .equ z80_write8, z80irqcallback+4\r
74 .equ z80_write16, z80_write8+4\r
75 .equ z80_in, z80_write16+4\r
76 .equ z80_out, z80_in+4\r
77 .equ z80_read8, z80_out+4\r
78 .equ z80_read16, z80_read8+4\r
79 .equ z80_rebaseSP, z80_read16+4\r
80 .equ z80_rebasePC, z80_rebaseSP+4\r
81\r
82 .equ VFlag, 0\r
83 .equ CFlag, 1\r
84 .equ ZFlag, 2\r
85 .equ SFlag, 3\r
86 .equ HFlag, 4\r
87 .equ NFlag, 5\r
88 .equ Flag3, 6\r
89 .equ Flag5, 7\r
90\r
91 .equ Z80_CFlag, 0\r
92 .equ Z80_NFlag, 1\r
93 .equ Z80_VFlag, 2\r
94 .equ Z80_Flag3, 3\r
95 .equ Z80_HFlag, 4\r
96 .equ Z80_Flag5, 5\r
97 .equ Z80_ZFlag, 6\r
98 .equ Z80_SFlag, 7\r
99\r
100 .equ Z80_IF1, 1<<0\r
101 .equ Z80_IF2, 1<<1\r
102 .equ Z80_HALT, 1<<2\r
103\r
104;@---------------------------------------\r
105\r
106.text\r
107\r
108.if DRZ80_FOR_PICODRIVE\r
109.include "port_config.s"\r
110\r
111.macro YM2612Read_and_ret8\r
112 stmfd sp!,{r3,r12,lr}\r
113.if EXTERNAL_YM2612\r
114 ldr r1,=PicoOpt\r
115 ldr r1,[r1]\r
116 tst r1,#0x200\r
117 bne 10f\r
118 bl YM2612Read_\r
119 ldmfd sp!,{r3,r12,pc}\r
12010:\r
121 bl YM2612Read_940\r
122.else\r
123 bl YM2612Read_\r
124.endif\r
125 ldmfd sp!,{r3,r12,pc}\r
126.endm\r
127\r
128.macro YM2612Read_and_ret16\r
129 stmfd sp!,{r3,r12,lr}\r
130.if EXTERNAL_YM2612\r
131 ldr r0,=PicoOpt\r
132 ldr r0,[r0]\r
133 tst r0,#0x200\r
134 bne 10f\r
135 bl YM2612Read_\r
136 orr r0,r0,r0,lsl #8\r
137 ldmfd sp!,{r3,r12,pc}\r
13810:\r
139 bl YM2612Read_940\r
140 orr r0,r0,r0,lsl #8\r
141.else\r
142 bl YM2612Read_\r
143 orr r0,r0,r0,lsl #8\r
144.endif\r
145 ldmfd sp!,{r3,r12,pc}\r
146.endm\r
147\r
148pico_z80_read8: @ addr\r
149 cmp r0,#0x2000 @ Z80 RAM\r
150 ldrlt r1,[cpucontext,#z80sp_base]\r
151 ldrltb r0,[r1,r0]\r
152 bxlt lr\r
153\r
154 cmp r0,#0x8000 @ 68k bank\r
155 blt 1f\r
156 ldr r2,=(Pico+0x22212)\r
157 ldrh r1,[r2]\r
158 bic r0,r0,#0x3f8000\r
159 orr r0,r0,r1,lsl #15\r
160 ldr r1,[r2,#-0xe] @ ROM size\r
161 cmp r0,r1\r
162 ldrlt r1,[r2,#-0x12] @ ROM\r
163 eorlt r0,r0,#1 @ our ROM is byteswapped\r
164 ldrltb r0,[r1,r0]\r
165 bxlt lr\r
166 stmfd sp!,{r3,r12,lr}\r
167 bl PicoRead8\r
168 ldmfd sp!,{r3,r12,pc}\r
1691:\r
170 mov r1,r0,lsr #13\r
171 cmp r1,#2 @ YM2612 (0x4000-0x5fff)\r
172 bne 0f\r
173 and r0,r0,#3\r
174 YM2612Read_and_ret8\r
1750:\r
176 cmp r0,#0x4000\r
177 movge r0,#0xff\r
178 bxge lr\r
179 ldr r1,[cpucontext,#z80sp_base]\r
180 bic r0,r0,#0x0fe000 @ Z80 RAM (mirror)\r
181 ldrb r0,[r1,r0]\r
182 bx lr\r
183\r
184pico_z80_read16: @ addr\r
185 cmp r0,#0x2000 @ Z80 RAM\r
186 bge 2f\r
187 ldr r1,[cpucontext,#z80sp_base]\r
188 ldrb r0,[r1,r0]!\r
189 ldrb r1,[r1,#1]\r
190 orr r0,r0,r1,lsl #8\r
191 bx lr\r
192\r
1932:\r
194 cmp r0,#0x8000 @ 68k bank\r
195 blt 1f\r
196 ldr r2,=(Pico+0x22212)\r
197 ldrh r1,[r2]\r
198 bic r0,r0,#0x1f8000\r
199 orr r0,r0,r1,lsl #15\r
200 ldr r1,[r2,#-0xe] @ ROM size\r
201 cmp r0,r1\r
202 ldr r1,[r2,#-0x12] @ ROM\r
203 tst r0,#1\r
204 eor r0,r0,#1\r
205 ldrb r0,[r1,r0]!\r
206 ldreqb r1,[r1,#-1]\r
207 ldrneb r1,[r1,#3] @ this is due to byteswapped ROM\r
208 orr r0,r0,r1,lsl #8\r
209 bx lr\r
2103:\r
211 stmfd sp!,{r3-r5,r12,lr}\r
212 mov r4,r0\r
213 bl PicoRead8\r
214 mov r5,r0\r
215 add r0,r4,#1\r
216 bl PicoRead8\r
217 orr r0,r5,r0,lsl #8\r
218 ldmfd sp!,{r3-r5,r12,pc}\r
2191:\r
220 mov r1,r0,lsr #13\r
221 cmp r1,#2 @ YM2612 (0x4000-0x5fff)\r
222 bne 0f\r
223 and r0,r0,#3\r
224 YM2612Read_and_ret16\r
2250:\r
226 cmp r0,#0x4000\r
227 movge r0,#0xff\r
228 bxge lr\r
229 ldr r1,[cpucontext,#z80sp_base]\r
230 bic r0,r0,#0x0fe000 @ Z80 RAM (mirror)\r
231 ldrb r0,[r1,r0]!\r
232 ldrb r1,[r1,#1]\r
233 orr r0,r0,r1,lsl #8\r
234 bx lr\r
235\r
236pico_z80_write8: @ data, addr\r
237 cmp r1,#0x4000\r
238 bge 1f\r
239 ldr r2,[cpucontext,#z80sp_base]\r
240 bic r1,r1,#0x0fe000 @ Z80 RAM\r
241 strb r0,[r2,r1]\r
242 bx lr\r
2431:\r
244 stmfd sp!,{r3,r12,lr}\r
245 bl z80_write\r
246 ldmfd sp!,{r3,r12,pc}\r
247\r
248pico_z80_write16: @ data, addr\r
249 cmp r1,#0x4000\r
250 bge 1f\r
251 ldr r2,[cpucontext,#z80sp_base]\r
252 bic r1,r1,#0x0fe000 @ Z80 RAM\r
253 strb r0,[r2,r1]!\r
254 mov r0,r0,lsr #8\r
255 strb r0,[r2,#1]\r
256 bx lr\r
2571:\r
258 stmfd sp!,{r3-r5,r12,lr}\r
259 mov r4,r0\r
260 mov r5,r1\r
261 bl z80_write\r
262 mov r0,r4,lsr #8\r
263 add r1,r5,#1\r
264 bl z80_write\r
265 ldmfd sp!,{r3-r5,r12,pc}\r
266\r
267 .pool\r
268.endif\r
269\r
270.macro fetch cycs\r
271 subs z80_icount,z80_icount,#\cycs\r
272.if UPDATE_CONTEXT\r
273 str z80pc,[cpucontext,#z80pc_pointer]\r
274 str z80_icount,[cpucontext,#cycles_pointer]\r
275 ldr r1,[cpucontext,#z80pc_base]\r
276 sub r2,z80pc,r1\r
277 str r2,[cpucontext,#previouspc]\r
278.endif\r
279 ldrplb r0,[z80pc],#1\r
280 ldrpl pc,[opcodes,r0, lsl #2]\r
281 bmi z80_execute_end\r
282.endm\r
283\r
284.macro eatcycles cycs\r
285 sub z80_icount,z80_icount,#\cycs\r
286.if UPDATE_CONTEXT\r
287 str z80_icount,[cpucontext,#cycles_pointer]\r
288.endif\r
289.endm\r
290\r
291.macro readmem8\r
292.if UPDATE_CONTEXT\r
293 str z80pc,[cpucontext,#z80pc_pointer]\r
294.endif\r
295.if DRZ80_FOR_PICODRIVE\r
296 bl pico_z80_read8\r
297.else\r
298 stmfd sp!,{r3,r12}\r
299 mov lr,pc\r
300 ldr pc,[cpucontext,#z80_read8] ;@ r0 = addr - data returned in r0\r
301 ldmfd sp!,{r3,r12}\r
302.endif\r
303.endm\r
304\r
305.macro readmem8HL\r
306 mov r0,z80hl, lsr #16\r
307 readmem8\r
308.endm\r
309\r
310.macro readmem16\r
311.if UPDATE_CONTEXT\r
312 str z80pc,[cpucontext,#z80pc_pointer]\r
313.endif\r
314.if DRZ80_FOR_PICODRIVE\r
315 bl pico_z80_read16\r
316.else\r
317 stmfd sp!,{r3,r12}\r
318 mov lr,pc\r
319 ldr pc,[cpucontext,#z80_read16]\r
320 ldmfd sp!,{r3,r12}\r
321.endif\r
322.endm\r
323\r
324.macro writemem8\r
325.if UPDATE_CONTEXT\r
326 str z80pc,[cpucontext,#z80pc_pointer]\r
327.endif\r
328.if DRZ80_FOR_PICODRIVE\r
329 bl pico_z80_write8\r
330.else\r
331 stmfd sp!,{r3,r12}\r
332 mov lr,pc\r
333 ldr pc,[cpucontext,#z80_write8] ;@ r0=data r1=addr\r
334 ldmfd sp!,{r3,r12}\r
335.endif\r
336.endm\r
337\r
338.macro writemem8DE\r
339 mov r1,z80de, lsr #16\r
340 writemem8\r
341.endm\r
342\r
343.macro writemem8HL\r
344 mov r1,z80hl, lsr #16\r
345 writemem8\r
346.endm\r
347\r
348.macro writemem16\r
349.if UPDATE_CONTEXT\r
350 str z80pc,[cpucontext,#z80pc_pointer]\r
351.endif\r
352.if DRZ80_FOR_PICODRIVE\r
353 bl pico_z80_write16\r
354.else\r
355 stmfd sp!,{r3,r12}\r
356 mov lr,pc\r
357 ldr pc,[cpucontext,#z80_write16] ;@ r0=data r1=addr\r
358 ldmfd sp!,{r3,r12}\r
359.endif\r
360.endm\r
361\r
362.macro copymem8HL_DE\r
363.if UPDATE_CONTEXT\r
364 str z80pc,[cpucontext,#z80pc_pointer]\r
365.endif\r
366 mov r0,z80hl, lsr #16\r
367.if DRZ80_FOR_PICODRIVE\r
368 bl pico_z80_read8\r
369.else\r
370 stmfd sp!,{r3,r12}\r
371 mov lr,pc\r
372 ldr pc,[cpucontext,#z80_read8] ;@ r0 = addr - data returned in r0\r
373.endif\r
374.if UPDATE_CONTEXT\r
375 str z80pc,[cpucontext,#z80pc_pointer]\r
376.endif\r
377 mov r1,z80de, lsr #16\r
378.if DRZ80_FOR_PICODRIVE\r
379 bl pico_z80_write8\r
380.else\r
381 mov lr,pc\r
382 ldr pc,[cpucontext,#z80_write8] ;@ r0=data r1=addr\r
383 ldmfd sp!,{r3,r12}\r
384.endif\r
385.endm\r
386;@---------------------------------------\r
387\r
388.macro rebasepc\r
389.if UPDATE_CONTEXT\r
390 str z80pc,[cpucontext,#z80pc_pointer]\r
391.endif\r
392.if DRZ80_FOR_PICODRIVE\r
393 bic r0,r0,#0xfe000\r
394 ldr r1,[cpucontext,#z80pc_base]\r
395 add z80pc,r1,r0\r
396.else\r
397 stmfd sp!,{r3,r12}\r
398 mov lr,pc\r
399 ldr pc,[cpucontext,#z80_rebasePC] ;@ r0=new pc - external function sets z80pc_base and returns new z80pc in r0\r
400 ldmfd sp!,{r3,r12}\r
401 mov z80pc,r0\r
402.endif\r
403.endm\r
404\r
405.macro rebasesp\r
406.if UPDATE_CONTEXT\r
407 str z80pc,[cpucontext,#z80pc_pointer]\r
408.endif\r
409.if DRZ80_FOR_PICODRIVE\r
410 bic r0,r0,#0xfe000\r
411 ldr r1,[cpucontext,#z80sp_base]\r
412 add r0,r1,r0\r
413.else\r
414 stmfd sp!,{r3,r12}\r
415 mov lr,pc\r
416 ldr pc,[cpucontext,#z80_rebaseSP] ;@ external function must rebase sp\r
417 ldmfd sp!,{r3,r12}\r
418.endif\r
419.endm\r
420;@----------------------------------------------------------------------------\r
421\r
422.macro opADC\r
423 movs z80f,z80f,lsr#2 ;@ get C\r
424 subcs r0,r0,#0x100\r
425 eor z80f,r0,z80a,lsr#24 ;@ prepare for check of half carry\r
426 adcs z80a,z80a,r0,ror#8\r
427 mrs r0,cpsr ;@ S,Z,V&C\r
428 eor z80f,z80f,z80a,lsr#24\r
429 and z80f,z80f,#1<<HFlag ;@ H, correct\r
430 orr z80f,z80f,r0,lsr#28\r
431.endm\r
432\r
433.macro opADCA\r
434 movs z80f,z80f,lsr#2 ;@ get C\r
435 orrcs z80a,z80a,#0x00800000\r
436 adds z80a,z80a,z80a\r
437 mrs z80f,cpsr ;@ S,Z,V&C\r
438 mov z80f,z80f,lsr#28\r
439 tst z80a,#0x10000000 ;@ H, correct\r
440 orrne z80f,z80f,#1<<HFlag\r
441 fetch 4\r
442.endm\r
443\r
444.macro opADCH reg\r
445 mov r0,\reg,lsr#24\r
446 opADC\r
447 fetch 4\r
448.endm\r
449\r
450.macro opADCL reg\r
451 movs z80f,z80f,lsr#2 ;@ get C\r
452 adc r0,\reg,\reg,lsr#15\r
453 orrcs z80a,z80a,#0x00800000\r
454 mov r1,z80a,lsl#4 ;@ Prepare for check of half carry\r
455 adds z80a,z80a,r0,lsl#23\r
456 mrs z80f,cpsr ;@ S,Z,V&C\r
457 mov z80f,z80f,lsr#28\r
458 cmn r1,r0,lsl#27\r
459 orrcs z80f,z80f,#1<<HFlag ;@ H, correct\r
460 fetch 4\r
461.endm\r
462\r
463.macro opADCb\r
464 opADC\r
465.endm\r
466;@---------------------------------------\r
467\r
468.macro opADD reg shift\r
469 mov r1,z80a,lsl#4 ;@ Prepare for check of half carry\r
470 adds z80a,z80a,\reg,lsl#\shift\r
471 mrs z80f,cpsr ;@ S,Z,V&C\r
472 mov z80f,z80f,lsr#28\r
473 cmn r1,\reg,lsl#\shift+4\r
474 orrcs z80f,z80f,#1<<HFlag\r
475.endm\r
476\r
477.macro opADDA\r
478 adds z80a,z80a,z80a\r
479 mrs z80f,cpsr ;@ S,Z,V&C\r
480 mov z80f,z80f,lsr#28\r
481 tst z80a,#0x10000000 ;@ H, correct\r
482 orrne z80f,z80f,#1<<HFlag\r
483 fetch 4\r
484.endm\r
485\r
486.macro opADDH reg\r
487 and r0,\reg,#0xFF000000\r
488 opADD r0 0\r
489 fetch 4\r
490.endm\r
491\r
492.macro opADDL reg\r
493 opADD \reg 8\r
494 fetch 4\r
495.endm\r
496\r
497.macro opADDb \r
498 opADD r0 24\r
499.endm\r
500;@---------------------------------------\r
501\r
502.macro opADC16 reg\r
503 movs z80f,z80f,lsr#2 ;@ get C\r
504 adc r0,z80a,\reg,lsr#15\r
505 orrcs z80hl,z80hl,#0x00008000\r
506 mov r1,z80hl,lsl#4\r
507 adds z80hl,z80hl,r0,lsl#15\r
508 mrs z80f,cpsr ;@ S, Z, V & C\r
509 mov z80f,z80f,lsr#28\r
510 cmn r1,r0,lsl#19\r
511 orrcs z80f,z80f,#1<<HFlag\r
512 fetch 15\r
513.endm\r
514\r
515.macro opADC16HL\r
516 movs z80f,z80f,lsr#2 ;@ get C\r
517 orrcs z80hl,z80hl,#0x00008000\r
518 adds z80hl,z80hl,z80hl\r
519 mrs z80f,cpsr ;@ S, Z, V & C\r
520 mov z80f,z80f,lsr#28\r
521 tst z80hl,#0x10000000 ;@ H, correct.\r
522 orrne z80f,z80f,#1<<HFlag\r
523 fetch 15\r
524.endm\r
525\r
526.macro opADD16 reg1 reg2\r
527 mov r1,\reg1,lsl#4 ;@ Prepare for check of half carry\r
528 adds \reg1,\reg1,\reg2\r
529 bic z80f,z80f,#(1<<CFlag)|(1<<HFlag)|(1<<NFlag)\r
530 orrcs z80f,z80f,#1<<CFlag\r
531 cmn r1,\reg2,lsl#4\r
532 orrcs z80f,z80f,#1<<HFlag\r
533.endm\r
534\r
535.macro opADD16s reg1 reg2 shift\r
536 mov r1,\reg1,lsl#4 ;@ Prepare for check of half carry\r
537 adds \reg1,\reg1,\reg2,lsl#\shift\r
538 bic z80f,z80f,#(1<<CFlag)|(1<<HFlag)|(1<<NFlag)\r
539 orrcs z80f,z80f,#1<<CFlag\r
540 cmn r1,\reg2,lsl#4+\shift\r
541 orrcs z80f,z80f,#1<<HFlag\r
542.endm\r
543\r
544.macro opADD16_2 reg\r
545 adds \reg,\reg,\reg\r
546 bic z80f,z80f,#(1<<CFlag)|(1<<HFlag)|(1<<NFlag)\r
547 orrcs z80f,z80f,#1<<CFlag\r
548 tst \reg,#0x10000000 ;@ H, correct.\r
549 orrne z80f,z80f,#1<<HFlag\r
550.endm\r
551;@---------------------------------------\r
552\r
553.macro opAND reg shift\r
554 and z80a,z80a,\reg,lsl#\shift\r
555 sub r0,opcodes,#0x100\r
556 ldrb z80f,[r0,z80a, lsr #24]\r
557 orr z80f,z80f,#1<<HFlag\r
558.endm\r
559\r
560.macro opANDA\r
561 sub r0,opcodes,#0x100\r
562 ldrb z80f,[r0,z80a, lsr #24]\r
563 orr z80f,z80f,#1<<HFlag\r
564 fetch 4\r
565.endm\r
566\r
567.macro opANDH reg\r
568 opAND \reg 0\r
569 fetch 4\r
570.endm\r
571\r
572.macro opANDL reg\r
573 opAND \reg 8\r
574 fetch 4\r
575.endm\r
576\r
577.macro opANDb\r
578 opAND r0 24\r
579.endm\r
580;@---------------------------------------\r
581\r
582.macro opBITH reg bit\r
583 and z80f,z80f,#1<<CFlag\r
584 tst \reg,#1<<(24+\bit)\r
585 orreq z80f,z80f,#(1<<HFlag)|(1<<ZFlag)|(1<<VFlag)\r
586 orrne z80f,z80f,#(1<<HFlag)\r
587 fetch 8\r
588.endm\r
589\r
590.macro opBIT7H reg\r
591 and z80f,z80f,#1<<CFlag\r
592 tst \reg,#1<<(24+7)\r
593 orreq z80f,z80f,#(1<<HFlag)|(1<<ZFlag)|(1<<VFlag)\r
594 orrne z80f,z80f,#(1<<HFlag)|(1<<SFlag)\r
595 fetch 8\r
596.endm\r
597\r
598.macro opBITL reg bit\r
599 and z80f,z80f,#1<<CFlag\r
600 tst \reg,#1<<(16+\bit)\r
601 orreq z80f,z80f,#(1<<HFlag)|(1<<ZFlag)|(1<<VFlag)\r
602 orrne z80f,z80f,#(1<<HFlag)\r
603 fetch 8\r
604.endm\r
605\r
606.macro opBIT7L reg\r
607 and z80f,z80f,#1<<CFlag\r
608 tst \reg,#1<<(16+7)\r
609 orreq z80f,z80f,#(1<<HFlag)|(1<<ZFlag)|(1<<VFlag)\r
610 orrne z80f,z80f,#(1<<HFlag)|(1<<SFlag)\r
611 fetch 8\r
612.endm\r
613\r
614.macro opBITb bit\r
615 and z80f,z80f,#1<<CFlag\r
616 tst r0,#1<<\bit\r
617 orreq z80f,z80f,#(1<<HFlag)|(1<<ZFlag)|(1<<VFlag)\r
618 orrne z80f,z80f,#(1<<HFlag)\r
619.endm\r
620\r
621.macro opBIT7b\r
622 and z80f,z80f,#1<<CFlag\r
623 tst r0,#1<<7\r
624 orreq z80f,z80f,#(1<<HFlag)|(1<<ZFlag)|(1<<VFlag)\r
625 orrne z80f,z80f,#(1<<HFlag)|(1<<SFlag)\r
626.endm\r
627;@---------------------------------------\r
628\r
629.macro opCP reg shift\r
630 mov r1,z80a,lsl#4 ;@ prepare for check of half carry\r
631 cmp z80a,\reg,lsl#\shift\r
632 mrs z80f,cpsr\r
633 mov z80f,z80f,lsr#28 ;@ S,Z,V&C\r
634 eor z80f,z80f,#(1<<CFlag)|(1<<NFlag) ;@ invert C and set n\r
635 cmp r1,\reg,lsl#\shift+4\r
636 orrcc z80f,z80f,#1<<HFlag\r
637.endm\r
638\r
639.macro opCPA\r
640 mov z80f,#(1<<ZFlag)|(1<<NFlag) ;@ set Z & n\r
641 fetch 4\r
642.endm\r
643\r
644.macro opCPH reg\r
645 and r0,\reg,#0xFF000000\r
646 opCP r0 0\r
647 fetch 4\r
648.endm\r
649\r
650.macro opCPL reg\r
651 opCP \reg 8\r
652 fetch 4\r
653.endm\r
654\r
655.macro opCPb\r
656 opCP r0 24\r
657.endm\r
658;@---------------------------------------\r
659\r
660.macro opDEC8 reg ;@for A and memory\r
661 and z80f,z80f,#1<<CFlag ;@save carry\r
662 orr z80f,z80f,#1<<NFlag ;@set n\r
663 tst \reg,#0x0f000000\r
664 orreq z80f,z80f,#1<<HFlag\r
665 subs \reg,\reg,#0x01000000\r
666 orrmi z80f,z80f,#1<<SFlag\r
667 orrvs z80f,z80f,#1<<VFlag\r
668 orreq z80f,z80f,#1<<ZFlag\r
669.endm\r
670\r
671.macro opDEC8H reg ;@for B, D & H\r
672 and z80f,z80f,#1<<CFlag ;@save carry\r
673 orr z80f,z80f,#1<<NFlag ;@set n\r
674 tst \reg,#0x0f000000\r
675 orreq z80f,z80f,#1<<HFlag\r
676 subs \reg,\reg,#0x01000000\r
677 orrmi z80f,z80f,#1<<SFlag\r
678 orrvs z80f,z80f,#1<<VFlag\r
679 tst \reg,#0xff000000 ;@Z\r
680 orreq z80f,z80f,#1<<ZFlag\r
681.endm\r
682\r
683.macro opDEC8L reg ;@for C, E & L\r
684 mov \reg,\reg,ror#24\r
685 opDEC8H \reg\r
686 mov \reg,\reg,ror#8\r
687.endm\r
688\r
689.macro opDEC8b ;@for memory\r
690 mov r0,r0,lsl#24\r
691 opDEC8 r0\r
692 mov r0,r0,lsr#24\r
693.endm\r
694;@---------------------------------------\r
695\r
696.macro opIN\r
697 stmfd sp!,{r3,r12}\r
698 mov lr,pc\r
699 ldr pc,[cpucontext,#z80_in] ;@ r0=port - data returned in r0\r
700 ldmfd sp!,{r3,r12}\r
701.endm\r
702\r
703.macro opIN_C\r
704 mov r0,z80bc, lsr #16\r
705 opIN\r
706.endm\r
707;@---------------------------------------\r
708\r
709.macro opINC8 reg ;@for A and memory\r
710 and z80f,z80f,#1<<CFlag ;@save carry, clear n\r
711 adds \reg,\reg,#0x01000000\r
712 orrmi z80f,z80f,#1<<SFlag\r
713 orrvs z80f,z80f,#1<<VFlag\r
714 orrcs z80f,z80f,#1<<ZFlag ;@cs when going from 0xFF to 0x00\r
715 tst \reg,#0x0f000000\r
716 orreq z80f,z80f,#1<<HFlag\r
717.endm\r
718\r
719.macro opINC8H reg ;@for B, D & H\r
720 opINC8 \reg\r
721.endm\r
722\r
723.macro opINC8L reg ;@for C, E & L\r
724 mov \reg,\reg,ror#24\r
725 opINC8 \reg\r
726 mov \reg,\reg,ror#8\r
727.endm\r
728\r
729.macro opINC8b ;@for memory\r
730 mov r0,r0,lsl#24\r
731 opINC8 r0\r
732 mov r0,r0,lsr#24\r
733.endm\r
734;@---------------------------------------\r
735\r
736.macro opOR reg shift\r
737 orr z80a,z80a,\reg,lsl#\shift\r
738 sub r0,opcodes,#0x100\r
739 ldrb z80f,[r0,z80a, lsr #24]\r
740.endm\r
741\r
742.macro opORA\r
743 sub r0,opcodes,#0x100\r
744 ldrb z80f,[r0,z80a, lsr #24]\r
745 fetch 4\r
746.endm\r
747\r
748.macro opORH reg\r
749 and r0,\reg,#0xFF000000\r
750 opOR r0 0\r
751 fetch 4\r
752.endm\r
753\r
754.macro opORL reg\r
755 opOR \reg 8\r
756 fetch 4\r
757.endm\r
758\r
759.macro opORb\r
760 opOR r0 24\r
761.endm\r
762;@---------------------------------------\r
763\r
764.macro opOUT\r
765 stmfd sp!,{r3,r12}\r
766 mov lr,pc\r
767 ldr pc,[cpucontext,#z80_out] ;@ r0=port r1=data\r
768 ldmfd sp!,{r3,r12}\r
769.endm\r
770\r
771.macro opOUT_C\r
772 mov r0,z80bc, lsr #16\r
773 opOUT\r
774.endm\r
775;@---------------------------------------\r
776\r
777.macro opPOP\r
778.if FAST_Z80SP\r
779.if DRZ80_FOR_PICODRIVE\r
780 @ notaz: try to protect against stack overflows, which tend to happen in Picodrive because of poor timing\r
781 ldr r2,[cpucontext,#z80sp_base]\r
782 ldrb r0,[z80sp],#1\r
783 add r2,r2,#0x2000\r
784 cmp z80sp,r2\r
785@ subge z80sp,z80sp,#0x2000 @ unstable?\r
786 ldrb r1,[z80sp],#1\r
787 cmp z80sp,r2\r
788@ subge z80sp,z80sp,#0x2000\r
789 orr r0,r0,r1, lsl #8\r
790.else\r
791 ldrb r0,[z80sp],#1\r
792 ldrb r1,[z80sp],#1\r
793 orr r0,r0,r1, lsl #8\r
794.endif\r
795.else\r
796 mov r0,z80sp\r
797 readmem16\r
798 add z80sp,z80sp,#2\r
799.endif\r
800.endm\r
801\r
802.macro opPOPreg reg\r
803 opPOP\r
804 mov \reg,r0, lsl #16\r
805 fetch 10\r
806.endm\r
807;@---------------------------------------\r
808\r
809.macro opPUSHareg reg @ reg > r1\r
810.if FAST_Z80SP\r
811.if DRZ80_FOR_PICODRIVE\r
812 @ notaz: try to protect against stack overflows, which tend to happen in Picodrive because of poor timing\r
813 ldr r0,[cpucontext,#z80sp_base]\r
814 cmp z80sp,r0\r
815 addle z80sp,z80sp,#0x2000\r
816 mov r1,\reg, lsr #8\r
817 strb r1,[z80sp,#-1]!\r
818 cmp z80sp,r0\r
819 addle z80sp,z80sp,#0x2000\r
820 strb \reg,[z80sp,#-1]!\r
821.else\r
822 mov r1,\reg, lsr #8\r
823 strb r1,[z80sp,#-1]!\r
824 strb \reg,[z80sp,#-1]!\r
825.endif\r
826.else\r
827 mov r0,\reg\r
828 sub z80sp,z80sp,#2\r
829 mov r1,z80sp\r
830 writemem16\r
831.endif\r
832.endm\r
833\r
834.macro opPUSHreg reg\r
835.if FAST_Z80SP\r
836.if DRZ80_FOR_PICODRIVE\r
837 ldr r0,[cpucontext,#z80sp_base]\r
838 cmp z80sp,r0\r
839 addle z80sp,z80sp,#0x2000\r
840 mov r1,\reg, lsr #24\r
841 strb r1,[z80sp,#-1]!\r
842 cmp z80sp,r0\r
843 addle z80sp,z80sp,#0x2000\r
844 mov r1,\reg, lsr #16\r
845 strb r1,[z80sp,#-1]!\r
846.else\r
847 mov r1,\reg, lsr #24\r
848 strb r1,[z80sp,#-1]!\r
849 mov r1,\reg, lsr #16\r
850 strb r1,[z80sp,#-1]!\r
851.endif\r
852.else\r
853 mov r0,\reg,lsr #16\r
854 sub z80sp,z80sp,#2\r
855 mov r1,z80sp\r
856 writemem16\r
857.endif\r
858.endm\r
859;@---------------------------------------\r
860\r
861.macro opRESmemHL bit\r
862.if DRZ80_FOR_PICODRIVE\r
863 mov r0,z80hl, lsr #16\r
864 bl pico_z80_read8\r
865 bic r0,r0,#1<<\bit\r
866 mov r1,z80hl, lsr #16\r
867 bl pico_z80_write8\r
868.else\r
869 mov r0,z80hl, lsr #16\r
870 stmfd sp!,{r3,r12}\r
871 mov lr,pc\r
872 ldr pc,[cpucontext,#z80_read8] ;@ r0 = addr - data returned in r0\r
873 bic r0,r0,#1<<\bit\r
874 mov r1,z80hl, lsr #16\r
875 mov lr,pc\r
876 ldr pc,[cpucontext,#z80_write8] ;@ r0=data r1=addr\r
877 ldmfd sp!,{r3,r12}\r
878.endif\r
879 fetch 15\r
880.endm\r
881;@---------------------------------------\r
882\r
883.macro opRESmem bit\r
884.if DRZ80_FOR_PICODRIVE\r
885 stmfd sp!,{r0} ;@ save addr as well\r
886 bl pico_z80_read8\r
887 bic r0,r0,#1<<\bit\r
888 ldmfd sp!,{r1} ;@ restore addr into r1\r
889 bl pico_z80_write8\r
890.else\r
891 stmfd sp!,{r3,r12}\r
892 stmfd sp!,{r0} ;@ save addr as well\r
893 mov lr,pc\r
894 ldr pc,[cpucontext,#z80_read8] ;@ r0=addr - data returned in r0\r
895 bic r0,r0,#1<<\bit\r
896 ldmfd sp!,{r1} ;@ restore addr into r1\r
897 mov lr,pc\r
898 ldr pc,[cpucontext,#z80_write8] ;@ r0=data r1=addr\r
899 ldmfd sp!,{r3,r12}\r
900.endif\r
901 fetch 23\r
902.endm\r
903;@---------------------------------------\r
904\r
905.macro opRL reg1 reg2 shift\r
906 movs \reg1,\reg2,lsl \shift\r
907 tst z80f,#1<<CFlag ;@doesn't affect ARM carry, as long as the imidiate value is < 0x100. Watch out!\r
908 orrne \reg1,\reg1,#0x01000000\r
909;@ and r2,z80f,#1<<CFlag\r
910;@ orr $x,$x,r2,lsl#23\r
911 sub r1,opcodes,#0x100\r
912 ldrb z80f,[r1,\reg1,lsr#24] ;@get PZS\r
913 orrcs z80f,z80f,#1<<CFlag\r
914.endm\r
915\r
916.macro opRLA\r
917 opRL z80a, z80a, #1\r
918 fetch 8\r
919.endm\r
920\r
921.macro opRLH reg\r
922 and r0,\reg,#0xFF000000 ;@mask high to r0\r
923 adds \reg,\reg,r0\r
924 tst z80f,#1<<CFlag ;@doesn't affect ARM carry, as long as the imidiate value is < 0x100. Watch out!\r
925 orrne \reg,\reg,#0x01000000\r
926 sub r1,opcodes,#0x100\r
927 ldrb z80f,[r1,\reg,lsr#24] ;@get PZS\r
928 orrcs z80f,z80f,#1<<CFlag\r
929 fetch 8\r
930.endm\r
931\r
932.macro opRLL reg\r
933 opRL r0, \reg, #9\r
934 and \reg,\reg,#0xFF000000 ;@mask out high\r
935 orr \reg,\reg,r0,lsr#8\r
936 fetch 8\r
937.endm\r
938\r
939.macro opRLb\r
940 opRL r0, r0, #25\r
941 mov r0,r0,lsr#24\r
942.endm\r
943;@---------------------------------------\r
944\r
945.macro opRLC reg1 reg2 shift\r
946 movs \reg1,\reg2,lsl#\shift\r
947 orrcs \reg1,\reg1,#0x01000000\r
948 sub r1,opcodes,#0x100\r
949 ldrb z80f,[r1,\reg1,lsr#24]\r
950 orrcs z80f,z80f,#1<<CFlag\r
951.endm\r
952\r
953.macro opRLCA\r
954 opRLC z80a, z80a, 1\r
955 fetch 8\r
956.endm\r
957\r
958.macro opRLCH reg\r
959 and r0,\reg,#0xFF000000 ;@mask high to r0\r
960 adds \reg,\reg,r0\r
961 orrcs \reg,\reg,#0x01000000\r
962 sub r1,opcodes,#0x100\r
963 ldrb z80f,[r1,\reg,lsr#24]\r
964 orrcs z80f,z80f,#1<<CFlag\r
965 fetch 8\r
966.endm\r
967\r
968.macro opRLCL reg\r
969 opRLC r0, \reg, 9\r
970 and \reg,\reg,#0xFF000000 ;@mask out high\r
971 orr \reg,\reg,r0,lsr#8\r
972 fetch 8\r
973.endm\r
974\r
975.macro opRLCb\r
976 opRLC r0, r0, 25\r
977 mov r0,r0,lsr#24\r
978.endm\r
979;@---------------------------------------\r
980\r
981.macro opRR reg1 reg2 shift\r
982 movs \reg1,\reg2,lsr#\shift\r
983 tst z80f,#1<<CFlag ;@doesn't affect ARM carry, as long as the imidiate value is < 0x100. Watch out!\r
984 orrne \reg1,\reg1,#0x00000080\r
985;@ and r2,z80_f,#PSR_C\r
986;@ orr \reg1,\reg1,r2,lsl#6\r
987 sub r1,opcodes,#0x100\r
988 ldrb z80f,[r1,\reg1]\r
989 orrcs z80f,z80f,#1<<CFlag\r
990.endm\r
991\r
992.macro opRRA\r
993 orr z80a,z80a,z80f,lsr#1 ;@get C\r
994 movs z80a,z80a,ror#25\r
995 mov z80a,z80a,lsl#24\r
996 sub r1,opcodes,#0x100\r
997 ldrb z80f,[r1,z80a,lsr#24]\r
998 orrcs z80f,z80f,#1<<CFlag\r
999 fetch 8\r
1000.endm\r
1001\r
1002.macro opRRH reg\r
1003 orr r0,\reg,z80f,lsr#1 ;@get C\r
1004 movs r0,r0,ror#25\r
1005 and \reg,\reg,#0x00FF0000 ;@mask out low\r
1006 orr \reg,\reg,r0,lsl#24\r
1007 sub r1,opcodes,#0x100\r
1008 ldrb z80f,[r1,\reg,lsr#24]\r
1009 orrcs z80f,z80f,#1<<CFlag\r
1010 fetch 8\r
1011.endm\r
1012\r
1013.macro opRRL reg\r
1014 and r0,\reg,#0x00FF0000 ;@mask out low to r0\r
1015 opRR r0 r0 17\r
1016 and \reg,\reg,#0xFF000000 ;@mask out high\r
1017 orr \reg,\reg,r0,lsl#16\r
1018 fetch 8\r
1019.endm\r
1020\r
1021.macro opRRb\r
1022 opRR r0 r0 1\r
1023.endm\r
1024;@---------------------------------------\r
1025\r
1026.macro opRRC reg1 reg2 shift\r
1027 movs \reg1,\reg2,lsr#\shift\r
1028 orrcs \reg1,\reg1,#0x00000080\r
1029 sub r1,opcodes,#0x100\r
1030 ldrb z80f,[r1,\reg1]\r
1031 orrcs z80f,z80f,#1<<CFlag\r
1032.endm\r
1033\r
1034.macro opRRCA\r
1035 opRRC z80a, z80a, 25\r
1036 mov z80a,z80a,lsl#24\r
1037 fetch 8\r
1038.endm\r
1039\r
1040.macro opRRCH reg\r
1041 opRRC r0, \reg, 25\r
1042 and \reg,\reg,#0x00FF0000 ;@mask out low\r
1043 orr \reg,\reg,r0,lsl#24\r
1044 fetch 8\r
1045.endm\r
1046\r
1047.macro opRRCL reg\r
1048 and r0,\reg,#0x00FF0000 ;@mask low to r0\r
1049 opRRC r0, r0, 17\r
1050 and \reg,\reg,#0xFF000000 ;@mask out high\r
1051 orr \reg,\reg,r0,lsl#16\r
1052 fetch 8\r
1053.endm\r
1054\r
1055.macro opRRCb\r
1056 opRRC r0, r0, 1\r
1057.endm\r
1058;@---------------------------------------\r
1059\r
1060.macro opRST addr\r
1061 ldr r0,[cpucontext,#z80pc_base]\r
1062 sub r2,z80pc,r0\r
1063 opPUSHareg r2\r
1064 mov r0,#\addr\r
1065 rebasepc\r
1066 fetch 11\r
1067.endm\r
1068;@---------------------------------------\r
1069\r
1070.macro opSBC\r
1071 eor z80f,z80f,#1<<CFlag ;@ invert C\r
1072 movs z80f,z80f,lsr#2 ;@ get C\r
1073 subcc r0,r0,#0x100\r
1074 eor z80f,r0,z80a,lsr#24 ;@ prepare for check of H\r
1075 sbcs z80a,z80a,r0,ror#8\r
1076 mrs r0,cpsr\r
1077 eor z80f,z80f,z80a,lsr#24\r
1078 and z80f,z80f,#1<<HFlag ;@ H, correct\r
1079 orr z80f,z80f,r0,lsr#28 ;@ S,Z,V&C\r
1080 eor z80f,z80f,#(1<<CFlag)|(1<<NFlag) ;@ invert C and set n.\r
1081.endm\r
1082\r
1083.macro opSBCA\r
1084 movs z80f,z80f,lsr#2 ;@ get C\r
1085 movcc z80a,#0x00000000\r
1086 movcs z80a,#0xFF000000\r
1087 movcc z80f,#(1<<NFlag)|(1<<ZFlag)\r
1088 movcs z80f,#(1<<NFlag)|(1<<SFlag)|(1<<CFlag)|(1<<HFlag)\r
1089 fetch 4\r
1090.endm\r
1091\r
1092.macro opSBCH reg\r
1093 mov r0,\reg,lsr#24\r
1094 opSBC\r
1095 fetch 4\r
1096.endm\r
1097\r
1098.macro opSBCL reg\r
1099 mov r0,\reg,lsl#8\r
1100 eor z80f,z80f,#1<<CFlag ;@ invert C\r
1101 movs z80f,z80f,lsr#2 ;@ get C\r
1102 sbccc r0,r0,#0xFF000000\r
1103 mov r1,z80a,lsl#4 ;@ prepare for check of H\r
1104 sbcs z80a,z80a,r0\r
1105 mrs z80f,cpsr\r
1106 mov z80f,z80f,lsr#28 ;@ S,Z,V&C\r
1107 eor z80f,z80f,#(1<<CFlag)|(1<<NFlag) ;@ invert C and set n.\r
1108 cmp r1,r0,lsl#4\r
1109 orrcc z80f,z80f,#1<<HFlag ;@ H, correct\r
1110 fetch 4\r
1111.endm\r
1112\r
1113.macro opSBCb\r
1114 opSBC\r
1115.endm\r
1116;@---------------------------------------\r
1117\r
1118.macro opSBC16 reg\r
1119 eor z80f,z80f,#1<<CFlag ;@ invert C\r
1120 movs z80f,z80f,lsr#2 ;@ get C\r
1121 sbc r1,r1,r1 ;@ set r1 to -1 or 0.\r
1122 orr r0,\reg,r1,lsr#16\r
1123 mov r1,z80hl,lsl#4 ;@ prepare for check of H\r
1124 sbcs z80hl,z80hl,r0\r
1125 mrs z80f,cpsr\r
1126 mov z80f,z80f,lsr#28 ;@ S,Z,V&C\r
1127 eor z80f,z80f,#(1<<CFlag)|(1<<NFlag) ;@ invert C and set n.\r
1128 cmp r1,r0,lsl#4\r
1129 orrcc z80f,z80f,#1<<HFlag ;@ H, correct\r
1130 fetch 15\r
1131.endm\r
1132\r
1133.macro opSBC16HL\r
1134 movs z80f,z80f,lsr#2 ;@ get C\r
1135 mov z80hl,#0x00000000\r
1136 subcs z80hl,z80hl,#0x00010000\r
1137 movcc z80f,#(1<<NFlag)|(1<<ZFlag)\r
1138 movcs z80f,#(1<<NFlag)|(1<<SFlag)|(1<<CFlag)|(1<<HFlag)\r
1139 fetch 15\r
1140.endm\r
1141;@---------------------------------------\r
1142\r
1143.macro opSETmemHL bit\r
1144.if DRZ80_FOR_PICODRIVE\r
1145 mov r0,z80hl, lsr #16\r
1146 bl pico_z80_read8\r
1147 orr r0,r0,#1<<\bit\r
1148 mov r1,z80hl, lsr #16\r
1149 bl pico_z80_write8\r
1150.else\r
1151 mov r0,z80hl, lsr #16\r
1152 stmfd sp!,{r3,r12}\r
1153 mov lr,pc\r
1154 ldr pc,[cpucontext,#z80_read8] ;@ r0 = addr - data returned in r0\r
1155 orr r0,r0,#1<<\bit\r
1156 mov r1,z80hl, lsr #16\r
1157 mov lr,pc\r
1158 ldr pc,[cpucontext,#z80_write8] ;@ r0=data r1=addr\r
1159 ldmfd sp!,{r3,r12}\r
1160.endif\r
1161 fetch 15\r
1162.endm\r
1163;@---------------------------------------\r
1164\r
1165.macro opSETmem bit\r
1166.if DRZ80_FOR_PICODRIVE\r
1167 stmfd sp!,{r0} ;@ save addr as well\r
1168 bl pico_z80_read8\r
1169 orr r0,r0,#1<<\bit\r
1170 ldmfd sp!,{r1} ;@ restore addr into r1\r
1171 bl pico_z80_write8\r
1172.else\r
1173 stmfd sp!,{r3,r12}\r
1174 stmfd sp!,{r0} ;@ save addr as well\r
1175 mov lr,pc\r
1176 ldr pc,[cpucontext,#z80_read8] ;@ r0=addr - data returned in r0\r
1177 orr r0,r0,#1<<\bit\r
1178 ldmfd sp!,{r1} ;@ restore addr into r1\r
1179 mov lr,pc\r
1180 ldr pc,[cpucontext,#z80_write8] ;@ r0=data r1=addr\r
1181 ldmfd sp!,{r3,r12}\r
1182.endif\r
1183 fetch 23\r
1184.endm\r
1185;@---------------------------------------\r
1186\r
1187.macro opSLA reg1 reg2 shift\r
1188 movs \reg1,\reg2,lsl#\shift\r
1189 sub r1,opcodes,#0x100\r
1190 ldrb z80f,[r1,\reg1,lsr#24]\r
1191 orrcs z80f,z80f,#1<<CFlag\r
1192.endm\r
1193\r
1194.macro opSLAA\r
1195 opSLA z80a, z80a, 1\r
1196 fetch 8\r
1197.endm\r
1198\r
1199.macro opSLAH reg\r
1200 and r0,\reg,#0xFF000000 ;@mask high to r0\r
1201 adds \reg,\reg,r0\r
1202 sub r1,opcodes,#0x100\r
1203 ldrb z80f,[r1,\reg,lsr#24]\r
1204 orrcs z80f,z80f,#1<<CFlag\r
1205 fetch 8\r
1206.endm\r
1207\r
1208.macro opSLAL reg\r
1209 opSLA r0, \reg, 9\r
1210 and \reg,\reg,#0xFF000000 ;@mask out high\r
1211 orr \reg,\reg,r0,lsr#8\r
1212 fetch 8\r
1213.endm\r
1214\r
1215.macro opSLAb\r
1216 opSLA r0, r0, 25\r
1217 mov r0,r0,lsr#24\r
1218.endm\r
1219;@---------------------------------------\r
1220\r
1221.macro opSLL reg1 reg2 shift\r
1222 movs \reg1,\reg2,lsl#\shift\r
1223 orr \reg1,\reg1,#0x01000000\r
1224 sub r1,opcodes,#0x100\r
1225 ldrb z80f,[r1,\reg1,lsr#24]\r
1226 orrcs z80f,z80f,#1<<CFlag\r
1227.endm\r
1228\r
1229.macro opSLLA\r
1230 opSLL z80a, z80a, 1\r
1231 fetch 8\r
1232.endm\r
1233\r
1234.macro opSLLH reg\r
1235 and r0,\reg,#0xFF000000 ;@mask high to r0\r
1236 adds \reg,\reg,r0\r
1237 orr \reg,\reg,#0x01000000\r
1238 sub r1,opcodes,#0x100\r
1239 ldrb z80f,[r1,\reg,lsr#24]\r
1240 orrcs z80f,z80f,#1<<CFlag\r
1241 fetch 8\r
1242.endm\r
1243\r
1244.macro opSLLL reg\r
1245 opSLL r0, \reg, 9\r
1246 and \reg,\reg,#0xFF000000 ;@mask out high\r
1247 orr \reg,\reg,r0,lsr#8\r
1248 fetch 8\r
1249.endm\r
1250\r
1251.macro opSLLb\r
1252 opSLL r0, r0, 25\r
1253 mov r0,r0,lsr#24\r
1254.endm\r
1255;@---------------------------------------\r
1256\r
1257.macro opSRA reg1 reg2\r
1258 movs \reg1,\reg2,asr#25\r
1259 and \reg1,\reg1,#0xFF\r
1260 sub r1,opcodes,#0x100\r
1261 ldrb z80f,[r1,\reg1]\r
1262 orrcs z80f,z80f,#1<<CFlag\r
1263.endm\r
1264\r
1265.macro opSRAA\r
1266 movs r0,z80a,asr#25\r
1267 mov z80a,r0,lsl#24\r
1268 sub r1,opcodes,#0x100\r
1269 ldrb z80f,[r1,z80a,lsr#24]\r
1270 orrcs z80f,z80f,#1<<CFlag\r
1271 fetch 8\r
1272.endm\r
1273\r
1274.macro opSRAH reg\r
1275 movs r0,\reg,asr#25\r
1276 and \reg,\reg,#0x00FF0000 ;@mask out low\r
1277 orr \reg,\reg,r0,lsl#24\r
1278 sub r1,opcodes,#0x100\r
1279 ldrb z80f,[r1,\reg,lsr#24]\r
1280 orrcs z80f,z80f,#1<<CFlag\r
1281 fetch 8\r
1282.endm\r
1283\r
1284.macro opSRAL reg\r
1285 mov r0,\reg,lsl#8\r
1286 opSRA r0, r0\r
1287 and \reg,\reg,#0xFF000000 ;@mask out high\r
1288 orr \reg,\reg,r0,lsl#16\r
1289 fetch 8\r
1290.endm\r
1291\r
1292.macro opSRAb\r
1293 mov r0,r0,lsl#24\r
1294 opSRA r0, r0\r
1295.endm\r
1296;@---------------------------------------\r
1297\r
1298.macro opSRL reg1 reg2 shift\r
1299 movs \reg1,\reg2,lsr#\shift\r
1300 sub r1,opcodes,#0x100\r
1301 ldrb z80f,[r1,\reg1]\r
1302 orrcs z80f,z80f,#1<<CFlag\r
1303.endm\r
1304\r
1305.macro opSRLA\r
1306 opSRL z80a, z80a, 25\r
1307 mov z80a,z80a,lsl#24\r
1308 fetch 8\r
1309.endm\r
1310\r
1311.macro opSRLH reg\r
1312 opSRL r0, \reg, 25\r
1313 and \reg,\reg,#0x00FF0000 ;@mask out low\r
1314 orr \reg,\reg,r0,lsl#24\r
1315 fetch 8\r
1316.endm\r
1317\r
1318.macro opSRLL reg\r
1319 mov r0,\reg,lsl#8\r
1320 opSRL r0, r0, 25\r
1321 and \reg,\reg,#0xFF000000 ;@mask out high\r
1322 orr \reg,\reg,r0,lsl#16\r
1323 fetch 8\r
1324.endm\r
1325\r
1326.macro opSRLb\r
1327 opSRL r0, r0, 1\r
1328.endm\r
1329;@---------------------------------------\r
1330\r
1331.macro opSUB reg shift\r
1332 mov r1,z80a,lsl#4 ;@ Prepare for check of half carry\r
1333 subs z80a,z80a,\reg,lsl#\shift\r
1334 mrs z80f,cpsr\r
1335 mov z80f,z80f,lsr#28 ;@ S,Z,V&C\r
1336 eor z80f,z80f,#(1<<CFlag)|(1<<NFlag) ;@ invert C and set n\r
1337 cmp r1,\reg,lsl#\shift+4\r
1338 orrcc z80f,z80f,#1<<HFlag\r
1339.endm\r
1340\r
1341.macro opSUBA\r
1342 mov z80a,#0\r
1343 mov z80f,#(1<<ZFlag)|(1<<NFlag) ;@ set Z & n\r
1344 fetch 4\r
1345.endm\r
1346\r
1347.macro opSUBH reg\r
1348 and r0,\reg,#0xFF000000\r
1349 opSUB r0, 0\r
1350 fetch 4\r
1351.endm\r
1352\r
1353.macro opSUBL reg\r
1354 opSUB \reg, 8\r
1355 fetch 4\r
1356.endm\r
1357\r
1358.macro opSUBb\r
1359 opSUB r0, 24\r
1360.endm\r
1361;@---------------------------------------\r
1362\r
1363.macro opXOR reg shift\r
1364 eor z80a,z80a,\reg,lsl#\shift\r
1365 sub r0,opcodes,#0x100\r
1366 ldrb z80f,[r0,z80a, lsr #24]\r
1367.endm\r
1368\r
1369.macro opXORA\r
1370 mov z80a,#0\r
1371 mov z80f,#(1<<ZFlag)|(1<<VFlag)\r
1372 fetch 4\r
1373.endm\r
1374\r
1375.macro opXORH reg\r
1376 and r0,\reg,#0xFF000000\r
1377 opXOR r0, 0\r
1378 fetch 4\r
1379.endm\r
1380\r
1381.macro opXORL reg\r
1382 opXOR \reg, 8\r
1383 fetch 4\r
1384.endm\r
1385\r
1386.macro opXORb\r
1387 opXOR r0, 24\r
1388.endm\r
1389;@---------------------------------------\r
1390\r
1391\r
1392;@ --------------------------- Framework --------------------------\r
1393 \r
1394.text\r
1395\r
1396DrZ80Run:\r
1397 ;@ r0 = pointer to cpu context\r
1398 ;@ r1 = ISTATES to execute \r
1399 ;@######################################### \r
1400 stmdb sp!,{r4-r12,lr} ;@ save registers on stack\r
1401 mov cpucontext,r0 ;@ setup main memory pointer\r
1402 mov z80_icount,r1 ;@ setup number of Tstates to execute\r
1403\r
1404.if INTERRUPT_MODE == 0\r
1405 ldrh r0,[cpucontext,#z80irq] @ 0x4C\r
1406.endif\r
1407 ldmia cpucontext,{z80pc-z80sp} ;@ load Z80 registers\r
1408\r
1409.if INTERRUPT_MODE == 0\r
1410 ;@ check ints\r
1411 tst r0,#1\r
1412 movnes r0,r0,lsr #8\r
1413 blne DoInterrupt\r
1414.endif\r
1415\r
1416 ldrb r0,[z80pc],#1 ;@ get first op code\r
1417 ldr opcodes,MAIN_opcodes_POINTER2\r
1418 ldr pc,[opcodes,r0, lsl #2] ;@ execute op code\r
1419\r
1420MAIN_opcodes_POINTER2: .word MAIN_opcodes\r
1421\r
1422\r
1423z80_execute_end:\r
1424 ;@ save registers in CPU context\r
1425 stmia cpucontext,{z80pc-z80sp} ;@ save Z80 registers\r
1426 mov r0,z80_icount\r
1427 ldmia sp!,{r4-r12,pc} ;@ restore registers from stack and return to C code\r
1428\r
1429.if INTERRUPT_MODE\r
1430Interrupt_local: .word Interrupt\r
1431.endif\r
1432\r
1433DoInterrupt:\r
1434.if INTERRUPT_MODE\r
1435 ;@ Don't do own int handler, call mames instead\r
1436\r
1437 ;@ save everything back into DrZ80 context\r
1438 stmia cpucontext,{z80pc-z80sp} ;@ save Z80 registers\r
1439 stmfd sp!,{r3,r4,r5,lr} ;@ save rest of regs on stack\r
1440 mov lr,pc\r
1441 ldr pc,Interrupt_local\r
1442 ldmfd sp!,{r3,r4,r5,lr} ;@ load regs from stack\r
1443 ;@ reload regs from DrZ80 context\r
1444 ldmia cpucontext,{z80pc-z80sp} ;@ load Z80 registers\r
1445 mov pc,lr ;@ return\r
1446.else\r
1447 stmfd sp!,{lr}\r
1448\r
1449 tst r0,#4 ;@ check halt\r
1450 addne z80pc,z80pc,#1\r
1451\r
1452 ldrb r1,[cpucontext,#z80im]\r
1453\r
1454 ;@ clear halt and int flags\r
1455 eor r0,r0,r0\r
1456 strb r0,[cpucontext,#z80if]\r
1457\r
1458 ;@ now check int mode\r
1459 tst r1,#1\r
1460 bne DoInterrupt_mode1\r
1461 tst r1,#2\r
1462 bne DoInterrupt_mode2\r
1463 b DoInterrupt_mode0\r
1464\r
1465DoInterrupt_mode0:\r
1466 ;@ get 3 byte vector\r
1467 ldr r2,[cpucontext, #z80irqvector]\r
1468 and r1,r2,#0xFF0000\r
1469 cmp r1,#0xCD0000 ;@ call\r
1470 bne 1f\r
1471 ;@ ########\r
1472 ;@ # call\r
1473 ;@ ########\r
1474 ;@ save current pc on stack\r
1475 ldr r0,[cpucontext,#z80pc_base]\r
1476 sub r0,z80pc,r0\r
1477.if FAST_Z80SP\r
1478 mov r1,r0, lsr #8\r
1479 strb r1,[z80sp,#-1]!\r
1480 strb r0,[z80sp,#-1]!\r
1481.else\r
1482 sub z80sp,z80sp,#2\r
1483 mov r1,z80sp\r
1484 writemem16\r
1485 ldr r2,[cpucontext, #z80irqvector]\r
1486.endif\r
1487 ;@ jump to vector\r
1488 mov r2,r2,lsl#16\r
1489 mov r0,r2,lsr#16\r
1490 ;@ rebase new pc\r
1491 rebasepc\r
1492\r
1493 b DoInterrupt_end\r
1494\r
14951:\r
1496 cmp r1,#0xC30000 ;@ jump\r
1497 bne DoInterrupt_mode1 ;@ rst\r
1498 ;@ #######\r
1499 ;@ # jump\r
1500 ;@ #######\r
1501 ;@ jump to vector\r
1502 mov r2,r2,lsl#16\r
1503 mov r0,r2,lsr#16\r
1504 ;@ rebase new pc\r
1505 rebasepc\r
1506\r
1507 b DoInterrupt_end\r
1508\r
1509DoInterrupt_mode1:\r
1510 ldr r0,[cpucontext,#z80pc_base]\r
1511 sub r2,z80pc,r0\r
1512 opPUSHareg r2\r
1513 mov r0,#0x38\r
1514 rebasepc\r
1515\r
1516 b DoInterrupt_end\r
1517\r
1518DoInterrupt_mode2:\r
1519 ;@ push pc on stack\r
1520 ldr r0,[cpucontext,#z80pc_base]\r
1521 sub r2,z80pc,r0\r
1522 opPUSHareg r2\r
1523\r
1524 ;@ get 1 byte vector address\r
1525 ldrb r0,[cpucontext, #z80irqvector]\r
1526 ldr r1,[cpucontext, #z80i]\r
1527 orr r0,r0,r1,lsr#16\r
1528\r
1529 ;@ read new pc from vector address\r
1530.if DRZ80_FOR_PICODRIVE\r
1531 bl pico_z80_read16\r
1532 bic r0,r0,#0xfe000\r
1533 ldr r1,[cpucontext,#z80pc_base]\r
1534 add z80pc,r1,r0\r
1535.if UPDATE_CONTEXT\r
1536 str z80pc,[cpucontext,#z80pc_pointer]\r
1537.endif\r
1538.else\r
1539 stmfd sp!,{r3,r12}\r
1540 mov lr,pc\r
1541 ldr pc,[cpucontext,#z80_read16]\r
1542\r
1543 ;@ rebase new pc\r
1544.if UPDATE_CONTEXT\r
1545 str z80pc,[cpucontext,#z80pc_pointer]\r
1546.endif\r
1547 mov lr,pc\r
1548 ldr pc,[cpucontext,#z80_rebasePC] ;@ r0=new pc - external function sets z80pc_base and returns new z80pc in r0\r
1549 ldmfd sp!,{r3,r12}\r
1550 mov z80pc,r0 \r
1551.endif\r
1552\r
1553DoInterrupt_end:\r
1554 ;@ interupt accepted so callback irq interface\r
1555 ldr r0,[cpucontext, #z80irqcallback]\r
1556 tst r0,r0\r
1557 ldmeqfd sp!,{pc}\r
1558 stmfd sp!,{r3,r12}\r
1559 mov lr,pc\r
1560 mov pc,r0 ;@ call callback function\r
1561 ldmfd sp!,{r3,r12}\r
1562 ldmfd sp!,{pc} ;@ return\r
1563\r
1564.endif\r
1565\r
1566.data\r
1567.align 4\r
1568\r
1569DAATable: .hword (0x00<<8)|(1<<ZFlag)|(1<<VFlag)\r
1570 .hword (0x01<<8) \r
1571 .hword (0x02<<8) \r
1572 .hword (0x03<<8) |(1<<VFlag)\r
1573 .hword (0x04<<8) \r
1574 .hword (0x05<<8) |(1<<VFlag)\r
1575 .hword (0x06<<8) |(1<<VFlag)\r
1576 .hword (0x07<<8) \r
1577 .hword (0x08<<8) \r
1578 .hword (0x09<<8) |(1<<VFlag)\r
1579 .hword (0x10<<8) |(1<<HFlag) \r
1580 .hword (0x11<<8) |(1<<HFlag) |(1<<VFlag)\r
1581 .hword (0x12<<8) |(1<<HFlag) |(1<<VFlag)\r
1582 .hword (0x13<<8) |(1<<HFlag) \r
1583 .hword (0x14<<8) |(1<<HFlag) |(1<<VFlag)\r
1584 .hword (0x15<<8) |(1<<HFlag) \r
1585 .hword (0x10<<8) \r
1586 .hword (0x11<<8) |(1<<VFlag)\r
1587 .hword (0x12<<8) |(1<<VFlag)\r
1588 .hword (0x13<<8) \r
1589 .hword (0x14<<8) |(1<<VFlag)\r
1590 .hword (0x15<<8) \r
1591 .hword (0x16<<8) \r
1592 .hword (0x17<<8) |(1<<VFlag)\r
1593 .hword (0x18<<8) |(1<<VFlag)\r
1594 .hword (0x19<<8) \r
1595 .hword (0x20<<8) |(1<<HFlag) \r
1596 .hword (0x21<<8) |(1<<HFlag) |(1<<VFlag)\r
1597 .hword (0x22<<8) |(1<<HFlag) |(1<<VFlag)\r
1598 .hword (0x23<<8) |(1<<HFlag) \r
1599 .hword (0x24<<8) |(1<<HFlag) |(1<<VFlag)\r
1600 .hword (0x25<<8) |(1<<HFlag) \r
1601 .hword (0x20<<8) \r
1602 .hword (0x21<<8) |(1<<VFlag)\r
1603 .hword (0x22<<8) |(1<<VFlag)\r
1604 .hword (0x23<<8) \r
1605 .hword (0x24<<8) |(1<<VFlag)\r
1606 .hword (0x25<<8) \r
1607 .hword (0x26<<8) \r
1608 .hword (0x27<<8) |(1<<VFlag)\r
1609 .hword (0x28<<8) |(1<<VFlag)\r
1610 .hword (0x29<<8) \r
1611 .hword (0x30<<8) |(1<<HFlag) |(1<<VFlag)\r
1612 .hword (0x31<<8) |(1<<HFlag) \r
1613 .hword (0x32<<8) |(1<<HFlag) \r
1614 .hword (0x33<<8) |(1<<HFlag) |(1<<VFlag)\r
1615 .hword (0x34<<8) |(1<<HFlag) \r
1616 .hword (0x35<<8) |(1<<HFlag) |(1<<VFlag)\r
1617 .hword (0x30<<8) |(1<<VFlag)\r
1618 .hword (0x31<<8) \r
1619 .hword (0x32<<8) \r
1620 .hword (0x33<<8) |(1<<VFlag)\r
1621 .hword (0x34<<8) \r
1622 .hword (0x35<<8) |(1<<VFlag)\r
1623 .hword (0x36<<8) |(1<<VFlag)\r
1624 .hword (0x37<<8) \r
1625 .hword (0x38<<8) \r
1626 .hword (0x39<<8) |(1<<VFlag)\r
1627 .hword (0x40<<8) |(1<<HFlag) \r
1628 .hword (0x41<<8) |(1<<HFlag) |(1<<VFlag)\r
1629 .hword (0x42<<8) |(1<<HFlag) |(1<<VFlag)\r
1630 .hword (0x43<<8) |(1<<HFlag) \r
1631 .hword (0x44<<8) |(1<<HFlag) |(1<<VFlag)\r
1632 .hword (0x45<<8) |(1<<HFlag) \r
1633 .hword (0x40<<8) \r
1634 .hword (0x41<<8) |(1<<VFlag)\r
1635 .hword (0x42<<8) |(1<<VFlag)\r
1636 .hword (0x43<<8) \r
1637 .hword (0x44<<8) |(1<<VFlag)\r
1638 .hword (0x45<<8) \r
1639 .hword (0x46<<8) \r
1640 .hword (0x47<<8) |(1<<VFlag)\r
1641 .hword (0x48<<8) |(1<<VFlag)\r
1642 .hword (0x49<<8) \r
1643 .hword (0x50<<8) |(1<<HFlag) |(1<<VFlag)\r
1644 .hword (0x51<<8) |(1<<HFlag) \r
1645 .hword (0x52<<8) |(1<<HFlag) \r
1646 .hword (0x53<<8) |(1<<HFlag) |(1<<VFlag)\r
1647 .hword (0x54<<8) |(1<<HFlag) \r
1648 .hword (0x55<<8) |(1<<HFlag) |(1<<VFlag)\r
1649 .hword (0x50<<8) |(1<<VFlag)\r
1650 .hword (0x51<<8) \r
1651 .hword (0x52<<8) \r
1652 .hword (0x53<<8) |(1<<VFlag)\r
1653 .hword (0x54<<8) \r
1654 .hword (0x55<<8) |(1<<VFlag)\r
1655 .hword (0x56<<8) |(1<<VFlag)\r
1656 .hword (0x57<<8) \r
1657 .hword (0x58<<8) \r
1658 .hword (0x59<<8) |(1<<VFlag)\r
1659 .hword (0x60<<8) |(1<<HFlag) |(1<<VFlag)\r
1660 .hword (0x61<<8) |(1<<HFlag) \r
1661 .hword (0x62<<8) |(1<<HFlag) \r
1662 .hword (0x63<<8) |(1<<HFlag) |(1<<VFlag)\r
1663 .hword (0x64<<8) |(1<<HFlag) \r
1664 .hword (0x65<<8) |(1<<HFlag) |(1<<VFlag)\r
1665 .hword (0x60<<8) |(1<<VFlag)\r
1666 .hword (0x61<<8) \r
1667 .hword (0x62<<8) \r
1668 .hword (0x63<<8) |(1<<VFlag)\r
1669 .hword (0x64<<8) \r
1670 .hword (0x65<<8) |(1<<VFlag)\r
1671 .hword (0x66<<8) |(1<<VFlag)\r
1672 .hword (0x67<<8) \r
1673 .hword (0x68<<8) \r
1674 .hword (0x69<<8) |(1<<VFlag)\r
1675 .hword (0x70<<8) |(1<<HFlag) \r
1676 .hword (0x71<<8) |(1<<HFlag) |(1<<VFlag)\r
1677 .hword (0x72<<8) |(1<<HFlag) |(1<<VFlag)\r
1678 .hword (0x73<<8) |(1<<HFlag) \r
1679 .hword (0x74<<8) |(1<<HFlag) |(1<<VFlag)\r
1680 .hword (0x75<<8) |(1<<HFlag) \r
1681 .hword (0x70<<8) \r
1682 .hword (0x71<<8) |(1<<VFlag)\r
1683 .hword (0x72<<8) |(1<<VFlag)\r
1684 .hword (0x73<<8) \r
1685 .hword (0x74<<8) |(1<<VFlag)\r
1686 .hword (0x75<<8) \r
1687 .hword (0x76<<8) \r
1688 .hword (0x77<<8) |(1<<VFlag)\r
1689 .hword (0x78<<8) |(1<<VFlag)\r
1690 .hword (0x79<<8) \r
1691 .hword (0x80<<8)|(1<<SFlag) |(1<<HFlag) \r
1692 .hword (0x81<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag)\r
1693 .hword (0x82<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag)\r
1694 .hword (0x83<<8)|(1<<SFlag) |(1<<HFlag) \r
1695 .hword (0x84<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag)\r
1696 .hword (0x85<<8)|(1<<SFlag) |(1<<HFlag) \r
1697 .hword (0x80<<8)|(1<<SFlag) \r
1698 .hword (0x81<<8)|(1<<SFlag) |(1<<VFlag)\r
1699 .hword (0x82<<8)|(1<<SFlag) |(1<<VFlag)\r
1700 .hword (0x83<<8)|(1<<SFlag) \r
1701 .hword (0x84<<8)|(1<<SFlag) |(1<<VFlag)\r
1702 .hword (0x85<<8)|(1<<SFlag) \r
1703 .hword (0x86<<8)|(1<<SFlag) \r
1704 .hword (0x87<<8)|(1<<SFlag) |(1<<VFlag)\r
1705 .hword (0x88<<8)|(1<<SFlag) |(1<<VFlag)\r
1706 .hword (0x89<<8)|(1<<SFlag) \r
1707 .hword (0x90<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag)\r
1708 .hword (0x91<<8)|(1<<SFlag) |(1<<HFlag) \r
1709 .hword (0x92<<8)|(1<<SFlag) |(1<<HFlag) \r
1710 .hword (0x93<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag)\r
1711 .hword (0x94<<8)|(1<<SFlag) |(1<<HFlag) \r
1712 .hword (0x95<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag)\r
1713 .hword (0x90<<8)|(1<<SFlag) |(1<<VFlag)\r
1714 .hword (0x91<<8)|(1<<SFlag) \r
1715 .hword (0x92<<8)|(1<<SFlag) \r
1716 .hword (0x93<<8)|(1<<SFlag) |(1<<VFlag)\r
1717 .hword (0x94<<8)|(1<<SFlag) \r
1718 .hword (0x95<<8)|(1<<SFlag) |(1<<VFlag)\r
1719 .hword (0x96<<8)|(1<<SFlag) |(1<<VFlag)\r
1720 .hword (0x97<<8)|(1<<SFlag) \r
1721 .hword (0x98<<8)|(1<<SFlag) \r
1722 .hword (0x99<<8)|(1<<SFlag) |(1<<VFlag)\r
1723 .hword (0x00<<8) |(1<<ZFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1724 .hword (0x01<<8) |(1<<HFlag) |(1<<CFlag)\r
1725 .hword (0x02<<8) |(1<<HFlag) |(1<<CFlag)\r
1726 .hword (0x03<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1727 .hword (0x04<<8) |(1<<HFlag) |(1<<CFlag)\r
1728 .hword (0x05<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1729 .hword (0x00<<8) |(1<<ZFlag) |(1<<VFlag) |(1<<CFlag)\r
1730 .hword (0x01<<8) |(1<<CFlag)\r
1731 .hword (0x02<<8) |(1<<CFlag)\r
1732 .hword (0x03<<8) |(1<<VFlag) |(1<<CFlag)\r
1733 .hword (0x04<<8) |(1<<CFlag)\r
1734 .hword (0x05<<8) |(1<<VFlag) |(1<<CFlag)\r
1735 .hword (0x06<<8) |(1<<VFlag) |(1<<CFlag)\r
1736 .hword (0x07<<8) |(1<<CFlag)\r
1737 .hword (0x08<<8) |(1<<CFlag)\r
1738 .hword (0x09<<8) |(1<<VFlag) |(1<<CFlag)\r
1739 .hword (0x10<<8) |(1<<HFlag) |(1<<CFlag)\r
1740 .hword (0x11<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1741 .hword (0x12<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1742 .hword (0x13<<8) |(1<<HFlag) |(1<<CFlag)\r
1743 .hword (0x14<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1744 .hword (0x15<<8) |(1<<HFlag) |(1<<CFlag)\r
1745 .hword (0x10<<8) |(1<<CFlag)\r
1746 .hword (0x11<<8) |(1<<VFlag) |(1<<CFlag)\r
1747 .hword (0x12<<8) |(1<<VFlag) |(1<<CFlag)\r
1748 .hword (0x13<<8) |(1<<CFlag)\r
1749 .hword (0x14<<8) |(1<<VFlag) |(1<<CFlag)\r
1750 .hword (0x15<<8) |(1<<CFlag)\r
1751 .hword (0x16<<8) |(1<<CFlag)\r
1752 .hword (0x17<<8) |(1<<VFlag) |(1<<CFlag)\r
1753 .hword (0x18<<8) |(1<<VFlag) |(1<<CFlag)\r
1754 .hword (0x19<<8) |(1<<CFlag)\r
1755 .hword (0x20<<8) |(1<<HFlag) |(1<<CFlag)\r
1756 .hword (0x21<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1757 .hword (0x22<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1758 .hword (0x23<<8) |(1<<HFlag) |(1<<CFlag)\r
1759 .hword (0x24<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1760 .hword (0x25<<8) |(1<<HFlag) |(1<<CFlag)\r
1761 .hword (0x20<<8) |(1<<CFlag)\r
1762 .hword (0x21<<8) |(1<<VFlag) |(1<<CFlag)\r
1763 .hword (0x22<<8) |(1<<VFlag) |(1<<CFlag)\r
1764 .hword (0x23<<8) |(1<<CFlag)\r
1765 .hword (0x24<<8) |(1<<VFlag) |(1<<CFlag)\r
1766 .hword (0x25<<8) |(1<<CFlag)\r
1767 .hword (0x26<<8) |(1<<CFlag)\r
1768 .hword (0x27<<8) |(1<<VFlag) |(1<<CFlag)\r
1769 .hword (0x28<<8) |(1<<VFlag) |(1<<CFlag)\r
1770 .hword (0x29<<8) |(1<<CFlag)\r
1771 .hword (0x30<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1772 .hword (0x31<<8) |(1<<HFlag) |(1<<CFlag)\r
1773 .hword (0x32<<8) |(1<<HFlag) |(1<<CFlag)\r
1774 .hword (0x33<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1775 .hword (0x34<<8) |(1<<HFlag) |(1<<CFlag)\r
1776 .hword (0x35<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1777 .hword (0x30<<8) |(1<<VFlag) |(1<<CFlag)\r
1778 .hword (0x31<<8) |(1<<CFlag)\r
1779 .hword (0x32<<8) |(1<<CFlag)\r
1780 .hword (0x33<<8) |(1<<VFlag) |(1<<CFlag)\r
1781 .hword (0x34<<8) |(1<<CFlag)\r
1782 .hword (0x35<<8) |(1<<VFlag) |(1<<CFlag)\r
1783 .hword (0x36<<8) |(1<<VFlag) |(1<<CFlag)\r
1784 .hword (0x37<<8) |(1<<CFlag)\r
1785 .hword (0x38<<8) |(1<<CFlag)\r
1786 .hword (0x39<<8) |(1<<VFlag) |(1<<CFlag)\r
1787 .hword (0x40<<8) |(1<<HFlag) |(1<<CFlag)\r
1788 .hword (0x41<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1789 .hword (0x42<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1790 .hword (0x43<<8) |(1<<HFlag) |(1<<CFlag)\r
1791 .hword (0x44<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1792 .hword (0x45<<8) |(1<<HFlag) |(1<<CFlag)\r
1793 .hword (0x40<<8) |(1<<CFlag)\r
1794 .hword (0x41<<8) |(1<<VFlag) |(1<<CFlag)\r
1795 .hword (0x42<<8) |(1<<VFlag) |(1<<CFlag)\r
1796 .hword (0x43<<8) |(1<<CFlag)\r
1797 .hword (0x44<<8) |(1<<VFlag) |(1<<CFlag)\r
1798 .hword (0x45<<8) |(1<<CFlag)\r
1799 .hword (0x46<<8) |(1<<CFlag)\r
1800 .hword (0x47<<8) |(1<<VFlag) |(1<<CFlag)\r
1801 .hword (0x48<<8) |(1<<VFlag) |(1<<CFlag)\r
1802 .hword (0x49<<8) |(1<<CFlag)\r
1803 .hword (0x50<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1804 .hword (0x51<<8) |(1<<HFlag) |(1<<CFlag)\r
1805 .hword (0x52<<8) |(1<<HFlag) |(1<<CFlag)\r
1806 .hword (0x53<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1807 .hword (0x54<<8) |(1<<HFlag) |(1<<CFlag)\r
1808 .hword (0x55<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1809 .hword (0x50<<8) |(1<<VFlag) |(1<<CFlag)\r
1810 .hword (0x51<<8) |(1<<CFlag)\r
1811 .hword (0x52<<8) |(1<<CFlag)\r
1812 .hword (0x53<<8) |(1<<VFlag) |(1<<CFlag)\r
1813 .hword (0x54<<8) |(1<<CFlag)\r
1814 .hword (0x55<<8) |(1<<VFlag) |(1<<CFlag)\r
1815 .hword (0x56<<8) |(1<<VFlag) |(1<<CFlag)\r
1816 .hword (0x57<<8) |(1<<CFlag)\r
1817 .hword (0x58<<8) |(1<<CFlag)\r
1818 .hword (0x59<<8) |(1<<VFlag) |(1<<CFlag)\r
1819 .hword (0x60<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1820 .hword (0x61<<8) |(1<<HFlag) |(1<<CFlag)\r
1821 .hword (0x62<<8) |(1<<HFlag) |(1<<CFlag)\r
1822 .hword (0x63<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1823 .hword (0x64<<8) |(1<<HFlag) |(1<<CFlag)\r
1824 .hword (0x65<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1825 .hword (0x60<<8) |(1<<VFlag) |(1<<CFlag)\r
1826 .hword (0x61<<8) |(1<<CFlag)\r
1827 .hword (0x62<<8) |(1<<CFlag)\r
1828 .hword (0x63<<8) |(1<<VFlag) |(1<<CFlag)\r
1829 .hword (0x64<<8) |(1<<CFlag)\r
1830 .hword (0x65<<8) |(1<<VFlag) |(1<<CFlag)\r
1831 .hword (0x66<<8) |(1<<VFlag) |(1<<CFlag)\r
1832 .hword (0x67<<8) |(1<<CFlag)\r
1833 .hword (0x68<<8) |(1<<CFlag)\r
1834 .hword (0x69<<8) |(1<<VFlag) |(1<<CFlag)\r
1835 .hword (0x70<<8) |(1<<HFlag) |(1<<CFlag)\r
1836 .hword (0x71<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1837 .hword (0x72<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1838 .hword (0x73<<8) |(1<<HFlag) |(1<<CFlag)\r
1839 .hword (0x74<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1840 .hword (0x75<<8) |(1<<HFlag) |(1<<CFlag)\r
1841 .hword (0x70<<8) |(1<<CFlag)\r
1842 .hword (0x71<<8) |(1<<VFlag) |(1<<CFlag)\r
1843 .hword (0x72<<8) |(1<<VFlag) |(1<<CFlag)\r
1844 .hword (0x73<<8) |(1<<CFlag)\r
1845 .hword (0x74<<8) |(1<<VFlag) |(1<<CFlag)\r
1846 .hword (0x75<<8) |(1<<CFlag)\r
1847 .hword (0x76<<8) |(1<<CFlag)\r
1848 .hword (0x77<<8) |(1<<VFlag) |(1<<CFlag)\r
1849 .hword (0x78<<8) |(1<<VFlag) |(1<<CFlag)\r
1850 .hword (0x79<<8) |(1<<CFlag)\r
1851 .hword (0x80<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
1852 .hword (0x81<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1853 .hword (0x82<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1854 .hword (0x83<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
1855 .hword (0x84<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1856 .hword (0x85<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
1857 .hword (0x80<<8)|(1<<SFlag) |(1<<CFlag)\r
1858 .hword (0x81<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1859 .hword (0x82<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1860 .hword (0x83<<8)|(1<<SFlag) |(1<<CFlag)\r
1861 .hword (0x84<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1862 .hword (0x85<<8)|(1<<SFlag) |(1<<CFlag)\r
1863 .hword (0x86<<8)|(1<<SFlag) |(1<<CFlag)\r
1864 .hword (0x87<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1865 .hword (0x88<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1866 .hword (0x89<<8)|(1<<SFlag) |(1<<CFlag)\r
1867 .hword (0x90<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1868 .hword (0x91<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
1869 .hword (0x92<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
1870 .hword (0x93<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1871 .hword (0x94<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
1872 .hword (0x95<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1873 .hword (0x90<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1874 .hword (0x91<<8)|(1<<SFlag) |(1<<CFlag)\r
1875 .hword (0x92<<8)|(1<<SFlag) |(1<<CFlag)\r
1876 .hword (0x93<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1877 .hword (0x94<<8)|(1<<SFlag) |(1<<CFlag)\r
1878 .hword (0x95<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1879 .hword (0x96<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1880 .hword (0x97<<8)|(1<<SFlag) |(1<<CFlag)\r
1881 .hword (0x98<<8)|(1<<SFlag) |(1<<CFlag)\r
1882 .hword (0x99<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1883 .hword (0xA0<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1884 .hword (0xA1<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
1885 .hword (0xA2<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
1886 .hword (0xA3<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1887 .hword (0xA4<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
1888 .hword (0xA5<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1889 .hword (0xA0<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1890 .hword (0xA1<<8)|(1<<SFlag) |(1<<CFlag)\r
1891 .hword (0xA2<<8)|(1<<SFlag) |(1<<CFlag)\r
1892 .hword (0xA3<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1893 .hword (0xA4<<8)|(1<<SFlag) |(1<<CFlag)\r
1894 .hword (0xA5<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1895 .hword (0xA6<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1896 .hword (0xA7<<8)|(1<<SFlag) |(1<<CFlag)\r
1897 .hword (0xA8<<8)|(1<<SFlag) |(1<<CFlag)\r
1898 .hword (0xA9<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1899 .hword (0xB0<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
1900 .hword (0xB1<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1901 .hword (0xB2<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1902 .hword (0xB3<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
1903 .hword (0xB4<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1904 .hword (0xB5<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
1905 .hword (0xB0<<8)|(1<<SFlag) |(1<<CFlag)\r
1906 .hword (0xB1<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1907 .hword (0xB2<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1908 .hword (0xB3<<8)|(1<<SFlag) |(1<<CFlag)\r
1909 .hword (0xB4<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1910 .hword (0xB5<<8)|(1<<SFlag) |(1<<CFlag)\r
1911 .hword (0xB6<<8)|(1<<SFlag) |(1<<CFlag)\r
1912 .hword (0xB7<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1913 .hword (0xB8<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1914 .hword (0xB9<<8)|(1<<SFlag) |(1<<CFlag)\r
1915 .hword (0xC0<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1916 .hword (0xC1<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
1917 .hword (0xC2<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
1918 .hword (0xC3<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1919 .hword (0xC4<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
1920 .hword (0xC5<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1921 .hword (0xC0<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1922 .hword (0xC1<<8)|(1<<SFlag) |(1<<CFlag)\r
1923 .hword (0xC2<<8)|(1<<SFlag) |(1<<CFlag)\r
1924 .hword (0xC3<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1925 .hword (0xC4<<8)|(1<<SFlag) |(1<<CFlag)\r
1926 .hword (0xC5<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1927 .hword (0xC6<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1928 .hword (0xC7<<8)|(1<<SFlag) |(1<<CFlag)\r
1929 .hword (0xC8<<8)|(1<<SFlag) |(1<<CFlag)\r
1930 .hword (0xC9<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1931 .hword (0xD0<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
1932 .hword (0xD1<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1933 .hword (0xD2<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1934 .hword (0xD3<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
1935 .hword (0xD4<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1936 .hword (0xD5<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
1937 .hword (0xD0<<8)|(1<<SFlag) |(1<<CFlag)\r
1938 .hword (0xD1<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1939 .hword (0xD2<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1940 .hword (0xD3<<8)|(1<<SFlag) |(1<<CFlag)\r
1941 .hword (0xD4<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1942 .hword (0xD5<<8)|(1<<SFlag) |(1<<CFlag)\r
1943 .hword (0xD6<<8)|(1<<SFlag) |(1<<CFlag)\r
1944 .hword (0xD7<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1945 .hword (0xD8<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1946 .hword (0xD9<<8)|(1<<SFlag) |(1<<CFlag)\r
1947 .hword (0xE0<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
1948 .hword (0xE1<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1949 .hword (0xE2<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1950 .hword (0xE3<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
1951 .hword (0xE4<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1952 .hword (0xE5<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
1953 .hword (0xE0<<8)|(1<<SFlag) |(1<<CFlag)\r
1954 .hword (0xE1<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1955 .hword (0xE2<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1956 .hword (0xE3<<8)|(1<<SFlag) |(1<<CFlag)\r
1957 .hword (0xE4<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1958 .hword (0xE5<<8)|(1<<SFlag) |(1<<CFlag)\r
1959 .hword (0xE6<<8)|(1<<SFlag) |(1<<CFlag)\r
1960 .hword (0xE7<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1961 .hword (0xE8<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1962 .hword (0xE9<<8)|(1<<SFlag) |(1<<CFlag)\r
1963 .hword (0xF0<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1964 .hword (0xF1<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
1965 .hword (0xF2<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
1966 .hword (0xF3<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1967 .hword (0xF4<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
1968 .hword (0xF5<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1969 .hword (0xF0<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1970 .hword (0xF1<<8)|(1<<SFlag) |(1<<CFlag)\r
1971 .hword (0xF2<<8)|(1<<SFlag) |(1<<CFlag)\r
1972 .hword (0xF3<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1973 .hword (0xF4<<8)|(1<<SFlag) |(1<<CFlag)\r
1974 .hword (0xF5<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1975 .hword (0xF6<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1976 .hword (0xF7<<8)|(1<<SFlag) |(1<<CFlag)\r
1977 .hword (0xF8<<8)|(1<<SFlag) |(1<<CFlag)\r
1978 .hword (0xF9<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
1979 .hword (0x00<<8) |(1<<ZFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1980 .hword (0x01<<8) |(1<<HFlag) |(1<<CFlag)\r
1981 .hword (0x02<<8) |(1<<HFlag) |(1<<CFlag)\r
1982 .hword (0x03<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1983 .hword (0x04<<8) |(1<<HFlag) |(1<<CFlag)\r
1984 .hword (0x05<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1985 .hword (0x00<<8) |(1<<ZFlag) |(1<<VFlag) |(1<<CFlag)\r
1986 .hword (0x01<<8) |(1<<CFlag)\r
1987 .hword (0x02<<8) |(1<<CFlag)\r
1988 .hword (0x03<<8) |(1<<VFlag) |(1<<CFlag)\r
1989 .hword (0x04<<8) |(1<<CFlag)\r
1990 .hword (0x05<<8) |(1<<VFlag) |(1<<CFlag)\r
1991 .hword (0x06<<8) |(1<<VFlag) |(1<<CFlag)\r
1992 .hword (0x07<<8) |(1<<CFlag)\r
1993 .hword (0x08<<8) |(1<<CFlag)\r
1994 .hword (0x09<<8) |(1<<VFlag) |(1<<CFlag)\r
1995 .hword (0x10<<8) |(1<<HFlag) |(1<<CFlag)\r
1996 .hword (0x11<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1997 .hword (0x12<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
1998 .hword (0x13<<8) |(1<<HFlag) |(1<<CFlag)\r
1999 .hword (0x14<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2000 .hword (0x15<<8) |(1<<HFlag) |(1<<CFlag)\r
2001 .hword (0x10<<8) |(1<<CFlag)\r
2002 .hword (0x11<<8) |(1<<VFlag) |(1<<CFlag)\r
2003 .hword (0x12<<8) |(1<<VFlag) |(1<<CFlag)\r
2004 .hword (0x13<<8) |(1<<CFlag)\r
2005 .hword (0x14<<8) |(1<<VFlag) |(1<<CFlag)\r
2006 .hword (0x15<<8) |(1<<CFlag)\r
2007 .hword (0x16<<8) |(1<<CFlag)\r
2008 .hword (0x17<<8) |(1<<VFlag) |(1<<CFlag)\r
2009 .hword (0x18<<8) |(1<<VFlag) |(1<<CFlag)\r
2010 .hword (0x19<<8) |(1<<CFlag)\r
2011 .hword (0x20<<8) |(1<<HFlag) |(1<<CFlag)\r
2012 .hword (0x21<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2013 .hword (0x22<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2014 .hword (0x23<<8) |(1<<HFlag) |(1<<CFlag)\r
2015 .hword (0x24<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2016 .hword (0x25<<8) |(1<<HFlag) |(1<<CFlag)\r
2017 .hword (0x20<<8) |(1<<CFlag)\r
2018 .hword (0x21<<8) |(1<<VFlag) |(1<<CFlag)\r
2019 .hword (0x22<<8) |(1<<VFlag) |(1<<CFlag)\r
2020 .hword (0x23<<8) |(1<<CFlag)\r
2021 .hword (0x24<<8) |(1<<VFlag) |(1<<CFlag)\r
2022 .hword (0x25<<8) |(1<<CFlag)\r
2023 .hword (0x26<<8) |(1<<CFlag)\r
2024 .hword (0x27<<8) |(1<<VFlag) |(1<<CFlag)\r
2025 .hword (0x28<<8) |(1<<VFlag) |(1<<CFlag)\r
2026 .hword (0x29<<8) |(1<<CFlag)\r
2027 .hword (0x30<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2028 .hword (0x31<<8) |(1<<HFlag) |(1<<CFlag)\r
2029 .hword (0x32<<8) |(1<<HFlag) |(1<<CFlag)\r
2030 .hword (0x33<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2031 .hword (0x34<<8) |(1<<HFlag) |(1<<CFlag)\r
2032 .hword (0x35<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2033 .hword (0x30<<8) |(1<<VFlag) |(1<<CFlag)\r
2034 .hword (0x31<<8) |(1<<CFlag)\r
2035 .hword (0x32<<8) |(1<<CFlag)\r
2036 .hword (0x33<<8) |(1<<VFlag) |(1<<CFlag)\r
2037 .hword (0x34<<8) |(1<<CFlag)\r
2038 .hword (0x35<<8) |(1<<VFlag) |(1<<CFlag)\r
2039 .hword (0x36<<8) |(1<<VFlag) |(1<<CFlag)\r
2040 .hword (0x37<<8) |(1<<CFlag)\r
2041 .hword (0x38<<8) |(1<<CFlag)\r
2042 .hword (0x39<<8) |(1<<VFlag) |(1<<CFlag)\r
2043 .hword (0x40<<8) |(1<<HFlag) |(1<<CFlag)\r
2044 .hword (0x41<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2045 .hword (0x42<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2046 .hword (0x43<<8) |(1<<HFlag) |(1<<CFlag)\r
2047 .hword (0x44<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2048 .hword (0x45<<8) |(1<<HFlag) |(1<<CFlag)\r
2049 .hword (0x40<<8) |(1<<CFlag)\r
2050 .hword (0x41<<8) |(1<<VFlag) |(1<<CFlag)\r
2051 .hword (0x42<<8) |(1<<VFlag) |(1<<CFlag)\r
2052 .hword (0x43<<8) |(1<<CFlag)\r
2053 .hword (0x44<<8) |(1<<VFlag) |(1<<CFlag)\r
2054 .hword (0x45<<8) |(1<<CFlag)\r
2055 .hword (0x46<<8) |(1<<CFlag)\r
2056 .hword (0x47<<8) |(1<<VFlag) |(1<<CFlag)\r
2057 .hword (0x48<<8) |(1<<VFlag) |(1<<CFlag)\r
2058 .hword (0x49<<8) |(1<<CFlag)\r
2059 .hword (0x50<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2060 .hword (0x51<<8) |(1<<HFlag) |(1<<CFlag)\r
2061 .hword (0x52<<8) |(1<<HFlag) |(1<<CFlag)\r
2062 .hword (0x53<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2063 .hword (0x54<<8) |(1<<HFlag) |(1<<CFlag)\r
2064 .hword (0x55<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2065 .hword (0x50<<8) |(1<<VFlag) |(1<<CFlag)\r
2066 .hword (0x51<<8) |(1<<CFlag)\r
2067 .hword (0x52<<8) |(1<<CFlag)\r
2068 .hword (0x53<<8) |(1<<VFlag) |(1<<CFlag)\r
2069 .hword (0x54<<8) |(1<<CFlag)\r
2070 .hword (0x55<<8) |(1<<VFlag) |(1<<CFlag)\r
2071 .hword (0x56<<8) |(1<<VFlag) |(1<<CFlag)\r
2072 .hword (0x57<<8) |(1<<CFlag)\r
2073 .hword (0x58<<8) |(1<<CFlag)\r
2074 .hword (0x59<<8) |(1<<VFlag) |(1<<CFlag)\r
2075 .hword (0x60<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2076 .hword (0x61<<8) |(1<<HFlag) |(1<<CFlag)\r
2077 .hword (0x62<<8) |(1<<HFlag) |(1<<CFlag)\r
2078 .hword (0x63<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2079 .hword (0x64<<8) |(1<<HFlag) |(1<<CFlag)\r
2080 .hword (0x65<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2081 .hword (0x06<<8) |(1<<VFlag)\r
2082 .hword (0x07<<8) \r
2083 .hword (0x08<<8) \r
2084 .hword (0x09<<8) |(1<<VFlag)\r
2085 .hword (0x0A<<8) |(1<<VFlag)\r
2086 .hword (0x0B<<8) \r
2087 .hword (0x0C<<8) |(1<<VFlag)\r
2088 .hword (0x0D<<8) \r
2089 .hword (0x0E<<8) \r
2090 .hword (0x0F<<8) |(1<<VFlag)\r
2091 .hword (0x10<<8) |(1<<HFlag) \r
2092 .hword (0x11<<8) |(1<<HFlag) |(1<<VFlag)\r
2093 .hword (0x12<<8) |(1<<HFlag) |(1<<VFlag)\r
2094 .hword (0x13<<8) |(1<<HFlag) \r
2095 .hword (0x14<<8) |(1<<HFlag) |(1<<VFlag)\r
2096 .hword (0x15<<8) |(1<<HFlag) \r
2097 .hword (0x16<<8) \r
2098 .hword (0x17<<8) |(1<<VFlag)\r
2099 .hword (0x18<<8) |(1<<VFlag)\r
2100 .hword (0x19<<8) \r
2101 .hword (0x1A<<8) \r
2102 .hword (0x1B<<8) |(1<<VFlag)\r
2103 .hword (0x1C<<8) \r
2104 .hword (0x1D<<8) |(1<<VFlag)\r
2105 .hword (0x1E<<8) |(1<<VFlag)\r
2106 .hword (0x1F<<8) \r
2107 .hword (0x20<<8) |(1<<HFlag) \r
2108 .hword (0x21<<8) |(1<<HFlag) |(1<<VFlag)\r
2109 .hword (0x22<<8) |(1<<HFlag) |(1<<VFlag)\r
2110 .hword (0x23<<8) |(1<<HFlag) \r
2111 .hword (0x24<<8) |(1<<HFlag) |(1<<VFlag)\r
2112 .hword (0x25<<8) |(1<<HFlag) \r
2113 .hword (0x26<<8) \r
2114 .hword (0x27<<8) |(1<<VFlag)\r
2115 .hword (0x28<<8) |(1<<VFlag)\r
2116 .hword (0x29<<8) \r
2117 .hword (0x2A<<8) \r
2118 .hword (0x2B<<8) |(1<<VFlag)\r
2119 .hword (0x2C<<8) \r
2120 .hword (0x2D<<8) |(1<<VFlag)\r
2121 .hword (0x2E<<8) |(1<<VFlag)\r
2122 .hword (0x2F<<8) \r
2123 .hword (0x30<<8) |(1<<HFlag) |(1<<VFlag)\r
2124 .hword (0x31<<8) |(1<<HFlag) \r
2125 .hword (0x32<<8) |(1<<HFlag) \r
2126 .hword (0x33<<8) |(1<<HFlag) |(1<<VFlag)\r
2127 .hword (0x34<<8) |(1<<HFlag) \r
2128 .hword (0x35<<8) |(1<<HFlag) |(1<<VFlag)\r
2129 .hword (0x36<<8) |(1<<VFlag)\r
2130 .hword (0x37<<8) \r
2131 .hword (0x38<<8) \r
2132 .hword (0x39<<8) |(1<<VFlag)\r
2133 .hword (0x3A<<8) |(1<<VFlag)\r
2134 .hword (0x3B<<8) \r
2135 .hword (0x3C<<8) |(1<<VFlag)\r
2136 .hword (0x3D<<8) \r
2137 .hword (0x3E<<8) \r
2138 .hword (0x3F<<8) |(1<<VFlag)\r
2139 .hword (0x40<<8) |(1<<HFlag) \r
2140 .hword (0x41<<8) |(1<<HFlag) |(1<<VFlag)\r
2141 .hword (0x42<<8) |(1<<HFlag) |(1<<VFlag)\r
2142 .hword (0x43<<8) |(1<<HFlag) \r
2143 .hword (0x44<<8) |(1<<HFlag) |(1<<VFlag)\r
2144 .hword (0x45<<8) |(1<<HFlag) \r
2145 .hword (0x46<<8) \r
2146 .hword (0x47<<8) |(1<<VFlag)\r
2147 .hword (0x48<<8) |(1<<VFlag)\r
2148 .hword (0x49<<8) \r
2149 .hword (0x4A<<8) \r
2150 .hword (0x4B<<8) |(1<<VFlag)\r
2151 .hword (0x4C<<8) \r
2152 .hword (0x4D<<8) |(1<<VFlag)\r
2153 .hword (0x4E<<8) |(1<<VFlag)\r
2154 .hword (0x4F<<8) \r
2155 .hword (0x50<<8) |(1<<HFlag) |(1<<VFlag)\r
2156 .hword (0x51<<8) |(1<<HFlag) \r
2157 .hword (0x52<<8) |(1<<HFlag) \r
2158 .hword (0x53<<8) |(1<<HFlag) |(1<<VFlag)\r
2159 .hword (0x54<<8) |(1<<HFlag) \r
2160 .hword (0x55<<8) |(1<<HFlag) |(1<<VFlag)\r
2161 .hword (0x56<<8) |(1<<VFlag)\r
2162 .hword (0x57<<8) \r
2163 .hword (0x58<<8) \r
2164 .hword (0x59<<8) |(1<<VFlag)\r
2165 .hword (0x5A<<8) |(1<<VFlag)\r
2166 .hword (0x5B<<8) \r
2167 .hword (0x5C<<8) |(1<<VFlag)\r
2168 .hword (0x5D<<8) \r
2169 .hword (0x5E<<8) \r
2170 .hword (0x5F<<8) |(1<<VFlag)\r
2171 .hword (0x60<<8) |(1<<HFlag) |(1<<VFlag)\r
2172 .hword (0x61<<8) |(1<<HFlag) \r
2173 .hword (0x62<<8) |(1<<HFlag) \r
2174 .hword (0x63<<8) |(1<<HFlag) |(1<<VFlag)\r
2175 .hword (0x64<<8) |(1<<HFlag) \r
2176 .hword (0x65<<8) |(1<<HFlag) |(1<<VFlag)\r
2177 .hword (0x66<<8) |(1<<VFlag)\r
2178 .hword (0x67<<8) \r
2179 .hword (0x68<<8) \r
2180 .hword (0x69<<8) |(1<<VFlag)\r
2181 .hword (0x6A<<8) |(1<<VFlag)\r
2182 .hword (0x6B<<8) \r
2183 .hword (0x6C<<8) |(1<<VFlag)\r
2184 .hword (0x6D<<8) \r
2185 .hword (0x6E<<8) \r
2186 .hword (0x6F<<8) |(1<<VFlag)\r
2187 .hword (0x70<<8) |(1<<HFlag) \r
2188 .hword (0x71<<8) |(1<<HFlag) |(1<<VFlag)\r
2189 .hword (0x72<<8) |(1<<HFlag) |(1<<VFlag)\r
2190 .hword (0x73<<8) |(1<<HFlag) \r
2191 .hword (0x74<<8) |(1<<HFlag) |(1<<VFlag)\r
2192 .hword (0x75<<8) |(1<<HFlag) \r
2193 .hword (0x76<<8) \r
2194 .hword (0x77<<8) |(1<<VFlag)\r
2195 .hword (0x78<<8) |(1<<VFlag)\r
2196 .hword (0x79<<8) \r
2197 .hword (0x7A<<8) \r
2198 .hword (0x7B<<8) |(1<<VFlag)\r
2199 .hword (0x7C<<8) \r
2200 .hword (0x7D<<8) |(1<<VFlag)\r
2201 .hword (0x7E<<8) |(1<<VFlag)\r
2202 .hword (0x7F<<8) \r
2203 .hword (0x80<<8)|(1<<SFlag) |(1<<HFlag) \r
2204 .hword (0x81<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag)\r
2205 .hword (0x82<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag)\r
2206 .hword (0x83<<8)|(1<<SFlag) |(1<<HFlag) \r
2207 .hword (0x84<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag)\r
2208 .hword (0x85<<8)|(1<<SFlag) |(1<<HFlag) \r
2209 .hword (0x86<<8)|(1<<SFlag) \r
2210 .hword (0x87<<8)|(1<<SFlag) |(1<<VFlag)\r
2211 .hword (0x88<<8)|(1<<SFlag) |(1<<VFlag)\r
2212 .hword (0x89<<8)|(1<<SFlag) \r
2213 .hword (0x8A<<8)|(1<<SFlag) \r
2214 .hword (0x8B<<8)|(1<<SFlag) |(1<<VFlag)\r
2215 .hword (0x8C<<8)|(1<<SFlag) \r
2216 .hword (0x8D<<8)|(1<<SFlag) |(1<<VFlag)\r
2217 .hword (0x8E<<8)|(1<<SFlag) |(1<<VFlag)\r
2218 .hword (0x8F<<8)|(1<<SFlag) \r
2219 .hword (0x90<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag)\r
2220 .hword (0x91<<8)|(1<<SFlag) |(1<<HFlag) \r
2221 .hword (0x92<<8)|(1<<SFlag) |(1<<HFlag) \r
2222 .hword (0x93<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag)\r
2223 .hword (0x94<<8)|(1<<SFlag) |(1<<HFlag) \r
2224 .hword (0x95<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag)\r
2225 .hword (0x96<<8)|(1<<SFlag) |(1<<VFlag)\r
2226 .hword (0x97<<8)|(1<<SFlag) \r
2227 .hword (0x98<<8)|(1<<SFlag) \r
2228 .hword (0x99<<8)|(1<<SFlag) |(1<<VFlag)\r
2229 .hword (0x9A<<8)|(1<<SFlag) |(1<<VFlag)\r
2230 .hword (0x9B<<8)|(1<<SFlag) \r
2231 .hword (0x9C<<8)|(1<<SFlag) |(1<<VFlag)\r
2232 .hword (0x9D<<8)|(1<<SFlag) \r
2233 .hword (0x9E<<8)|(1<<SFlag) \r
2234 .hword (0x9F<<8)|(1<<SFlag) |(1<<VFlag)\r
2235 .hword (0x00<<8) |(1<<ZFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2236 .hword (0x01<<8) |(1<<HFlag) |(1<<CFlag)\r
2237 .hword (0x02<<8) |(1<<HFlag) |(1<<CFlag)\r
2238 .hword (0x03<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2239 .hword (0x04<<8) |(1<<HFlag) |(1<<CFlag)\r
2240 .hword (0x05<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2241 .hword (0x06<<8) |(1<<VFlag) |(1<<CFlag)\r
2242 .hword (0x07<<8) |(1<<CFlag)\r
2243 .hword (0x08<<8) |(1<<CFlag)\r
2244 .hword (0x09<<8) |(1<<VFlag) |(1<<CFlag)\r
2245 .hword (0x0A<<8) |(1<<VFlag) |(1<<CFlag)\r
2246 .hword (0x0B<<8) |(1<<CFlag)\r
2247 .hword (0x0C<<8) |(1<<VFlag) |(1<<CFlag)\r
2248 .hword (0x0D<<8) |(1<<CFlag)\r
2249 .hword (0x0E<<8) |(1<<CFlag)\r
2250 .hword (0x0F<<8) |(1<<VFlag) |(1<<CFlag)\r
2251 .hword (0x10<<8) |(1<<HFlag) |(1<<CFlag)\r
2252 .hword (0x11<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2253 .hword (0x12<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2254 .hword (0x13<<8) |(1<<HFlag) |(1<<CFlag)\r
2255 .hword (0x14<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2256 .hword (0x15<<8) |(1<<HFlag) |(1<<CFlag)\r
2257 .hword (0x16<<8) |(1<<CFlag)\r
2258 .hword (0x17<<8) |(1<<VFlag) |(1<<CFlag)\r
2259 .hword (0x18<<8) |(1<<VFlag) |(1<<CFlag)\r
2260 .hword (0x19<<8) |(1<<CFlag)\r
2261 .hword (0x1A<<8) |(1<<CFlag)\r
2262 .hword (0x1B<<8) |(1<<VFlag) |(1<<CFlag)\r
2263 .hword (0x1C<<8) |(1<<CFlag)\r
2264 .hword (0x1D<<8) |(1<<VFlag) |(1<<CFlag)\r
2265 .hword (0x1E<<8) |(1<<VFlag) |(1<<CFlag)\r
2266 .hword (0x1F<<8) |(1<<CFlag)\r
2267 .hword (0x20<<8) |(1<<HFlag) |(1<<CFlag)\r
2268 .hword (0x21<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2269 .hword (0x22<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2270 .hword (0x23<<8) |(1<<HFlag) |(1<<CFlag)\r
2271 .hword (0x24<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2272 .hword (0x25<<8) |(1<<HFlag) |(1<<CFlag)\r
2273 .hword (0x26<<8) |(1<<CFlag)\r
2274 .hword (0x27<<8) |(1<<VFlag) |(1<<CFlag)\r
2275 .hword (0x28<<8) |(1<<VFlag) |(1<<CFlag)\r
2276 .hword (0x29<<8) |(1<<CFlag)\r
2277 .hword (0x2A<<8) |(1<<CFlag)\r
2278 .hword (0x2B<<8) |(1<<VFlag) |(1<<CFlag)\r
2279 .hword (0x2C<<8) |(1<<CFlag)\r
2280 .hword (0x2D<<8) |(1<<VFlag) |(1<<CFlag)\r
2281 .hword (0x2E<<8) |(1<<VFlag) |(1<<CFlag)\r
2282 .hword (0x2F<<8) |(1<<CFlag)\r
2283 .hword (0x30<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2284 .hword (0x31<<8) |(1<<HFlag) |(1<<CFlag)\r
2285 .hword (0x32<<8) |(1<<HFlag) |(1<<CFlag)\r
2286 .hword (0x33<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2287 .hword (0x34<<8) |(1<<HFlag) |(1<<CFlag)\r
2288 .hword (0x35<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2289 .hword (0x36<<8) |(1<<VFlag) |(1<<CFlag)\r
2290 .hword (0x37<<8) |(1<<CFlag)\r
2291 .hword (0x38<<8) |(1<<CFlag)\r
2292 .hword (0x39<<8) |(1<<VFlag) |(1<<CFlag)\r
2293 .hword (0x3A<<8) |(1<<VFlag) |(1<<CFlag)\r
2294 .hword (0x3B<<8) |(1<<CFlag)\r
2295 .hword (0x3C<<8) |(1<<VFlag) |(1<<CFlag)\r
2296 .hword (0x3D<<8) |(1<<CFlag)\r
2297 .hword (0x3E<<8) |(1<<CFlag)\r
2298 .hword (0x3F<<8) |(1<<VFlag) |(1<<CFlag)\r
2299 .hword (0x40<<8) |(1<<HFlag) |(1<<CFlag)\r
2300 .hword (0x41<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2301 .hword (0x42<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2302 .hword (0x43<<8) |(1<<HFlag) |(1<<CFlag)\r
2303 .hword (0x44<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2304 .hword (0x45<<8) |(1<<HFlag) |(1<<CFlag)\r
2305 .hword (0x46<<8) |(1<<CFlag)\r
2306 .hword (0x47<<8) |(1<<VFlag) |(1<<CFlag)\r
2307 .hword (0x48<<8) |(1<<VFlag) |(1<<CFlag)\r
2308 .hword (0x49<<8) |(1<<CFlag)\r
2309 .hword (0x4A<<8) |(1<<CFlag)\r
2310 .hword (0x4B<<8) |(1<<VFlag) |(1<<CFlag)\r
2311 .hword (0x4C<<8) |(1<<CFlag)\r
2312 .hword (0x4D<<8) |(1<<VFlag) |(1<<CFlag)\r
2313 .hword (0x4E<<8) |(1<<VFlag) |(1<<CFlag)\r
2314 .hword (0x4F<<8) |(1<<CFlag)\r
2315 .hword (0x50<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2316 .hword (0x51<<8) |(1<<HFlag) |(1<<CFlag)\r
2317 .hword (0x52<<8) |(1<<HFlag) |(1<<CFlag)\r
2318 .hword (0x53<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2319 .hword (0x54<<8) |(1<<HFlag) |(1<<CFlag)\r
2320 .hword (0x55<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2321 .hword (0x56<<8) |(1<<VFlag) |(1<<CFlag)\r
2322 .hword (0x57<<8) |(1<<CFlag)\r
2323 .hword (0x58<<8) |(1<<CFlag)\r
2324 .hword (0x59<<8) |(1<<VFlag) |(1<<CFlag)\r
2325 .hword (0x5A<<8) |(1<<VFlag) |(1<<CFlag)\r
2326 .hword (0x5B<<8) |(1<<CFlag)\r
2327 .hword (0x5C<<8) |(1<<VFlag) |(1<<CFlag)\r
2328 .hword (0x5D<<8) |(1<<CFlag)\r
2329 .hword (0x5E<<8) |(1<<CFlag)\r
2330 .hword (0x5F<<8) |(1<<VFlag) |(1<<CFlag)\r
2331 .hword (0x60<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2332 .hword (0x61<<8) |(1<<HFlag) |(1<<CFlag)\r
2333 .hword (0x62<<8) |(1<<HFlag) |(1<<CFlag)\r
2334 .hword (0x63<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2335 .hword (0x64<<8) |(1<<HFlag) |(1<<CFlag)\r
2336 .hword (0x65<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2337 .hword (0x66<<8) |(1<<VFlag) |(1<<CFlag)\r
2338 .hword (0x67<<8) |(1<<CFlag)\r
2339 .hword (0x68<<8) |(1<<CFlag)\r
2340 .hword (0x69<<8) |(1<<VFlag) |(1<<CFlag)\r
2341 .hword (0x6A<<8) |(1<<VFlag) |(1<<CFlag)\r
2342 .hword (0x6B<<8) |(1<<CFlag)\r
2343 .hword (0x6C<<8) |(1<<VFlag) |(1<<CFlag)\r
2344 .hword (0x6D<<8) |(1<<CFlag)\r
2345 .hword (0x6E<<8) |(1<<CFlag)\r
2346 .hword (0x6F<<8) |(1<<VFlag) |(1<<CFlag)\r
2347 .hword (0x70<<8) |(1<<HFlag) |(1<<CFlag)\r
2348 .hword (0x71<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2349 .hword (0x72<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2350 .hword (0x73<<8) |(1<<HFlag) |(1<<CFlag)\r
2351 .hword (0x74<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2352 .hword (0x75<<8) |(1<<HFlag) |(1<<CFlag)\r
2353 .hword (0x76<<8) |(1<<CFlag)\r
2354 .hword (0x77<<8) |(1<<VFlag) |(1<<CFlag)\r
2355 .hword (0x78<<8) |(1<<VFlag) |(1<<CFlag)\r
2356 .hword (0x79<<8) |(1<<CFlag)\r
2357 .hword (0x7A<<8) |(1<<CFlag)\r
2358 .hword (0x7B<<8) |(1<<VFlag) |(1<<CFlag)\r
2359 .hword (0x7C<<8) |(1<<CFlag)\r
2360 .hword (0x7D<<8) |(1<<VFlag) |(1<<CFlag)\r
2361 .hword (0x7E<<8) |(1<<VFlag) |(1<<CFlag)\r
2362 .hword (0x7F<<8) |(1<<CFlag)\r
2363 .hword (0x80<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
2364 .hword (0x81<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2365 .hword (0x82<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2366 .hword (0x83<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
2367 .hword (0x84<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2368 .hword (0x85<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
2369 .hword (0x86<<8)|(1<<SFlag) |(1<<CFlag)\r
2370 .hword (0x87<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2371 .hword (0x88<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2372 .hword (0x89<<8)|(1<<SFlag) |(1<<CFlag)\r
2373 .hword (0x8A<<8)|(1<<SFlag) |(1<<CFlag)\r
2374 .hword (0x8B<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2375 .hword (0x8C<<8)|(1<<SFlag) |(1<<CFlag)\r
2376 .hword (0x8D<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2377 .hword (0x8E<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2378 .hword (0x8F<<8)|(1<<SFlag) |(1<<CFlag)\r
2379 .hword (0x90<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2380 .hword (0x91<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
2381 .hword (0x92<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
2382 .hword (0x93<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2383 .hword (0x94<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
2384 .hword (0x95<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2385 .hword (0x96<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2386 .hword (0x97<<8)|(1<<SFlag) |(1<<CFlag)\r
2387 .hword (0x98<<8)|(1<<SFlag) |(1<<CFlag)\r
2388 .hword (0x99<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2389 .hword (0x9A<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2390 .hword (0x9B<<8)|(1<<SFlag) |(1<<CFlag)\r
2391 .hword (0x9C<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2392 .hword (0x9D<<8)|(1<<SFlag) |(1<<CFlag)\r
2393 .hword (0x9E<<8)|(1<<SFlag) |(1<<CFlag)\r
2394 .hword (0x9F<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2395 .hword (0xA0<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2396 .hword (0xA1<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
2397 .hword (0xA2<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
2398 .hword (0xA3<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2399 .hword (0xA4<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
2400 .hword (0xA5<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2401 .hword (0xA6<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2402 .hword (0xA7<<8)|(1<<SFlag) |(1<<CFlag)\r
2403 .hword (0xA8<<8)|(1<<SFlag) |(1<<CFlag)\r
2404 .hword (0xA9<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2405 .hword (0xAA<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2406 .hword (0xAB<<8)|(1<<SFlag) |(1<<CFlag)\r
2407 .hword (0xAC<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2408 .hword (0xAD<<8)|(1<<SFlag) |(1<<CFlag)\r
2409 .hword (0xAE<<8)|(1<<SFlag) |(1<<CFlag)\r
2410 .hword (0xAF<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2411 .hword (0xB0<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
2412 .hword (0xB1<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2413 .hword (0xB2<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2414 .hword (0xB3<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
2415 .hword (0xB4<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2416 .hword (0xB5<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
2417 .hword (0xB6<<8)|(1<<SFlag) |(1<<CFlag)\r
2418 .hword (0xB7<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2419 .hword (0xB8<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2420 .hword (0xB9<<8)|(1<<SFlag) |(1<<CFlag)\r
2421 .hword (0xBA<<8)|(1<<SFlag) |(1<<CFlag)\r
2422 .hword (0xBB<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2423 .hword (0xBC<<8)|(1<<SFlag) |(1<<CFlag)\r
2424 .hword (0xBD<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2425 .hword (0xBE<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2426 .hword (0xBF<<8)|(1<<SFlag) |(1<<CFlag)\r
2427 .hword (0xC0<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2428 .hword (0xC1<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
2429 .hword (0xC2<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
2430 .hword (0xC3<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2431 .hword (0xC4<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
2432 .hword (0xC5<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2433 .hword (0xC6<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2434 .hword (0xC7<<8)|(1<<SFlag) |(1<<CFlag)\r
2435 .hword (0xC8<<8)|(1<<SFlag) |(1<<CFlag)\r
2436 .hword (0xC9<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2437 .hword (0xCA<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2438 .hword (0xCB<<8)|(1<<SFlag) |(1<<CFlag)\r
2439 .hword (0xCC<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2440 .hword (0xCD<<8)|(1<<SFlag) |(1<<CFlag)\r
2441 .hword (0xCE<<8)|(1<<SFlag) |(1<<CFlag)\r
2442 .hword (0xCF<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2443 .hword (0xD0<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
2444 .hword (0xD1<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2445 .hword (0xD2<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2446 .hword (0xD3<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
2447 .hword (0xD4<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2448 .hword (0xD5<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
2449 .hword (0xD6<<8)|(1<<SFlag) |(1<<CFlag)\r
2450 .hword (0xD7<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2451 .hword (0xD8<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2452 .hword (0xD9<<8)|(1<<SFlag) |(1<<CFlag)\r
2453 .hword (0xDA<<8)|(1<<SFlag) |(1<<CFlag)\r
2454 .hword (0xDB<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2455 .hword (0xDC<<8)|(1<<SFlag) |(1<<CFlag)\r
2456 .hword (0xDD<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2457 .hword (0xDE<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2458 .hword (0xDF<<8)|(1<<SFlag) |(1<<CFlag)\r
2459 .hword (0xE0<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
2460 .hword (0xE1<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2461 .hword (0xE2<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2462 .hword (0xE3<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
2463 .hword (0xE4<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2464 .hword (0xE5<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
2465 .hword (0xE6<<8)|(1<<SFlag) |(1<<CFlag)\r
2466 .hword (0xE7<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2467 .hword (0xE8<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2468 .hword (0xE9<<8)|(1<<SFlag) |(1<<CFlag)\r
2469 .hword (0xEA<<8)|(1<<SFlag) |(1<<CFlag)\r
2470 .hword (0xEB<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2471 .hword (0xEC<<8)|(1<<SFlag) |(1<<CFlag)\r
2472 .hword (0xED<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2473 .hword (0xEE<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2474 .hword (0xEF<<8)|(1<<SFlag) |(1<<CFlag)\r
2475 .hword (0xF0<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2476 .hword (0xF1<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
2477 .hword (0xF2<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
2478 .hword (0xF3<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2479 .hword (0xF4<<8)|(1<<SFlag) |(1<<HFlag) |(1<<CFlag)\r
2480 .hword (0xF5<<8)|(1<<SFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2481 .hword (0xF6<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2482 .hword (0xF7<<8)|(1<<SFlag) |(1<<CFlag)\r
2483 .hword (0xF8<<8)|(1<<SFlag) |(1<<CFlag)\r
2484 .hword (0xF9<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2485 .hword (0xFA<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2486 .hword (0xFB<<8)|(1<<SFlag) |(1<<CFlag)\r
2487 .hword (0xFC<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2488 .hword (0xFD<<8)|(1<<SFlag) |(1<<CFlag)\r
2489 .hword (0xFE<<8)|(1<<SFlag) |(1<<CFlag)\r
2490 .hword (0xFF<<8)|(1<<SFlag) |(1<<VFlag) |(1<<CFlag)\r
2491 .hword (0x00<<8) |(1<<ZFlag) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2492 .hword (0x01<<8) |(1<<HFlag) |(1<<CFlag)\r
2493 .hword (0x02<<8) |(1<<HFlag) |(1<<CFlag)\r
2494 .hword (0x03<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2495 .hword (0x04<<8) |(1<<HFlag) |(1<<CFlag)\r
2496 .hword (0x05<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2497 .hword (0x06<<8) |(1<<VFlag) |(1<<CFlag)\r
2498 .hword (0x07<<8) |(1<<CFlag)\r
2499 .hword (0x08<<8) |(1<<CFlag)\r
2500 .hword (0x09<<8) |(1<<VFlag) |(1<<CFlag)\r
2501 .hword (0x0A<<8) |(1<<VFlag) |(1<<CFlag)\r
2502 .hword (0x0B<<8) |(1<<CFlag)\r
2503 .hword (0x0C<<8) |(1<<VFlag) |(1<<CFlag)\r
2504 .hword (0x0D<<8) |(1<<CFlag)\r
2505 .hword (0x0E<<8) |(1<<CFlag)\r
2506 .hword (0x0F<<8) |(1<<VFlag) |(1<<CFlag)\r
2507 .hword (0x10<<8) |(1<<HFlag) |(1<<CFlag)\r
2508 .hword (0x11<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2509 .hword (0x12<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2510 .hword (0x13<<8) |(1<<HFlag) |(1<<CFlag)\r
2511 .hword (0x14<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2512 .hword (0x15<<8) |(1<<HFlag) |(1<<CFlag)\r
2513 .hword (0x16<<8) |(1<<CFlag)\r
2514 .hword (0x17<<8) |(1<<VFlag) |(1<<CFlag)\r
2515 .hword (0x18<<8) |(1<<VFlag) |(1<<CFlag)\r
2516 .hword (0x19<<8) |(1<<CFlag)\r
2517 .hword (0x1A<<8) |(1<<CFlag)\r
2518 .hword (0x1B<<8) |(1<<VFlag) |(1<<CFlag)\r
2519 .hword (0x1C<<8) |(1<<CFlag)\r
2520 .hword (0x1D<<8) |(1<<VFlag) |(1<<CFlag)\r
2521 .hword (0x1E<<8) |(1<<VFlag) |(1<<CFlag)\r
2522 .hword (0x1F<<8) |(1<<CFlag)\r
2523 .hword (0x20<<8) |(1<<HFlag) |(1<<CFlag)\r
2524 .hword (0x21<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2525 .hword (0x22<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2526 .hword (0x23<<8) |(1<<HFlag) |(1<<CFlag)\r
2527 .hword (0x24<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2528 .hword (0x25<<8) |(1<<HFlag) |(1<<CFlag)\r
2529 .hword (0x26<<8) |(1<<CFlag)\r
2530 .hword (0x27<<8) |(1<<VFlag) |(1<<CFlag)\r
2531 .hword (0x28<<8) |(1<<VFlag) |(1<<CFlag)\r
2532 .hword (0x29<<8) |(1<<CFlag)\r
2533 .hword (0x2A<<8) |(1<<CFlag)\r
2534 .hword (0x2B<<8) |(1<<VFlag) |(1<<CFlag)\r
2535 .hword (0x2C<<8) |(1<<CFlag)\r
2536 .hword (0x2D<<8) |(1<<VFlag) |(1<<CFlag)\r
2537 .hword (0x2E<<8) |(1<<VFlag) |(1<<CFlag)\r
2538 .hword (0x2F<<8) |(1<<CFlag)\r
2539 .hword (0x30<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2540 .hword (0x31<<8) |(1<<HFlag) |(1<<CFlag)\r
2541 .hword (0x32<<8) |(1<<HFlag) |(1<<CFlag)\r
2542 .hword (0x33<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2543 .hword (0x34<<8) |(1<<HFlag) |(1<<CFlag)\r
2544 .hword (0x35<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2545 .hword (0x36<<8) |(1<<VFlag) |(1<<CFlag)\r
2546 .hword (0x37<<8) |(1<<CFlag)\r
2547 .hword (0x38<<8) |(1<<CFlag)\r
2548 .hword (0x39<<8) |(1<<VFlag) |(1<<CFlag)\r
2549 .hword (0x3A<<8) |(1<<VFlag) |(1<<CFlag)\r
2550 .hword (0x3B<<8) |(1<<CFlag)\r
2551 .hword (0x3C<<8) |(1<<VFlag) |(1<<CFlag)\r
2552 .hword (0x3D<<8) |(1<<CFlag)\r
2553 .hword (0x3E<<8) |(1<<CFlag)\r
2554 .hword (0x3F<<8) |(1<<VFlag) |(1<<CFlag)\r
2555 .hword (0x40<<8) |(1<<HFlag) |(1<<CFlag)\r
2556 .hword (0x41<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2557 .hword (0x42<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2558 .hword (0x43<<8) |(1<<HFlag) |(1<<CFlag)\r
2559 .hword (0x44<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2560 .hword (0x45<<8) |(1<<HFlag) |(1<<CFlag)\r
2561 .hword (0x46<<8) |(1<<CFlag)\r
2562 .hword (0x47<<8) |(1<<VFlag) |(1<<CFlag)\r
2563 .hword (0x48<<8) |(1<<VFlag) |(1<<CFlag)\r
2564 .hword (0x49<<8) |(1<<CFlag)\r
2565 .hword (0x4A<<8) |(1<<CFlag)\r
2566 .hword (0x4B<<8) |(1<<VFlag) |(1<<CFlag)\r
2567 .hword (0x4C<<8) |(1<<CFlag)\r
2568 .hword (0x4D<<8) |(1<<VFlag) |(1<<CFlag)\r
2569 .hword (0x4E<<8) |(1<<VFlag) |(1<<CFlag)\r
2570 .hword (0x4F<<8) |(1<<CFlag)\r
2571 .hword (0x50<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2572 .hword (0x51<<8) |(1<<HFlag) |(1<<CFlag)\r
2573 .hword (0x52<<8) |(1<<HFlag) |(1<<CFlag)\r
2574 .hword (0x53<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2575 .hword (0x54<<8) |(1<<HFlag) |(1<<CFlag)\r
2576 .hword (0x55<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2577 .hword (0x56<<8) |(1<<VFlag) |(1<<CFlag)\r
2578 .hword (0x57<<8) |(1<<CFlag)\r
2579 .hword (0x58<<8) |(1<<CFlag)\r
2580 .hword (0x59<<8) |(1<<VFlag) |(1<<CFlag)\r
2581 .hword (0x5A<<8) |(1<<VFlag) |(1<<CFlag)\r
2582 .hword (0x5B<<8) |(1<<CFlag)\r
2583 .hword (0x5C<<8) |(1<<VFlag) |(1<<CFlag)\r
2584 .hword (0x5D<<8) |(1<<CFlag)\r
2585 .hword (0x5E<<8) |(1<<CFlag)\r
2586 .hword (0x5F<<8) |(1<<VFlag) |(1<<CFlag)\r
2587 .hword (0x60<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2588 .hword (0x61<<8) |(1<<HFlag) |(1<<CFlag)\r
2589 .hword (0x62<<8) |(1<<HFlag) |(1<<CFlag)\r
2590 .hword (0x63<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2591 .hword (0x64<<8) |(1<<HFlag) |(1<<CFlag)\r
2592 .hword (0x65<<8) |(1<<HFlag) |(1<<VFlag) |(1<<CFlag)\r
2593 .hword (0x00<<8) |(1<<ZFlag) |(1<<VFlag)|(1<<NFlag) \r
2594 .hword (0x01<<8) |(1<<NFlag) \r
2595 .hword (0x02<<8) |(1<<NFlag) \r
2596 .hword (0x03<<8) |(1<<VFlag)|(1<<NFlag) \r
2597 .hword (0x04<<8) |(1<<NFlag) \r
2598 .hword (0x05<<8) |(1<<VFlag)|(1<<NFlag) \r
2599 .hword (0x06<<8) |(1<<VFlag)|(1<<NFlag) \r
2600 .hword (0x07<<8) |(1<<NFlag) \r
2601 .hword (0x08<<8) |(1<<NFlag) \r
2602 .hword (0x09<<8) |(1<<VFlag)|(1<<NFlag) \r
2603 .hword (0x04<<8) |(1<<NFlag) \r
2604 .hword (0x05<<8) |(1<<VFlag)|(1<<NFlag) \r
2605 .hword (0x06<<8) |(1<<VFlag)|(1<<NFlag) \r
2606 .hword (0x07<<8) |(1<<NFlag) \r
2607 .hword (0x08<<8) |(1<<NFlag) \r
2608 .hword (0x09<<8) |(1<<VFlag)|(1<<NFlag) \r
2609 .hword (0x10<<8) |(1<<NFlag) \r
2610 .hword (0x11<<8) |(1<<VFlag)|(1<<NFlag) \r
2611 .hword (0x12<<8) |(1<<VFlag)|(1<<NFlag) \r
2612 .hword (0x13<<8) |(1<<NFlag) \r
2613 .hword (0x14<<8) |(1<<VFlag)|(1<<NFlag) \r
2614 .hword (0x15<<8) |(1<<NFlag) \r
2615 .hword (0x16<<8) |(1<<NFlag) \r
2616 .hword (0x17<<8) |(1<<VFlag)|(1<<NFlag) \r
2617 .hword (0x18<<8) |(1<<VFlag)|(1<<NFlag) \r
2618 .hword (0x19<<8) |(1<<NFlag) \r
2619 .hword (0x14<<8) |(1<<VFlag)|(1<<NFlag) \r
2620 .hword (0x15<<8) |(1<<NFlag) \r
2621 .hword (0x16<<8) |(1<<NFlag) \r
2622 .hword (0x17<<8) |(1<<VFlag)|(1<<NFlag) \r
2623 .hword (0x18<<8) |(1<<VFlag)|(1<<NFlag) \r
2624 .hword (0x19<<8) |(1<<NFlag) \r
2625 .hword (0x20<<8) |(1<<NFlag) \r
2626 .hword (0x21<<8) |(1<<VFlag)|(1<<NFlag) \r
2627 .hword (0x22<<8) |(1<<VFlag)|(1<<NFlag) \r
2628 .hword (0x23<<8) |(1<<NFlag) \r
2629 .hword (0x24<<8) |(1<<VFlag)|(1<<NFlag) \r
2630 .hword (0x25<<8) |(1<<NFlag) \r
2631 .hword (0x26<<8) |(1<<NFlag) \r
2632 .hword (0x27<<8) |(1<<VFlag)|(1<<NFlag) \r
2633 .hword (0x28<<8) |(1<<VFlag)|(1<<NFlag) \r
2634 .hword (0x29<<8) |(1<<NFlag) \r
2635 .hword (0x24<<8) |(1<<VFlag)|(1<<NFlag) \r
2636 .hword (0x25<<8) |(1<<NFlag) \r
2637 .hword (0x26<<8) |(1<<NFlag) \r
2638 .hword (0x27<<8) |(1<<VFlag)|(1<<NFlag) \r
2639 .hword (0x28<<8) |(1<<VFlag)|(1<<NFlag) \r
2640 .hword (0x29<<8) |(1<<NFlag) \r
2641 .hword (0x30<<8) |(1<<VFlag)|(1<<NFlag) \r
2642 .hword (0x31<<8) |(1<<NFlag) \r
2643 .hword (0x32<<8) |(1<<NFlag) \r
2644 .hword (0x33<<8) |(1<<VFlag)|(1<<NFlag) \r
2645 .hword (0x34<<8) |(1<<NFlag) \r
2646 .hword (0x35<<8) |(1<<VFlag)|(1<<NFlag) \r
2647 .hword (0x36<<8) |(1<<VFlag)|(1<<NFlag) \r
2648 .hword (0x37<<8) |(1<<NFlag) \r
2649 .hword (0x38<<8) |(1<<NFlag) \r
2650 .hword (0x39<<8) |(1<<VFlag)|(1<<NFlag) \r
2651 .hword (0x34<<8) |(1<<NFlag) \r
2652 .hword (0x35<<8) |(1<<VFlag)|(1<<NFlag) \r
2653 .hword (0x36<<8) |(1<<VFlag)|(1<<NFlag) \r
2654 .hword (0x37<<8) |(1<<NFlag) \r
2655 .hword (0x38<<8) |(1<<NFlag) \r
2656 .hword (0x39<<8) |(1<<VFlag)|(1<<NFlag) \r
2657 .hword (0x40<<8) |(1<<NFlag) \r
2658 .hword (0x41<<8) |(1<<VFlag)|(1<<NFlag) \r
2659 .hword (0x42<<8) |(1<<VFlag)|(1<<NFlag) \r
2660 .hword (0x43<<8) |(1<<NFlag) \r
2661 .hword (0x44<<8) |(1<<VFlag)|(1<<NFlag) \r
2662 .hword (0x45<<8) |(1<<NFlag) \r
2663 .hword (0x46<<8) |(1<<NFlag) \r
2664 .hword (0x47<<8) |(1<<VFlag)|(1<<NFlag) \r
2665 .hword (0x48<<8) |(1<<VFlag)|(1<<NFlag) \r
2666 .hword (0x49<<8) |(1<<NFlag) \r
2667 .hword (0x44<<8) |(1<<VFlag)|(1<<NFlag) \r
2668 .hword (0x45<<8) |(1<<NFlag) \r
2669 .hword (0x46<<8) |(1<<NFlag) \r
2670 .hword (0x47<<8) |(1<<VFlag)|(1<<NFlag) \r
2671 .hword (0x48<<8) |(1<<VFlag)|(1<<NFlag) \r
2672 .hword (0x49<<8) |(1<<NFlag) \r
2673 .hword (0x50<<8) |(1<<VFlag)|(1<<NFlag) \r
2674 .hword (0x51<<8) |(1<<NFlag) \r
2675 .hword (0x52<<8) |(1<<NFlag) \r
2676 .hword (0x53<<8) |(1<<VFlag)|(1<<NFlag) \r
2677 .hword (0x54<<8) |(1<<NFlag) \r
2678 .hword (0x55<<8) |(1<<VFlag)|(1<<NFlag) \r
2679 .hword (0x56<<8) |(1<<VFlag)|(1<<NFlag) \r
2680 .hword (0x57<<8) |(1<<NFlag) \r
2681 .hword (0x58<<8) |(1<<NFlag) \r
2682 .hword (0x59<<8) |(1<<VFlag)|(1<<NFlag) \r
2683 .hword (0x54<<8) |(1<<NFlag) \r
2684 .hword (0x55<<8) |(1<<VFlag)|(1<<NFlag) \r
2685 .hword (0x56<<8) |(1<<VFlag)|(1<<NFlag) \r
2686 .hword (0x57<<8) |(1<<NFlag) \r
2687 .hword (0x58<<8) |(1<<NFlag) \r
2688 .hword (0x59<<8) |(1<<VFlag)|(1<<NFlag) \r
2689 .hword (0x60<<8) |(1<<VFlag)|(1<<NFlag) \r
2690 .hword (0x61<<8) |(1<<NFlag) \r
2691 .hword (0x62<<8) |(1<<NFlag) \r
2692 .hword (0x63<<8) |(1<<VFlag)|(1<<NFlag) \r
2693 .hword (0x64<<8) |(1<<NFlag) \r
2694 .hword (0x65<<8) |(1<<VFlag)|(1<<NFlag) \r
2695 .hword (0x66<<8) |(1<<VFlag)|(1<<NFlag) \r
2696 .hword (0x67<<8) |(1<<NFlag) \r
2697 .hword (0x68<<8) |(1<<NFlag) \r
2698 .hword (0x69<<8) |(1<<VFlag)|(1<<NFlag) \r
2699 .hword (0x64<<8) |(1<<NFlag) \r
2700 .hword (0x65<<8) |(1<<VFlag)|(1<<NFlag) \r
2701 .hword (0x66<<8) |(1<<VFlag)|(1<<NFlag) \r
2702 .hword (0x67<<8) |(1<<NFlag) \r
2703 .hword (0x68<<8) |(1<<NFlag) \r
2704 .hword (0x69<<8) |(1<<VFlag)|(1<<NFlag) \r
2705 .hword (0x70<<8) |(1<<NFlag) \r
2706 .hword (0x71<<8) |(1<<VFlag)|(1<<NFlag) \r
2707 .hword (0x72<<8) |(1<<VFlag)|(1<<NFlag) \r
2708 .hword (0x73<<8) |(1<<NFlag) \r
2709 .hword (0x74<<8) |(1<<VFlag)|(1<<NFlag) \r
2710 .hword (0x75<<8) |(1<<NFlag) \r
2711 .hword (0x76<<8) |(1<<NFlag) \r
2712 .hword (0x77<<8) |(1<<VFlag)|(1<<NFlag) \r
2713 .hword (0x78<<8) |(1<<VFlag)|(1<<NFlag) \r
2714 .hword (0x79<<8) |(1<<NFlag) \r
2715 .hword (0x74<<8) |(1<<VFlag)|(1<<NFlag) \r
2716 .hword (0x75<<8) |(1<<NFlag) \r
2717 .hword (0x76<<8) |(1<<NFlag) \r
2718 .hword (0x77<<8) |(1<<VFlag)|(1<<NFlag) \r
2719 .hword (0x78<<8) |(1<<VFlag)|(1<<NFlag) \r
2720 .hword (0x79<<8) |(1<<NFlag) \r
2721 .hword (0x80<<8)|(1<<SFlag) |(1<<NFlag) \r
2722 .hword (0x81<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag) \r
2723 .hword (0x82<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag) \r
2724 .hword (0x83<<8)|(1<<SFlag) |(1<<NFlag) \r
2725 .hword (0x84<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag) \r
2726 .hword (0x85<<8)|(1<<SFlag) |(1<<NFlag) \r
2727 .hword (0x86<<8)|(1<<SFlag) |(1<<NFlag) \r
2728 .hword (0x87<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag) \r
2729 .hword (0x88<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag) \r
2730 .hword (0x89<<8)|(1<<SFlag) |(1<<NFlag) \r
2731 .hword (0x84<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag) \r
2732 .hword (0x85<<8)|(1<<SFlag) |(1<<NFlag) \r
2733 .hword (0x86<<8)|(1<<SFlag) |(1<<NFlag) \r
2734 .hword (0x87<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag) \r
2735 .hword (0x88<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag) \r
2736 .hword (0x89<<8)|(1<<SFlag) |(1<<NFlag) \r
2737 .hword (0x90<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag) \r
2738 .hword (0x91<<8)|(1<<SFlag) |(1<<NFlag) \r
2739 .hword (0x92<<8)|(1<<SFlag) |(1<<NFlag) \r
2740 .hword (0x93<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag) \r
2741 .hword (0x94<<8)|(1<<SFlag) |(1<<NFlag) \r
2742 .hword (0x95<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag) \r
2743 .hword (0x96<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag) \r
2744 .hword (0x97<<8)|(1<<SFlag) |(1<<NFlag) \r
2745 .hword (0x98<<8)|(1<<SFlag) |(1<<NFlag) \r
2746 .hword (0x99<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag) \r
2747 .hword (0x34<<8) |(1<<NFlag)|(1<<CFlag)\r
2748 .hword (0x35<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2749 .hword (0x36<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2750 .hword (0x37<<8) |(1<<NFlag)|(1<<CFlag)\r
2751 .hword (0x38<<8) |(1<<NFlag)|(1<<CFlag)\r
2752 .hword (0x39<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2753 .hword (0x40<<8) |(1<<NFlag)|(1<<CFlag)\r
2754 .hword (0x41<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2755 .hword (0x42<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2756 .hword (0x43<<8) |(1<<NFlag)|(1<<CFlag)\r
2757 .hword (0x44<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2758 .hword (0x45<<8) |(1<<NFlag)|(1<<CFlag)\r
2759 .hword (0x46<<8) |(1<<NFlag)|(1<<CFlag)\r
2760 .hword (0x47<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2761 .hword (0x48<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2762 .hword (0x49<<8) |(1<<NFlag)|(1<<CFlag)\r
2763 .hword (0x44<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2764 .hword (0x45<<8) |(1<<NFlag)|(1<<CFlag)\r
2765 .hword (0x46<<8) |(1<<NFlag)|(1<<CFlag)\r
2766 .hword (0x47<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2767 .hword (0x48<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2768 .hword (0x49<<8) |(1<<NFlag)|(1<<CFlag)\r
2769 .hword (0x50<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2770 .hword (0x51<<8) |(1<<NFlag)|(1<<CFlag)\r
2771 .hword (0x52<<8) |(1<<NFlag)|(1<<CFlag)\r
2772 .hword (0x53<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2773 .hword (0x54<<8) |(1<<NFlag)|(1<<CFlag)\r
2774 .hword (0x55<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2775 .hword (0x56<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2776 .hword (0x57<<8) |(1<<NFlag)|(1<<CFlag)\r
2777 .hword (0x58<<8) |(1<<NFlag)|(1<<CFlag)\r
2778 .hword (0x59<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2779 .hword (0x54<<8) |(1<<NFlag)|(1<<CFlag)\r
2780 .hword (0x55<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2781 .hword (0x56<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2782 .hword (0x57<<8) |(1<<NFlag)|(1<<CFlag)\r
2783 .hword (0x58<<8) |(1<<NFlag)|(1<<CFlag)\r
2784 .hword (0x59<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2785 .hword (0x60<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2786 .hword (0x61<<8) |(1<<NFlag)|(1<<CFlag)\r
2787 .hword (0x62<<8) |(1<<NFlag)|(1<<CFlag)\r
2788 .hword (0x63<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2789 .hword (0x64<<8) |(1<<NFlag)|(1<<CFlag)\r
2790 .hword (0x65<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2791 .hword (0x66<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2792 .hword (0x67<<8) |(1<<NFlag)|(1<<CFlag)\r
2793 .hword (0x68<<8) |(1<<NFlag)|(1<<CFlag)\r
2794 .hword (0x69<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2795 .hword (0x64<<8) |(1<<NFlag)|(1<<CFlag)\r
2796 .hword (0x65<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2797 .hword (0x66<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2798 .hword (0x67<<8) |(1<<NFlag)|(1<<CFlag)\r
2799 .hword (0x68<<8) |(1<<NFlag)|(1<<CFlag)\r
2800 .hword (0x69<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2801 .hword (0x70<<8) |(1<<NFlag)|(1<<CFlag)\r
2802 .hword (0x71<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2803 .hword (0x72<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2804 .hword (0x73<<8) |(1<<NFlag)|(1<<CFlag)\r
2805 .hword (0x74<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2806 .hword (0x75<<8) |(1<<NFlag)|(1<<CFlag)\r
2807 .hword (0x76<<8) |(1<<NFlag)|(1<<CFlag)\r
2808 .hword (0x77<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2809 .hword (0x78<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2810 .hword (0x79<<8) |(1<<NFlag)|(1<<CFlag)\r
2811 .hword (0x74<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2812 .hword (0x75<<8) |(1<<NFlag)|(1<<CFlag)\r
2813 .hword (0x76<<8) |(1<<NFlag)|(1<<CFlag)\r
2814 .hword (0x77<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2815 .hword (0x78<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2816 .hword (0x79<<8) |(1<<NFlag)|(1<<CFlag)\r
2817 .hword (0x80<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2818 .hword (0x81<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2819 .hword (0x82<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2820 .hword (0x83<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2821 .hword (0x84<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2822 .hword (0x85<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2823 .hword (0x86<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2824 .hword (0x87<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2825 .hword (0x88<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2826 .hword (0x89<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2827 .hword (0x84<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2828 .hword (0x85<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2829 .hword (0x86<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2830 .hword (0x87<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2831 .hword (0x88<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2832 .hword (0x89<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2833 .hword (0x90<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2834 .hword (0x91<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2835 .hword (0x92<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2836 .hword (0x93<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2837 .hword (0x94<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2838 .hword (0x95<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2839 .hword (0x96<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2840 .hword (0x97<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2841 .hword (0x98<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2842 .hword (0x99<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2843 .hword (0x94<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2844 .hword (0x95<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2845 .hword (0x96<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2846 .hword (0x97<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2847 .hword (0x98<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2848 .hword (0x99<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2849 .hword (0xA0<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2850 .hword (0xA1<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2851 .hword (0xA2<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2852 .hword (0xA3<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2853 .hword (0xA4<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2854 .hword (0xA5<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2855 .hword (0xA6<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2856 .hword (0xA7<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2857 .hword (0xA8<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2858 .hword (0xA9<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2859 .hword (0xA4<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2860 .hword (0xA5<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2861 .hword (0xA6<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2862 .hword (0xA7<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2863 .hword (0xA8<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2864 .hword (0xA9<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2865 .hword (0xB0<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2866 .hword (0xB1<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2867 .hword (0xB2<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2868 .hword (0xB3<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2869 .hword (0xB4<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2870 .hword (0xB5<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2871 .hword (0xB6<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2872 .hword (0xB7<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2873 .hword (0xB8<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2874 .hword (0xB9<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2875 .hword (0xB4<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2876 .hword (0xB5<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2877 .hword (0xB6<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2878 .hword (0xB7<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2879 .hword (0xB8<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2880 .hword (0xB9<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2881 .hword (0xC0<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2882 .hword (0xC1<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2883 .hword (0xC2<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2884 .hword (0xC3<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2885 .hword (0xC4<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2886 .hword (0xC5<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2887 .hword (0xC6<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2888 .hword (0xC7<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2889 .hword (0xC8<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2890 .hword (0xC9<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2891 .hword (0xC4<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2892 .hword (0xC5<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2893 .hword (0xC6<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2894 .hword (0xC7<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2895 .hword (0xC8<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2896 .hword (0xC9<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2897 .hword (0xD0<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2898 .hword (0xD1<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2899 .hword (0xD2<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2900 .hword (0xD3<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2901 .hword (0xD4<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2902 .hword (0xD5<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2903 .hword (0xD6<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2904 .hword (0xD7<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2905 .hword (0xD8<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2906 .hword (0xD9<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2907 .hword (0xD4<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2908 .hword (0xD5<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2909 .hword (0xD6<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2910 .hword (0xD7<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2911 .hword (0xD8<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2912 .hword (0xD9<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2913 .hword (0xE0<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2914 .hword (0xE1<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2915 .hword (0xE2<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2916 .hword (0xE3<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2917 .hword (0xE4<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2918 .hword (0xE5<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2919 .hword (0xE6<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2920 .hword (0xE7<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2921 .hword (0xE8<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2922 .hword (0xE9<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2923 .hword (0xE4<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2924 .hword (0xE5<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2925 .hword (0xE6<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2926 .hword (0xE7<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2927 .hword (0xE8<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2928 .hword (0xE9<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2929 .hword (0xF0<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2930 .hword (0xF1<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2931 .hword (0xF2<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2932 .hword (0xF3<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2933 .hword (0xF4<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2934 .hword (0xF5<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2935 .hword (0xF6<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2936 .hword (0xF7<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2937 .hword (0xF8<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2938 .hword (0xF9<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2939 .hword (0xF4<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2940 .hword (0xF5<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2941 .hword (0xF6<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2942 .hword (0xF7<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2943 .hword (0xF8<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
2944 .hword (0xF9<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2945 .hword (0x00<<8) |(1<<ZFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2946 .hword (0x01<<8) |(1<<NFlag)|(1<<CFlag)\r
2947 .hword (0x02<<8) |(1<<NFlag)|(1<<CFlag)\r
2948 .hword (0x03<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2949 .hword (0x04<<8) |(1<<NFlag)|(1<<CFlag)\r
2950 .hword (0x05<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2951 .hword (0x06<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2952 .hword (0x07<<8) |(1<<NFlag)|(1<<CFlag)\r
2953 .hword (0x08<<8) |(1<<NFlag)|(1<<CFlag)\r
2954 .hword (0x09<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2955 .hword (0x04<<8) |(1<<NFlag)|(1<<CFlag)\r
2956 .hword (0x05<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2957 .hword (0x06<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2958 .hword (0x07<<8) |(1<<NFlag)|(1<<CFlag)\r
2959 .hword (0x08<<8) |(1<<NFlag)|(1<<CFlag)\r
2960 .hword (0x09<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2961 .hword (0x10<<8) |(1<<NFlag)|(1<<CFlag)\r
2962 .hword (0x11<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2963 .hword (0x12<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2964 .hword (0x13<<8) |(1<<NFlag)|(1<<CFlag)\r
2965 .hword (0x14<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2966 .hword (0x15<<8) |(1<<NFlag)|(1<<CFlag)\r
2967 .hword (0x16<<8) |(1<<NFlag)|(1<<CFlag)\r
2968 .hword (0x17<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2969 .hword (0x18<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2970 .hword (0x19<<8) |(1<<NFlag)|(1<<CFlag)\r
2971 .hword (0x14<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2972 .hword (0x15<<8) |(1<<NFlag)|(1<<CFlag)\r
2973 .hword (0x16<<8) |(1<<NFlag)|(1<<CFlag)\r
2974 .hword (0x17<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2975 .hword (0x18<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2976 .hword (0x19<<8) |(1<<NFlag)|(1<<CFlag)\r
2977 .hword (0x20<<8) |(1<<NFlag)|(1<<CFlag)\r
2978 .hword (0x21<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2979 .hword (0x22<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2980 .hword (0x23<<8) |(1<<NFlag)|(1<<CFlag)\r
2981 .hword (0x24<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2982 .hword (0x25<<8) |(1<<NFlag)|(1<<CFlag)\r
2983 .hword (0x26<<8) |(1<<NFlag)|(1<<CFlag)\r
2984 .hword (0x27<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2985 .hword (0x28<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2986 .hword (0x29<<8) |(1<<NFlag)|(1<<CFlag)\r
2987 .hword (0x24<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2988 .hword (0x25<<8) |(1<<NFlag)|(1<<CFlag)\r
2989 .hword (0x26<<8) |(1<<NFlag)|(1<<CFlag)\r
2990 .hword (0x27<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2991 .hword (0x28<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2992 .hword (0x29<<8) |(1<<NFlag)|(1<<CFlag)\r
2993 .hword (0x30<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2994 .hword (0x31<<8) |(1<<NFlag)|(1<<CFlag)\r
2995 .hword (0x32<<8) |(1<<NFlag)|(1<<CFlag)\r
2996 .hword (0x33<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2997 .hword (0x34<<8) |(1<<NFlag)|(1<<CFlag)\r
2998 .hword (0x35<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
2999 .hword (0x36<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3000 .hword (0x37<<8) |(1<<NFlag)|(1<<CFlag)\r
3001 .hword (0x38<<8) |(1<<NFlag)|(1<<CFlag)\r
3002 .hword (0x39<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3003 .hword (0x34<<8) |(1<<NFlag)|(1<<CFlag)\r
3004 .hword (0x35<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3005 .hword (0x36<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3006 .hword (0x37<<8) |(1<<NFlag)|(1<<CFlag)\r
3007 .hword (0x38<<8) |(1<<NFlag)|(1<<CFlag)\r
3008 .hword (0x39<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3009 .hword (0x40<<8) |(1<<NFlag)|(1<<CFlag)\r
3010 .hword (0x41<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3011 .hword (0x42<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3012 .hword (0x43<<8) |(1<<NFlag)|(1<<CFlag)\r
3013 .hword (0x44<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3014 .hword (0x45<<8) |(1<<NFlag)|(1<<CFlag)\r
3015 .hword (0x46<<8) |(1<<NFlag)|(1<<CFlag)\r
3016 .hword (0x47<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3017 .hword (0x48<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3018 .hword (0x49<<8) |(1<<NFlag)|(1<<CFlag)\r
3019 .hword (0x44<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3020 .hword (0x45<<8) |(1<<NFlag)|(1<<CFlag)\r
3021 .hword (0x46<<8) |(1<<NFlag)|(1<<CFlag)\r
3022 .hword (0x47<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3023 .hword (0x48<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3024 .hword (0x49<<8) |(1<<NFlag)|(1<<CFlag)\r
3025 .hword (0x50<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3026 .hword (0x51<<8) |(1<<NFlag)|(1<<CFlag)\r
3027 .hword (0x52<<8) |(1<<NFlag)|(1<<CFlag)\r
3028 .hword (0x53<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3029 .hword (0x54<<8) |(1<<NFlag)|(1<<CFlag)\r
3030 .hword (0x55<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3031 .hword (0x56<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3032 .hword (0x57<<8) |(1<<NFlag)|(1<<CFlag)\r
3033 .hword (0x58<<8) |(1<<NFlag)|(1<<CFlag)\r
3034 .hword (0x59<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3035 .hword (0x54<<8) |(1<<NFlag)|(1<<CFlag)\r
3036 .hword (0x55<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3037 .hword (0x56<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3038 .hword (0x57<<8) |(1<<NFlag)|(1<<CFlag)\r
3039 .hword (0x58<<8) |(1<<NFlag)|(1<<CFlag)\r
3040 .hword (0x59<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3041 .hword (0x60<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3042 .hword (0x61<<8) |(1<<NFlag)|(1<<CFlag)\r
3043 .hword (0x62<<8) |(1<<NFlag)|(1<<CFlag)\r
3044 .hword (0x63<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3045 .hword (0x64<<8) |(1<<NFlag)|(1<<CFlag)\r
3046 .hword (0x65<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3047 .hword (0x66<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3048 .hword (0x67<<8) |(1<<NFlag)|(1<<CFlag)\r
3049 .hword (0x68<<8) |(1<<NFlag)|(1<<CFlag)\r
3050 .hword (0x69<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3051 .hword (0x64<<8) |(1<<NFlag)|(1<<CFlag)\r
3052 .hword (0x65<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3053 .hword (0x66<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3054 .hword (0x67<<8) |(1<<NFlag)|(1<<CFlag)\r
3055 .hword (0x68<<8) |(1<<NFlag)|(1<<CFlag)\r
3056 .hword (0x69<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3057 .hword (0x70<<8) |(1<<NFlag)|(1<<CFlag)\r
3058 .hword (0x71<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3059 .hword (0x72<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3060 .hword (0x73<<8) |(1<<NFlag)|(1<<CFlag)\r
3061 .hword (0x74<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3062 .hword (0x75<<8) |(1<<NFlag)|(1<<CFlag)\r
3063 .hword (0x76<<8) |(1<<NFlag)|(1<<CFlag)\r
3064 .hword (0x77<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3065 .hword (0x78<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3066 .hword (0x79<<8) |(1<<NFlag)|(1<<CFlag)\r
3067 .hword (0x74<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3068 .hword (0x75<<8) |(1<<NFlag)|(1<<CFlag)\r
3069 .hword (0x76<<8) |(1<<NFlag)|(1<<CFlag)\r
3070 .hword (0x77<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3071 .hword (0x78<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3072 .hword (0x79<<8) |(1<<NFlag)|(1<<CFlag)\r
3073 .hword (0x80<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3074 .hword (0x81<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3075 .hword (0x82<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3076 .hword (0x83<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3077 .hword (0x84<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3078 .hword (0x85<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3079 .hword (0x86<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3080 .hword (0x87<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3081 .hword (0x88<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3082 .hword (0x89<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3083 .hword (0x84<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3084 .hword (0x85<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3085 .hword (0x86<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3086 .hword (0x87<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3087 .hword (0x88<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3088 .hword (0x89<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3089 .hword (0x90<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3090 .hword (0x91<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3091 .hword (0x92<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3092 .hword (0x93<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3093 .hword (0x94<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3094 .hword (0x95<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3095 .hword (0x96<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3096 .hword (0x97<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3097 .hword (0x98<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3098 .hword (0x99<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3099 .hword (0x94<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3100 .hword (0x95<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3101 .hword (0x96<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3102 .hword (0x97<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3103 .hword (0x98<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3104 .hword (0x99<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3105 .hword (0xFA<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3106 .hword (0xFB<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag) \r
3107 .hword (0xFC<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3108 .hword (0xFD<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag) \r
3109 .hword (0xFE<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag) \r
3110 .hword (0xFF<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3111 .hword (0x00<<8) |(1<<ZFlag) |(1<<VFlag)|(1<<NFlag) \r
3112 .hword (0x01<<8) |(1<<NFlag) \r
3113 .hword (0x02<<8) |(1<<NFlag) \r
3114 .hword (0x03<<8) |(1<<VFlag)|(1<<NFlag) \r
3115 .hword (0x04<<8) |(1<<NFlag) \r
3116 .hword (0x05<<8) |(1<<VFlag)|(1<<NFlag) \r
3117 .hword (0x06<<8) |(1<<VFlag)|(1<<NFlag) \r
3118 .hword (0x07<<8) |(1<<NFlag) \r
3119 .hword (0x08<<8) |(1<<NFlag) \r
3120 .hword (0x09<<8) |(1<<VFlag)|(1<<NFlag) \r
3121 .hword (0x0A<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3122 .hword (0x0B<<8) |(1<<HFlag) |(1<<NFlag) \r
3123 .hword (0x0C<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3124 .hword (0x0D<<8) |(1<<HFlag) |(1<<NFlag) \r
3125 .hword (0x0E<<8) |(1<<HFlag) |(1<<NFlag) \r
3126 .hword (0x0F<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3127 .hword (0x10<<8) |(1<<NFlag) \r
3128 .hword (0x11<<8) |(1<<VFlag)|(1<<NFlag) \r
3129 .hword (0x12<<8) |(1<<VFlag)|(1<<NFlag) \r
3130 .hword (0x13<<8) |(1<<NFlag) \r
3131 .hword (0x14<<8) |(1<<VFlag)|(1<<NFlag) \r
3132 .hword (0x15<<8) |(1<<NFlag) \r
3133 .hword (0x16<<8) |(1<<NFlag) \r
3134 .hword (0x17<<8) |(1<<VFlag)|(1<<NFlag) \r
3135 .hword (0x18<<8) |(1<<VFlag)|(1<<NFlag) \r
3136 .hword (0x19<<8) |(1<<NFlag) \r
3137 .hword (0x1A<<8) |(1<<HFlag) |(1<<NFlag) \r
3138 .hword (0x1B<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3139 .hword (0x1C<<8) |(1<<HFlag) |(1<<NFlag) \r
3140 .hword (0x1D<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3141 .hword (0x1E<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3142 .hword (0x1F<<8) |(1<<HFlag) |(1<<NFlag) \r
3143 .hword (0x20<<8) |(1<<NFlag) \r
3144 .hword (0x21<<8) |(1<<VFlag)|(1<<NFlag) \r
3145 .hword (0x22<<8) |(1<<VFlag)|(1<<NFlag) \r
3146 .hword (0x23<<8) |(1<<NFlag) \r
3147 .hword (0x24<<8) |(1<<VFlag)|(1<<NFlag) \r
3148 .hword (0x25<<8) |(1<<NFlag) \r
3149 .hword (0x26<<8) |(1<<NFlag) \r
3150 .hword (0x27<<8) |(1<<VFlag)|(1<<NFlag) \r
3151 .hword (0x28<<8) |(1<<VFlag)|(1<<NFlag) \r
3152 .hword (0x29<<8) |(1<<NFlag) \r
3153 .hword (0x2A<<8) |(1<<HFlag) |(1<<NFlag) \r
3154 .hword (0x2B<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3155 .hword (0x2C<<8) |(1<<HFlag) |(1<<NFlag) \r
3156 .hword (0x2D<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3157 .hword (0x2E<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3158 .hword (0x2F<<8) |(1<<HFlag) |(1<<NFlag) \r
3159 .hword (0x30<<8) |(1<<VFlag)|(1<<NFlag) \r
3160 .hword (0x31<<8) |(1<<NFlag) \r
3161 .hword (0x32<<8) |(1<<NFlag) \r
3162 .hword (0x33<<8) |(1<<VFlag)|(1<<NFlag) \r
3163 .hword (0x34<<8) |(1<<NFlag) \r
3164 .hword (0x35<<8) |(1<<VFlag)|(1<<NFlag) \r
3165 .hword (0x36<<8) |(1<<VFlag)|(1<<NFlag) \r
3166 .hword (0x37<<8) |(1<<NFlag) \r
3167 .hword (0x38<<8) |(1<<NFlag) \r
3168 .hword (0x39<<8) |(1<<VFlag)|(1<<NFlag) \r
3169 .hword (0x3A<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3170 .hword (0x3B<<8) |(1<<HFlag) |(1<<NFlag) \r
3171 .hword (0x3C<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3172 .hword (0x3D<<8) |(1<<HFlag) |(1<<NFlag) \r
3173 .hword (0x3E<<8) |(1<<HFlag) |(1<<NFlag) \r
3174 .hword (0x3F<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3175 .hword (0x40<<8) |(1<<NFlag) \r
3176 .hword (0x41<<8) |(1<<VFlag)|(1<<NFlag) \r
3177 .hword (0x42<<8) |(1<<VFlag)|(1<<NFlag) \r
3178 .hword (0x43<<8) |(1<<NFlag) \r
3179 .hword (0x44<<8) |(1<<VFlag)|(1<<NFlag) \r
3180 .hword (0x45<<8) |(1<<NFlag) \r
3181 .hword (0x46<<8) |(1<<NFlag) \r
3182 .hword (0x47<<8) |(1<<VFlag)|(1<<NFlag) \r
3183 .hword (0x48<<8) |(1<<VFlag)|(1<<NFlag) \r
3184 .hword (0x49<<8) |(1<<NFlag) \r
3185 .hword (0x4A<<8) |(1<<HFlag) |(1<<NFlag) \r
3186 .hword (0x4B<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3187 .hword (0x4C<<8) |(1<<HFlag) |(1<<NFlag) \r
3188 .hword (0x4D<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3189 .hword (0x4E<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3190 .hword (0x4F<<8) |(1<<HFlag) |(1<<NFlag) \r
3191 .hword (0x50<<8) |(1<<VFlag)|(1<<NFlag) \r
3192 .hword (0x51<<8) |(1<<NFlag) \r
3193 .hword (0x52<<8) |(1<<NFlag) \r
3194 .hword (0x53<<8) |(1<<VFlag)|(1<<NFlag) \r
3195 .hword (0x54<<8) |(1<<NFlag) \r
3196 .hword (0x55<<8) |(1<<VFlag)|(1<<NFlag) \r
3197 .hword (0x56<<8) |(1<<VFlag)|(1<<NFlag) \r
3198 .hword (0x57<<8) |(1<<NFlag) \r
3199 .hword (0x58<<8) |(1<<NFlag) \r
3200 .hword (0x59<<8) |(1<<VFlag)|(1<<NFlag) \r
3201 .hword (0x5A<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3202 .hword (0x5B<<8) |(1<<HFlag) |(1<<NFlag) \r
3203 .hword (0x5C<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3204 .hword (0x5D<<8) |(1<<HFlag) |(1<<NFlag) \r
3205 .hword (0x5E<<8) |(1<<HFlag) |(1<<NFlag) \r
3206 .hword (0x5F<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3207 .hword (0x60<<8) |(1<<VFlag)|(1<<NFlag) \r
3208 .hword (0x61<<8) |(1<<NFlag) \r
3209 .hword (0x62<<8) |(1<<NFlag) \r
3210 .hword (0x63<<8) |(1<<VFlag)|(1<<NFlag) \r
3211 .hword (0x64<<8) |(1<<NFlag) \r
3212 .hword (0x65<<8) |(1<<VFlag)|(1<<NFlag) \r
3213 .hword (0x66<<8) |(1<<VFlag)|(1<<NFlag) \r
3214 .hword (0x67<<8) |(1<<NFlag) \r
3215 .hword (0x68<<8) |(1<<NFlag) \r
3216 .hword (0x69<<8) |(1<<VFlag)|(1<<NFlag) \r
3217 .hword (0x6A<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3218 .hword (0x6B<<8) |(1<<HFlag) |(1<<NFlag) \r
3219 .hword (0x6C<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3220 .hword (0x6D<<8) |(1<<HFlag) |(1<<NFlag) \r
3221 .hword (0x6E<<8) |(1<<HFlag) |(1<<NFlag) \r
3222 .hword (0x6F<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3223 .hword (0x70<<8) |(1<<NFlag) \r
3224 .hword (0x71<<8) |(1<<VFlag)|(1<<NFlag) \r
3225 .hword (0x72<<8) |(1<<VFlag)|(1<<NFlag) \r
3226 .hword (0x73<<8) |(1<<NFlag) \r
3227 .hword (0x74<<8) |(1<<VFlag)|(1<<NFlag) \r
3228 .hword (0x75<<8) |(1<<NFlag) \r
3229 .hword (0x76<<8) |(1<<NFlag) \r
3230 .hword (0x77<<8) |(1<<VFlag)|(1<<NFlag) \r
3231 .hword (0x78<<8) |(1<<VFlag)|(1<<NFlag) \r
3232 .hword (0x79<<8) |(1<<NFlag) \r
3233 .hword (0x7A<<8) |(1<<HFlag) |(1<<NFlag) \r
3234 .hword (0x7B<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3235 .hword (0x7C<<8) |(1<<HFlag) |(1<<NFlag) \r
3236 .hword (0x7D<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3237 .hword (0x7E<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3238 .hword (0x7F<<8) |(1<<HFlag) |(1<<NFlag) \r
3239 .hword (0x80<<8)|(1<<SFlag) |(1<<NFlag) \r
3240 .hword (0x81<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag) \r
3241 .hword (0x82<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag) \r
3242 .hword (0x83<<8)|(1<<SFlag) |(1<<NFlag) \r
3243 .hword (0x84<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag) \r
3244 .hword (0x85<<8)|(1<<SFlag) |(1<<NFlag) \r
3245 .hword (0x86<<8)|(1<<SFlag) |(1<<NFlag) \r
3246 .hword (0x87<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag) \r
3247 .hword (0x88<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag) \r
3248 .hword (0x89<<8)|(1<<SFlag) |(1<<NFlag) \r
3249 .hword (0x8A<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag) \r
3250 .hword (0x8B<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3251 .hword (0x8C<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag) \r
3252 .hword (0x8D<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3253 .hword (0x8E<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag) \r
3254 .hword (0x8F<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag) \r
3255 .hword (0x90<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag) \r
3256 .hword (0x91<<8)|(1<<SFlag) |(1<<NFlag) \r
3257 .hword (0x92<<8)|(1<<SFlag) |(1<<NFlag) \r
3258 .hword (0x93<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag) \r
3259 .hword (0x34<<8) |(1<<NFlag)|(1<<CFlag)\r
3260 .hword (0x35<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3261 .hword (0x36<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3262 .hword (0x37<<8) |(1<<NFlag)|(1<<CFlag)\r
3263 .hword (0x38<<8) |(1<<NFlag)|(1<<CFlag)\r
3264 .hword (0x39<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3265 .hword (0x3A<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3266 .hword (0x3B<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3267 .hword (0x3C<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3268 .hword (0x3D<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3269 .hword (0x3E<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3270 .hword (0x3F<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3271 .hword (0x40<<8) |(1<<NFlag)|(1<<CFlag)\r
3272 .hword (0x41<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3273 .hword (0x42<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3274 .hword (0x43<<8) |(1<<NFlag)|(1<<CFlag)\r
3275 .hword (0x44<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3276 .hword (0x45<<8) |(1<<NFlag)|(1<<CFlag)\r
3277 .hword (0x46<<8) |(1<<NFlag)|(1<<CFlag)\r
3278 .hword (0x47<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3279 .hword (0x48<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3280 .hword (0x49<<8) |(1<<NFlag)|(1<<CFlag)\r
3281 .hword (0x4A<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3282 .hword (0x4B<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3283 .hword (0x4C<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3284 .hword (0x4D<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3285 .hword (0x4E<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3286 .hword (0x4F<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3287 .hword (0x50<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3288 .hword (0x51<<8) |(1<<NFlag)|(1<<CFlag)\r
3289 .hword (0x52<<8) |(1<<NFlag)|(1<<CFlag)\r
3290 .hword (0x53<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3291 .hword (0x54<<8) |(1<<NFlag)|(1<<CFlag)\r
3292 .hword (0x55<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3293 .hword (0x56<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3294 .hword (0x57<<8) |(1<<NFlag)|(1<<CFlag)\r
3295 .hword (0x58<<8) |(1<<NFlag)|(1<<CFlag)\r
3296 .hword (0x59<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3297 .hword (0x5A<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3298 .hword (0x5B<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3299 .hword (0x5C<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3300 .hword (0x5D<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3301 .hword (0x5E<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3302 .hword (0x5F<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3303 .hword (0x60<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3304 .hword (0x61<<8) |(1<<NFlag)|(1<<CFlag)\r
3305 .hword (0x62<<8) |(1<<NFlag)|(1<<CFlag)\r
3306 .hword (0x63<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3307 .hword (0x64<<8) |(1<<NFlag)|(1<<CFlag)\r
3308 .hword (0x65<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3309 .hword (0x66<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3310 .hword (0x67<<8) |(1<<NFlag)|(1<<CFlag)\r
3311 .hword (0x68<<8) |(1<<NFlag)|(1<<CFlag)\r
3312 .hword (0x69<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3313 .hword (0x6A<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3314 .hword (0x6B<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3315 .hword (0x6C<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3316 .hword (0x6D<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3317 .hword (0x6E<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3318 .hword (0x6F<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3319 .hword (0x70<<8) |(1<<NFlag)|(1<<CFlag)\r
3320 .hword (0x71<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3321 .hword (0x72<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3322 .hword (0x73<<8) |(1<<NFlag)|(1<<CFlag)\r
3323 .hword (0x74<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3324 .hword (0x75<<8) |(1<<NFlag)|(1<<CFlag)\r
3325 .hword (0x76<<8) |(1<<NFlag)|(1<<CFlag)\r
3326 .hword (0x77<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3327 .hword (0x78<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3328 .hword (0x79<<8) |(1<<NFlag)|(1<<CFlag)\r
3329 .hword (0x7A<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3330 .hword (0x7B<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3331 .hword (0x7C<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3332 .hword (0x7D<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3333 .hword (0x7E<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3334 .hword (0x7F<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3335 .hword (0x80<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3336 .hword (0x81<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3337 .hword (0x82<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3338 .hword (0x83<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3339 .hword (0x84<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3340 .hword (0x85<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3341 .hword (0x86<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3342 .hword (0x87<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3343 .hword (0x88<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3344 .hword (0x89<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3345 .hword (0x8A<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3346 .hword (0x8B<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3347 .hword (0x8C<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3348 .hword (0x8D<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3349 .hword (0x8E<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3350 .hword (0x8F<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3351 .hword (0x90<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3352 .hword (0x91<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3353 .hword (0x92<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3354 .hword (0x93<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3355 .hword (0x94<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3356 .hword (0x95<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3357 .hword (0x96<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3358 .hword (0x97<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3359 .hword (0x98<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3360 .hword (0x99<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3361 .hword (0x9A<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3362 .hword (0x9B<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3363 .hword (0x9C<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3364 .hword (0x9D<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3365 .hword (0x9E<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3366 .hword (0x9F<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3367 .hword (0xA0<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3368 .hword (0xA1<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3369 .hword (0xA2<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3370 .hword (0xA3<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3371 .hword (0xA4<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3372 .hword (0xA5<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3373 .hword (0xA6<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3374 .hword (0xA7<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3375 .hword (0xA8<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3376 .hword (0xA9<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3377 .hword (0xAA<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3378 .hword (0xAB<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3379 .hword (0xAC<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3380 .hword (0xAD<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3381 .hword (0xAE<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3382 .hword (0xAF<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3383 .hword (0xB0<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3384 .hword (0xB1<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3385 .hword (0xB2<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3386 .hword (0xB3<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3387 .hword (0xB4<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3388 .hword (0xB5<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3389 .hword (0xB6<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3390 .hword (0xB7<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3391 .hword (0xB8<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3392 .hword (0xB9<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3393 .hword (0xBA<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3394 .hword (0xBB<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3395 .hword (0xBC<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3396 .hword (0xBD<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3397 .hword (0xBE<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3398 .hword (0xBF<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3399 .hword (0xC0<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3400 .hword (0xC1<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3401 .hword (0xC2<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3402 .hword (0xC3<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3403 .hword (0xC4<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3404 .hword (0xC5<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3405 .hword (0xC6<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3406 .hword (0xC7<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3407 .hword (0xC8<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3408 .hword (0xC9<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3409 .hword (0xCA<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3410 .hword (0xCB<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3411 .hword (0xCC<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3412 .hword (0xCD<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3413 .hword (0xCE<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3414 .hword (0xCF<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3415 .hword (0xD0<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3416 .hword (0xD1<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3417 .hword (0xD2<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3418 .hword (0xD3<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3419 .hword (0xD4<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3420 .hword (0xD5<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3421 .hword (0xD6<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3422 .hword (0xD7<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3423 .hword (0xD8<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3424 .hword (0xD9<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3425 .hword (0xDA<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3426 .hword (0xDB<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3427 .hword (0xDC<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3428 .hword (0xDD<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3429 .hword (0xDE<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3430 .hword (0xDF<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3431 .hword (0xE0<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3432 .hword (0xE1<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3433 .hword (0xE2<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3434 .hword (0xE3<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3435 .hword (0xE4<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3436 .hword (0xE5<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3437 .hword (0xE6<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3438 .hword (0xE7<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3439 .hword (0xE8<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3440 .hword (0xE9<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3441 .hword (0xEA<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3442 .hword (0xEB<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3443 .hword (0xEC<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3444 .hword (0xED<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3445 .hword (0xEE<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3446 .hword (0xEF<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3447 .hword (0xF0<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3448 .hword (0xF1<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3449 .hword (0xF2<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3450 .hword (0xF3<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3451 .hword (0xF4<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3452 .hword (0xF5<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3453 .hword (0xF6<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3454 .hword (0xF7<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3455 .hword (0xF8<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3456 .hword (0xF9<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3457 .hword (0xFA<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3458 .hword (0xFB<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3459 .hword (0xFC<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3460 .hword (0xFD<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3461 .hword (0xFE<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3462 .hword (0xFF<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3463 .hword (0x00<<8) |(1<<ZFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3464 .hword (0x01<<8) |(1<<NFlag)|(1<<CFlag)\r
3465 .hword (0x02<<8) |(1<<NFlag)|(1<<CFlag)\r
3466 .hword (0x03<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3467 .hword (0x04<<8) |(1<<NFlag)|(1<<CFlag)\r
3468 .hword (0x05<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3469 .hword (0x06<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3470 .hword (0x07<<8) |(1<<NFlag)|(1<<CFlag)\r
3471 .hword (0x08<<8) |(1<<NFlag)|(1<<CFlag)\r
3472 .hword (0x09<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3473 .hword (0x0A<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3474 .hword (0x0B<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3475 .hword (0x0C<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3476 .hword (0x0D<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3477 .hword (0x0E<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3478 .hword (0x0F<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3479 .hword (0x10<<8) |(1<<NFlag)|(1<<CFlag)\r
3480 .hword (0x11<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3481 .hword (0x12<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3482 .hword (0x13<<8) |(1<<NFlag)|(1<<CFlag)\r
3483 .hword (0x14<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3484 .hword (0x15<<8) |(1<<NFlag)|(1<<CFlag)\r
3485 .hword (0x16<<8) |(1<<NFlag)|(1<<CFlag)\r
3486 .hword (0x17<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3487 .hword (0x18<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3488 .hword (0x19<<8) |(1<<NFlag)|(1<<CFlag)\r
3489 .hword (0x1A<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3490 .hword (0x1B<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3491 .hword (0x1C<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3492 .hword (0x1D<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3493 .hword (0x1E<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3494 .hword (0x1F<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3495 .hword (0x20<<8) |(1<<NFlag)|(1<<CFlag)\r
3496 .hword (0x21<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3497 .hword (0x22<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3498 .hword (0x23<<8) |(1<<NFlag)|(1<<CFlag)\r
3499 .hword (0x24<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3500 .hword (0x25<<8) |(1<<NFlag)|(1<<CFlag)\r
3501 .hword (0x26<<8) |(1<<NFlag)|(1<<CFlag)\r
3502 .hword (0x27<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3503 .hword (0x28<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3504 .hword (0x29<<8) |(1<<NFlag)|(1<<CFlag)\r
3505 .hword (0x2A<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3506 .hword (0x2B<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3507 .hword (0x2C<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3508 .hword (0x2D<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3509 .hword (0x2E<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3510 .hword (0x2F<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3511 .hword (0x30<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3512 .hword (0x31<<8) |(1<<NFlag)|(1<<CFlag)\r
3513 .hword (0x32<<8) |(1<<NFlag)|(1<<CFlag)\r
3514 .hword (0x33<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3515 .hword (0x34<<8) |(1<<NFlag)|(1<<CFlag)\r
3516 .hword (0x35<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3517 .hword (0x36<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3518 .hword (0x37<<8) |(1<<NFlag)|(1<<CFlag)\r
3519 .hword (0x38<<8) |(1<<NFlag)|(1<<CFlag)\r
3520 .hword (0x39<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3521 .hword (0x3A<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3522 .hword (0x3B<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3523 .hword (0x3C<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3524 .hword (0x3D<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3525 .hword (0x3E<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3526 .hword (0x3F<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3527 .hword (0x40<<8) |(1<<NFlag)|(1<<CFlag)\r
3528 .hword (0x41<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3529 .hword (0x42<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3530 .hword (0x43<<8) |(1<<NFlag)|(1<<CFlag)\r
3531 .hword (0x44<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3532 .hword (0x45<<8) |(1<<NFlag)|(1<<CFlag)\r
3533 .hword (0x46<<8) |(1<<NFlag)|(1<<CFlag)\r
3534 .hword (0x47<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3535 .hword (0x48<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3536 .hword (0x49<<8) |(1<<NFlag)|(1<<CFlag)\r
3537 .hword (0x4A<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3538 .hword (0x4B<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3539 .hword (0x4C<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3540 .hword (0x4D<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3541 .hword (0x4E<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3542 .hword (0x4F<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3543 .hword (0x50<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3544 .hword (0x51<<8) |(1<<NFlag)|(1<<CFlag)\r
3545 .hword (0x52<<8) |(1<<NFlag)|(1<<CFlag)\r
3546 .hword (0x53<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3547 .hword (0x54<<8) |(1<<NFlag)|(1<<CFlag)\r
3548 .hword (0x55<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3549 .hword (0x56<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3550 .hword (0x57<<8) |(1<<NFlag)|(1<<CFlag)\r
3551 .hword (0x58<<8) |(1<<NFlag)|(1<<CFlag)\r
3552 .hword (0x59<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3553 .hword (0x5A<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3554 .hword (0x5B<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3555 .hword (0x5C<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3556 .hword (0x5D<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3557 .hword (0x5E<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3558 .hword (0x5F<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3559 .hword (0x60<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3560 .hword (0x61<<8) |(1<<NFlag)|(1<<CFlag)\r
3561 .hword (0x62<<8) |(1<<NFlag)|(1<<CFlag)\r
3562 .hword (0x63<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3563 .hword (0x64<<8) |(1<<NFlag)|(1<<CFlag)\r
3564 .hword (0x65<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3565 .hword (0x66<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3566 .hword (0x67<<8) |(1<<NFlag)|(1<<CFlag)\r
3567 .hword (0x68<<8) |(1<<NFlag)|(1<<CFlag)\r
3568 .hword (0x69<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3569 .hword (0x6A<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3570 .hword (0x6B<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3571 .hword (0x6C<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3572 .hword (0x6D<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3573 .hword (0x6E<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3574 .hword (0x6F<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3575 .hword (0x70<<8) |(1<<NFlag)|(1<<CFlag)\r
3576 .hword (0x71<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3577 .hword (0x72<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3578 .hword (0x73<<8) |(1<<NFlag)|(1<<CFlag)\r
3579 .hword (0x74<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3580 .hword (0x75<<8) |(1<<NFlag)|(1<<CFlag)\r
3581 .hword (0x76<<8) |(1<<NFlag)|(1<<CFlag)\r
3582 .hword (0x77<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3583 .hword (0x78<<8) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3584 .hword (0x79<<8) |(1<<NFlag)|(1<<CFlag)\r
3585 .hword (0x7A<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3586 .hword (0x7B<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3587 .hword (0x7C<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3588 .hword (0x7D<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3589 .hword (0x7E<<8) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3590 .hword (0x7F<<8) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3591 .hword (0x80<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3592 .hword (0x81<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3593 .hword (0x82<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3594 .hword (0x83<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3595 .hword (0x84<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3596 .hword (0x85<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3597 .hword (0x86<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3598 .hword (0x87<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3599 .hword (0x88<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3600 .hword (0x89<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3601 .hword (0x8A<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3602 .hword (0x8B<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3603 .hword (0x8C<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3604 .hword (0x8D<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3605 .hword (0x8E<<8)|(1<<SFlag) |(1<<HFlag)|(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3606 .hword (0x8F<<8)|(1<<SFlag) |(1<<HFlag) |(1<<NFlag)|(1<<CFlag)\r
3607 .hword (0x90<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3608 .hword (0x91<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3609 .hword (0x92<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3610 .hword (0x93<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3611 .hword (0x94<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3612 .hword (0x95<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3613 .hword (0x96<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3614 .hword (0x97<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3615 .hword (0x98<<8)|(1<<SFlag) |(1<<NFlag)|(1<<CFlag)\r
3616 .hword (0x99<<8)|(1<<SFlag) |(1<<VFlag)|(1<<NFlag)|(1<<CFlag)\r
3617 \r
3618.align 4\r
3619\r
3620AF_Z80: .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 0\r
3621 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 1\r
3622 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 2\r
3623 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 3\r
3624 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 4\r
3625 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 5\r
3626 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 6\r
3627 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 7\r
3628 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 8\r
3629 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 9\r
3630 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 10\r
3631 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 11\r
3632 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 12\r
3633 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 13\r
3634 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 14\r
3635 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 15\r
3636 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 16\r
3637 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 17\r
3638 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 18\r
3639 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 19\r
3640 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 20\r
3641 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 21\r
3642 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 22\r
3643 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 23\r
3644 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 24\r
3645 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 25\r
3646 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 26\r
3647 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 27\r
3648 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 28\r
3649 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 29\r
3650 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 30\r
3651 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 31\r
3652 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 32\r
3653 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 33\r
3654 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 34\r
3655 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 35\r
3656 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 36\r
3657 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 37\r
3658 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 38\r
3659 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 39\r
3660 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 40\r
3661 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 41\r
3662 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 42\r
3663 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 43\r
3664 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 44\r
3665 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 45\r
3666 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 46\r
3667 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 47\r
3668 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 48\r
3669 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 49\r
3670 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 50\r
3671 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 51\r
3672 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 52\r
3673 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 53\r
3674 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 54\r
3675 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 55\r
3676 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 56\r
3677 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 57\r
3678 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 58\r
3679 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 59\r
3680 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 60\r
3681 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 61\r
3682 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 62\r
3683 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 63\r
3684 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 64\r
3685 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 65\r
3686 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 66\r
3687 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 67\r
3688 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 68\r
3689 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 69\r
3690 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 70\r
3691 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 71\r
3692 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 72\r
3693 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 73\r
3694 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 74\r
3695 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 75\r
3696 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 76\r
3697 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 77\r
3698 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 78\r
3699 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 79\r
3700 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 80\r
3701 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 81\r
3702 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 82\r
3703 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 83\r
3704 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 84\r
3705 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 85\r
3706 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 86\r
3707 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 87\r
3708 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 88\r
3709 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 89\r
3710 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 90\r
3711 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 91\r
3712 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 92\r
3713 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 93\r
3714 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 94\r
3715 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 95\r
3716 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 96\r
3717 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 97\r
3718 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 98\r
3719 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 99\r
3720 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 100\r
3721 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 101\r
3722 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 102\r
3723 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 103\r
3724 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 104\r
3725 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 105\r
3726 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 106\r
3727 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 107\r
3728 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 108\r
3729 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 109\r
3730 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 110\r
3731 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 111\r
3732 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 112\r
3733 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 113\r
3734 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 114\r
3735 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 115\r
3736 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 116\r
3737 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 117\r
3738 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 118\r
3739 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 119\r
3740 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 120\r
3741 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 121\r
3742 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 122\r
3743 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 123\r
3744 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 124\r
3745 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 125\r
3746 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 126\r
3747 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 127\r
3748 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 128\r
3749 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 129\r
3750 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 130\r
3751 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 131\r
3752 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 132\r
3753 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 133\r
3754 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 134\r
3755 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 135\r
3756 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 136\r
3757 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 137\r
3758 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 138\r
3759 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 139\r
3760 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 140\r
3761 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 141\r
3762 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 142\r
3763 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 143\r
3764 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 144\r
3765 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 145\r
3766 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 146\r
3767 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 147\r
3768 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 148\r
3769 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 149\r
3770 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 150\r
3771 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 151\r
3772 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 152\r
3773 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 153\r
3774 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 154\r
3775 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 155\r
3776 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 156\r
3777 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 157\r
3778 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 158\r
3779 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 159\r
3780 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 160\r
3781 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 161\r
3782 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 162\r
3783 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 163\r
3784 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 164\r
3785 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 165\r
3786 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 166\r
3787 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 167\r
3788 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 168\r
3789 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 169\r
3790 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 170\r
3791 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 171\r
3792 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 172\r
3793 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 173\r
3794 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 174\r
3795 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 175\r
3796 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 176\r
3797 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 177\r
3798 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 178\r
3799 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 179\r
3800 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 180\r
3801 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 181\r
3802 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 182\r
3803 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 183\r
3804 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 184\r
3805 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 185\r
3806 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 186\r
3807 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 187\r
3808 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 188\r
3809 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 189\r
3810 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 190\r
3811 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 191\r
3812 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 192\r
3813 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 193\r
3814 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 194\r
3815 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 195\r
3816 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 196\r
3817 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 197\r
3818 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 198\r
3819 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 199\r
3820 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 200\r
3821 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 201\r
3822 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 202\r
3823 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 203\r
3824 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 204\r
3825 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 205\r
3826 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 206\r
3827 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 207\r
3828 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 208\r
3829 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 209\r
3830 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 210\r
3831 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 211\r
3832 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 212\r
3833 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 213\r
3834 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 214\r
3835 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 215\r
3836 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 216\r
3837 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 217\r
3838 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 218\r
3839 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 219\r
3840 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 220\r
3841 .byte (0<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 221\r
3842 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 222\r
3843 .byte (1<<Z80_CFlag)|(0<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 223\r
3844 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 224\r
3845 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 225\r
3846 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 226\r
3847 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 227\r
3848 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 228\r
3849 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 229\r
3850 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 230\r
3851 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 231\r
3852 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 232\r
3853 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 233\r
3854 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 234\r
3855 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 235\r
3856 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 236\r
3857 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 237\r
3858 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 238\r
3859 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(0<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 239\r
3860 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 240\r
3861 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 241\r
3862 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 242\r
3863 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 243\r
3864 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 244\r
3865 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 245\r
3866 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 246\r
3867 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(0<<Z80_SFlag) ;@ 247\r
3868 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 248\r
3869 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 249\r
3870 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 250\r
3871 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(0<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 251\r
3872 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 252\r
3873 .byte (0<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 253\r
3874 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(0<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 254\r
3875 .byte (1<<Z80_CFlag)|(1<<Z80_NFlag)|(1<<Z80_VFlag)|(1<<Z80_HFlag)|(1<<Z80_ZFlag)|(1<<Z80_SFlag) ;@ 255\r
3876\r
3877.align 4\r
3878\r
3879AF_ARM: .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 0\r
3880 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 1\r
3881 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 2\r
3882 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 3\r
3883 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 4\r
3884 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 5\r
3885 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 6\r
3886 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 7\r
3887 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 8\r
3888 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 9\r
3889 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 10\r
3890 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 11\r
3891 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 12\r
3892 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 13\r
3893 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 14\r
3894 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 15\r
3895 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 16\r
3896 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 17\r
3897 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 18\r
3898 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 19\r
3899 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 20\r
3900 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 21\r
3901 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 22\r
3902 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 23\r
3903 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 24\r
3904 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 25\r
3905 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 26\r
3906 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 27\r
3907 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 28\r
3908 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 29\r
3909 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 30\r
3910 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 31\r
3911 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 32\r
3912 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 33\r
3913 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 34\r
3914 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 35\r
3915 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 36\r
3916 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 37\r
3917 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 38\r
3918 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 39\r
3919 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 40\r
3920 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 41\r
3921 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 42\r
3922 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 43\r
3923 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 44\r
3924 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 45\r
3925 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 46\r
3926 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 47\r
3927 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 48\r
3928 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 49\r
3929 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 50\r
3930 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 51\r
3931 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 52\r
3932 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 53\r
3933 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 54\r
3934 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 55\r
3935 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 56\r
3936 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 57\r
3937 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 58\r
3938 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 59\r
3939 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 60\r
3940 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 61\r
3941 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 62\r
3942 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(0<<SFlag) ;@ 63\r
3943 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 64\r
3944 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 65\r
3945 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 66\r
3946 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 67\r
3947 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 68\r
3948 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 69\r
3949 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 70\r
3950 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 71\r
3951 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 72\r
3952 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 73\r
3953 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 74\r
3954 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 75\r
3955 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 76\r
3956 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 77\r
3957 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 78\r
3958 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 79\r
3959 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 80\r
3960 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 81\r
3961 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 82\r
3962 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 83\r
3963 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 84\r
3964 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 85\r
3965 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 86\r
3966 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 87\r
3967 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 88\r
3968 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 89\r
3969 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 90\r
3970 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 91\r
3971 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 92\r
3972 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 93\r
3973 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 94\r
3974 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 95\r
3975 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 96\r
3976 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 97\r
3977 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 98\r
3978 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 99\r
3979 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 100\r
3980 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 101\r
3981 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 102\r
3982 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 103\r
3983 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 104\r
3984 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 105\r
3985 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 106\r
3986 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 107\r
3987 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 108\r
3988 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 109\r
3989 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 110\r
3990 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 111\r
3991 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 112\r
3992 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 113\r
3993 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 114\r
3994 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 115\r
3995 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 116\r
3996 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 117\r
3997 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 118\r
3998 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 119\r
3999 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 120\r
4000 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 121\r
4001 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 122\r
4002 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 123\r
4003 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 124\r
4004 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 125\r
4005 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 126\r
4006 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(0<<SFlag) ;@ 127\r
4007 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 128\r
4008 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 129\r
4009 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 130\r
4010 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 131\r
4011 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 132\r
4012 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 133\r
4013 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 134\r
4014 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 135\r
4015 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 136\r
4016 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 137\r
4017 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 138\r
4018 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 139\r
4019 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 140\r
4020 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 141\r
4021 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 142\r
4022 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 143\r
4023 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 144\r
4024 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 145\r
4025 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 146\r
4026 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 147\r
4027 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 148\r
4028 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 149\r
4029 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 150\r
4030 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 151\r
4031 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 152\r
4032 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 153\r
4033 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 154\r
4034 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 155\r
4035 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 156\r
4036 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 157\r
4037 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 158\r
4038 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 159\r
4039 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 160\r
4040 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 161\r
4041 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 162\r
4042 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 163\r
4043 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 164\r
4044 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 165\r
4045 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 166\r
4046 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 167\r
4047 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 168\r
4048 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 169\r
4049 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 170\r
4050 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 171\r
4051 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 172\r
4052 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 173\r
4053 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 174\r
4054 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 175\r
4055 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 176\r
4056 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 177\r
4057 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 178\r
4058 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 179\r
4059 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 180\r
4060 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 181\r
4061 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 182\r
4062 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 183\r
4063 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 184\r
4064 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 185\r
4065 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 186\r
4066 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 187\r
4067 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 188\r
4068 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 189\r
4069 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 190\r
4070 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(0<<ZFlag)|(1<<SFlag) ;@ 191\r
4071 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 192\r
4072 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 193\r
4073 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 194\r
4074 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 195\r
4075 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 196\r
4076 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 197\r
4077 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 198\r
4078 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 199\r
4079 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 200\r
4080 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 201\r
4081 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 202\r
4082 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 203\r
4083 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 204\r
4084 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 205\r
4085 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 206\r
4086 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 207\r
4087 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 208\r
4088 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 209\r
4089 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 210\r
4090 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 211\r
4091 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 212\r
4092 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 213\r
4093 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 214\r
4094 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 215\r
4095 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 216\r
4096 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 217\r
4097 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 218\r
4098 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 219\r
4099 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 220\r
4100 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 221\r
4101 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 222\r
4102 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 223\r
4103 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 224\r
4104 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 225\r
4105 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 226\r
4106 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 227\r
4107 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 228\r
4108 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 229\r
4109 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 230\r
4110 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 231\r
4111 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 232\r
4112 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 233\r
4113 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 234\r
4114 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 235\r
4115 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 236\r
4116 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 237\r
4117 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 238\r
4118 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(0<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 239\r
4119 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 240\r
4120 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 241\r
4121 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 242\r
4122 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 243\r
4123 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 244\r
4124 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 245\r
4125 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 246\r
4126 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 247\r
4127 .byte (0<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 248\r
4128 .byte (1<<CFlag)|(0<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 249\r
4129 .byte (0<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 250\r
4130 .byte (1<<CFlag)|(1<<NFlag)|(0<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 251\r
4131 .byte (0<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 252\r
4132 .byte (1<<CFlag)|(0<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 253\r
4133 .byte (0<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 254\r
4134 .byte (1<<CFlag)|(1<<NFlag)|(1<<VFlag)|(1<<HFlag)|(1<<ZFlag)|(1<<SFlag) ;@ 255\r
4135\r
4136.align 4\r
4137\r
4138PZSTable_data: .byte (1<<ZFlag)|(1<<VFlag),0,0,(1<<VFlag),0,(1<<VFlag),(1<<VFlag),0\r
4139 .byte 0,(1<<VFlag),(1<<VFlag),0,(1<<VFlag),0,0,(1<<VFlag)\r
4140 .byte 0,(1<<VFlag),(1<<VFlag),0,(1<<VFlag),0,0,(1<<VFlag),(1<<VFlag),0,0,(1<<VFlag),0,(1<<VFlag),(1<<VFlag),0\r
4141 .byte 0,(1<<VFlag),(1<<VFlag),0,(1<<VFlag),0,0,(1<<VFlag),(1<<VFlag),0,0,(1<<VFlag),0,(1<<VFlag),(1<<VFlag),0\r
4142 .byte (1<<VFlag),0,0,(1<<VFlag),0,(1<<VFlag),(1<<VFlag),0,0,(1<<VFlag),(1<<VFlag),0,(1<<VFlag),0,0,(1<<VFlag)\r
4143 .byte 0,(1<<VFlag),(1<<VFlag),0,(1<<VFlag),0,0,(1<<VFlag),(1<<VFlag),0,0,(1<<VFlag),0,(1<<VFlag),(1<<VFlag),0\r
4144 .byte (1<<VFlag),0,0,(1<<VFlag),0,(1<<VFlag),(1<<VFlag),0,0,(1<<VFlag),(1<<VFlag),0,(1<<VFlag),0,0,(1<<VFlag)\r
4145 .byte (1<<VFlag),0,0,(1<<VFlag),0,(1<<VFlag),(1<<VFlag),0,0,(1<<VFlag),(1<<VFlag),0,(1<<VFlag),0,0,(1<<VFlag)\r
4146 .byte 0,(1<<VFlag),(1<<VFlag),0,(1<<VFlag),0,0,(1<<VFlag),(1<<VFlag),0,0,(1<<VFlag),0,(1<<VFlag),(1<<VFlag),0\r
4147 .byte (1<<SFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)\r
4148 .byte (1<<SFlag)|(1<<VFlag),(1<<SFlag),(1<<SFlag),(1<<SFlag)|(1<<VFlag)\r
4149 .byte (1<<SFlag)|(1<<VFlag),(1<<SFlag),(1<<SFlag),(1<<SFlag)|(1<<VFlag)\r
4150 .byte (1<<SFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)\r
4151 .byte (1<<SFlag)|(1<<VFlag),(1<<SFlag),(1<<SFlag),(1<<SFlag)|(1<<VFlag)\r
4152 .byte (1<<SFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)\r
4153 .byte (1<<SFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)\r
4154 .byte (1<<SFlag)|(1<<VFlag),(1<<SFlag),(1<<SFlag),(1<<SFlag)|(1<<VFlag)\r
4155 .byte (1<<SFlag)|(1<<VFlag),(1<<SFlag),(1<<SFlag),(1<<SFlag)|(1<<VFlag)\r
4156 .byte (1<<SFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)\r
4157 .byte (1<<SFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)\r
4158 .byte (1<<SFlag)|(1<<VFlag),(1<<SFlag),(1<<SFlag),(1<<SFlag)|(1<<VFlag)\r
4159 .byte (1<<SFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)\r
4160 .byte (1<<SFlag)|(1<<VFlag),(1<<SFlag),(1<<SFlag),(1<<SFlag)|(1<<VFlag)\r
4161 .byte (1<<SFlag)|(1<<VFlag),(1<<SFlag),(1<<SFlag),(1<<SFlag)|(1<<VFlag)\r
4162 .byte (1<<SFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)\r
4163 .byte (1<<SFlag)|(1<<VFlag),(1<<SFlag),(1<<SFlag),(1<<SFlag)|(1<<VFlag)\r
4164 .byte (1<<SFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)\r
4165 .byte (1<<SFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)\r
4166 .byte (1<<SFlag)|(1<<VFlag),(1<<SFlag),(1<<SFlag),(1<<SFlag)|(1<<VFlag)\r
4167 .byte (1<<SFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)\r
4168 .byte (1<<SFlag)|(1<<VFlag),(1<<SFlag),(1<<SFlag),(1<<SFlag)|(1<<VFlag)\r
4169 .byte (1<<SFlag)|(1<<VFlag),(1<<SFlag),(1<<SFlag),(1<<SFlag)|(1<<VFlag)\r
4170 .byte (1<<SFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)\r
4171 .byte (1<<SFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)\r
4172 .byte (1<<SFlag)|(1<<VFlag),(1<<SFlag),(1<<SFlag),(1<<SFlag)|(1<<VFlag)\r
4173 .byte (1<<SFlag)|(1<<VFlag),(1<<SFlag),(1<<SFlag),(1<<SFlag)|(1<<VFlag)\r
4174 .byte (1<<SFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)\r
4175 .byte (1<<SFlag)|(1<<VFlag),(1<<SFlag),(1<<SFlag),(1<<SFlag)|(1<<VFlag)\r
4176 .byte (1<<SFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)\r
4177 .byte (1<<SFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)|(1<<VFlag),(1<<SFlag)\r
4178 .byte (1<<SFlag)|(1<<VFlag),(1<<SFlag),(1<<SFlag),(1<<SFlag)|(1<<VFlag) \r
4179\r
4180.align 4\r
4181\r
4182MAIN_opcodes: \r
4183 .word opcode_0_0,opcode_0_1,opcode_0_2,opcode_0_3,opcode_0_4,opcode_0_5,opcode_0_6,opcode_0_7\r
4184 .word opcode_0_8,opcode_0_9,opcode_0_A,opcode_0_B,opcode_0_C,opcode_0_D,opcode_0_E,opcode_0_F\r
4185 .word opcode_1_0,opcode_1_1,opcode_1_2,opcode_1_3,opcode_1_4,opcode_1_5,opcode_1_6,opcode_1_7\r
4186 .word opcode_1_8,opcode_1_9,opcode_1_A,opcode_1_B,opcode_1_C,opcode_1_D,opcode_1_E,opcode_1_F\r
4187 .word opcode_2_0,opcode_2_1,opcode_2_2,opcode_2_3,opcode_2_4,opcode_2_5,opcode_2_6,opcode_2_7\r
4188 .word opcode_2_8,opcode_2_9,opcode_2_A,opcode_2_B,opcode_2_C,opcode_2_D,opcode_2_E,opcode_2_F\r
4189 .word opcode_3_0,opcode_3_1,opcode_3_2,opcode_3_3,opcode_3_4,opcode_3_5,opcode_3_6,opcode_3_7\r
4190 .word opcode_3_8,opcode_3_9,opcode_3_A,opcode_3_B,opcode_3_C,opcode_3_D,opcode_3_E,opcode_3_F\r
4191 .word opcode_4_0,opcode_4_1,opcode_4_2,opcode_4_3,opcode_4_4,opcode_4_5,opcode_4_6,opcode_4_7\r
4192 .word opcode_4_8,opcode_4_9,opcode_4_A,opcode_4_B,opcode_4_C,opcode_4_D,opcode_4_E,opcode_4_F\r
4193 .word opcode_5_0,opcode_5_1,opcode_5_2,opcode_5_3,opcode_5_4,opcode_5_5,opcode_5_6,opcode_5_7\r
4194 .word opcode_5_8,opcode_5_9,opcode_5_A,opcode_5_B,opcode_5_C,opcode_5_D,opcode_5_E,opcode_5_F\r
4195 .word opcode_6_0,opcode_6_1,opcode_6_2,opcode_6_3,opcode_6_4,opcode_6_5,opcode_6_6,opcode_6_7\r
4196 .word opcode_6_8,opcode_6_9,opcode_6_A,opcode_6_B,opcode_6_C,opcode_6_D,opcode_6_E,opcode_6_F\r
4197 .word opcode_7_0,opcode_7_1,opcode_7_2,opcode_7_3,opcode_7_4,opcode_7_5,opcode_7_6,opcode_7_7\r
4198 .word opcode_7_8,opcode_7_9,opcode_7_A,opcode_7_B,opcode_7_C,opcode_7_D,opcode_7_E,opcode_7_F\r
4199 .word opcode_8_0,opcode_8_1,opcode_8_2,opcode_8_3,opcode_8_4,opcode_8_5,opcode_8_6,opcode_8_7\r
4200 .word opcode_8_8,opcode_8_9,opcode_8_A,opcode_8_B,opcode_8_C,opcode_8_D,opcode_8_E,opcode_8_F\r
4201 .word opcode_9_0,opcode_9_1,opcode_9_2,opcode_9_3,opcode_9_4,opcode_9_5,opcode_9_6,opcode_9_7\r
4202 .word opcode_9_8,opcode_9_9,opcode_9_A,opcode_9_B,opcode_9_C,opcode_9_D,opcode_9_E,opcode_9_F\r
4203 .word opcode_A_0,opcode_A_1,opcode_A_2,opcode_A_3,opcode_A_4,opcode_A_5,opcode_A_6,opcode_A_7\r
4204 .word opcode_A_8,opcode_A_9,opcode_A_A,opcode_A_B,opcode_A_C,opcode_A_D,opcode_A_E,opcode_A_F\r
4205 .word opcode_B_0,opcode_B_1,opcode_B_2,opcode_B_3,opcode_B_4,opcode_B_5,opcode_B_6,opcode_B_7\r
4206 .word opcode_B_8,opcode_B_9,opcode_B_A,opcode_B_B,opcode_B_C,opcode_B_D,opcode_B_E,opcode_B_F\r
4207 .word opcode_C_0,opcode_C_1,opcode_C_2,opcode_C_3,opcode_C_4,opcode_C_5,opcode_C_6,opcode_C_7\r
4208 .word opcode_C_8,opcode_C_9,opcode_C_A,opcode_C_B,opcode_C_C,opcode_C_D,opcode_C_E,opcode_C_F\r
4209 .word opcode_D_0,opcode_D_1,opcode_D_2,opcode_D_3,opcode_D_4,opcode_D_5,opcode_D_6,opcode_D_7\r
4210 .word opcode_D_8,opcode_D_9,opcode_D_A,opcode_D_B,opcode_D_C,opcode_D_D,opcode_D_E,opcode_D_F\r
4211 .word opcode_E_0,opcode_E_1,opcode_E_2,opcode_E_3,opcode_E_4,opcode_E_5,opcode_E_6,opcode_E_7\r
4212 .word opcode_E_8,opcode_E_9,opcode_E_A,opcode_E_B,opcode_E_C,opcode_E_D,opcode_E_E,opcode_E_F\r
4213 .word opcode_F_0,opcode_F_1,opcode_F_2,opcode_F_3,opcode_F_4,opcode_F_5,opcode_F_6,opcode_F_7\r
4214 .word opcode_F_8,opcode_F_9,opcode_F_A,opcode_F_B,opcode_F_C,opcode_F_D,opcode_F_E,opcode_F_F\r
4215\r
4216.align 4\r
4217\r
4218EI_DUMMY_opcodes:\r
4219 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@0\r
4220 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@0\r
4221 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@1\r
4222 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@1\r
4223 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@2\r
4224 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@2\r
4225 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@3\r
4226 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@3\r
4227 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@4\r
4228 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@4\r
4229 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@5\r
4230 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@5\r
4231 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@6\r
4232 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@6\r
4233 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@7\r
4234 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@7\r
4235 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@8\r
4236 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@8\r
4237 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@9\r
4238 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@9\r
4239 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@A\r
4240 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@A\r
4241 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@B\r
4242 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@B\r
4243 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@C\r
4244 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@C\r
4245 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@D\r
4246 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@D\r
4247 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@E\r
4248 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@E\r
4249 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@F\r
4250 .word ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return,ei_return ;@F\r
4251\r
4252.text\r
4253.align 4\r
4254\r
4255;@NOP\r
4256opcode_0_0:\r
4257;@LD B,B\r
4258opcode_4_0:\r
4259;@LD C,C\r
4260opcode_4_9:\r
4261;@LD D,D\r
4262opcode_5_2:\r
4263;@LD E,E\r
4264opcode_5_B:\r
4265;@LD H,H\r
4266opcode_6_4:\r
4267;@LD L,L\r
4268opcode_6_D:\r
4269;@LD A,A\r
4270opcode_7_F:\r
4271 fetch 4\r
4272;@LD BC,NN\r
4273opcode_0_1:\r
4274 ldrb r0,[z80pc],#1\r
4275 ldrb r1,[z80pc],#1\r
4276 orr r0,r0,r1, lsl #8\r
4277 mov z80bc,r0, lsl #16\r
4278 fetch 10\r
4279;@LD (BC),A\r
4280opcode_0_2:\r
4281 mov r0,z80a, lsr #24\r
4282 mov r1,z80bc, lsr #16\r
4283 writemem8\r
4284 fetch 7\r
4285;@INC BC\r
4286opcode_0_3:\r
4287 add z80bc,z80bc,#1<<16\r
4288 fetch 6\r
4289;@INC B\r
4290opcode_0_4:\r
4291 opINC8H z80bc\r
4292 fetch 4\r
4293;@DEC B\r
4294opcode_0_5:\r
4295 opDEC8H z80bc\r
4296 fetch 4\r
4297;@LD B,N\r
4298opcode_0_6:\r
4299 ldrb r1,[z80pc],#1\r
4300 and z80bc,z80bc,#0xFF<<16\r
4301 orr z80bc,z80bc,r1, lsl #24\r
4302 fetch 7\r
4303;@RLCA\r
4304opcode_0_7:\r
4305 bic z80f,z80f,#(1<<NFlag)|(1<<HFlag)|(1<<CFlag)\r
4306 movs z80a,z80a, lsl #1\r
4307 orrcs z80a,z80a,#1<<24\r
4308 orrcs z80f,z80f,#1<<CFlag\r
4309 fetch 4\r
4310;@EX AF,AF'\r
4311opcode_0_8:\r
4312 add r1,cpucontext,#z80a2\r
4313 swp z80a,z80a,[r1]\r
4314 add r1,cpucontext,#z80f2\r
4315 swp z80f,z80f,[r1]\r
4316 fetch 4\r
4317;@ADD HL,BC\r
4318opcode_0_9:\r
4319 opADD16 z80hl z80bc\r
4320 fetch 11\r
4321;@LD A,(BC)\r
4322opcode_0_A:\r
4323 mov r0,z80bc, lsr #16\r
4324 readmem8\r
4325 mov z80a,r0, lsl #24\r
4326 fetch 7\r
4327;@DEC BC\r
4328opcode_0_B:\r
4329 sub z80bc,z80bc,#1<<16\r
4330 fetch 6\r
4331;@INC C\r
4332opcode_0_C:\r
4333 opINC8L z80bc\r
4334 fetch 4\r
4335;@DEC C\r
4336opcode_0_D:\r
4337 opDEC8L z80bc\r
4338 fetch 4\r
4339;@LD C,N\r
4340opcode_0_E:\r
4341 ldrb r1,[z80pc],#1\r
4342 and z80bc,z80bc,#0xFF<<24\r
4343 orr z80bc,z80bc,r1, lsl #16\r
4344 fetch 7\r
4345;@RRCA\r
4346opcode_0_F:\r
4347 bic z80f,z80f,#(1<<NFlag)|(1<<HFlag)|(1<<CFlag)\r
4348 movs z80a,z80a, lsr #25\r
4349 orrcs z80a,z80a,#1<<7\r
4350 orrcs z80f,z80f,#1<<CFlag\r
4351 mov z80a,z80a, lsl #24\r
4352 fetch 4\r
4353;@DJNZ $+2\r
4354opcode_1_0:\r
4355 sub z80bc,z80bc,#1<<24\r
4356 tst z80bc,#0xFF<<24\r
4357 ldrsb r1,[z80pc],#1\r
4358 addne z80pc,z80pc,r1\r
4359 subne z80_icount,z80_icount,#5\r
4360 fetch 8\r
4361\r
4362;@LD DE,NN\r
4363opcode_1_1:\r
4364 ldrb r0,[z80pc],#1\r
4365 ldrb r1,[z80pc],#1\r
4366 orr r0,r0,r1, lsl #8\r
4367 mov z80de,r0, lsl #16\r
4368 fetch 10\r
4369;@LD (DE),A\r
4370opcode_1_2:\r
4371 mov r0,z80a, lsr #24\r
4372 writemem8DE\r
4373 fetch 7\r
4374;@INC DE\r
4375opcode_1_3:\r
4376 add z80de,z80de,#1<<16\r
4377 fetch 6\r
4378;@INC D\r
4379opcode_1_4:\r
4380 opINC8H z80de\r
4381 fetch 4\r
4382;@DEC D\r
4383opcode_1_5:\r
4384 opDEC8H z80de\r
4385 fetch 4\r
4386;@LD D,N\r
4387opcode_1_6:\r
4388 ldrb r1,[z80pc],#1\r
4389 and z80de,z80de,#0xFF<<16\r
4390 orr z80de,z80de,r1, lsl #24\r
4391 fetch 7\r
4392;@RLA\r
4393opcode_1_7:\r
4394 tst z80f,#1<<CFlag\r
4395 orrne z80a,z80a,#1<<23\r
4396 bic z80f,z80f,#(1<<NFlag)|(1<<HFlag)|(1<<CFlag)\r
4397 movs z80a,z80a, lsl #1\r
4398 orrcs z80f,z80f,#1<<CFlag\r
4399 fetch 4\r
4400;@JR $+2\r
4401opcode_1_8:\r
4402 ldrsb r1,[z80pc],#1\r
4403 add z80pc,z80pc,r1\r
4404 fetch 12\r
4405;@ADD HL,DE\r
4406opcode_1_9:\r
4407 opADD16 z80hl z80de\r
4408 fetch 11\r
4409;@LD A,(DE)\r
4410opcode_1_A:\r
4411 mov r0,z80de, lsr #16\r
4412 readmem8\r
4413 mov z80a,r0, lsl #24\r
4414 fetch 7\r
4415;@DEC DE\r
4416opcode_1_B:\r
4417 sub z80de,z80de,#1<<16\r
4418 fetch 6\r
4419;@INC E\r
4420opcode_1_C:\r
4421 opINC8L z80de\r
4422 fetch 4\r
4423;@DEC E\r
4424opcode_1_D:\r
4425 opDEC8L z80de\r
4426 fetch 4\r
4427;@LD E,N\r
4428opcode_1_E:\r
4429 ldrb r0,[z80pc],#1\r
4430 and z80de,z80de,#0xFF<<24\r
4431 orr z80de,z80de,r0, lsl #16\r
4432 fetch 7\r
4433;@RRA\r
4434opcode_1_F:\r
4435 orr z80a,z80a,z80f,lsr#1 ;@get C\r
4436 bic z80f,z80f,#(1<<NFlag)|(1<<HFlag)|(1<<CFlag)\r
4437 movs z80a,z80a,ror#25\r
4438 orrcs z80f,z80f,#1<<CFlag\r
4439 mov z80a,z80a,lsl#24\r
4440 fetch 4\r
4441;@JR NZ,$+2\r
4442opcode_2_0:\r
4443 tst z80f,#1<<ZFlag\r
4444 beq opcode_1_8\r
4445 add z80pc,z80pc,#1\r
4446 fetch 7\r
4447;@LD HL,NN\r
4448opcode_2_1:\r
4449 ldrb r0,[z80pc],#1\r
4450 ldrb r1,[z80pc],#1\r
4451 orr r0,r0,r1, lsl #8\r
4452 mov z80hl,r0, lsl #16\r
4453 fetch 10\r
4454;@LD (NN),HL\r
4455opcode_ED_63:\r
4456 eatcycles 4\r
4457;@LD (NN),HL\r
4458opcode_2_2:\r
4459 ldrb r0,[z80pc],#1\r
4460 ldrb r1,[z80pc],#1\r
4461 orr r1,r0,r1, lsl #8\r
4462 mov r0,z80hl, lsr #16\r
4463 writemem16\r
4464 fetch 16\r
4465;@INC HL\r
4466opcode_2_3:\r
4467 add z80hl,z80hl,#1<<16\r
4468 fetch 6\r
4469;@INC H\r
4470opcode_2_4:\r
4471 opINC8H z80hl\r
4472 fetch 4\r
4473;@DEC H\r
4474opcode_2_5:\r
4475 opDEC8H z80hl\r
4476 fetch 4\r
4477;@LD H,N\r
4478opcode_2_6:\r
4479 ldrb r1,[z80pc],#1\r
4480 and z80hl,z80hl,#0xFF<<16\r
4481 orr z80hl,z80hl,r1, lsl #24\r
4482 fetch 7\r
4483DAATABLE_LOCAL: .word DAATable\r
4484;@DAA\r
4485opcode_2_7:\r
4486 mov r1,z80a, lsr #24\r
4487 tst z80f,#1<<CFlag\r
4488 orrne r1,r1,#256\r
4489 tst z80f,#1<<HFlag\r
4490 orrne r1,r1,#512\r
4491 tst z80f,#1<<NFlag\r
4492 orrne r1,r1,#1024\r
4493 ldr r2,DAATABLE_LOCAL\r
4494 add r2,r2,r1, lsl #1\r
4495 ldrh r1,[r2]\r
4496 and z80f,r1,#0xFF\r
4497 and r2,r1,#0xFF<<8\r
4498 mov z80a,r2, lsl #16\r
4499 fetch 4\r
4500;@JR Z,$+2\r
4501opcode_2_8:\r
4502 tst z80f,#1<<ZFlag\r
4503 bne opcode_1_8\r
4504 add z80pc,z80pc,#1\r
4505 fetch 7\r
4506;@ADD HL,HL\r
4507opcode_2_9:\r
4508 opADD16_2 z80hl\r
4509 fetch 11\r
4510;@LD HL,(NN)\r
4511opcode_ED_6B:\r
4512 eatcycles 4\r
4513;@LD HL,(NN)\r
4514opcode_2_A:\r
4515 ldrb r0,[z80pc],#1\r
4516 ldrb r1,[z80pc],#1\r
4517 orr r0,r0,r1, lsl #8\r
4518 readmem16\r
4519 mov z80hl,r0, lsl #16\r
4520 fetch 16\r
4521;@DEC HL\r
4522opcode_2_B:\r
4523 sub z80hl,z80hl,#1<<16\r
4524 fetch 6\r
4525;@INC L\r
4526opcode_2_C:\r
4527 opINC8L z80hl\r
4528 fetch 4\r
4529;@DEC L\r
4530opcode_2_D:\r
4531 opDEC8L z80hl\r
4532 fetch 4\r
4533;@LD L,N\r
4534opcode_2_E:\r
4535 ldrb r0,[z80pc],#1\r
4536 and z80hl,z80hl,#0xFF<<24\r
4537 orr z80hl,z80hl,r0, lsl #16\r
4538 fetch 7\r
4539;@CPL\r
4540opcode_2_F:\r
4541 eor z80a,z80a,#0xFF<<24\r
4542 orr z80f,z80f,#(1<<NFlag)|(1<<HFlag)\r
4543 fetch 4\r
4544;@JR NC,$+2\r
4545opcode_3_0:\r
4546 tst z80f,#1<<CFlag\r
4547 beq opcode_1_8\r
4548 add z80pc,z80pc,#1\r
4549 fetch 7\r
4550;@LD SP,NN\r
4551opcode_3_1:\r
4552 ldrb r0,[z80pc],#1\r
4553 ldrb r1,[z80pc],#1\r
4554\r
4555.if FAST_Z80SP\r
4556 orr r0,r0,r1, lsl #8\r
4557 rebasesp\r
4558 mov z80sp,r0\r
4559.else\r
4560 orr z80sp,r0,r1, lsl #8\r
4561.endif\r
4562 fetch 10\r
4563;@LD (NN),A\r
4564opcode_3_2:\r
4565 ldrb r0,[z80pc],#1\r
4566 ldrb r1,[z80pc],#1\r
4567 orr r1,r0,r1, lsl #8\r
4568 mov r0,z80a, lsr #24\r
4569 writemem8\r
4570 fetch 13\r
4571;@INC SP\r
4572opcode_3_3:\r
4573 add z80sp,z80sp,#1\r
4574 fetch 6\r
4575;@INC (HL)\r
4576opcode_3_4:\r
4577 readmem8HL\r
4578 opINC8b\r
4579 writemem8HL\r
4580 fetch 11\r
4581;@DEC (HL)\r
4582opcode_3_5:\r
4583 readmem8HL\r
4584 opDEC8b\r
4585 writemem8HL\r
4586 fetch 11\r
4587;@LD (HL),N\r
4588opcode_3_6:\r
4589 ldrb r0,[z80pc],#1\r
4590 writemem8HL\r
4591 fetch 10\r
4592;@SCF\r
4593opcode_3_7:\r
4594 bic z80f,z80f,#(1<<NFlag)|(1<<HFlag)\r
4595 orr z80f,z80f,#1<<CFlag\r
4596 fetch 4\r
4597;@JR C,$+2\r
4598opcode_3_8:\r
4599 tst z80f,#1<<CFlag\r
4600 bne opcode_1_8\r
4601 add z80pc,z80pc,#1\r
4602 fetch 8\r
4603;@ADD HL,SP\r
4604opcode_3_9:\r
4605.if FAST_Z80SP\r
4606 ldr r0,[cpucontext,#z80sp_base]\r
4607 sub r0,z80sp,r0\r
4608 opADD16s z80hl r0 16\r
4609.else\r
4610 opADD16s z80hl z80sp 16\r
4611.endif\r
4612 fetch 11\r
4613;@LD A,(NN)\r
4614opcode_3_A:\r
4615 ldrb r0,[z80pc],#1\r
4616 ldrb r1,[z80pc],#1\r
4617 orr r0,r0,r1, lsl #8\r
4618 readmem8\r
4619 mov z80a,r0, lsl #24\r
4620 fetch 11\r
4621;@DEC SP\r
4622opcode_3_B:\r
4623 sub z80sp,z80sp,#1\r
4624 fetch 6\r
4625;@INC A\r
4626opcode_3_C:\r
4627 opINC8 z80a\r
4628 fetch 4\r
4629;@DEC A\r
4630opcode_3_D:\r
4631 opDEC8 z80a\r
4632 fetch 4\r
4633;@LD A,N\r
4634opcode_3_E:\r
4635 ldrb r0,[z80pc],#1\r
4636 mov z80a,r0, lsl #24\r
4637 fetch 7\r
4638;@CCF\r
4639opcode_3_F:\r
4640 bic z80f,z80f,#(1<<NFlag)|(1<<HFlag)\r
4641 tst z80f,#1<<CFlag\r
4642 orrne z80f,z80f,#1<<HFlag\r
4643 eor z80f,z80f,#1<<CFlag\r
4644 fetch 4\r
4645\r
4646;@LD B,C\r
4647opcode_4_1:\r
4648 and z80bc,z80bc,#0xFF<<16\r
4649 orr z80bc,z80bc,z80bc, lsl #8\r
4650 fetch 4\r
4651;@LD B,D\r
4652opcode_4_2:\r
4653 and z80bc,z80bc,#0xFF<<16\r
4654 and r1,z80de,#0xFF<<24\r
4655 orr z80bc,z80bc,r1\r
4656 fetch 4\r
4657;@LD B,E\r
4658opcode_4_3:\r
4659 and z80bc,z80bc,#0xFF<<16\r
4660 and r1,z80de,#0xFF<<16\r
4661 orr z80bc,z80bc,r1, lsl #8\r
4662 fetch 4\r
4663;@LD B,H\r
4664opcode_4_4:\r
4665 and z80bc,z80bc,#0xFF<<16\r
4666 and r1,z80hl,#0xFF<<24\r
4667 orr z80bc,z80bc,r1\r
4668 fetch 4\r
4669;@LD B,L\r
4670opcode_4_5:\r
4671 and z80bc,z80bc,#0xFF<<16\r
4672 and r1,z80hl,#0xFF<<16\r
4673 orr z80bc,z80bc,r1, lsl #8\r
4674 fetch 4\r
4675;@LD B,(HL)\r
4676opcode_4_6:\r
4677 readmem8HL\r
4678 and z80bc,z80bc,#0xFF<<16\r
4679 orr z80bc,z80bc,r0, lsl #24\r
4680 fetch 7\r
4681;@LD B,A\r
4682opcode_4_7:\r
4683 and z80bc,z80bc,#0xFF<<16\r
4684 orr z80bc,z80bc,z80a\r
4685 fetch 4\r
4686;@LD C,B\r
4687opcode_4_8:\r
4688 and z80bc,z80bc,#0xFF<<24\r
4689 orr z80bc,z80bc,z80bc, lsr #8\r
4690 fetch 4\r
4691;@LD C,D\r
4692opcode_4_A:\r
4693 and z80bc,z80bc,#0xFF<<24\r
4694 and r1,z80de,#0xFF<<24\r
4695 orr z80bc,z80bc,r1, lsr #8\r
4696 fetch 4\r
4697;@LD C,E\r
4698opcode_4_B:\r
4699 and z80bc,z80bc,#0xFF<<24\r
4700 and r1,z80de,#0xFF<<16\r
4701 orr z80bc,z80bc,r1 \r
4702 fetch 4\r
4703;@LD C,H\r
4704opcode_4_C:\r
4705 and z80bc,z80bc,#0xFF<<24\r
4706 and r1,z80hl,#0xFF<<24\r
4707 orr z80bc,z80bc,r1, lsr #8\r
4708 fetch 4\r
4709;@LD C,L\r
4710opcode_4_D:\r
4711 and z80bc,z80bc,#0xFF<<24\r
4712 and r1,z80hl,#0xFF<<16\r
4713 orr z80bc,z80bc,r1 \r
4714 fetch 4\r
4715;@LD C,(HL)\r
4716opcode_4_E:\r
4717 readmem8HL\r
4718 and z80bc,z80bc,#0xFF<<24\r
4719 orr z80bc,z80bc,r0, lsl #16\r
4720 fetch 7\r
4721;@LD C,A\r
4722opcode_4_F:\r
4723 and z80bc,z80bc,#0xFF<<24\r
4724 orr z80bc,z80bc,z80a, lsr #8\r
4725 fetch 4\r
4726;@LD D,B\r
4727opcode_5_0:\r
4728 and z80de,z80de,#0xFF<<16\r
4729 and r1,z80bc,#0xFF<<24\r
4730 orr z80de,z80de,r1\r
4731 fetch 4\r
4732;@LD D,C\r
4733opcode_5_1:\r
4734 and z80de,z80de,#0xFF<<16\r
4735 orr z80de,z80de,z80bc, lsl #8\r
4736 fetch 4\r
4737;@LD D,E\r
4738opcode_5_3:\r
4739 and z80de,z80de,#0xFF<<16\r
4740 orr z80de,z80de,z80de, lsl #8\r
4741 fetch 4\r
4742;@LD D,H\r
4743opcode_5_4:\r
4744 and z80de,z80de,#0xFF<<16\r
4745 and r1,z80hl,#0xFF<<24\r
4746 orr z80de,z80de,r1\r
4747 fetch 4\r
4748;@LD D,L\r
4749opcode_5_5:\r
4750 and z80de,z80de,#0xFF<<16\r
4751 orr z80de,z80de,z80hl, lsl #8\r
4752 fetch 4\r
4753;@LD D,(HL)\r
4754opcode_5_6:\r
4755 readmem8HL\r
4756 and z80de,z80de,#0xFF<<16\r
4757 orr z80de,z80de,r0, lsl #24\r
4758 fetch 7\r
4759;@LD D,A\r
4760opcode_5_7:\r
4761 and z80de,z80de,#0xFF<<16\r
4762 orr z80de,z80de,z80a\r
4763 fetch 4\r
4764;@LD E,B\r
4765opcode_5_8:\r
4766 and z80de,z80de,#0xFF<<24\r
4767 and r1,z80bc,#0xFF<<24\r
4768 orr z80de,z80de,r1, lsr #8\r
4769 fetch 4\r
4770;@LD E,C\r
4771opcode_5_9:\r
4772 and z80de,z80de,#0xFF<<24\r
4773 and r1,z80bc,#0xFF<<16\r
4774 orr z80de,z80de,r1 \r
4775 fetch 4\r
4776;@LD E,D\r
4777opcode_5_A:\r
4778 and z80de,z80de,#0xFF<<24\r
4779 orr z80de,z80de,z80de, lsr #8\r
4780 fetch 4\r
4781;@LD E,H\r
4782opcode_5_C:\r
4783 and z80de,z80de,#0xFF<<24\r
4784 and r1,z80hl,#0xFF<<24\r
4785 orr z80de,z80de,r1, lsr #8\r
4786 fetch 4\r
4787;@LD E,L\r
4788opcode_5_D:\r
4789 and z80de,z80de,#0xFF<<24\r
4790 and r1,z80hl,#0xFF<<16\r
4791 orr z80de,z80de,r1 \r
4792 fetch 4\r
4793;@LD E,(HL)\r
4794opcode_5_E:\r
4795 readmem8HL\r
4796 and z80de,z80de,#0xFF<<24\r
4797 orr z80de,z80de,r0, lsl #16\r
4798 fetch 7\r
4799;@LD E,A\r
4800opcode_5_F:\r
4801 and z80de,z80de,#0xFF<<24\r
4802 orr z80de,z80de,z80a, lsr #8\r
4803 fetch 4\r
4804\r
4805;@LD H,B\r
4806opcode_6_0:\r
4807 and z80hl,z80hl,#0xFF<<16\r
4808 and r1,z80bc,#0xFF<<24\r
4809 orr z80hl,z80hl,r1\r
4810 fetch 4\r
4811;@LD H,C\r
4812opcode_6_1:\r
4813 and z80hl,z80hl,#0xFF<<16\r
4814 orr z80hl,z80hl,z80bc, lsl #8\r
4815 fetch 4\r
4816;@LD H,D\r
4817opcode_6_2:\r
4818 and z80hl,z80hl,#0xFF<<16\r
4819 and r1,z80de,#0xFF<<24\r
4820 orr z80hl,z80hl,r1\r
4821 fetch 4\r
4822;@LD H,E\r
4823opcode_6_3:\r
4824 and z80hl,z80hl,#0xFF<<16\r
4825 orr z80hl,z80hl,z80de, lsl #8\r
4826 fetch 4\r
4827;@LD H,L\r
4828opcode_6_5:\r
4829 and z80hl,z80hl,#0xFF<<16\r
4830 orr z80hl,z80hl,z80hl, lsl #8\r
4831 fetch 4\r
4832;@LD H,(HL)\r
4833opcode_6_6:\r
4834 readmem8HL\r
4835 and z80hl,z80hl,#0xFF<<16\r
4836 orr z80hl,z80hl,r0, lsl #24\r
4837 fetch 7\r
4838;@LD H,A\r
4839opcode_6_7:\r
4840 and z80hl,z80hl,#0xFF<<16\r
4841 orr z80hl,z80hl,z80a\r
4842 fetch 4\r
4843\r
4844;@LD L,B\r
4845opcode_6_8:\r
4846 and z80hl,z80hl,#0xFF<<24\r
4847 and r1,z80bc,#0xFF<<24\r
4848 orr z80hl,z80hl,r1, lsr #8\r
4849 fetch 4\r
4850;@LD L,C\r
4851opcode_6_9:\r
4852 and z80hl,z80hl,#0xFF<<24\r
4853 and r1,z80bc,#0xFF<<16\r
4854 orr z80hl,z80hl,r1\r
4855 fetch 4\r
4856;@LD L,D\r
4857opcode_6_A:\r
4858 and z80hl,z80hl,#0xFF<<24\r
4859 and r1,z80de,#0xFF<<24\r
4860 orr z80hl,z80hl,r1, lsr #8\r
4861 fetch 4\r
4862;@LD L,E\r
4863opcode_6_B:\r
4864 and z80hl,z80hl,#0xFF<<24\r
4865 and r1,z80de,#0xFF<<16\r
4866 orr z80hl,z80hl,r1\r
4867 fetch 4\r
4868;@LD L,H\r
4869opcode_6_C:\r
4870 and z80hl,z80hl,#0xFF<<24\r
4871 orr z80hl,z80hl,z80hl, lsr #8\r
4872 fetch 4\r
4873;@LD L,(HL)\r
4874opcode_6_E:\r
4875 readmem8HL\r
4876 and z80hl,z80hl,#0xFF<<24\r
4877 orr z80hl,z80hl,r0, lsl #16\r
4878 fetch 7\r
4879;@LD L,A\r
4880opcode_6_F:\r
4881 and z80hl,z80hl,#0xFF<<24\r
4882 orr z80hl,z80hl,z80a, lsr #8\r
4883 fetch 4\r
4884\r
4885;@LD (HL),B\r
4886opcode_7_0:\r
4887 mov r0,z80bc, lsr #24\r
4888 writemem8HL\r
4889 fetch 7\r
4890;@LD (HL),C\r
4891opcode_7_1:\r
4892 mov r0,z80bc, lsr #16\r
4893 and r0,r0,#0xFF\r
4894 writemem8HL\r
4895 fetch 7\r
4896;@LD (HL),D\r
4897opcode_7_2:\r
4898 mov r0,z80de, lsr #24\r
4899 writemem8HL\r
4900 fetch 7\r
4901;@LD (HL),E\r
4902opcode_7_3:\r
4903 mov r0,z80de, lsr #16\r
4904 and r0,r0,#0xFF\r
4905 writemem8HL\r
4906 fetch 7\r
4907;@LD (HL),H\r
4908opcode_7_4:\r
4909 mov r0,z80hl, lsr #24\r
4910 writemem8HL\r
4911 fetch 7\r
4912;@LD (HL),L\r
4913opcode_7_5:\r
4914 mov r1,z80hl, lsr #16\r
4915 and r0,r1,#0xFF\r
4916 writemem8\r
4917 fetch 7\r
4918;@HALT\r
4919opcode_7_6:\r
4920 sub z80pc,z80pc,#1\r
4921 ldrb r0,[cpucontext,#z80if]\r
4922 orr r0,r0,#Z80_HALT\r
4923 strb r0,[cpucontext,#z80if]\r
4924 b z80_execute_end\r
4925;@LD (HL),A\r
4926opcode_7_7:\r
4927 mov r0,z80a, lsr #24\r
4928 writemem8HL\r
4929 fetch 7\r
4930\r
4931;@LD A,B\r
4932opcode_7_8:\r
4933 and z80a,z80bc,#0xFF<<24\r
4934 fetch 4\r
4935;@LD A,C\r
4936opcode_7_9:\r
4937 mov z80a,z80bc, lsl #8\r
4938 fetch 4\r
4939;@LD A,D\r
4940opcode_7_A:\r
4941 and z80a,z80de,#0xFF<<24\r
4942 fetch 4\r
4943;@LD A,E\r
4944opcode_7_B:\r
4945 mov z80a,z80de, lsl #8\r
4946 fetch 4\r
4947;@LD A,H\r
4948opcode_7_C:\r
4949 and z80a,z80hl,#0xFF<<24\r
4950 fetch 4\r
4951;@LD A,L\r
4952opcode_7_D:\r
4953 mov z80a,z80hl, lsl #8\r
4954 fetch 4\r
4955;@LD A,(HL)\r
4956opcode_7_E:\r
4957 readmem8HL\r
4958 mov z80a,r0, lsl #24\r
4959 fetch 7\r
4960\r
4961;@ADD A,B\r
4962opcode_8_0:\r
4963 opADDH z80bc\r
4964;@ADD A,C\r
4965opcode_8_1:\r
4966 opADDL z80bc\r
4967;@ADD A,D\r
4968opcode_8_2:\r
4969 opADDH z80de\r
4970;@ADD A,E\r
4971opcode_8_3:\r
4972 opADDL z80de\r
4973;@ADD A,H\r
4974opcode_8_4:\r
4975 opADDH z80hl\r
4976;@ADD A,L\r
4977opcode_8_5:\r
4978 opADDL z80hl\r
4979;@ADD A,(HL)\r
4980opcode_8_6:\r
4981 readmem8HL\r
4982 opADDb\r
4983 fetch 7\r
4984;@ADD A,A\r
4985opcode_8_7:\r
4986 opADDA\r
4987\r
4988;@ADC A,B\r
4989opcode_8_8:\r
4990 opADCH z80bc\r
4991;@ADC A,C\r
4992opcode_8_9:\r
4993 opADCL z80bc\r
4994;@ADC A,D\r
4995opcode_8_A:\r
4996 opADCH z80de\r
4997;@ADC A,E\r
4998opcode_8_B:\r
4999 opADCL z80de\r
5000;@ADC A,H\r
5001opcode_8_C:\r
5002 opADCH z80hl\r
5003;@ADC A,L\r
5004opcode_8_D:\r
5005 opADCL z80hl\r
5006;@ADC A,(HL)\r
5007opcode_8_E:\r
5008 readmem8HL\r
5009 opADCb\r
5010 fetch 7\r
5011;@ADC A,A\r
5012opcode_8_F:\r
5013 opADCA\r
5014\r
5015;@SUB B\r
5016opcode_9_0:\r
5017 opSUBH z80bc\r
5018;@SUB C\r
5019opcode_9_1:\r
5020 opSUBL z80bc\r
5021;@SUB D\r
5022opcode_9_2:\r
5023 opSUBH z80de\r
5024;@SUB E\r
5025opcode_9_3:\r
5026 opSUBL z80de\r
5027;@SUB H\r
5028opcode_9_4:\r
5029 opSUBH z80hl\r
5030;@SUB L\r
5031opcode_9_5:\r
5032 opSUBL z80hl\r
5033;@SUB (HL)\r
5034opcode_9_6:\r
5035 readmem8HL\r
5036 opSUBb\r
5037 fetch 7\r
5038;@SUB A\r
5039opcode_9_7:\r
5040 opSUBA\r
5041\r
5042;@SBC B \r
5043opcode_9_8:\r
5044 opSBCH z80bc\r
5045;@SBC C\r
5046opcode_9_9:\r
5047 opSBCL z80bc\r
5048;@SBC D\r
5049opcode_9_A:\r
5050 opSBCH z80de\r
5051;@SBC E\r
5052opcode_9_B:\r
5053 opSBCL z80de\r
5054;@SBC H\r
5055opcode_9_C:\r
5056 opSBCH z80hl\r
5057;@SBC L\r
5058opcode_9_D:\r
5059 opSBCL z80hl\r
5060;@SBC (HL)\r
5061opcode_9_E:\r
5062 readmem8HL\r
5063 opSBCb\r
5064 fetch 7\r
5065;@SBC A\r
5066opcode_9_F:\r
5067 opSBCA\r
5068\r
5069;@AND B\r
5070opcode_A_0:\r
5071 opANDH z80bc\r
5072;@AND C\r
5073opcode_A_1:\r
5074 opANDL z80bc\r
5075;@AND D\r
5076opcode_A_2:\r
5077 opANDH z80de\r
5078;@AND E\r
5079opcode_A_3:\r
5080 opANDL z80de\r
5081;@AND H\r
5082opcode_A_4:\r
5083 opANDH z80hl\r
5084;@AND L\r
5085opcode_A_5:\r
5086 opANDL z80hl\r
5087;@AND (HL)\r
5088opcode_A_6:\r
5089 readmem8HL\r
5090 opANDb\r
5091 fetch 7\r
5092;@AND A\r
5093opcode_A_7:\r
5094 opANDA\r
5095\r
5096;@XOR B\r
5097opcode_A_8:\r
5098 opXORH z80bc\r
5099;@XOR C\r
5100opcode_A_9:\r
5101 opXORL z80bc\r
5102;@XOR D\r
5103opcode_A_A:\r
5104 opXORH z80de\r
5105;@XOR E\r
5106opcode_A_B:\r
5107 opXORL z80de\r
5108;@XOR H\r
5109opcode_A_C:\r
5110 opXORH z80hl\r
5111;@XOR L\r
5112opcode_A_D:\r
5113 opXORL z80hl\r
5114;@XOR (HL)\r
5115opcode_A_E:\r
5116 readmem8HL\r
5117 opXORb\r
5118 fetch 7\r
5119;@XOR A\r
5120opcode_A_F:\r
5121 opXORA\r
5122\r
5123;@OR B\r
5124opcode_B_0:\r
5125 opORH z80bc\r
5126;@OR C\r
5127opcode_B_1:\r
5128 opORL z80bc\r
5129;@OR D\r
5130opcode_B_2:\r
5131 opORH z80de\r
5132;@OR E\r
5133opcode_B_3:\r
5134 opORL z80de\r
5135;@OR H\r
5136opcode_B_4:\r
5137 opORH z80hl\r
5138;@OR L\r
5139opcode_B_5:\r
5140 opORL z80hl\r
5141;@OR (HL)\r
5142opcode_B_6:\r
5143 readmem8HL\r
5144 opORb\r
5145 fetch 7\r
5146;@OR A\r
5147opcode_B_7:\r
5148 opORA\r
5149\r
5150;@CP B\r
5151opcode_B_8:\r
5152 opCPH z80bc\r
5153;@CP C\r
5154opcode_B_9:\r
5155 opCPL z80bc\r
5156;@CP D\r
5157opcode_B_A:\r
5158 opCPH z80de\r
5159;@CP E\r
5160opcode_B_B:\r
5161 opCPL z80de\r
5162;@CP H\r
5163opcode_B_C:\r
5164 opCPH z80hl\r
5165;@CP L\r
5166opcode_B_D:\r
5167 opCPL z80hl\r
5168;@CP (HL)\r
5169opcode_B_E:\r
5170 readmem8HL\r
5171 opCPb\r
5172 fetch 7\r
5173;@CP A\r
5174opcode_B_F:\r
5175 opCPA\r
5176\r
5177;@RET NZ\r
5178opcode_C_0:\r
5179 tst z80f,#1<<ZFlag\r
5180 beq opcode_C_9 ;@unconditional RET\r
5181 fetch 5\r
5182\r
5183;@POP BC\r
5184opcode_C_1:\r
5185 opPOPreg z80bc\r
5186\r
5187;@JP NZ,$+3\r
5188opcode_C_2:\r
5189 tst z80f,#1<<ZFlag\r
5190 beq opcode_C_3 ;@unconditional JP\r
5191 add z80pc,z80pc,#2\r
5192 fetch 10\r
5193;@JP $+3\r
5194opcode_C_3:\r
5195 ldrb r0,[z80pc],#1\r
5196 ldrb r1,[z80pc],#1\r
5197 orr r0,r0,r1, lsl #8\r
5198 rebasepc\r
5199 fetch 10\r
5200;@CALL NZ,NN\r
5201opcode_C_4:\r
5202 tst z80f,#1<<ZFlag\r
5203 beq opcode_C_D ;@unconditional CALL\r
5204 add z80pc,z80pc,#2\r
5205 fetch 10\r
5206\r
5207;@PUSH BC\r
5208opcode_C_5:\r
5209 opPUSHreg z80bc\r
5210 fetch 11\r
5211;@ADD A,N\r
5212opcode_C_6:\r
5213 ldrb r0,[z80pc],#1\r
5214 opADDb\r
5215 fetch 7\r
5216;@RST 0\r
5217opcode_C_7:\r
5218 opRST 0x00\r
5219\r
5220;@RET Z\r
5221opcode_C_8:\r
5222 tst z80f,#1<<ZFlag\r
5223 bne opcode_C_9 ;@unconditional RET\r
5224 fetch 5\r
5225;@RET\r
5226opcode_C_9:\r
5227 opPOP\r
5228 rebasepc\r
5229 fetch 10\r
5230;@JP Z,$+3\r
5231opcode_C_A:\r
5232 tst z80f,#1<<ZFlag\r
5233 bne opcode_C_3 ;@unconditional JP\r
5234 add z80pc,z80pc,#2\r
5235 fetch 10\r
5236\r
5237;@This reads this opcodes_CB lookup table to find the location of\r
5238;@the CB sub for the intruction and then branches to that location\r
5239opcode_C_B:\r
5240 ldrb r0,[z80pc],#1\r
5241 ldr pc,[pc,r0, lsl #2]\r
5242opcodes_CB: .word 0x00000000\r
5243 .word opcode_CB_00,opcode_CB_01,opcode_CB_02,opcode_CB_03,opcode_CB_04,opcode_CB_05,opcode_CB_06,opcode_CB_07\r
5244 .word opcode_CB_08,opcode_CB_09,opcode_CB_0A,opcode_CB_0B,opcode_CB_0C,opcode_CB_0D,opcode_CB_0E,opcode_CB_0F\r
5245 .word opcode_CB_10,opcode_CB_11,opcode_CB_12,opcode_CB_13,opcode_CB_14,opcode_CB_15,opcode_CB_16,opcode_CB_17\r
5246 .word opcode_CB_18,opcode_CB_19,opcode_CB_1A,opcode_CB_1B,opcode_CB_1C,opcode_CB_1D,opcode_CB_1E,opcode_CB_1F\r
5247 .word opcode_CB_20,opcode_CB_21,opcode_CB_22,opcode_CB_23,opcode_CB_24,opcode_CB_25,opcode_CB_26,opcode_CB_27\r
5248 .word opcode_CB_28,opcode_CB_29,opcode_CB_2A,opcode_CB_2B,opcode_CB_2C,opcode_CB_2D,opcode_CB_2E,opcode_CB_2F\r
5249 .word opcode_CB_30,opcode_CB_31,opcode_CB_32,opcode_CB_33,opcode_CB_34,opcode_CB_35,opcode_CB_36,opcode_CB_37\r
5250 .word opcode_CB_38,opcode_CB_39,opcode_CB_3A,opcode_CB_3B,opcode_CB_3C,opcode_CB_3D,opcode_CB_3E,opcode_CB_3F\r
5251 .word opcode_CB_40,opcode_CB_41,opcode_CB_42,opcode_CB_43,opcode_CB_44,opcode_CB_45,opcode_CB_46,opcode_CB_47\r
5252 .word opcode_CB_48,opcode_CB_49,opcode_CB_4A,opcode_CB_4B,opcode_CB_4C,opcode_CB_4D,opcode_CB_4E,opcode_CB_4F\r
5253 .word opcode_CB_50,opcode_CB_51,opcode_CB_52,opcode_CB_53,opcode_CB_54,opcode_CB_55,opcode_CB_56,opcode_CB_57\r
5254 .word opcode_CB_58,opcode_CB_59,opcode_CB_5A,opcode_CB_5B,opcode_CB_5C,opcode_CB_5D,opcode_CB_5E,opcode_CB_5F\r
5255 .word opcode_CB_60,opcode_CB_61,opcode_CB_62,opcode_CB_63,opcode_CB_64,opcode_CB_65,opcode_CB_66,opcode_CB_67\r
5256 .word opcode_CB_68,opcode_CB_69,opcode_CB_6A,opcode_CB_6B,opcode_CB_6C,opcode_CB_6D,opcode_CB_6E,opcode_CB_6F\r
5257 .word opcode_CB_70,opcode_CB_71,opcode_CB_72,opcode_CB_73,opcode_CB_74,opcode_CB_75,opcode_CB_76,opcode_CB_77\r
5258 .word opcode_CB_78,opcode_CB_79,opcode_CB_7A,opcode_CB_7B,opcode_CB_7C,opcode_CB_7D,opcode_CB_7E,opcode_CB_7F\r
5259 .word opcode_CB_80,opcode_CB_81,opcode_CB_82,opcode_CB_83,opcode_CB_84,opcode_CB_85,opcode_CB_86,opcode_CB_87\r
5260 .word opcode_CB_88,opcode_CB_89,opcode_CB_8A,opcode_CB_8B,opcode_CB_8C,opcode_CB_8D,opcode_CB_8E,opcode_CB_8F\r
5261 .word opcode_CB_90,opcode_CB_91,opcode_CB_92,opcode_CB_93,opcode_CB_94,opcode_CB_95,opcode_CB_96,opcode_CB_97\r
5262 .word opcode_CB_98,opcode_CB_99,opcode_CB_9A,opcode_CB_9B,opcode_CB_9C,opcode_CB_9D,opcode_CB_9E,opcode_CB_9F\r
5263 .word opcode_CB_A0,opcode_CB_A1,opcode_CB_A2,opcode_CB_A3,opcode_CB_A4,opcode_CB_A5,opcode_CB_A6,opcode_CB_A7\r
5264 .word opcode_CB_A8,opcode_CB_A9,opcode_CB_AA,opcode_CB_AB,opcode_CB_AC,opcode_CB_AD,opcode_CB_AE,opcode_CB_AF\r
5265 .word opcode_CB_B0,opcode_CB_B1,opcode_CB_B2,opcode_CB_B3,opcode_CB_B4,opcode_CB_B5,opcode_CB_B6,opcode_CB_B7\r
5266 .word opcode_CB_B8,opcode_CB_B9,opcode_CB_BA,opcode_CB_BB,opcode_CB_BC,opcode_CB_BD,opcode_CB_BE,opcode_CB_BF\r
5267 .word opcode_CB_C0,opcode_CB_C1,opcode_CB_C2,opcode_CB_C3,opcode_CB_C4,opcode_CB_C5,opcode_CB_C6,opcode_CB_C7\r
5268 .word opcode_CB_C8,opcode_CB_C9,opcode_CB_CA,opcode_CB_CB,opcode_CB_CC,opcode_CB_CD,opcode_CB_CE,opcode_CB_CF\r
5269 .word opcode_CB_D0,opcode_CB_D1,opcode_CB_D2,opcode_CB_D3,opcode_CB_D4,opcode_CB_D5,opcode_CB_D6,opcode_CB_D7\r
5270 .word opcode_CB_D8,opcode_CB_D9,opcode_CB_DA,opcode_CB_DB,opcode_CB_DC,opcode_CB_DD,opcode_CB_DE,opcode_CB_DF\r
5271 .word opcode_CB_E0,opcode_CB_E1,opcode_CB_E2,opcode_CB_E3,opcode_CB_E4,opcode_CB_E5,opcode_CB_E6,opcode_CB_E7\r
5272 .word opcode_CB_E8,opcode_CB_E9,opcode_CB_EA,opcode_CB_EB,opcode_CB_EC,opcode_CB_ED,opcode_CB_EE,opcode_CB_EF\r
5273 .word opcode_CB_F0,opcode_CB_F1,opcode_CB_F2,opcode_CB_F3,opcode_CB_F4,opcode_CB_F5,opcode_CB_F6,opcode_CB_F7\r
5274 .word opcode_CB_F8,opcode_CB_F9,opcode_CB_FA,opcode_CB_FB,opcode_CB_FC,opcode_CB_FD,opcode_CB_FE,opcode_CB_FF\r
5275\r
5276;@CALL Z,NN\r
5277opcode_C_C:\r
5278 tst z80f,#1<<ZFlag\r
5279 bne opcode_C_D ;@unconditional CALL\r
5280 add z80pc,z80pc,#2\r
5281 fetch 10\r
5282;@CALL NN\r
5283opcode_C_D:\r
5284 ldrb r0,[z80pc],#1\r
5285 ldrb r1,[z80pc],#1\r
5286 ldr r2,[cpucontext,#z80pc_base]\r
5287 sub r2,z80pc,r2\r
5288 orr z80pc,r0,r1, lsl #8\r
5289 opPUSHareg r2\r
5290 mov r0,z80pc\r
5291 rebasepc\r
5292 fetch 17\r
5293;@ADC A,N\r
5294opcode_C_E:\r
5295 ldrb r0,[z80pc],#1\r
5296 opADCb\r
5297 fetch 7\r
5298;@RST 8H\r
5299opcode_C_F:\r
5300 opRST 0x08\r
5301\r
5302;@RET NC\r
5303opcode_D_0:\r
5304 tst z80f,#1<<CFlag\r
5305 beq opcode_C_9 ;@unconditional RET\r
5306 fetch 5\r
5307;@POP DE\r
5308opcode_D_1:\r
5309 opPOPreg z80de\r
5310\r
5311;@JP NC, $+3\r
5312opcode_D_2 :\r
5313 tst z80f,#1<<CFlag\r
5314 beq opcode_C_3 ;@unconditional JP\r
5315 add z80pc,z80pc,#2\r
5316 fetch 10\r
5317;@OUT (N),A\r
5318opcode_D_3:\r
5319 ldrb r0,[z80pc],#1\r
5320 orr r0,r0,z80a,lsr#16\r
5321 mov r1,z80a, lsr #24\r
5322 opOUT\r
5323 fetch 11\r
5324;@CALL NC,NN\r
5325opcode_D_4:\r
5326 tst z80f,#1<<CFlag\r
5327 beq opcode_C_D ;@unconditional CALL\r
5328 add z80pc,z80pc,#2\r
5329 fetch 10\r
5330;@PUSH DE\r
5331opcode_D_5:\r
5332 opPUSHreg z80de\r
5333 fetch 11\r
5334;@SUB N\r
5335opcode_D_6:\r
5336 ldrb r0,[z80pc],#1\r
5337 opSUBb\r
5338 fetch 7\r
5339\r
5340;@RST 10H\r
5341opcode_D_7:\r
5342 opRST 0x10\r
5343\r
5344;@RET C\r
5345opcode_D_8:\r
5346 tst z80f,#1<<CFlag\r
5347 bne opcode_C_9 ;@unconditional RET\r
5348 fetch 5\r
5349;@EXX\r
5350opcode_D_9:\r
5351 add r1,cpucontext,#z80bc2\r
5352 swp z80bc,z80bc,[r1]\r
5353 add r1,cpucontext,#z80de2\r
5354 swp z80de,z80de,[r1]\r
5355 add r1,cpucontext,#z80hl2\r
5356 swp z80hl,z80hl,[r1]\r
5357 fetch 4\r
5358;@JP C,$+3\r
5359opcode_D_A:\r
5360 tst z80f,#1<<CFlag\r
5361 bne opcode_C_3 ;@unconditional JP\r
5362 add z80pc,z80pc,#2\r
5363 fetch 10\r
5364;@IN A,(N)\r
5365opcode_D_B:\r
5366 ldrb r0,[z80pc],#1\r
5367 orr r0,r0,z80a,lsr#16\r
5368 opIN\r
5369 mov z80a,r0, lsl #24 ;@ r0 = data read\r
5370 fetch 11\r
5371;@CALL C,NN\r
5372opcode_D_C:\r
5373 tst z80f,#1<<CFlag\r
5374 bne opcode_C_D ;@unconditional CALL\r
5375 add z80pc,z80pc,#2\r
5376 fetch 10\r
5377\r
5378;@opcodes_DD\r
5379opcode_D_D:\r
5380 add z80xx,cpucontext,#z80ix\r
5381 b opcode_D_D_F_D\r
5382opcode_F_D:\r
5383 add z80xx,cpucontext,#z80iy\r
5384opcode_D_D_F_D:\r
5385 ldrb r0,[z80pc],#1\r
5386 ldr pc,[pc,r0, lsl #2]\r
5387opcodes_DD: .word 0x00000000\r
5388 .word opcode_0_0, opcode_0_1, opcode_0_2, opcode_0_3, opcode_0_4, opcode_0_5, opcode_0_6, opcode_0_7\r
5389 .word opcode_0_8, opcode_DD_09,opcode_0_A, opcode_0_B, opcode_0_C, opcode_0_D, opcode_0_E, opcode_0_F\r
5390 .word opcode_1_0, opcode_1_1, opcode_1_2, opcode_1_3, opcode_1_4, opcode_1_5, opcode_1_6, opcode_1_7\r
5391 .word opcode_1_8, opcode_DD_19,opcode_1_A, opcode_1_B, opcode_1_C, opcode_1_D, opcode_1_E, opcode_1_F\r
5392 .word opcode_2_0, opcode_DD_21,opcode_DD_22,opcode_DD_23,opcode_DD_24,opcode_DD_25,opcode_DD_26,opcode_2_7\r
5393 .word opcode_2_8, opcode_DD_29,opcode_DD_2A,opcode_DD_2B,opcode_DD_2C,opcode_DD_2D,opcode_DD_2E,opcode_2_F\r
5394 .word opcode_3_0, opcode_3_1, opcode_3_2, opcode_3_3, opcode_DD_34,opcode_DD_35,opcode_DD_36,opcode_3_7\r
5395 .word opcode_3_8, opcode_DD_39,opcode_3_A, opcode_3_B, opcode_3_C, opcode_3_D, opcode_3_E, opcode_3_F\r
5396 .word opcode_4_0, opcode_4_1, opcode_4_2, opcode_4_3, opcode_DD_44,opcode_DD_45,opcode_DD_46,opcode_4_7\r
5397 .word opcode_4_8, opcode_4_9, opcode_4_A, opcode_4_B, opcode_DD_4C,opcode_DD_4D,opcode_DD_4E,opcode_4_F\r
5398 .word opcode_5_0, opcode_5_1, opcode_5_2, opcode_5_3, opcode_DD_54,opcode_DD_55,opcode_DD_56,opcode_5_7\r
5399 .word opcode_5_8, opcode_5_9, opcode_5_A, opcode_5_B, opcode_DD_5C,opcode_DD_5D,opcode_DD_5E,opcode_5_F\r
5400 .word opcode_DD_60,opcode_DD_61,opcode_DD_62,opcode_DD_63,opcode_DD_64,opcode_DD_65,opcode_DD_66,opcode_DD_67\r
5401 .word opcode_DD_68,opcode_DD_69,opcode_DD_6A,opcode_DD_6B,opcode_DD_6C,opcode_DD_6D,opcode_DD_6E,opcode_DD_6F\r
5402 .word opcode_DD_70,opcode_DD_71,opcode_DD_72,opcode_DD_73,opcode_DD_74,opcode_DD_75,opcode_7_6, opcode_DD_77\r
5403 .word opcode_7_8, opcode_7_9, opcode_7_A, opcode_7_B, opcode_DD_7C,opcode_DD_7D,opcode_DD_7E,opcode_7_F\r
5404 .word opcode_8_0, opcode_8_1, opcode_8_2, opcode_8_3, opcode_DD_84,opcode_DD_85,opcode_DD_86,opcode_8_7\r
5405 .word opcode_8_8, opcode_8_9, opcode_8_A, opcode_8_B, opcode_DD_8C,opcode_DD_8D,opcode_DD_8E,opcode_8_F\r
5406 .word opcode_9_0, opcode_9_1, opcode_9_2, opcode_9_3, opcode_DD_94,opcode_DD_95,opcode_DD_96,opcode_9_7\r
5407 .word opcode_9_8, opcode_9_9, opcode_9_A, opcode_9_B, opcode_DD_9C,opcode_DD_9D,opcode_DD_9E,opcode_9_F\r
5408 .word opcode_A_0, opcode_A_1, opcode_A_2, opcode_A_3, opcode_DD_A4,opcode_DD_A5,opcode_DD_A6,opcode_A_7\r
5409 .word opcode_A_8, opcode_A_9, opcode_A_A, opcode_A_B, opcode_DD_AC,opcode_DD_AD,opcode_DD_AE,opcode_A_F\r
5410 .word opcode_B_0, opcode_B_1, opcode_B_2, opcode_B_3, opcode_DD_B4,opcode_DD_B5,opcode_DD_B6,opcode_B_7\r
5411 .word opcode_B_8, opcode_B_9, opcode_B_A, opcode_B_B, opcode_DD_BC,opcode_DD_BD,opcode_DD_BE,opcode_B_F\r
5412 .word opcode_C_0, opcode_C_1, opcode_C_2, opcode_C_3, opcode_C_4, opcode_C_5, opcode_C_6, opcode_C_7\r
5413 .word opcode_C_8, opcode_C_9, opcode_C_A, opcode_DD_CB,opcode_C_C, opcode_C_D, opcode_C_E, opcode_C_F\r
5414 .word opcode_D_0, opcode_D_1, opcode_D_2, opcode_D_3, opcode_D_4, opcode_D_5, opcode_D_6, opcode_D_7\r
5415 .word opcode_D_8, opcode_D_9, opcode_D_A, opcode_D_B, opcode_D_C, opcode_D_D, opcode_D_E, opcode_D_F\r
5416 .word opcode_E_0, opcode_DD_E1,opcode_E_2, opcode_DD_E3,opcode_E_4, opcode_DD_E5,opcode_E_6, opcode_E_7\r
5417 .word opcode_E_8, opcode_DD_E9,opcode_E_A, opcode_E_B, opcode_E_C, opcode_E_D, opcode_E_E, opcode_E_F\r
5418 .word opcode_F_0, opcode_F_1, opcode_F_2, opcode_F_3, opcode_F_4, opcode_F_5, opcode_F_6, opcode_F_7\r
5419 .word opcode_F_8, opcode_DD_F9,opcode_F_A, opcode_F_B, opcode_F_C, opcode_F_D, opcode_F_E, opcode_F_F\r
5420\r
5421;@SBC A,N\r
5422opcode_D_E:\r
5423 ldrb r0,[z80pc],#1\r
5424 opSBCb\r
5425 fetch 7\r
5426;@RST 18H\r
5427opcode_D_F:\r
5428 opRST 0x18\r
5429\r
5430;@RET PO\r
5431opcode_E_0:\r
5432 tst z80f,#1<<VFlag\r
5433 beq opcode_C_9 ;@unconditional RET\r
5434 fetch 5\r
5435;@POP HL\r
5436opcode_E_1:\r
5437 opPOPreg z80hl\r
5438\r
5439;@JP PO,$+3\r
5440opcode_E_2:\r
5441 tst z80f,#1<<VFlag\r
5442 beq opcode_C_3 ;@unconditional JP\r
5443 add z80pc,z80pc,#2\r
5444 fetch 10\r
5445;@EX (SP),HL\r
5446opcode_E_3:\r
5447.if FAST_Z80SP\r
5448 ldrb r0,[z80sp]\r
5449 ldrb r1,[z80sp,#1]\r
5450 orr r0,r0,r1, lsl #8\r
5451 mov r1,z80hl, lsr #24\r
5452 strb r1,[z80sp,#1]\r
5453 mov r1,z80hl, lsr #16\r
5454 strb r1,[z80sp]\r
5455 mov z80hl,r0, lsl #16\r
5456.else\r
5457 mov r0,z80sp\r
5458 readmem16\r
5459 mov r1,r0\r
5460 mov r0,z80hl,lsr#16\r
5461 mov z80hl,r1,lsl#16\r
5462 mov r1,z80sp\r
5463 writemem16\r
5464.endif\r
5465 fetch 19\r
5466;@CALL PO,NN\r
5467opcode_E_4:\r
5468 tst z80f,#1<<VFlag\r
5469 beq opcode_C_D ;@unconditional CALL\r
5470 add z80pc,z80pc,#2\r
5471 fetch 10\r
5472;@PUSH HL\r
5473opcode_E_5:\r
5474 opPUSHreg z80hl\r
5475 fetch 11\r
5476;@AND N\r
5477opcode_E_6:\r
5478 ldrb r0,[z80pc],#1\r
5479 opANDb\r
5480 fetch 7\r
5481;@RST 20H\r
5482opcode_E_7:\r
5483 opRST 0x20\r
5484\r
5485;@RET PE\r
5486opcode_E_8:\r
5487 tst z80f,#1<<VFlag\r
5488 bne opcode_C_9 ;@unconditional RET\r
5489 fetch 5\r
5490;@JP (HL)\r
5491opcode_E_9:\r
5492 mov r0,z80hl, lsr #16\r
5493 rebasepc\r
5494 fetch 4\r
5495;@JP PE,$+3\r
5496opcode_E_A:\r
5497 tst z80f,#1<<VFlag\r
5498 bne opcode_C_3 ;@unconditional JP\r
5499 add z80pc,z80pc,#2\r
5500 fetch 10\r
5501;@EX DE,HL\r
5502opcode_E_B:\r
5503 mov r1,z80de\r
5504 mov z80de,z80hl\r
5505 mov z80hl,r1\r
5506 fetch 4\r
5507;@CALL PE,NN\r
5508opcode_E_C:\r
5509 tst z80f,#1<<VFlag\r
5510 bne opcode_C_D ;@unconditional CALL\r
5511 add z80pc,z80pc,#2\r
5512 fetch 10\r
5513\r
5514;@This should be caught at start\r
5515opcode_E_D:\r
5516 ldrb r1,[z80pc],#1\r
5517 ldr pc,[pc,r1, lsl #2]\r
5518opcodes_ED: .word 0x00000000\r
5519 .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
5520 .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
5521 .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
5522 .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
5523 .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
5524 .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
5525 .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
5526 .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
5527 .word opcode_ED_40,opcode_ED_41,opcode_ED_42,opcode_ED_43,opcode_ED_44,opcode_ED_45,opcode_ED_46,opcode_ED_47\r
5528 .word opcode_ED_48,opcode_ED_49,opcode_ED_4A,opcode_ED_4B,opcode_ED_44,opcode_ED_4D,opcode_ED_46,opcode_ED_4F\r
5529 .word opcode_ED_50,opcode_ED_51,opcode_ED_52,opcode_ED_53,opcode_ED_44,opcode_ED_45,opcode_ED_56,opcode_ED_57\r
5530 .word opcode_ED_58,opcode_ED_59,opcode_ED_5A,opcode_ED_5B,opcode_ED_44,opcode_ED_45,opcode_ED_5E,opcode_ED_5F\r
5531 .word opcode_ED_60,opcode_ED_61,opcode_ED_62,opcode_ED_63,opcode_ED_44,opcode_ED_45,opcode_ED_46,opcode_ED_67\r
5532 .word opcode_ED_68,opcode_ED_69,opcode_ED_6A,opcode_ED_6B,opcode_ED_44,opcode_ED_45,opcode_ED_46,opcode_ED_6F\r
5533 .word opcode_ED_70,opcode_ED_71,opcode_ED_72,opcode_ED_73,opcode_ED_44,opcode_ED_45,opcode_ED_56,opcode_ED_NF\r
5534 .word opcode_ED_78,opcode_ED_79,opcode_ED_7A,opcode_ED_7B,opcode_ED_44,opcode_ED_45,opcode_ED_5E,opcode_ED_NF\r
5535 .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
5536 .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
5537 .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
5538 .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
5539 .word opcode_ED_A0,opcode_ED_A1,opcode_ED_A2,opcode_ED_A3,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
5540 .word opcode_ED_A8,opcode_ED_A9,opcode_ED_AA,opcode_ED_AB,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
5541 .word opcode_ED_B0,opcode_ED_B1,opcode_ED_B2,opcode_ED_B3,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
5542 .word opcode_ED_B8,opcode_ED_B9,opcode_ED_BA,opcode_ED_BB,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
5543 .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
5544 .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
5545 .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
5546 .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
5547 .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
5548 .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
5549 .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
5550 .word opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF,opcode_ED_NF\r
5551\r
5552;@XOR N\r
5553opcode_E_E:\r
5554 ldrb r0,[z80pc],#1\r
5555 opXORb\r
5556 fetch 7\r
5557;@RST 28H\r
5558opcode_E_F:\r
5559 opRST 0x28\r
5560\r
5561;@RET P\r
5562opcode_F_0:\r
5563 tst z80f,#1<<SFlag\r
5564 beq opcode_C_9 ;@unconditional RET\r
5565 fetch 5\r
5566;@POP AF\r
5567opcode_F_1:\r
5568.if FAST_Z80SP\r
5569 ldrb z80f,[z80sp],#1\r
5570 sub r0,opcodes,#0x200\r
5571 ldrb z80f,[r0,z80f]\r
5572 ldrb z80a,[z80sp],#1\r
5573 mov z80a,z80a, lsl #24\r
5574.else\r
5575 mov r0,z80sp\r
5576 readmem16\r
5577 add z80sp,z80sp,#2\r
5578 and z80a,r0,#0xFF00\r
5579 mov z80a,z80a,lsl#16\r
5580 and z80f,r0,#0xFF\r
5581 sub r0,opcodes,#0x200\r
5582 ldrb z80f,[r0,z80f]\r
5583.endif\r
5584 fetch 10\r
5585;@JP P,$+3\r
5586opcode_F_2:\r
5587 tst z80f,#1<<SFlag\r
5588 beq opcode_C_3 ;@unconditional JP\r
5589 add z80pc,z80pc,#2\r
5590 fetch 10\r
5591;@DI\r
5592opcode_F_3:\r
5593 ldrb r1,[cpucontext,#z80if]\r
5594 bic r1,r1,#(Z80_IF1)|(Z80_IF2)\r
5595 strb r1,[cpucontext,#z80if]\r
5596 fetch 4\r
5597;@CALL P,NN\r
5598opcode_F_4:\r
5599 tst z80f,#1<<SFlag\r
5600 beq opcode_C_D ;@unconditional CALL\r
5601 add z80pc,z80pc,#2\r
5602 fetch 10\r
5603;@PUSH AF\r
5604opcode_F_5:\r
5605 sub r0,opcodes,#0x300\r
5606 ldrb r0,[r0,z80f]\r
5607 orr r2,r0,z80a,lsr#16\r
5608 opPUSHareg r2\r
5609 fetch 11\r
5610;@OR N\r
5611opcode_F_6:\r
5612 ldrb r0,[z80pc],#1\r
5613 opORb\r
5614 fetch 7\r
5615;@RST 30H\r
5616opcode_F_7:\r
5617 opRST 0x30\r
5618\r
5619;@RET M\r
5620opcode_F_8:\r
5621 tst z80f,#1<<SFlag\r
5622 bne opcode_C_9 ;@unconditional RET\r
5623 fetch 5\r
5624;@LD SP,HL\r
5625opcode_F_9:\r
5626.if FAST_Z80SP\r
5627 mov r0,z80hl, lsr #16\r
5628 rebasesp\r
5629 mov z80sp,r0\r
5630.else\r
5631 mov z80sp,z80hl, lsr #16\r
5632.endif\r
5633 fetch 4\r
5634;@JP M,$+3\r
5635opcode_F_A:\r
5636 tst z80f,#1<<SFlag\r
5637 bne opcode_C_3 ;@unconditional JP\r
5638 add z80pc,z80pc,#2\r
5639 fetch 10\r
5640MAIN_opcodes_POINTER: .word MAIN_opcodes\r
5641EI_DUMMY_opcodes_POINTER: .word EI_DUMMY_opcodes\r
5642;@EI\r
5643opcode_F_B:\r
5644 ldrb r1,[cpucontext,#z80if]\r
5645 tst r1,#Z80_IF1\r
5646 bne ei_return_exit\r
5647\r
5648 orr r1,r1,#(Z80_IF1)|(Z80_IF2)\r
5649 strb r1,[cpucontext,#z80if]\r
5650\r
5651 mov r2,opcodes\r
5652 ldr opcodes,EI_DUMMY_opcodes_POINTER\r
5653 ldr pc,[r2,r0, lsl #2]\r
5654\r
5655ei_return:\r
5656 ;@point that program returns from EI to check interupts\r
5657 ;@an interupt can not be taken directly after a EI opcode\r
5658 ;@ reset z80pc and opcode pointer\r
5659 ldrh r0,[cpucontext,#z80irq] @ 0x4C\r
5660 sub z80pc,z80pc,#1\r
5661 ldr opcodes,MAIN_opcodes_POINTER\r
5662 ;@ check ints\r
5663 tst r0,#1\r
5664 movnes r0,r0,lsr #8\r
5665 blne DoInterrupt\r
5666 ;@ continue\r
5667ei_return_exit:\r
5668 fetch 4\r
5669\r
5670;@CALL M,NN\r
5671opcode_F_C:\r
5672 tst z80f,#1<<SFlag\r
5673 bne opcode_C_D ;@unconditional CALL\r
5674 add z80pc,z80pc,#2\r
5675 fetch 10\r
5676\r
5677;@SHOULD BE CAUGHT AT START - FD SECTION\r
5678\r
5679;@CP N\r
5680opcode_F_E:\r
5681 ldrb r0,[z80pc],#1\r
5682 opCPb\r
5683 fetch 7\r
5684;@RST 38H\r
5685opcode_F_F:\r
5686 opRST 0x38\r
5687\r
5688\r
5689;@##################################\r
5690;@##################################\r
5691;@### opcodes CB #########################\r
5692;@##################################\r
5693;@##################################\r
5694\r
5695\r
5696;@RLC B\r
5697opcode_CB_00:\r
5698 opRLCH z80bc\r
5699;@RLC C\r
5700opcode_CB_01:\r
5701 opRLCL z80bc\r
5702;@RLC D\r
5703opcode_CB_02:\r
5704 opRLCH z80de\r
5705;@RLC E\r
5706opcode_CB_03:\r
5707 opRLCL z80de\r
5708;@RLC H\r
5709opcode_CB_04:\r
5710 opRLCH z80hl\r
5711;@RLC L\r
5712opcode_CB_05:\r
5713 opRLCL z80hl\r
5714;@RLC (HL)\r
5715opcode_CB_06:\r
5716 readmem8HL\r
5717 opRLCb\r
5718 writemem8HL\r
5719 fetch 15\r
5720;@RLC A\r
5721opcode_CB_07:\r
5722 opRLCA\r
5723\r
5724;@RRC B\r
5725opcode_CB_08:\r
5726 opRRCH z80bc\r
5727;@RRC C\r
5728opcode_CB_09:\r
5729 opRRCL z80bc\r
5730;@RRC D\r
5731opcode_CB_0A:\r
5732 opRRCH z80de\r
5733;@RRC E\r
5734opcode_CB_0B:\r
5735 opRRCL z80de\r
5736;@RRC H\r
5737opcode_CB_0C:\r
5738 opRRCH z80hl\r
5739;@RRC L\r
5740opcode_CB_0D:\r
5741 opRRCL z80hl\r
5742;@RRC (HL)\r
5743opcode_CB_0E :\r
5744 readmem8HL\r
5745 opRRCb\r
5746 writemem8HL\r
5747 fetch 15\r
5748;@RRC A\r
5749opcode_CB_0F:\r
5750 opRRCA\r
5751\r
5752;@RL B\r
5753opcode_CB_10:\r
5754 opRLH z80bc\r
5755;@RL C\r
5756opcode_CB_11:\r
5757 opRLL z80bc\r
5758;@RL D\r
5759opcode_CB_12:\r
5760 opRLH z80de\r
5761;@RL E\r
5762opcode_CB_13:\r
5763 opRLL z80de\r
5764;@RL H\r
5765opcode_CB_14:\r
5766 opRLH z80hl\r
5767;@RL L\r
5768opcode_CB_15:\r
5769 opRLL z80hl\r
5770;@RL (HL)\r
5771opcode_CB_16:\r
5772 readmem8HL\r
5773 opRLb\r
5774 writemem8HL\r
5775 fetch 15\r
5776;@RL A\r
5777opcode_CB_17:\r
5778 opRLA\r
5779\r
5780;@RR B \r
5781opcode_CB_18:\r
5782 opRRH z80bc\r
5783;@RR C\r
5784opcode_CB_19:\r
5785 opRRL z80bc\r
5786;@RR D\r
5787opcode_CB_1A:\r
5788 opRRH z80de\r
5789;@RR E\r
5790opcode_CB_1B:\r
5791 opRRL z80de\r
5792;@RR H\r
5793opcode_CB_1C:\r
5794 opRRH z80hl\r
5795;@RR L\r
5796opcode_CB_1D:\r
5797 opRRL z80hl\r
5798;@RR (HL)\r
5799opcode_CB_1E:\r
5800 readmem8HL\r
5801 opRRb\r
5802 writemem8HL\r
5803 fetch 15\r
5804;@RR A\r
5805opcode_CB_1F:\r
5806 opRRA\r
5807\r
5808;@SLA B\r
5809opcode_CB_20:\r
5810 opSLAH z80bc\r
5811;@SLA C\r
5812opcode_CB_21:\r
5813 opSLAL z80bc\r
5814;@SLA D\r
5815opcode_CB_22:\r
5816 opSLAH z80de\r
5817;@SLA E\r
5818opcode_CB_23:\r
5819 opSLAL z80de\r
5820;@SLA H\r
5821opcode_CB_24:\r
5822 opSLAH z80hl\r
5823;@SLA L\r
5824opcode_CB_25:\r
5825 opSLAL z80hl\r
5826;@SLA (HL)\r
5827opcode_CB_26:\r
5828 readmem8HL\r
5829 opSLAb\r
5830 writemem8HL\r
5831 fetch 15\r
5832;@SLA A\r
5833opcode_CB_27:\r
5834 opSLAA\r
5835\r
5836;@SRA B\r
5837opcode_CB_28:\r
5838 opSRAH z80bc\r
5839;@SRA C\r
5840opcode_CB_29:\r
5841 opSRAL z80bc\r
5842;@SRA D\r
5843opcode_CB_2A:\r
5844 opSRAH z80de\r
5845;@SRA E\r
5846opcode_CB_2B:\r
5847 opSRAL z80de\r
5848;@SRA H\r
5849opcode_CB_2C:\r
5850 opSRAH z80hl\r
5851;@SRA L\r
5852opcode_CB_2D:\r
5853 opSRAL z80hl\r
5854;@SRA (HL)\r
5855opcode_CB_2E:\r
5856 readmem8HL\r
5857 opSRAb\r
5858 writemem8HL\r
5859 fetch 15\r
5860;@SRA A\r
5861opcode_CB_2F:\r
5862 opSRAA\r
5863\r
5864;@SLL B\r
5865opcode_CB_30:\r
5866 opSLLH z80bc\r
5867;@SLL C\r
5868opcode_CB_31:\r
5869 opSLLL z80bc\r
5870;@SLL D\r
5871opcode_CB_32:\r
5872 opSLLH z80de\r
5873;@SLL E\r
5874opcode_CB_33:\r
5875 opSLLL z80de\r
5876;@SLL H\r
5877opcode_CB_34:\r
5878 opSLLH z80hl\r
5879;@SLL L\r
5880opcode_CB_35:\r
5881 opSLLL z80hl\r
5882;@SLL (HL)\r
5883opcode_CB_36:\r
5884 readmem8HL\r
5885 opSLLb\r
5886 writemem8HL\r
5887 fetch 15\r
5888;@SLL A\r
5889opcode_CB_37:\r
5890 opSLLA\r
5891\r
5892;@SRL B\r
5893opcode_CB_38:\r
5894 opSRLH z80bc\r
5895;@SRL C\r
5896opcode_CB_39:\r
5897 opSRLL z80bc\r
5898;@SRL D\r
5899opcode_CB_3A:\r
5900 opSRLH z80de\r
5901;@SRL E\r
5902opcode_CB_3B:\r
5903 opSRLL z80de\r
5904;@SRL H\r
5905opcode_CB_3C:\r
5906 opSRLH z80hl\r
5907;@SRL L\r
5908opcode_CB_3D:\r
5909 opSRLL z80hl\r
5910;@SRL (HL)\r
5911opcode_CB_3E:\r
5912 readmem8HL\r
5913 opSRLb\r
5914 writemem8HL\r
5915 fetch 15\r
5916;@SRL A\r
5917opcode_CB_3F:\r
5918 opSRLA\r
5919\r
5920\r
5921;@BIT 0,B\r
5922opcode_CB_40:\r
5923 opBITH z80bc 0\r
5924;@BIT 0,C\r
5925opcode_CB_41:\r
5926 opBITL z80bc 0\r
5927;@BIT 0,D\r
5928opcode_CB_42:\r
5929 opBITH z80de 0\r
5930;@BIT 0,E\r
5931opcode_CB_43:\r
5932 opBITL z80de 0\r
5933;@BIT 0,H\r
5934opcode_CB_44:\r
5935 opBITH z80hl 0\r
5936;@BIT 0,L\r
5937opcode_CB_45:\r
5938 opBITL z80hl 0\r
5939;@BIT 0,(HL)\r
5940opcode_CB_46:\r
5941 readmem8HL\r
5942 opBITb 0\r
5943 fetch 12\r
5944;@BIT 0,A\r
5945opcode_CB_47:\r
5946 opBITH z80a 0\r
5947\r
5948;@BIT 1,B\r
5949opcode_CB_48:\r
5950 opBITH z80bc 1\r
5951;@BIT 1,C\r
5952opcode_CB_49:\r
5953 opBITL z80bc 1\r
5954;@BIT 1,D\r
5955opcode_CB_4A:\r
5956 opBITH z80de 1\r
5957;@BIT 1,E\r
5958opcode_CB_4B:\r
5959 opBITL z80de 1\r
5960;@BIT 1,H\r
5961opcode_CB_4C:\r
5962 opBITH z80hl 1\r
5963;@BIT 1,L\r
5964opcode_CB_4D:\r
5965 opBITL z80hl 1\r
5966;@BIT 1,(HL)\r
5967opcode_CB_4E:\r
5968 readmem8HL\r
5969 opBITb 1\r
5970 fetch 12\r
5971;@BIT 1,A\r
5972opcode_CB_4F:\r
5973 opBITH z80a 1\r
5974\r
5975;@BIT 2,B\r
5976opcode_CB_50:\r
5977 opBITH z80bc 2\r
5978;@BIT 2,C\r
5979opcode_CB_51:\r
5980 opBITL z80bc 2\r
5981;@BIT 2,D\r
5982opcode_CB_52:\r
5983 opBITH z80de 2\r
5984;@BIT 2,E\r
5985opcode_CB_53:\r
5986 opBITL z80de 2\r
5987;@BIT 2,H\r
5988opcode_CB_54:\r
5989 opBITH z80hl 2\r
5990;@BIT 2,L\r
5991opcode_CB_55:\r
5992 opBITL z80hl 2\r
5993;@BIT 2,(HL)\r
5994opcode_CB_56:\r
5995 readmem8HL\r
5996 opBITb 2\r
5997 fetch 12\r
5998;@BIT 2,A\r
5999opcode_CB_57:\r
6000 opBITH z80a 2\r
6001\r
6002;@BIT 3,B\r
6003opcode_CB_58:\r
6004 opBITH z80bc 3\r
6005;@BIT 3,C\r
6006opcode_CB_59:\r
6007 opBITL z80bc 3\r
6008;@BIT 3,D\r
6009opcode_CB_5A:\r
6010 opBITH z80de 3\r
6011;@BIT 3,E\r
6012opcode_CB_5B:\r
6013 opBITL z80de 3\r
6014;@BIT 3,H\r
6015opcode_CB_5C:\r
6016 opBITH z80hl 3\r
6017;@BIT 3,L\r
6018opcode_CB_5D:\r
6019 opBITL z80hl 3\r
6020;@BIT 3,(HL)\r
6021opcode_CB_5E:\r
6022 readmem8HL\r
6023 opBITb 3\r
6024 fetch 12\r
6025;@BIT 3,A\r
6026opcode_CB_5F:\r
6027 opBITH z80a 3\r
6028\r
6029;@BIT 4,B\r
6030opcode_CB_60:\r
6031 opBITH z80bc 4\r
6032;@BIT 4,C\r
6033opcode_CB_61:\r
6034 opBITL z80bc 4\r
6035;@BIT 4,D\r
6036opcode_CB_62:\r
6037 opBITH z80de 4\r
6038;@BIT 4,E\r
6039opcode_CB_63:\r
6040 opBITL z80de 4\r
6041;@BIT 4,H\r
6042opcode_CB_64:\r
6043 opBITH z80hl 4\r
6044;@BIT 4,L\r
6045opcode_CB_65:\r
6046 opBITL z80hl 4\r
6047;@BIT 4,(HL)\r
6048opcode_CB_66:\r
6049 readmem8HL\r
6050 opBITb 4\r
6051 fetch 12\r
6052;@BIT 4,A\r
6053opcode_CB_67:\r
6054 opBITH z80a 4\r
6055\r
6056;@BIT 5,B\r
6057opcode_CB_68:\r
6058 opBITH z80bc 5\r
6059;@BIT 5,C\r
6060opcode_CB_69:\r
6061 opBITL z80bc 5\r
6062;@BIT 5,D\r
6063opcode_CB_6A:\r
6064 opBITH z80de 5\r
6065;@BIT 5,E\r
6066opcode_CB_6B:\r
6067 opBITL z80de 5\r
6068;@BIT 5,H\r
6069opcode_CB_6C:\r
6070 opBITH z80hl 5\r
6071;@BIT 5,L\r
6072opcode_CB_6D:\r
6073 opBITL z80hl 5\r
6074;@BIT 5,(HL)\r
6075opcode_CB_6E:\r
6076 readmem8HL\r
6077 opBITb 5\r
6078 fetch 12\r
6079;@BIT 5,A\r
6080opcode_CB_6F:\r
6081 opBITH z80a 5\r
6082\r
6083;@BIT 6,B\r
6084opcode_CB_70:\r
6085 opBITH z80bc 6\r
6086;@BIT 6,C\r
6087opcode_CB_71:\r
6088 opBITL z80bc 6\r
6089;@BIT 6,D\r
6090opcode_CB_72:\r
6091 opBITH z80de 6\r
6092;@BIT 6,E\r
6093opcode_CB_73:\r
6094 opBITL z80de 6\r
6095;@BIT 6,H\r
6096opcode_CB_74:\r
6097 opBITH z80hl 6\r
6098;@BIT 6,L\r
6099opcode_CB_75:\r
6100 opBITL z80hl 6\r
6101;@BIT 6,(HL)\r
6102opcode_CB_76:\r
6103 readmem8HL\r
6104 opBITb 6\r
6105 fetch 12\r
6106;@BIT 6,A\r
6107opcode_CB_77:\r
6108 opBITH z80a 6\r
6109\r
6110;@BIT 7,B\r
6111opcode_CB_78:\r
6112 opBIT7H z80bc\r
6113;@BIT 7,C\r
6114opcode_CB_79:\r
6115 opBIT7L z80bc\r
6116;@BIT 7,D\r
6117opcode_CB_7A:\r
6118 opBIT7H z80de\r
6119;@BIT 7,E\r
6120opcode_CB_7B:\r
6121 opBIT7L z80de\r
6122;@BIT 7,H\r
6123opcode_CB_7C:\r
6124 opBIT7H z80hl\r
6125;@BIT 7,L\r
6126opcode_CB_7D:\r
6127 opBIT7L z80hl\r
6128;@BIT 7,(HL)\r
6129opcode_CB_7E:\r
6130 readmem8HL\r
6131 opBIT7b\r
6132 fetch 12\r
6133;@BIT 7,A\r
6134opcode_CB_7F:\r
6135 opBIT7H z80a\r
6136\r
6137;@RES 0,B\r
6138opcode_CB_80:\r
6139 bic z80bc,z80bc,#1<<24\r
6140 fetch 8\r
6141;@RES 0,C\r
6142opcode_CB_81:\r
6143 bic z80bc,z80bc,#1<<16\r
6144 fetch 8\r
6145;@RES 0,D\r
6146opcode_CB_82:\r
6147 bic z80de,z80de,#1<<24\r
6148 fetch 8\r
6149;@RES 0,E\r
6150opcode_CB_83:\r
6151 bic z80de,z80de,#1<<16\r
6152 fetch 8\r
6153;@RES 0,H\r
6154opcode_CB_84:\r
6155 bic z80hl,z80hl,#1<<24\r
6156 fetch 8\r
6157;@RES 0,L\r
6158opcode_CB_85:\r
6159 bic z80hl,z80hl,#1<<16\r
6160 fetch 8\r
6161;@RES 0,(HL)\r
6162opcode_CB_86:\r
6163 opRESmemHL 0\r
6164;@RES 0,A\r
6165opcode_CB_87:\r
6166 bic z80a,z80a,#1<<24\r
6167 fetch 8\r
6168\r
6169;@RES 1,B\r
6170opcode_CB_88:\r
6171 bic z80bc,z80bc,#1<<25\r
6172 fetch 8\r
6173;@RES 1,C\r
6174opcode_CB_89:\r
6175 bic z80bc,z80bc,#1<<17\r
6176 fetch 8\r
6177;@RES 1,D\r
6178opcode_CB_8A:\r
6179 bic z80de,z80de,#1<<25\r
6180 fetch 8\r
6181;@RES 1,E\r
6182opcode_CB_8B:\r
6183 bic z80de,z80de,#1<<17\r
6184 fetch 8\r
6185;@RES 1,H\r
6186opcode_CB_8C:\r
6187 bic z80hl,z80hl,#1<<25\r
6188 fetch 8\r
6189;@RES 1,L\r
6190opcode_CB_8D:\r
6191 bic z80hl,z80hl,#1<<17\r
6192 fetch 8\r
6193;@RES 1,(HL)\r
6194opcode_CB_8E:\r
6195 opRESmemHL 1\r
6196;@RES 1,A\r
6197opcode_CB_8F:\r
6198 bic z80a,z80a,#1<<25\r
6199 fetch 8\r
6200\r
6201;@RES 2,B\r
6202opcode_CB_90:\r
6203 bic z80bc,z80bc,#1<<26\r
6204 fetch 8\r
6205;@RES 2,C\r
6206opcode_CB_91:\r
6207 bic z80bc,z80bc,#1<<18\r
6208 fetch 8\r
6209;@RES 2,D\r
6210opcode_CB_92:\r
6211 bic z80de,z80de,#1<<26\r
6212 fetch 8\r
6213;@RES 2,E\r
6214opcode_CB_93:\r
6215 bic z80de,z80de,#1<<18\r
6216 fetch 8\r
6217;@RES 2,H\r
6218opcode_CB_94:\r
6219 bic z80hl,z80hl,#1<<26\r
6220 fetch 8\r
6221;@RES 2,L\r
6222opcode_CB_95:\r
6223 bic z80hl,z80hl,#1<<18\r
6224 fetch 8\r
6225;@RES 2,(HL)\r
6226opcode_CB_96:\r
6227 opRESmemHL 2\r
6228;@RES 2,A\r
6229opcode_CB_97:\r
6230 bic z80a,z80a,#1<<26\r
6231 fetch 8\r
6232\r
6233;@RES 3,B\r
6234opcode_CB_98:\r
6235 bic z80bc,z80bc,#1<<27\r
6236 fetch 8\r
6237;@RES 3,C\r
6238opcode_CB_99:\r
6239 bic z80bc,z80bc,#1<<19\r
6240 fetch 8\r
6241;@RES 3,D\r
6242opcode_CB_9A:\r
6243 bic z80de,z80de,#1<<27\r
6244 fetch 8\r
6245;@RES 3,E\r
6246opcode_CB_9B:\r
6247 bic z80de,z80de,#1<<19\r
6248 fetch 8\r
6249;@RES 3,H\r
6250opcode_CB_9C:\r
6251 bic z80hl,z80hl,#1<<27\r
6252 fetch 8\r
6253;@RES 3,L\r
6254opcode_CB_9D:\r
6255 bic z80hl,z80hl,#1<<19\r
6256 fetch 8\r
6257;@RES 3,(HL)\r
6258opcode_CB_9E:\r
6259 opRESmemHL 3\r
6260;@RES 3,A\r
6261opcode_CB_9F:\r
6262 bic z80a,z80a,#1<<27\r
6263 fetch 8\r
6264\r
6265;@RES 4,B\r
6266opcode_CB_A0:\r
6267 bic z80bc,z80bc,#1<<28\r
6268 fetch 8\r
6269;@RES 4,C\r
6270opcode_CB_A1:\r
6271 bic z80bc,z80bc,#1<<20\r
6272 fetch 8\r
6273;@RES 4,D\r
6274opcode_CB_A2:\r
6275 bic z80de,z80de,#1<<28\r
6276 fetch 8\r
6277;@RES 4,E\r
6278opcode_CB_A3:\r
6279 bic z80de,z80de,#1<<20\r
6280 fetch 8\r
6281;@RES 4,H\r
6282opcode_CB_A4:\r
6283 bic z80hl,z80hl,#1<<28\r
6284 fetch 8\r
6285;@RES 4,L\r
6286opcode_CB_A5:\r
6287 bic z80hl,z80hl,#1<<20\r
6288 fetch 8\r
6289;@RES 4,(HL)\r
6290opcode_CB_A6:\r
6291 opRESmemHL 4\r
6292;@RES 4,A\r
6293opcode_CB_A7:\r
6294 bic z80a,z80a,#1<<28\r
6295 fetch 8\r
6296\r
6297;@RES 5,B\r
6298opcode_CB_A8:\r
6299 bic z80bc,z80bc,#1<<29\r
6300 fetch 8\r
6301;@RES 5,C\r
6302opcode_CB_A9:\r
6303 bic z80bc,z80bc,#1<<21\r
6304 fetch 8\r
6305;@RES 5,D\r
6306opcode_CB_AA:\r
6307 bic z80de,z80de,#1<<29\r
6308 fetch 8\r
6309;@RES 5,E\r
6310opcode_CB_AB:\r
6311 bic z80de,z80de,#1<<21\r
6312 fetch 8\r
6313;@RES 5,H\r
6314opcode_CB_AC:\r
6315 bic z80hl,z80hl,#1<<29\r
6316 fetch 8\r
6317;@RES 5,L\r
6318opcode_CB_AD:\r
6319 bic z80hl,z80hl,#1<<21\r
6320 fetch 8\r
6321;@RES 5,(HL)\r
6322opcode_CB_AE:\r
6323 opRESmemHL 5\r
6324;@RES 5,A\r
6325opcode_CB_AF:\r
6326 bic z80a,z80a,#1<<29\r
6327 fetch 8\r
6328\r
6329;@RES 6,B\r
6330opcode_CB_B0:\r
6331 bic z80bc,z80bc,#1<<30\r
6332 fetch 8\r
6333;@RES 6,C\r
6334opcode_CB_B1:\r
6335 bic z80bc,z80bc,#1<<22\r
6336 fetch 8\r
6337;@RES 6,D\r
6338opcode_CB_B2:\r
6339 bic z80de,z80de,#1<<30\r
6340 fetch 8\r
6341;@RES 6,E\r
6342opcode_CB_B3:\r
6343 bic z80de,z80de,#1<<22\r
6344 fetch 8\r
6345;@RES 6,H\r
6346opcode_CB_B4:\r
6347 bic z80hl,z80hl,#1<<30\r
6348 fetch 8\r
6349;@RES 6,L\r
6350opcode_CB_B5:\r
6351 bic z80hl,z80hl,#1<<22\r
6352 fetch 8\r
6353;@RES 6,(HL)\r
6354opcode_CB_B6:\r
6355 opRESmemHL 6\r
6356;@RES 6,A\r
6357opcode_CB_B7:\r
6358 bic z80a,z80a,#1<<30\r
6359 fetch 8\r
6360\r
6361;@RES 7,B\r
6362opcode_CB_B8:\r
6363 bic z80bc,z80bc,#1<<31\r
6364 fetch 8\r
6365;@RES 7,C\r
6366opcode_CB_B9:\r
6367 bic z80bc,z80bc,#1<<23\r
6368 fetch 8\r
6369;@RES 7,D\r
6370opcode_CB_BA:\r
6371 bic z80de,z80de,#1<<31\r
6372 fetch 8\r
6373;@RES 7,E\r
6374opcode_CB_BB:\r
6375 bic z80de,z80de,#1<<23\r
6376 fetch 8\r
6377;@RES 7,H\r
6378opcode_CB_BC:\r
6379 bic z80hl,z80hl,#1<<31\r
6380 fetch 8\r
6381;@RES 7,L\r
6382opcode_CB_BD:\r
6383 bic z80hl,z80hl,#1<<23\r
6384 fetch 8\r
6385;@RES 7,(HL)\r
6386opcode_CB_BE:\r
6387 opRESmemHL 7\r
6388;@RES 7,A\r
6389opcode_CB_BF:\r
6390 bic z80a,z80a,#1<<31\r
6391 fetch 8\r
6392\r
6393;@SET 0,B\r
6394opcode_CB_C0:\r
6395 orr z80bc,z80bc,#1<<24\r
6396 fetch 8\r
6397;@SET 0,C\r
6398opcode_CB_C1:\r
6399 orr z80bc,z80bc,#1<<16\r
6400 fetch 8\r
6401;@SET 0,D\r
6402opcode_CB_C2:\r
6403 orr z80de,z80de,#1<<24\r
6404 fetch 8\r
6405;@SET 0,E\r
6406opcode_CB_C3:\r
6407 orr z80de,z80de,#1<<16\r
6408 fetch 8\r
6409;@SET 0,H\r
6410opcode_CB_C4:\r
6411 orr z80hl,z80hl,#1<<24\r
6412 fetch 8\r
6413;@SET 0,L\r
6414opcode_CB_C5:\r
6415 orr z80hl,z80hl,#1<<16\r
6416 fetch 8\r
6417;@SET 0,(HL)\r
6418opcode_CB_C6:\r
6419 opSETmemHL 0\r
6420;@SET 0,A\r
6421opcode_CB_C7:\r
6422 orr z80a,z80a,#1<<24\r
6423 fetch 8\r
6424\r
6425;@SET 1,B\r
6426opcode_CB_C8:\r
6427 orr z80bc,z80bc,#1<<25\r
6428 fetch 8\r
6429;@SET 1,C\r
6430opcode_CB_C9:\r
6431 orr z80bc,z80bc,#1<<17\r
6432 fetch 8\r
6433;@SET 1,D\r
6434opcode_CB_CA:\r
6435 orr z80de,z80de,#1<<25\r
6436 fetch 8\r
6437;@SET 1,E\r
6438opcode_CB_CB:\r
6439 orr z80de,z80de,#1<<17\r
6440 fetch 8\r
6441;@SET 1,H\r
6442opcode_CB_CC:\r
6443 orr z80hl,z80hl,#1<<25\r
6444 fetch 8\r
6445;@SET 1,L\r
6446opcode_CB_CD:\r
6447 orr z80hl,z80hl,#1<<17\r
6448 fetch 8\r
6449;@SET 1,(HL)\r
6450opcode_CB_CE:\r
6451 opSETmemHL 1\r
6452;@SET 1,A\r
6453opcode_CB_CF:\r
6454 orr z80a,z80a,#1<<25\r
6455 fetch 8\r
6456\r
6457;@SET 2,B\r
6458opcode_CB_D0:\r
6459 orr z80bc,z80bc,#1<<26\r
6460 fetch 8\r
6461;@SET 2,C\r
6462opcode_CB_D1:\r
6463 orr z80bc,z80bc,#1<<18\r
6464 fetch 8\r
6465;@SET 2,D\r
6466opcode_CB_D2:\r
6467 orr z80de,z80de,#1<<26\r
6468 fetch 8\r
6469;@SET 2,E\r
6470opcode_CB_D3:\r
6471 orr z80de,z80de,#1<<18\r
6472 fetch 8\r
6473;@SET 2,H\r
6474opcode_CB_D4:\r
6475 orr z80hl,z80hl,#1<<26\r
6476 fetch 8\r
6477;@SET 2,L\r
6478opcode_CB_D5:\r
6479 orr z80hl,z80hl,#1<<18\r
6480 fetch 8\r
6481;@SET 2,(HL)\r
6482opcode_CB_D6:\r
6483 opSETmemHL 2\r
6484;@SET 2,A\r
6485opcode_CB_D7:\r
6486 orr z80a,z80a,#1<<26\r
6487 fetch 8\r
6488\r
6489;@SET 3,B\r
6490opcode_CB_D8:\r
6491 orr z80bc,z80bc,#1<<27\r
6492 fetch 8\r
6493;@SET 3,C\r
6494opcode_CB_D9:\r
6495 orr z80bc,z80bc,#1<<19\r
6496 fetch 8\r
6497;@SET 3,D\r
6498opcode_CB_DA:\r
6499 orr z80de,z80de,#1<<27\r
6500 fetch 8\r
6501;@SET 3,E\r
6502opcode_CB_DB:\r
6503 orr z80de,z80de,#1<<19\r
6504 fetch 8\r
6505;@SET 3,H\r
6506opcode_CB_DC:\r
6507 orr z80hl,z80hl,#1<<27\r
6508 fetch 8\r
6509;@SET 3,L\r
6510opcode_CB_DD:\r
6511 orr z80hl,z80hl,#1<<19\r
6512 fetch 8\r
6513;@SET 3,(HL)\r
6514opcode_CB_DE:\r
6515 opSETmemHL 3\r
6516;@SET 3,A\r
6517opcode_CB_DF:\r
6518 orr z80a,z80a,#1<<27\r
6519 fetch 8\r
6520\r
6521;@SET 4,B\r
6522opcode_CB_E0:\r
6523 orr z80bc,z80bc,#1<<28\r
6524 fetch 8\r
6525;@SET 4,C\r
6526opcode_CB_E1:\r
6527 orr z80bc,z80bc,#1<<20\r
6528 fetch 8\r
6529;@SET 4,D\r
6530opcode_CB_E2:\r
6531 orr z80de,z80de,#1<<28\r
6532 fetch 8\r
6533;@SET 4,E\r
6534opcode_CB_E3:\r
6535 orr z80de,z80de,#1<<20\r
6536 fetch 8\r
6537;@SET 4,H\r
6538opcode_CB_E4:\r
6539 orr z80hl,z80hl,#1<<28\r
6540 fetch 8\r
6541;@SET 4,L\r
6542opcode_CB_E5:\r
6543 orr z80hl,z80hl,#1<<20\r
6544 fetch 8\r
6545;@SET 4,(HL)\r
6546opcode_CB_E6:\r
6547 opSETmemHL 4\r
6548;@SET 4,A\r
6549opcode_CB_E7:\r
6550 orr z80a,z80a,#1<<28\r
6551 fetch 8\r
6552\r
6553;@SET 5,B\r
6554opcode_CB_E8:\r
6555 orr z80bc,z80bc,#1<<29\r
6556 fetch 8\r
6557;@SET 5,C\r
6558opcode_CB_E9:\r
6559 orr z80bc,z80bc,#1<<21\r
6560 fetch 8\r
6561;@SET 5,D\r
6562opcode_CB_EA:\r
6563 orr z80de,z80de,#1<<29\r
6564 fetch 8\r
6565;@SET 5,E\r
6566opcode_CB_EB:\r
6567 orr z80de,z80de,#1<<21\r
6568 fetch 8\r
6569;@SET 5,H\r
6570opcode_CB_EC:\r
6571 orr z80hl,z80hl,#1<<29\r
6572 fetch 8\r
6573;@SET 5,L\r
6574opcode_CB_ED:\r
6575 orr z80hl,z80hl,#1<<21\r
6576 fetch 8\r
6577;@SET 5,(HL)\r
6578opcode_CB_EE:\r
6579 opSETmemHL 5\r
6580;@SET 5,A\r
6581opcode_CB_EF:\r
6582 orr z80a,z80a,#1<<29\r
6583 fetch 8\r
6584\r
6585;@SET 6,B\r
6586opcode_CB_F0:\r
6587 orr z80bc,z80bc,#1<<30\r
6588 fetch 8\r
6589;@SET 6,C\r
6590opcode_CB_F1:\r
6591 orr z80bc,z80bc,#1<<22\r
6592 fetch 8\r
6593;@SET 6,D\r
6594opcode_CB_F2:\r
6595 orr z80de,z80de,#1<<30\r
6596 fetch 8\r
6597;@SET 6,E\r
6598opcode_CB_F3:\r
6599 orr z80de,z80de,#1<<22\r
6600 fetch 8\r
6601;@SET 6,H\r
6602opcode_CB_F4:\r
6603 orr z80hl,z80hl,#1<<30\r
6604 fetch 8\r
6605;@SET 6,L\r
6606opcode_CB_F5:\r
6607 orr z80hl,z80hl,#1<<22\r
6608 fetch 8\r
6609;@SET 6,(HL)\r
6610opcode_CB_F6:\r
6611 opSETmemHL 6\r
6612;@SET 6,A\r
6613opcode_CB_F7:\r
6614 orr z80a,z80a,#1<<30\r
6615 fetch 8\r
6616\r
6617;@SET 7,B\r
6618opcode_CB_F8:\r
6619 orr z80bc,z80bc,#1<<31\r
6620 fetch 8\r
6621;@SET 7,C\r
6622opcode_CB_F9:\r
6623 orr z80bc,z80bc,#1<<23\r
6624 fetch 8\r
6625;@SET 7,D\r
6626opcode_CB_FA:\r
6627 orr z80de,z80de,#1<<31\r
6628 fetch 8\r
6629;@SET 7,E\r
6630opcode_CB_FB:\r
6631 orr z80de,z80de,#1<<23\r
6632 fetch 8\r
6633;@SET 7,H\r
6634opcode_CB_FC:\r
6635 orr z80hl,z80hl,#1<<31\r
6636 fetch 8\r
6637;@SET 7,L\r
6638opcode_CB_FD:\r
6639 orr z80hl,z80hl,#1<<23\r
6640 fetch 8\r
6641;@SET 7,(HL)\r
6642opcode_CB_FE:\r
6643 opSETmemHL 7\r
6644;@SET 7,A\r
6645opcode_CB_FF:\r
6646 orr z80a,z80a,#1<<31\r
6647 fetch 8\r
6648\r
6649\r
6650\r
6651;@##################################\r
6652;@##################################\r
6653;@### opcodes DD #########################\r
6654;@##################################\r
6655;@##################################\r
6656;@Because the DD opcodes are not a complete range from 00-FF I have\r
6657;@created this sub routine that will catch any undocumented ops\r
6658;@halt the emulator and mov the current instruction to r0\r
6659;@at a later stage I may change to display a text message on the screen\r
6660opcode_DD_NF:\r
6661 eatcycles 4\r
6662 ldr pc,[opcodes,r0, lsl #2]\r
6663;@ mov r2,#0x10*4\r
6664;@ cmp r2,z80xx\r
6665;@ bne opcode_FD_NF\r
6666;@ mov r0,#0xDD00\r
6667;@ orr r0,r0,r1\r
6668;@ b end_loop\r
6669;@opcode_FD_NF:\r
6670;@ mov r0,#0xFD00\r
6671;@ orr r0,r0,r1\r
6672;@ b end_loop\r
6673opcode_DD_NF2:\r
6674 mov r0,#0xDD0000\r
6675 orr r0,r0,#0xCB00\r
6676 orr r0,r0,r1\r
6677 b end_loop\r
6678\r
6679;@ADD IX,BC\r
6680opcode_DD_09:\r
6681 ldr r0,[z80xx]\r
6682 opADD16 r0 z80bc\r
6683 str r0,[z80xx]\r
6684 fetch 15\r
6685;@ADD IX,DE\r
6686opcode_DD_19:\r
6687 ldr r0,[z80xx]\r
6688 opADD16 r0 z80de\r
6689 str r0,[z80xx]\r
6690 fetch 15\r
6691;@LD IX,NN\r
6692opcode_DD_21:\r
6693 ldrb r0,[z80pc],#1\r
6694 ldrb r1,[z80pc],#1\r
6695 orr r0,r0,r1, lsl #8\r
6696 strh r0,[z80xx,#2]\r
6697 fetch 14\r
6698;@LD (NN),IX\r
6699opcode_DD_22:\r
6700 ldrb r0,[z80pc],#1\r
6701 ldrb r1,[z80pc],#1\r
6702 orr r1,r0,r1, lsl #8\r
6703 ldrh r0,[z80xx,#2]\r
6704 writemem16\r
6705 fetch 20\r
6706;@INC IX\r
6707opcode_DD_23:\r
6708 ldr r0,[z80xx]\r
6709 add r0,r0,#1<<16\r
6710 str r0,[z80xx]\r
6711 fetch 10\r
6712;@INC I (IX)\r
6713opcode_DD_24:\r
6714 ldr r0,[z80xx]\r
6715 opINC8H r0\r
6716 str r0,[z80xx]\r
6717 fetch 8\r
6718;@DEC I (IX)\r
6719opcode_DD_25:\r
6720 ldr r0,[z80xx]\r
6721 opDEC8H r0\r
6722 str r0,[z80xx]\r
6723 fetch 8\r
6724;@LD I,N (IX)\r
6725opcode_DD_26:\r
6726 ldrb r0,[z80pc],#1\r
6727 strb r0,[z80xx,#3]\r
6728 fetch 11\r
6729;@ADD IX,IX\r
6730opcode_DD_29:\r
6731 ldr r0,[z80xx]\r
6732 opADD16_2 r0\r
6733 str r0,[z80xx]\r
6734 fetch 15\r
6735;@LD IX,(NN)\r
6736opcode_DD_2A:\r
6737 ldrb r0,[z80pc],#1\r
6738 ldrb r1,[z80pc],#1\r
6739 orr r0,r0,r1, lsl #8\r
6740 stmfd sp!,{z80xx}\r
6741 readmem16\r
6742 ldmfd sp!,{z80xx}\r
6743 strh r0,[z80xx,#2]\r
6744 fetch 20\r
6745;@DEC IX\r
6746opcode_DD_2B:\r
6747 ldr r0,[z80xx]\r
6748 sub r0,r0,#1<<16\r
6749 str r0,[z80xx]\r
6750 fetch 10\r
6751;@INC X (IX)\r
6752opcode_DD_2C:\r
6753 ldr r0,[z80xx]\r
6754 opINC8L r0\r
6755 str r0,[z80xx]\r
6756 fetch 8\r
6757;@DEC X (IX)\r
6758opcode_DD_2D:\r
6759 ldr r0,[z80xx]\r
6760 opDEC8L r0\r
6761 str r0,[z80xx]\r
6762 fetch 8\r
6763;@LD X,N (IX)\r
6764opcode_DD_2E:\r
6765 ldrb r0,[z80pc],#1\r
6766 strb r0,[z80xx,#2]\r
6767 fetch 11\r
6768;@INC (IX+N)\r
6769opcode_DD_34:\r
6770 ldrsb r0,[z80pc],#1\r
6771 ldr r1,[z80xx]\r
6772 add r0,r0,r1, lsr #16\r
6773 stmfd sp!,{r0} ;@ save addr\r
6774 readmem8\r
6775 opINC8b\r
6776 ldmfd sp!,{r1} ;@ restore addr into r1\r
6777 writemem8\r
6778 fetch 23\r
6779;@DEC (IX+N)\r
6780opcode_DD_35:\r
6781 ldrsb r0,[z80pc],#1\r
6782 ldr r1,[z80xx]\r
6783 add r0,r0,r1, lsr #16\r
6784 stmfd sp!,{r0} ;@ save addr\r
6785 readmem8\r
6786 opDEC8b\r
6787 ldmfd sp!,{r1} ;@ restore addr into r1\r
6788 writemem8\r
6789 fetch 23\r
6790;@LD (IX+N),N\r
6791opcode_DD_36:\r
6792 ldrsb r2,[z80pc],#1\r
6793 ldrb r0,[z80pc],#1\r
6794 ldr r1,[z80xx]\r
6795 add r1,r2,r1, lsr #16\r
6796 writemem8\r
6797 fetch 19\r
6798;@ADD IX,SP\r
6799opcode_DD_39:\r
6800 ldr r0,[z80xx]\r
6801.if FAST_Z80SP\r
6802 ldr r2,[cpucontext,#z80sp_base]\r
6803 sub r2,z80sp,r2\r
6804 opADD16s r0 r2 16\r
6805.else\r
6806 opADD16s r0 z80sp 16\r
6807.endif\r
6808 str r0,[z80xx]\r
6809 fetch 15\r
6810;@LD B,I ( IX )\r
6811opcode_DD_44:\r
6812 ldrb r0,[z80xx,#3]\r
6813 and z80bc,z80bc,#0xFF<<16\r
6814 orr z80bc,z80bc,r0, lsl #24\r
6815 fetch 8\r
6816;@LD B,X ( IX )\r
6817opcode_DD_45:\r
6818 ldrb r0,[z80xx,#2]\r
6819 and z80bc,z80bc,#0xFF<<16\r
6820 orr z80bc,z80bc,r0, lsl #24\r
6821 fetch 8\r
6822;@LD B,(IX,N)\r
6823opcode_DD_46:\r
6824 ldrsb r0,[z80pc],#1\r
6825 ldr r1,[z80xx]\r
6826 add r0,r0,r1, lsr #16\r
6827 readmem8\r
6828 and z80bc,z80bc,#0xFF<<16\r
6829 orr z80bc,z80bc,r0, lsl #24\r
6830 fetch 19\r
6831;@LD C,I (IX)\r
6832opcode_DD_4C:\r
6833 ldrb r0,[z80xx,#3]\r
6834 and z80bc,z80bc,#0xFF<<24\r
6835 orr z80bc,z80bc,r0, lsl #16\r
6836 fetch 8\r
6837;@LD C,X (IX)\r
6838opcode_DD_4D:\r
6839 ldrb r0,[z80xx,#2]\r
6840 and z80bc,z80bc,#0xFF<<24\r
6841 orr z80bc,z80bc,r0, lsl #16\r
6842 fetch 8\r
6843;@LD C,(IX,N)\r
6844opcode_DD_4E:\r
6845 ldrsb r0,[z80pc],#1\r
6846 ldr r1,[z80xx]\r
6847 add r0,r0,r1, lsr #16\r
6848 readmem8\r
6849 and z80bc,z80bc,#0xFF<<24\r
6850 orr z80bc,z80bc,r0, lsl #16\r
6851 fetch 19\r
6852\r
6853;@LD D,I (IX)\r
6854opcode_DD_54:\r
6855 ldrb r0,[z80xx,#3]\r
6856 and z80de,z80de,#0xFF<<16\r
6857 orr z80de,z80de,r0, lsl #24\r
6858 fetch 8\r
6859;@LD D,X (IX)\r
6860opcode_DD_55:\r
6861 ldrb r0,[z80xx,#2]\r
6862 and z80de,z80de,#0xFF<<16\r
6863 orr z80de,z80de,r0, lsl #24\r
6864 fetch 8\r
6865;@LD D,(IX,N)\r
6866opcode_DD_56:\r
6867 ldrsb r0,[z80pc],#1\r
6868 ldr r1,[z80xx]\r
6869 add r0,r0,r1, lsr #16\r
6870 readmem8\r
6871 and z80de,z80de,#0xFF<<16\r
6872 orr z80de,z80de,r0, lsl #24\r
6873 fetch 19\r
6874;@LD E,I (IX)\r
6875opcode_DD_5C:\r
6876 ldrb r0,[z80xx,#3]\r
6877 and z80de,z80de,#0xFF<<24\r
6878 orr z80de,z80de,r0, lsl #16\r
6879 fetch 8\r
6880;@LD E,X (IX)\r
6881opcode_DD_5D:\r
6882 ldrb r0,[z80xx,#2]\r
6883 and z80de,z80de,#0xFF<<24\r
6884 orr z80de,z80de,r0, lsl #16\r
6885 fetch 8\r
6886;@LD E,(IX,N)\r
6887opcode_DD_5E:\r
6888 ldrsb r0,[z80pc],#1\r
6889 ldr r1,[z80xx]\r
6890 add r0,r0,r1, lsr #16\r
6891 readmem8\r
6892 and z80de,z80de,#0xFF<<24\r
6893 orr z80de,z80de,r0, lsl #16\r
6894 fetch 19\r
6895;@LD I,B (IX)\r
6896opcode_DD_60:\r
6897 mov r0,z80bc,lsr#24\r
6898 strb r0,[z80xx,#3]\r
6899 fetch 8\r
6900;@LD I,C (IX)\r
6901opcode_DD_61:\r
6902 mov r0,z80bc,lsr#16\r
6903 strb r0,[z80xx,#3]\r
6904 fetch 8\r
6905;@LD I,D (IX)\r
6906opcode_DD_62:\r
6907 mov r0,z80de,lsr#24\r
6908 strb r0,[z80xx,#3]\r
6909 fetch 8\r
6910;@LD I,E (IX)\r
6911opcode_DD_63:\r
6912 mov r0,z80de,lsr#16\r
6913 strb r0,[z80xx,#3]\r
6914 fetch 8\r
6915;@LD I,I (IX)\r
6916opcode_DD_64:\r
6917 fetch 8\r
6918;@LD I,X (IX)\r
6919opcode_DD_65:\r
6920 ldrb r0,[z80xx,#2]\r
6921 strb r0,[z80xx,#3]\r
6922 fetch 8\r
6923;@LD H,(IX,N)\r
6924opcode_DD_66:\r
6925 ldrsb r0,[z80pc],#1\r
6926 ldr r1,[z80xx]\r
6927 add r0,r0,r1, lsr #16\r
6928 readmem8\r
6929 and z80hl,z80hl,#0xFF<<16\r
6930 orr z80hl,z80hl,r0, lsl #24\r
6931 fetch 19\r
6932;@LD I,A (IX)\r
6933opcode_DD_67:\r
6934 mov r0,z80a,lsr#24\r
6935 strb r0,[z80xx,#3]\r
6936 fetch 8\r
6937;@LD X,B (IX)\r
6938opcode_DD_68:\r
6939 mov r0,z80bc,lsr#24\r
6940 strb r0,[z80xx,#2]\r
6941 fetch 8\r
6942;@LD X,C (IX)\r
6943opcode_DD_69:\r
6944 mov r0,z80bc,lsr#16\r
6945 strb r0,[z80xx,#2]\r
6946 fetch 8\r
6947;@LD X,D (IX)\r
6948opcode_DD_6A:\r
6949 mov r0,z80de,lsr#24\r
6950 strb r0,[z80xx,#2]\r
6951 fetch 8\r
6952;@LD X,E (IX)\r
6953opcode_DD_6B:\r
6954 mov r0,z80de,lsr#16\r
6955 strb r0,[z80xx,#2]\r
6956 fetch 8\r
6957;@LD X,I (IX)\r
6958opcode_DD_6C:\r
6959 ldrb r0,[z80xx,#3]\r
6960 strb r0,[z80xx,#2]\r
6961 fetch 8\r
6962;@LD X,X (IX)\r
6963opcode_DD_6D:\r
6964 fetch 8\r
6965;@LD L,(IX,N)\r
6966opcode_DD_6E:\r
6967 ldrsb r0,[z80pc],#1\r
6968 ldr r1,[z80xx]\r
6969 add r0,r0,r1, lsr #16\r
6970 readmem8\r
6971 and z80hl,z80hl,#0xFF<<24\r
6972 orr z80hl,z80hl,r0, lsl #16\r
6973 fetch 19\r
6974;@LD X,A (IX)\r
6975opcode_DD_6F:\r
6976 mov r0,z80a,lsr#24\r
6977 strb r0,[z80xx,#2]\r
6978 fetch 8\r
6979\r
6980;@LD (IX,N),B\r
6981opcode_DD_70:\r
6982 ldrsb r0,[z80pc],#1\r
6983 ldr r1,[z80xx]\r
6984 add r1,r0,r1, lsr #16\r
6985 mov r0,z80bc, lsr #24\r
6986 writemem8\r
6987 fetch 19\r
6988;@LD (IX,N),C\r
6989opcode_DD_71:\r
6990 ldrsb r0,[z80pc],#1\r
6991 ldr r1,[z80xx]\r
6992 add r1,r0,r1, lsr #16\r
6993 mov r0,z80bc, lsr #16\r
6994 and r0,r0,#0xFF\r
6995 writemem8\r
6996 fetch 19\r
6997;@LD (IX,N),D\r
6998opcode_DD_72:\r
6999 ldrsb r0,[z80pc],#1\r
7000 ldr r1,[z80xx]\r
7001 add r1,r0,r1, lsr #16\r
7002 mov r0,z80de, lsr #24\r
7003 writemem8\r
7004 fetch 19\r
7005;@LD (IX,N),E\r
7006opcode_DD_73:\r
7007 ldrsb r0,[z80pc],#1\r
7008 ldr r1,[z80xx]\r
7009 add r1,r0,r1, lsr #16\r
7010 mov r0,z80de, lsr #16\r
7011 and r0,r0,#0xFF\r
7012 writemem8\r
7013 fetch 19\r
7014;@LD (IX,N),H\r
7015opcode_DD_74:\r
7016 ldrsb r0,[z80pc],#1\r
7017 ldr r1,[z80xx]\r
7018 add r1,r0,r1, lsr #16\r
7019 mov r0,z80hl, lsr #24\r
7020 writemem8\r
7021 fetch 19\r
7022;@LD (IX,N),L\r
7023opcode_DD_75:\r
7024 ldrsb r0,[z80pc],#1\r
7025 ldr r1,[z80xx]\r
7026 add r1,r0,r1, lsr #16\r
7027 mov r0,z80hl, lsr #16\r
7028 and r0,r0,#0xFF\r
7029 writemem8\r
7030 fetch 19\r
7031;@LD (IX,N),A\r
7032opcode_DD_77:\r
7033 ldrsb r0,[z80pc],#1\r
7034 ldr r1,[z80xx]\r
7035 add r1,r0,r1, lsr #16\r
7036 mov r0,z80a, lsr #24\r
7037 writemem8\r
7038 fetch 19\r
7039\r
7040;@LD A,I from (IX)\r
7041opcode_DD_7C:\r
7042 ldrb r0,[z80xx,#3]\r
7043 mov z80a,r0, lsl #24\r
7044 fetch 8\r
7045;@LD A,X from (IX)\r
7046opcode_DD_7D:\r
7047 ldrb r0,[z80xx,#2]\r
7048 mov z80a,r0, lsl #24\r
7049 fetch 8\r
7050;@LD A,(IX,N)\r
7051opcode_DD_7E:\r
7052 ldrsb r0,[z80pc],#1\r
7053 ldr r1,[z80xx]\r
7054 add r0,r0,r1, lsr #16\r
7055 readmem8\r
7056 mov z80a,r0, lsl #24\r
7057 fetch 19\r
7058\r
7059;@ADD A,I ( IX)\r
7060opcode_DD_84:\r
7061 ldrb r0,[z80xx,#3]\r
7062 opADDb\r
7063 fetch 8\r
7064;@ADD A,X ( IX)\r
7065opcode_DD_85:\r
7066 ldrb r0,[z80xx,#2]\r
7067 opADDb\r
7068 fetch 8\r
7069;@ADD A,(IX+N)\r
7070opcode_DD_86:\r
7071 ldrsb r0,[z80pc],#1\r
7072 ldr r1,[z80xx]\r
7073 add r0,r0,r1, lsr #16\r
7074 readmem8\r
7075 opADDb\r
7076 fetch 19\r
7077\r
7078;@ADC A,I (IX)\r
7079opcode_DD_8C:\r
7080 ldrb r0,[z80xx,#3]\r
7081 opADCb\r
7082 fetch 8\r
7083;@ADC A,X (IX)\r
7084opcode_DD_8D:\r
7085 ldrb r0,[z80xx,#2]\r
7086 opADCb\r
7087 fetch 8\r
7088;@ADC A,(IX+N)\r
7089opcode_DD_8E:\r
7090 ldrsb r0,[z80pc],#1\r
7091 ldr r1,[z80xx]\r
7092 add r0,r0,r1, lsr #16\r
7093 readmem8\r
7094 opADCb\r
7095 fetch 19\r
7096\r
7097;@SUB A,I (IX)\r
7098opcode_DD_94:\r
7099 ldrb r0,[z80xx,#3]\r
7100 opSUBb\r
7101 fetch 8\r
7102;@SUB A,X (IX)\r
7103opcode_DD_95:\r
7104 ldrb r0,[z80xx,#2]\r
7105 opSUBb\r
7106 fetch 8\r
7107;@SUB A,(IX+N)\r
7108opcode_DD_96:\r
7109 ldrsb r0,[z80pc],#1\r
7110 ldr r1,[z80xx]\r
7111 add r0,r0,r1, lsr #16\r
7112 readmem8\r
7113 opSUBb\r
7114 fetch 19\r
7115\r
7116;@SBC A,I (IX)\r
7117opcode_DD_9C:\r
7118 ldrb r0,[z80xx,#3]\r
7119 opSBCb\r
7120 fetch 8\r
7121;@SBC A,X (IX)\r
7122opcode_DD_9D:\r
7123 ldrb r0,[z80xx,#2]\r
7124 opSBCb\r
7125 fetch 8\r
7126;@SBC A,(IX+N)\r
7127opcode_DD_9E:\r
7128 ldrsb r0,[z80pc],#1\r
7129 ldr r1,[z80xx]\r
7130 add r0,r0,r1, lsr #16\r
7131 readmem8\r
7132 opSBCb\r
7133 fetch 19\r
7134\r
7135;@AND I (IX)\r
7136opcode_DD_A4:\r
7137 ldrb r0,[z80xx,#3]\r
7138 opANDb\r
7139 fetch 8\r
7140;@AND X (IX)\r
7141opcode_DD_A5:\r
7142 ldrb r0,[z80xx,#2]\r
7143 opANDb\r
7144 fetch 8\r
7145;@AND (IX+N)\r
7146opcode_DD_A6:\r
7147 ldrsb r0,[z80pc],#1\r
7148 ldr r1,[z80xx]\r
7149 add r0,r0,r1, lsr #16\r
7150 readmem8\r
7151 opANDb\r
7152 fetch 19\r
7153\r
7154;@XOR I (IX)\r
7155opcode_DD_AC:\r
7156 ldrb r0,[z80xx,#3]\r
7157 opXORb\r
7158 fetch 8\r
7159;@XOR X (IX)\r
7160opcode_DD_AD:\r
7161 ldrb r0,[z80xx,#2]\r
7162 opXORb\r
7163 fetch 8\r
7164;@XOR (IX+N)\r
7165opcode_DD_AE:\r
7166 ldrsb r0,[z80pc],#1\r
7167 ldr r1,[z80xx]\r
7168 add r0,r0,r1, lsr #16\r
7169 readmem8\r
7170 opXORb\r
7171 fetch 19\r
7172\r
7173;@OR I (IX)\r
7174opcode_DD_B4:\r
7175 ldrb r0,[z80xx,#3]\r
7176 opORb\r
7177 fetch 8\r
7178;@OR X (IX)\r
7179opcode_DD_B5:\r
7180 ldrb r0,[z80xx,#2]\r
7181 opORb\r
7182 fetch 8\r
7183;@OR (IX+N)\r
7184opcode_DD_B6:\r
7185 ldrsb r0,[z80pc],#1\r
7186 ldr r1,[z80xx]\r
7187 add r0,r0,r1, lsr #16\r
7188 readmem8\r
7189 opORb\r
7190 fetch 19\r
7191\r
7192;@CP I (IX)\r
7193opcode_DD_BC:\r
7194 ldrb r0,[z80xx,#3]\r
7195 opCPb\r
7196 fetch 8\r
7197;@CP X (IX)\r
7198opcode_DD_BD:\r
7199 ldrb r0,[z80xx,#2]\r
7200 opCPb\r
7201 fetch 8\r
7202;@CP (IX+N)\r
7203opcode_DD_BE:\r
7204 ldrsb r0,[z80pc],#1\r
7205 ldr r1,[z80xx]\r
7206 add r0,r0,r1, lsr #16\r
7207 readmem8\r
7208 opCPb\r
7209 fetch 19\r
7210\r
7211\r
7212opcodes_DD_CB_LOCAL: .word opcodes_DD_CB\r
7213opcode_DD_CB:\r
7214;@Looks up the opcode on the opcodes_DD_CB table and then \r
7215;@moves the PC to the location of the subroutine\r
7216 ldrsb r0,[z80pc],#1\r
7217 ldr r1,[z80xx]\r
7218 add r0,r0,r1, lsr #16\r
7219\r
7220 ldrb r1,[z80pc],#1\r
7221 ldr pc,[pc,r1, lsl #2]\r
7222 .word 0x00\r
7223opcodes_DD_CB:\r
7224 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_06,opcode_DD_NF2\r
7225 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_0E,opcode_DD_NF2\r
7226 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_16,opcode_DD_NF2\r
7227 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_1E,opcode_DD_NF2\r
7228 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_26,opcode_DD_NF2\r
7229 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_2E,opcode_DD_NF2\r
7230 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_36,opcode_DD_NF2\r
7231 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_3E,opcode_DD_NF2\r
7232 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_46,opcode_DD_NF2\r
7233 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_4E,opcode_DD_NF2\r
7234 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_56,opcode_DD_NF2\r
7235 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_5E,opcode_DD_NF2\r
7236 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_66,opcode_DD_NF2\r
7237 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_6E,opcode_DD_NF2\r
7238 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_76,opcode_DD_NF2\r
7239 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_7E,opcode_DD_NF2\r
7240 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_86,opcode_DD_NF2\r
7241 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_8E,opcode_DD_NF2\r
7242 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_96,opcode_DD_NF2\r
7243 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_9E,opcode_DD_NF2\r
7244 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_A6,opcode_DD_NF2\r
7245 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_AE,opcode_DD_NF2\r
7246 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_B6,opcode_DD_NF2\r
7247 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_BE,opcode_DD_NF2\r
7248 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_C6,opcode_DD_NF2\r
7249 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_CE,opcode_DD_NF2\r
7250 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_D6,opcode_DD_NF2\r
7251 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_DE,opcode_DD_NF2\r
7252 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_E6,opcode_DD_NF2\r
7253 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_EE,opcode_DD_NF2\r
7254 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_F6,opcode_DD_NF2\r
7255 .word opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_NF2,opcode_DD_CB_FE,opcode_DD_NF2\r
7256\r
7257;@RLC (IX+N) \r
7258opcode_DD_CB_06:\r
7259 stmfd sp!,{r0} ;@ save addr\r
7260 readmem8\r
7261 opRLCb\r
7262 ldmfd sp!,{r1} ;@ restore addr into r1\r
7263 writemem8\r
7264 fetch 23\r
7265;@RRC (IX+N) \r
7266opcode_DD_CB_0E:\r
7267 stmfd sp!,{r0} ;@ save addr\r
7268 readmem8\r
7269 opRRCb\r
7270 ldmfd sp!,{r1} ;@ restore addr into r1\r
7271 writemem8\r
7272 fetch 23\r
7273;@RL (IX+N) \r
7274opcode_DD_CB_16:\r
7275 stmfd sp!,{r0} ;@ save addr\r
7276 readmem8\r
7277 opRLb\r
7278 ldmfd sp!,{r1} ;@ restore addr into r1\r
7279 writemem8\r
7280 fetch 23\r
7281;@RR (IX+N) \r
7282opcode_DD_CB_1E:\r
7283 stmfd sp!,{r0} ;@ save addr \r
7284 readmem8\r
7285 opRRb\r
7286 ldmfd sp!,{r1} ;@ restore addr into r1\r
7287 writemem8\r
7288 fetch 23\r
7289\r
7290;@SLA (IX+N) \r
7291opcode_DD_CB_26:\r
7292 stmfd sp!,{r0} ;@ save addr \r
7293 readmem8\r
7294 opSLAb\r
7295 ldmfd sp!,{r1} ;@ restore addr into r1\r
7296 writemem8\r
7297 fetch 23\r
7298;@SRA (IX+N) \r
7299opcode_DD_CB_2E:\r
7300 stmfd sp!,{r0} ;@ save addr \r
7301 readmem8\r
7302 opSRAb\r
7303 ldmfd sp!,{r1} ;@ restore addr into r1\r
7304 writemem8\r
7305 fetch 23\r
7306;@SLL (IX+N) \r
7307opcode_DD_CB_36:\r
7308 stmfd sp!,{r0} ;@ save addr \r
7309 readmem8\r
7310 opSLLb\r
7311 ldmfd sp!,{r1} ;@ restore addr into r1\r
7312 writemem8\r
7313 fetch 23\r
7314;@SRL (IX+N)\r
7315opcode_DD_CB_3E:\r
7316 stmfd sp!,{r0} ;@ save addr \r
7317 readmem8\r
7318 opSRLb\r
7319 ldmfd sp!,{r1} ;@ restore addr into r1\r
7320 writemem8\r
7321 fetch 23\r
7322\r
7323;@BIT 0,(IX+N) \r
7324opcode_DD_CB_46:\r
7325 readmem8\r
7326 opBITb 0\r
7327 fetch 20\r
7328;@BIT 1,(IX+N) \r
7329opcode_DD_CB_4E:\r
7330 readmem8\r
7331 opBITb 1\r
7332 fetch 20\r
7333;@BIT 2,(IX+N) \r
7334opcode_DD_CB_56:\r
7335 readmem8\r
7336 opBITb 2\r
7337 fetch 20\r
7338;@BIT 3,(IX+N) \r
7339opcode_DD_CB_5E:\r
7340 readmem8\r
7341 opBITb 3\r
7342 fetch 20\r
7343;@BIT 4,(IX+N) \r
7344opcode_DD_CB_66:\r
7345 readmem8\r
7346 opBITb 4\r
7347 fetch 20\r
7348;@BIT 5,(IX+N) \r
7349opcode_DD_CB_6E:\r
7350 readmem8\r
7351 opBITb 5\r
7352 fetch 20\r
7353;@BIT 6,(IX+N) \r
7354opcode_DD_CB_76:\r
7355 readmem8\r
7356 opBITb 6\r
7357 fetch 20\r
7358;@BIT 7,(IX+N) \r
7359opcode_DD_CB_7E:\r
7360 readmem8\r
7361 opBIT7b\r
7362 fetch 20\r
7363;@RES 0,(IX+N) \r
7364opcode_DD_CB_86:\r
7365 opRESmem 0\r
7366;@RES 1,(IX+N) \r
7367opcode_DD_CB_8E:\r
7368 opRESmem 1\r
7369;@RES 2,(IX+N) \r
7370opcode_DD_CB_96:\r
7371 opRESmem 2\r
7372;@RES 3,(IX+N) \r
7373opcode_DD_CB_9E:\r
7374 opRESmem 3\r
7375;@RES 4,(IX+N) \r
7376opcode_DD_CB_A6:\r
7377 opRESmem 4\r
7378;@RES 5,(IX+N) \r
7379opcode_DD_CB_AE:\r
7380 opRESmem 5\r
7381;@RES 6,(IX+N) \r
7382opcode_DD_CB_B6:\r
7383 opRESmem 6\r
7384;@RES 7,(IX+N) \r
7385opcode_DD_CB_BE:\r
7386 opRESmem 7\r
7387\r
7388;@SET 0,(IX+N) \r
7389opcode_DD_CB_C6:\r
7390 opSETmem 0\r
7391;@SET 1,(IX+N) \r
7392opcode_DD_CB_CE:\r
7393 opSETmem 1\r
7394;@SET 2,(IX+N) \r
7395opcode_DD_CB_D6:\r
7396 opSETmem 2\r
7397;@SET 3,(IX+N) \r
7398opcode_DD_CB_DE:\r
7399 opSETmem 3\r
7400;@SET 4,(IX+N) \r
7401opcode_DD_CB_E6:\r
7402 opSETmem 4\r
7403;@SET 5,(IX+N) \r
7404opcode_DD_CB_EE:\r
7405 opSETmem 5\r
7406;@SET 6,(IX+N) \r
7407opcode_DD_CB_F6:\r
7408 opSETmem 6\r
7409;@SET 7,(IX+N) \r
7410opcode_DD_CB_FE:\r
7411 opSETmem 7\r
7412\r
7413\r
7414\r
7415;@POP IX\r
7416opcode_DD_E1:\r
7417.if FAST_Z80SP\r
7418 opPOP\r
7419.else\r
7420 mov r0,z80sp\r
7421 stmfd sp!,{z80xx}\r
7422 readmem16\r
7423 ldmfd sp!,{z80xx}\r
7424 add z80sp,z80sp,#2\r
7425.endif\r
7426 strh r0,[z80xx,#2]\r
7427 fetch 14\r
7428;@EX (SP),IX\r
7429opcode_DD_E3:\r
7430.if FAST_Z80SP\r
7431 ldrb r0,[z80sp]\r
7432 ldrb r1,[z80sp,#1]\r
7433 orr r2,r0,r1, lsl #8\r
7434 ldrh r1,[z80xx,#2]\r
7435 mov r0,r1, lsr #8\r
7436 strb r0,[z80sp,#1]\r
7437 strb r1,[z80sp]\r
7438 strh r2,[z80xx,#2]\r
7439.else\r
7440 mov r0,z80sp\r
7441 stmfd sp!,{z80xx}\r
7442 readmem16\r
7443 ldmfd sp!,{z80xx}\r
7444 mov r2,r0\r
7445 ldrh r0,[z80xx,#2]\r
7446 strh r2,[z80xx,#2]\r
7447 mov r1,z80sp\r
7448 writemem16\r
7449.endif\r
7450 fetch 23\r
7451;@PUSH IX\r
7452opcode_DD_E5:\r
7453 ldr r2,[z80xx]\r
7454 opPUSHreg r2\r
7455 fetch 15\r
7456;@JP (IX)\r
7457opcode_DD_E9:\r
7458 ldrh r0,[z80xx,#2]\r
7459 rebasepc\r
7460 fetch 8\r
7461;@LD SP,IX\r
7462opcode_DD_F9:\r
7463.if FAST_Z80SP\r
7464 ldrh r0,[z80xx,#2]\r
7465 rebasesp\r
7466 mov z80sp,r0\r
7467.else\r
7468 ldrh z80sp,[z80xx,#2]\r
7469.endif\r
7470 fetch 10\r
7471\r
7472;@##################################\r
7473;@##################################\r
7474;@### opcodes ED #########################\r
7475;@##################################\r
7476;@##################################\r
7477\r
7478opcode_ED_NF:\r
7479 fetch 8\r
7480;@ ldrb r0,[z80pc],#1\r
7481;@ ldr pc,[opcodes,r0, lsl #2]\r
7482;@ mov r0,#0xED00\r
7483;@ orr r0,r0,r1\r
7484;@ b end_loop\r
7485\r
7486;@IN B,(C)\r
7487opcode_ED_40:\r
7488 opIN_C\r
7489 and z80bc,z80bc,#0xFF<<16\r
7490 orr z80bc,z80bc,r0, lsl #24\r
7491 sub r1,opcodes,#0x100\r
7492 ldrb r0,[r1,r0]\r
7493 and z80f,z80f,#1<<CFlag\r
7494 orr z80f,z80f,r0\r
7495 fetch 12\r
7496;@OUT (C),B\r
7497opcode_ED_41:\r
7498 mov r1,z80bc, lsr #24\r
7499 opOUT_C\r
7500 fetch 12\r
7501\r
7502;@SBC HL,BC\r
7503opcode_ED_42:\r
7504 opSBC16 z80bc\r
7505\r
7506;@LD (NN),BC\r
7507opcode_ED_43:\r
7508 ldrb r0,[z80pc],#1\r
7509 ldrb r1,[z80pc],#1\r
7510 orr r1,r0,r1, lsl #8\r
7511 mov r0,z80bc, lsr #16\r
7512 writemem16\r
7513 fetch 20\r
7514;@NEG\r
7515opcode_ED_44:\r
7516 rsbs z80a,z80a,#0\r
7517 mrs z80f,cpsr\r
7518 mov z80f,z80f,lsr#28 ;@S,Z,V&C\r
7519 eor z80f,z80f,#(1<<CFlag)|(1<<NFlag) ;@invert C and set n.\r
7520 tst z80a,#0x0F000000 ;@H, correct\r
7521 orrne z80f,z80f,#1<<HFlag\r
7522 fetch 8\r
7523 \r
7524;@RETN, moved to ED_4D\r
7525;@opcode_ED_45:\r
7526\r
7527;@IM 0\r
7528opcode_ED_46:\r
7529 strb z80a,[cpucontext,#z80im]\r
7530 fetch 8\r
7531;@LD I,A\r
7532opcode_ED_47:\r
7533 str z80a,[cpucontext,#z80i]\r
7534 fetch 9\r
7535;@IN C,(C)\r
7536opcode_ED_48:\r
7537 opIN_C\r
7538 and z80bc,z80bc,#0xFF<<24\r
7539 orr z80bc,z80bc,r0, lsl #16\r
7540 sub r1,opcodes,#0x100\r
7541 ldrb r0,[r1,r0]\r
7542 and z80f,z80f,#1<<CFlag\r
7543 orr z80f,z80f,r0\r
7544 fetch 12\r
7545;@OUT (C),C\r
7546opcode_ED_49:\r
7547 mov r0,z80bc, lsr #16\r
7548 and r1,r0,#0xFF\r
7549 opOUT\r
7550 fetch 12\r
7551;@ADC HL,BC\r
7552opcode_ED_4A:\r
7553 opADC16 z80bc\r
7554;@LD BC,(NN)\r
7555opcode_ED_4B:\r
7556 ldrb r0,[z80pc],#1\r
7557 ldrb r1,[z80pc],#1\r
7558 orr r0,r0,r1, lsl #8\r
7559 readmem16\r
7560 mov z80bc,r0, lsl #16\r
7561 fetch 20\r
7562\r
7563;@RETN\r
7564opcode_ED_45:\r
7565;@RETI\r
7566opcode_ED_4D:\r
7567 ldrb r0,[cpucontext,#z80if]\r
7568 tst r0,#Z80_IF2\r
7569 orrne r0,r0,#Z80_IF1\r
7570 biceq r0,r0,#Z80_IF1\r
7571 strb r0,[cpucontext,#z80if]\r
7572 opPOP\r
7573 rebasepc\r
7574 fetch 14\r
7575\r
7576;@LD R,A\r
7577opcode_ED_4F:\r
7578 mov r0,z80a,lsr#24\r
7579 strb r0,[cpucontext,#z80r]\r
7580 fetch 9\r
7581\r
7582;@IN D,(C)\r
7583opcode_ED_50:\r
7584 opIN_C\r
7585 and z80de,z80de,#0xFF<<16\r
7586 orr z80de,z80de,r0, lsl #24\r
7587 sub r1,opcodes,#0x100\r
7588 ldrb r0,[r1,r0]\r
7589 and z80f,z80f,#1<<CFlag\r
7590 orr z80f,z80f,r0\r
7591 fetch 12\r
7592;@OUT (C),D\r
7593opcode_ED_51:\r
7594 mov r1,z80de, lsr #24\r
7595 opOUT_C\r
7596 fetch 12\r
7597;@SBC HL,DE\r
7598opcode_ED_52:\r
7599 opSBC16 z80de\r
7600;@LD (NN),DE\r
7601opcode_ED_53:\r
7602 ldrb r0,[z80pc],#1\r
7603 ldrb r1,[z80pc],#1\r
7604 orr r1,r0,r1, lsl #8\r
7605 mov r0,z80de, lsr #16\r
7606 writemem16\r
7607 fetch 20\r
7608;@IM 1\r
7609opcode_ED_56:\r
7610 mov r0,#1\r
7611 strb r0,[cpucontext,#z80im]\r
7612 fetch 8\r
7613;@LD A,I\r
7614opcode_ED_57:\r
7615 ldr z80a,[cpucontext,#z80i]\r
7616 tst z80a,#0xFF000000\r
7617 and z80f,z80f,#(1<<CFlag)\r
7618 orreq z80f,z80f,#(1<<ZFlag)\r
7619 orrmi z80f,z80f,#(1<<SFlag)\r
7620 ldrb r0,[cpucontext,#z80if]\r
7621 tst r0,#Z80_IF2\r
7622 orrne z80f,z80f,#(1<<VFlag)\r
7623 fetch 9\r
7624;@IN E,(C)\r
7625opcode_ED_58:\r
7626 opIN_C\r
7627 and z80de,z80de,#0xFF<<24\r
7628 orr z80de,z80de,r0, lsl #16\r
7629 sub r1,opcodes,#0x100\r
7630 ldrb r0,[r1,r0]\r
7631 and z80f,z80f,#1<<CFlag\r
7632 orr z80f,z80f,r0\r
7633 fetch 12\r
7634;@OUT (C),E\r
7635opcode_ED_59:\r
7636 mov r1,z80de, lsr #16\r
7637 and r1,r1,#0xFF\r
7638 opOUT_C\r
7639 fetch 12\r
7640;@ADC HL,DE\r
7641opcode_ED_5A:\r
7642 opADC16 z80de\r
7643;@LD DE,(NN)\r
7644opcode_ED_5B:\r
7645 ldrb r0,[z80pc],#1\r
7646 ldrb r1,[z80pc],#1\r
7647 orr r0,r0,r1, lsl #8\r
7648 readmem16\r
7649 mov z80de,r0, lsl #16\r
7650 fetch 20\r
7651;@IM 2\r
7652opcode_ED_5E:\r
7653 mov r0,#2\r
7654 strb r0,[cpucontext,#z80im]\r
7655 fetch 8\r
7656;@LD A,R\r
7657opcode_ED_5F:\r
7658 ldrb r0,[cpucontext,#z80r]\r
7659 and r0,r0,#0x80\r
7660 rsb r1,z80_icount,#0\r
7661 and r1,r1,#0x7F\r
7662 orr r0,r0,r1\r
7663 movs z80a,r0, lsl #24\r
7664 and z80f,z80f,#1<<CFlag\r
7665 orrmi z80f,z80f,#(1<<SFlag)\r
7666 orreq z80f,z80f,#(1<<ZFlag)\r
7667 ldrb r0,[cpucontext,#z80if]\r
7668 tst r0,#Z80_IF2\r
7669 orrne z80f,z80f,#(1<<VFlag)\r
7670 fetch 9\r
7671;@IN H,(C)\r
7672opcode_ED_60:\r
7673 opIN_C\r
7674 and z80hl,z80hl,#0xFF<<16\r
7675 orr z80hl,z80hl,r0, lsl #24\r
7676 sub r1,opcodes,#0x100\r
7677 ldrb r0,[r1,r0]\r
7678 and z80f,z80f,#1<<CFlag\r
7679 orr z80f,z80f,r0\r
7680 fetch 12\r
7681;@OUT (C),H\r
7682opcode_ED_61:\r
7683 mov r1,z80hl, lsr #24\r
7684 opOUT_C\r
7685 fetch 12\r
7686;@SBC HL,HL\r
7687opcode_ED_62:\r
7688 opSBC16HL\r
7689;@RRD\r
7690opcode_ED_67:\r
7691 readmem8HL\r
7692 mov r1,r0,ror#4\r
7693 orr r0,r1,z80a,lsr#20\r
7694 bic z80a,z80a,#0x0F000000\r
7695 orr z80a,z80a,r1,lsr#4\r
7696 writemem8HL\r
7697 sub r1,opcodes,#0x100\r
7698 ldrb r0,[r1,z80a, lsr #24]\r
7699 and z80f,z80f,#1<<CFlag\r
7700 orr z80f,z80f,r0\r
7701 fetch 18\r
7702;@IN L,(C)\r
7703opcode_ED_68:\r
7704 opIN_C\r
7705 and z80hl,z80hl,#0xFF<<24\r
7706 orr z80hl,z80hl,r0, lsl #16\r
7707 and z80f,z80f,#1<<CFlag\r
7708 sub r1,opcodes,#0x100\r
7709 ldrb r0,[r1,r0]\r
7710 orr z80f,z80f,r0\r
7711 fetch 12\r
7712;@OUT (C),L\r
7713opcode_ED_69:\r
7714 mov r1,z80hl, lsr #16\r
7715 and r1,r1,#0xFF\r
7716 opOUT_C\r
7717 fetch 12\r
7718;@ADC HL,HL\r
7719opcode_ED_6A:\r
7720 opADC16HL\r
7721;@RLD\r
7722opcode_ED_6F:\r
7723 readmem8HL\r
7724 orr r0,r0,z80a,lsl#4\r
7725 mov r0,r0,ror#28\r
7726 and z80a,z80a,#0xF0000000\r
7727 orr z80a,z80a,r0,lsl#16\r
7728 and z80a,z80a,#0xFF000000\r
7729 writemem8HL\r
7730 sub r1,opcodes,#0x100\r
7731 ldrb r0,[r1,z80a, lsr #24]\r
7732 and z80f,z80f,#1<<CFlag\r
7733 orr z80f,z80f,r0\r
7734 fetch 18\r
7735;@IN F,(C)\r
7736opcode_ED_70:\r
7737 opIN_C\r
7738 and z80f,z80f,#1<<CFlag\r
7739 sub r1,opcodes,#0x100\r
7740 ldrb r0,[r1,r0]\r
7741 orr z80f,z80f,r0\r
7742 fetch 12\r
7743;@OUT (C),0\r
7744opcode_ED_71:\r
7745 mov r1,#0\r
7746 opOUT_C\r
7747 fetch 12\r
7748\r
7749;@SBC HL,SP\r
7750opcode_ED_72:\r
7751.if FAST_Z80SP\r
7752 ldr r0,[cpucontext,#z80sp_base]\r
7753 sub r0,z80sp,r0\r
7754 mov r0, r0, lsl #16\r
7755.else\r
7756 mov r0,z80sp,lsl#16\r
7757.endif\r
7758 opSBC16 r0\r
7759;@LD (NN),SP\r
7760opcode_ED_73:\r
7761 ldrb r0,[z80pc],#1\r
7762 ldrb r1,[z80pc],#1\r
7763 orr r1,r0,r1, lsl #8\r
7764.if FAST_Z80SP\r
7765 ldr r0,[cpucontext,#z80sp_base]\r
7766 sub r0,z80sp,r0\r
7767.else\r
7768 mov r0,z80sp\r
7769.endif\r
7770 writemem16\r
7771 fetch 16\r
7772;@IN A,(C)\r
7773opcode_ED_78:\r
7774 opIN_C\r
7775 mov z80a,r0, lsl #24\r
7776 and z80f,z80f,#1<<CFlag\r
7777 sub r1,opcodes,#0x100\r
7778 ldrb r0,[r1,r0]\r
7779 orr z80f,z80f,r0\r
7780 fetch 12\r
7781;@OUT (C),A\r
7782opcode_ED_79:\r
7783 mov r1,z80a, lsr #24\r
7784 opOUT_C\r
7785 fetch 12\r
7786;@ADC HL,SP\r
7787opcode_ED_7A:\r
7788.if FAST_Z80SP\r
7789 ldr r0,[cpucontext,#z80sp_base]\r
7790 sub r0,z80sp,r0\r
7791 mov r0, r0, lsl #16\r
7792.else\r
7793 mov r0,z80sp,lsl#16\r
7794.endif\r
7795 opADC16 r0\r
7796;@LD SP,(NN)\r
7797opcode_ED_7B:\r
7798 ldrb r0,[z80pc],#1\r
7799 ldrb r1,[z80pc],#1\r
7800 orr r0,r0,r1, lsl #8\r
7801 readmem16\r
7802.if FAST_Z80SP\r
7803 rebasesp\r
7804.endif\r
7805 mov z80sp,r0\r
7806 fetch 20\r
7807;@LDI\r
7808opcode_ED_A0:\r
7809 copymem8HL_DE\r
7810 add z80hl,z80hl,#1<<16\r
7811 add z80de,z80de,#1<<16\r
7812 subs z80bc,z80bc,#1<<16\r
7813 bic z80f,z80f,#(1<<VFlag)|(1<<NFlag)|(1<<HFlag)\r
7814 orrne z80f,z80f,#1<<VFlag\r
7815 fetch 16\r
7816;@CPI\r
7817opcode_ED_A1:\r
7818 readmem8HL\r
7819 add z80hl,z80hl,#0x00010000\r
7820 mov r1,z80a,lsl#4\r
7821 cmp z80a,r0,lsl#24\r
7822 and z80f,z80f,#1<<CFlag\r
7823 orr z80f,z80f,#1<<NFlag\r
7824 orrmi z80f,z80f,#1<<SFlag\r
7825 orreq z80f,z80f,#1<<ZFlag\r
7826 cmp r1,r0,lsl#28\r
7827 orrcc z80f,z80f,#1<<HFlag\r
7828 subs z80bc,z80bc,#0x00010000\r
7829 orrne z80f,z80f,#1<<VFlag\r
7830 fetch 16\r
7831;@INI\r
7832opcode_ED_A2:\r
7833 opIN_C\r
7834 and z80f,r0,#0x80\r
7835 mov z80f,z80f,lsr#2 ;@NFlag set by bit 7\r
7836;@ mov r1,z80bc,lsl#8\r
7837;@ add r1,r1,#0x01000000\r
7838;@ adds r1,r1,r0,lsl#24\r
7839;@ orrcs z80f,z80f,#(1<<CFlag)|(1<<HFlag) ;@ CF & HF set if (HL) + ((C+1) & 0xFF) > 0xFF\r
7840 writemem8HL\r
7841 add z80hl,z80hl,#1<<16\r
7842 sub z80bc,z80bc,#1<<24\r
7843 tst z80bc,#0xFF<<24\r
7844 orrmi z80f,z80f,#1<<SFlag\r
7845 orreq z80f,z80f,#1<<ZFlag\r
7846 fetch 16\r
7847\r
7848;@OUTI\r
7849opcode_ED_A3:\r
7850 readmem8HL\r
7851 add z80hl,z80hl,#1<<16\r
7852 and z80f,r0,#0x80\r
7853 mov z80f,z80f,lsr#2 ;@NFlag set by bit 7\r
7854 mov r1,z80hl,lsl#8\r
7855 adds r1,r1,r0,lsl#24\r
7856 orrcs z80f,z80f,#(1<<CFlag)|(1<<HFlag) ;@ CF & HF set if (HL)+L > 0xFF\r
7857 sub z80bc,z80bc,#1<<24\r
7858 tst z80bc,#0xFF<<24\r
7859 orrmi z80f,z80f,#1<<SFlag\r
7860 orreq z80f,z80f,#1<<ZFlag\r
7861 mov r1,r0\r
7862 opOUT_C\r
7863 fetch 16\r
7864\r
7865;@LDD\r
7866opcode_ED_A8:\r
7867 copymem8HL_DE\r
7868 sub z80hl,z80hl,#1<<16\r
7869 sub z80de,z80de,#1<<16\r
7870 subs z80bc,z80bc,#1<<16\r
7871 bic z80f,z80f,#(1<<VFlag)|(1<<NFlag)|(1<<HFlag)\r
7872 orrne z80f,z80f,#1<<VFlag\r
7873 fetch 16\r
7874\r
7875;@CPD\r
7876opcode_ED_A9:\r
7877 readmem8HL\r
7878 sub z80hl,z80hl,#1<<16\r
7879 mov r1,z80a,lsl#4\r
7880 cmp z80a,r0,lsl#24\r
7881 and z80f,z80f,#1<<CFlag\r
7882 orr z80f,z80f,#1<<NFlag\r
7883 orrmi z80f,z80f,#1<<SFlag\r
7884 orreq z80f,z80f,#1<<ZFlag\r
7885 cmp r1,r0,lsl#28\r
7886 orrcc z80f,z80f,#1<<HFlag\r
7887 subs z80bc,z80bc,#0x00010000\r
7888 orrne z80f,z80f,#1<<VFlag\r
7889 fetch 16\r
7890\r
7891;@IND\r
7892opcode_ED_AA:\r
7893 opIN_C\r
7894 and z80f,r0,#0x80\r
7895 mov z80f,z80f,lsr#2 ;@NFlag set by bit 7\r
7896;@ mov r1,z80bc,lsl#8\r
7897;@ sub r1,r1,#0x01000000\r
7898;@ adds r1,r1,r0,lsl#24\r
7899;@ orrcs z80f,z80f,#(1<<CFlag)|(1<<HFlag) ;@ CF & HF set if (HL) + ((C-1) & 0xFF) > 0xFF\r
7900 writemem8HL\r
7901 sub z80hl,z80hl,#1<<16\r
7902 sub z80bc,z80bc,#1<<24\r
7903 tst z80bc,#0xFF<<24\r
7904 orrmi z80f,z80f,#1<<SFlag\r
7905 orreq z80f,z80f,#1<<ZFlag\r
7906 fetch 16\r
7907\r
7908;@OUTD\r
7909opcode_ED_AB:\r
7910 readmem8HL\r
7911 sub z80hl,z80hl,#1<<16\r
7912 and z80f,r0,#0x80\r
7913 mov z80f,z80f,lsr#2 ;@NFlag set by bit 7\r
7914 mov r1,z80hl,lsl#8\r
7915 adds r1,r1,r0,lsl#24\r
7916 orrcs z80f,z80f,#(1<<CFlag)|(1<<HFlag) ;@ CF & HF set if r0+HL > 0xFF\r
7917 sub z80bc,z80bc,#1<<24\r
7918 tst z80bc,#0xFF<<24\r
7919 orrmi z80f,z80f,#1<<SFlag\r
7920 orreq z80f,z80f,#1<<ZFlag\r
7921 mov r1,r0\r
7922 opOUT_C\r
7923 fetch 16\r
7924;@LDIR\r
7925opcode_ED_B0:\r
7926 copymem8HL_DE\r
7927 add z80hl,z80hl,#1<<16\r
7928 add z80de,z80de,#1<<16\r
7929 subs z80bc,z80bc,#1<<16\r
7930 bic z80f,z80f,#(1<<VFlag)|(1<<NFlag)|(1<<HFlag)\r
7931 orrne z80f,z80f,#1<<VFlag\r
7932 subne z80pc,z80pc,#2\r
7933 subne z80_icount,z80_icount,#5\r
7934 fetch 16\r
7935\r
7936;@CPIR\r
7937opcode_ED_B1:\r
7938 readmem8HL\r
7939 add z80hl,z80hl,#1<<16 \r
7940 mov r1,z80a,lsl#4\r
7941 cmp z80a,r0,lsl#24\r
7942 and z80f,z80f,#1<<CFlag\r
7943 orr z80f,z80f,#1<<NFlag\r
7944 orrmi z80f,z80f,#1<<SFlag\r
7945 orreq z80f,z80f,#1<<ZFlag\r
7946 cmp r1,r0,lsl#28\r
7947 orrcc z80f,z80f,#1<<HFlag\r
7948 subs z80bc,z80bc,#1<<16\r
7949 bne opcode_ED_B1_decpc\r
7950 fetch 16\r
7951opcode_ED_B1_decpc:\r
7952 orr z80f,z80f,#1<<VFlag\r
7953 tst z80f,#1<<ZFlag\r
7954 subeq z80pc,z80pc,#2\r
7955 subeq z80_icount,z80_icount,#5\r
7956 fetch 16\r
7957;@INIR\r
7958opcode_ED_B2:\r
7959 opIN_C\r
7960 and z80f,r0,#0x80\r
7961 mov z80f,z80f,lsr#2 ;@NFlag set by bit 7\r
7962;@ mov r1,z80bc,lsl#8\r
7963;@ add r1,r1,#0x01000000\r
7964;@ adds r1,r1,r0,lsl#24\r
7965;@ orrcs z80f,z80f,#(1<<CFlag)|(1<<HFlag) ;@ CF & HF set if (HL) + ((C+1) & 0xFF) > 0xFF\r
7966 writemem8HL\r
7967 add z80hl,z80hl,#1<<16\r
7968 sub z80bc,z80bc,#1<<24\r
7969 tst z80bc,#0xFF<<24\r
7970 orrmi z80f,z80f,#1<<SFlag\r
7971 orreq z80f,z80f,#1<<ZFlag\r
7972 subne z80pc,z80pc,#2\r
7973 subne z80_icount,z80_icount,#5\r
7974 fetch 16\r
7975;@OTIR\r
7976opcode_ED_B3:\r
7977 readmem8HL\r
7978 add z80hl,z80hl,#1<<16\r
7979 and z80f,r0,#0x80\r
7980 mov z80f,z80f,lsr#2 ;@NFlag set by bit 7\r
7981 mov r1,z80hl,lsl#8\r
7982 adds r1,r1,r0,lsl#24\r
7983 orrcs z80f,z80f,#(1<<CFlag)|(1<<HFlag) ;@ CF & HF set if r0+HL > 0xFF\r
7984 sub z80bc,z80bc,#1<<24\r
7985 tst z80bc,#0xFF<<24\r
7986 orrmi z80f,z80f,#1<<SFlag\r
7987 orreq z80f,z80f,#1<<ZFlag\r
7988 subne z80pc,z80pc,#2\r
7989 subne z80_icount,z80_icount,#5\r
7990 mov r1,r0\r
7991 opOUT_C\r
7992 fetch 16\r
7993;@LDDR\r
7994opcode_ED_B8:\r
7995 copymem8HL_DE\r
7996 sub z80hl,z80hl,#1<<16\r
7997 sub z80de,z80de,#1<<16\r
7998 subs z80bc,z80bc,#1<<16\r
7999 bic z80f,z80f,#(1<<VFlag)|(1<<NFlag)|(1<<HFlag)\r
8000 orrne z80f,z80f,#1<<VFlag\r
8001 subne z80pc,z80pc,#2\r
8002 subne z80_icount,z80_icount,#5\r
8003 fetch 16\r
8004\r
8005;@CPDR\r
8006opcode_ED_B9:\r
8007 readmem8HL\r
8008 sub z80hl,z80hl,#1<<16\r
8009 mov r1,z80a,lsl#4\r
8010 cmp z80a,r0,lsl#24\r
8011 and z80f,z80f,#1<<CFlag\r
8012 orr z80f,z80f,#1<<NFlag\r
8013 orrmi z80f,z80f,#1<<SFlag\r
8014 orreq z80f,z80f,#1<<ZFlag\r
8015 cmp r1,r0,lsl#28\r
8016 orrcc z80f,z80f,#1<<HFlag\r
8017 subs z80bc,z80bc,#1<<16\r
8018 bne opcode_ED_B9_decpc\r
8019 fetch 16\r
8020opcode_ED_B9_decpc:\r
8021 orr z80f,z80f,#1<<VFlag\r
8022 tst z80f,#1<<ZFlag\r
8023 subeq z80pc,z80pc,#2\r
8024 subeq z80_icount,z80_icount,#5\r
8025 fetch 16\r
8026;@INDR\r
8027opcode_ED_BA:\r
8028 opIN_C\r
8029 and z80f,r0,#0x80\r
8030 mov z80f,z80f,lsr#2 ;@NFlag set by bit 7\r
8031;@ mov r1,z80bc,lsl#8\r
8032;@ sub r1,r1,#0x01000000\r
8033;@ adds r1,r1,r0,lsl#24\r
8034;@ orrcs z80f,z80f,#(1<<CFlag)|(1<<HFlag) ;@ CF & HF set if (HL) + ((C-1) & 0xFF) > 0xFF\r
8035 writemem8HL\r
8036 sub z80hl,z80hl,#1<<16\r
8037 sub z80bc,z80bc,#1<<24\r
8038 tst z80bc,#0xFF<<24\r
8039 orrmi z80f,z80f,#1<<SFlag\r
8040 orreq z80f,z80f,#1<<ZFlag\r
8041 subne z80pc,z80pc,#2\r
8042 subne z80_icount,z80_icount,#5\r
8043 fetch 16\r
8044;@OTDR\r
8045opcode_ED_BB:\r
8046 readmem8HL\r
8047 sub z80hl,z80hl,#1<<16\r
8048 and z80f,r0,#0x80\r
8049 mov z80f,z80f,lsr#2 ;@NFlag set by bit 7\r
8050 mov r1,z80hl,lsl#8\r
8051 adds r1,r1,r0,lsl#24\r
8052 orrcs z80f,z80f,#(1<<CFlag)|(1<<HFlag) ;@ CF & HF set if r0+HL > 0xFF\r
8053 sub z80bc,z80bc,#1<<24\r
8054 tst z80bc,#0xFF<<24\r
8055 orrmi z80f,z80f,#1<<SFlag\r
8056 orreq z80f,z80f,#1<<ZFlag\r
8057 subne z80pc,z80pc,#2\r
8058 subne z80_icount,z80_icount,#5\r
8059 mov r1,r0\r
8060 opOUT_C\r
8061 fetch 16\r
8062;@##################################\r
8063;@##################################\r
8064;@### opcodes FD #########################\r
8065;@##################################\r
8066;@##################################\r
8067;@Since DD and FD opcodes are all the same apart from the address\r
8068;@register they use. When a FD intruction the program runs the code\r
8069;@from the DD location but the address of the IY reg is passed instead\r
8070;@of IX\r
8071\r
8072end_loop:\r
8073 b end_loop\r
8074\r
8075\r
8076\r
fast MegaDrive/MegaCD/32X emulator