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1 | #include <stdarg.h> |
2 | |
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3 | #if (DRC_DEBUG & 1) |
4 | #define COUNT_OP \ |
5 | host_insn_count++ |
6 | #else |
7 | #define COUNT_OP |
8 | #endif |
9 | |
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10 | enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI }; |
11 | |
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12 | #define CONTEXT_REG xBP |
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13 | |
14 | #define EMIT_PTR(ptr, val, type) \ |
15 | *(type *)(ptr) = val |
16 | |
17 | #define EMIT(val, type) { \ |
18 | EMIT_PTR(tcache_ptr, val, type); \ |
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19 | tcache_ptr += sizeof(type); \ |
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20 | } |
21 | |
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22 | #define EMIT_OP(op) { \ |
23 | COUNT_OP; \ |
24 | EMIT(op, u8); \ |
25 | } |
26 | |
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27 | #define EMIT_MODRM(mod,r,rm) \ |
28 | EMIT(((mod)<<6) | ((r)<<3) | (rm), u8) |
29 | |
30 | #define EMIT_OP_MODRM(op,mod,r,rm) { \ |
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31 | EMIT_OP(op); \ |
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32 | EMIT_MODRM(mod, r, rm); \ |
33 | } |
34 | |
35 | #define emith_move_r_r(dst, src) \ |
36 | EMIT_OP_MODRM(0x8b, 3, dst, src) |
37 | |
38 | #define emith_move_r_imm(r, imm) { \ |
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39 | EMIT_OP(0xb8 + (r)); \ |
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40 | EMIT(imm, u32); \ |
41 | } |
42 | |
43 | #define emith_add_r_imm(r, imm) { \ |
44 | EMIT_OP_MODRM(0x81, 3, 0, r); \ |
45 | EMIT(imm, u32); \ |
46 | } |
47 | |
48 | #define emith_sub_r_imm(r, imm) { \ |
49 | EMIT_OP_MODRM(0x81, 3, 5, r); \ |
50 | EMIT(imm, u32); \ |
51 | } |
52 | |
53 | // XXX: offs is 8bit only |
54 | #define emith_ctx_read(r, offs) { \ |
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55 | EMIT_OP_MODRM(0x8b, 1, r, xBP); \ |
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56 | EMIT(offs, u8); /* mov tmp, [ebp+#offs] */ \ |
57 | } |
58 | |
59 | #define emith_ctx_write(r, offs) { \ |
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60 | EMIT_OP_MODRM(0x89, 1, r, xBP); \ |
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61 | EMIT(offs, u8); /* mov [ebp+#offs], tmp */ \ |
62 | } |
63 | |
64 | #define emith_ctx_sub(val, offs) { \ |
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65 | EMIT_OP_MODRM(0x81, 1, 5, xBP); \ |
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66 | EMIT(offs, u8); \ |
67 | EMIT(val, u32); /* sub [ebp+#offs], dword val */ \ |
68 | } |
69 | |
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70 | #define emith_jump(ptr) { \ |
71 | u32 disp = (u32)ptr - ((u32)tcache_ptr + 5); \ |
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72 | EMIT_OP(0xe9); \ |
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73 | EMIT(disp, u32); \ |
74 | } |
75 | |
76 | #define emith_call(ptr) { \ |
77 | u32 disp = (u32)ptr - ((u32)tcache_ptr + 5); \ |
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78 | EMIT_OP(0xe8); \ |
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79 | EMIT(disp, u32); \ |
80 | } |
81 | |
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82 | #define EMITH_CONDITIONAL(code, is_nonzero) { \ |
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83 | u8 *ptr = tcache_ptr; \ |
84 | tcache_ptr = tcache_ptr + 2; \ |
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85 | code; \ |
86 | EMIT_PTR(ptr, ((is_nonzero) ? 0x75 : 0x74), u8); \ |
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87 | EMIT_PTR(ptr + 1, (tcache_ptr - (ptr + 2)), u8); \ |
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88 | } |
89 | |
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90 | #define arg2reg(rd, arg) \ |
91 | switch (arg) { \ |
92 | case 0: rd = xAX; break; \ |
93 | case 1: rd = xDX; break; \ |
94 | case 2: rd = xCX; break; \ |
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95 | } |
96 | |
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97 | #define emith_pass_arg_r(arg, reg) { \ |
98 | int rd = 7; \ |
99 | arg2reg(rd, arg); \ |
100 | emith_move_r_r(rd, reg); \ |
101 | } |
102 | |
103 | #define emith_pass_arg_imm(arg, imm) { \ |
104 | int rd = 7; \ |
105 | arg2reg(rd, arg); \ |
106 | emith_move_r_imm(rd, imm); \ |
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107 | } |
108 | |
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109 | /* SH2 drc specific */ |
110 | #define emith_test_t() { \ |
111 | if (reg_map_g2h[SHR_SR] == -1) { \ |
112 | EMIT_OP_MODRM(0xf6, 1, 0, 5); \ |
113 | EMIT(SHR_SR * 4, u8); \ |
114 | EMIT(0x01, u8); /* test [ebp+SHR_SR], byte 1 */ \ |
115 | } else { \ |
116 | EMIT_OP_MODRM(0xf7, 3, 0, reg_map_g2h[SHR_SR]); \ |
117 | EMIT(0x01, u16); /* test <reg>, word 1 */ \ |
118 | } \ |
119 | } |
120 | |