[picodrive.git] / cpu / drc / emit_x86.c

/*
 * note:
 *  temp registers must be eax-edx due to use of SETcc.
 * note about silly things like emith_eor_r_r_r:
 *  these are here because the compiler was designed
 *  for ARM as it's primary target.
 */
#include <stdarg.h>

enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };

#define CONTEXT_REG xBP

#define IOP_JMP 0xeb
#define IOP_JO  0x70
#define IOP_JNO 0x71
#define IOP_JB  0x72
#define IOP_JAE 0x73
#define IOP_JE  0x74
#define IOP_JNE 0x75
#define IOP_JBE 0x76
#define IOP_JA  0x77
#define IOP_JS  0x78
#define IOP_JNS 0x79
#define IOP_JL  0x7c
#define IOP_JGE 0x7d
#define IOP_JLE 0x7e
#define IOP_JG  0x7f

// unified conditions (we just use rel8 jump instructions for x86)
#define DCOND_EQ IOP_JE
#define DCOND_NE IOP_JNE
#define DCOND_MI IOP_JS      // MInus
#define DCOND_PL IOP_JNS     // PLus or zero
#define DCOND_HI IOP_JA      // higher (unsigned)
#define DCOND_HS IOP_JAE     // higher || same (unsigned)
#define DCOND_LO IOP_JB      // lower (unsigned)
#define DCOND_LS IOP_JBE     // lower || same (unsigned)
#define DCOND_GE IOP_JGE     // greater || equal (signed)
#define DCOND_GT IOP_JG      // greater (signed)
#define DCOND_LE IOP_JLE     // less || equal (signed)
#define DCOND_LT IOP_JL      // less (signed)
#define DCOND_VS IOP_JO      // oVerflow Set
#define DCOND_VC IOP_JNO     // oVerflow Clear

#define EMIT_PTR(ptr, val, type) \
	*(type *)(ptr) = val

#define EMIT(val, type) { \
	EMIT_PTR(tcache_ptr, val, type); \
	tcache_ptr += sizeof(type); \
}

#define EMIT_OP(op) { \
	COUNT_OP; \
	EMIT(op, u8); \
}

#define EMIT_MODRM(mod,r,rm) \
	EMIT(((mod)<<6) | ((r)<<3) | (rm), u8)

#define EMIT_SIB(scale,index,base) \
	EMIT(((scale)<<6) | ((index)<<3) | (base), u8)

#define EMIT_OP_MODRM(op,mod,r,rm) { \
	EMIT_OP(op); \
	EMIT_MODRM(mod, r, rm); \
}

#define JMP8_POS(ptr) \
	ptr = tcache_ptr; \
	tcache_ptr += 2

#define JMP8_EMIT(op, ptr) \
	EMIT_PTR(ptr, op, u8); \
	EMIT_PTR(ptr + 1, (tcache_ptr - (ptr+2)), u8)

// _r_r
#define emith_move_r_r(dst, src) \
	EMIT_OP_MODRM(0x8b, 3, dst, src)

#define emith_add_r_r(d, s) \
	EMIT_OP_MODRM(0x01, 3, s, d)

#define emith_sub_r_r(d, s) \
	EMIT_OP_MODRM(0x29, 3, s, d)

#define emith_adc_r_r(d, s) \
	EMIT_OP_MODRM(0x11, 3, s, d)

#define emith_sbc_r_r(d, s) \
	EMIT_OP_MODRM(0x19, 3, s, d) /* SBB */

#define emith_or_r_r(d, s) \
	EMIT_OP_MODRM(0x09, 3, s, d)

#define emith_and_r_r(d, s) \
	EMIT_OP_MODRM(0x21, 3, s, d)

#define emith_eor_r_r(d, s) \
	EMIT_OP_MODRM(0x31, 3, s, d) /* XOR */

#define emith_tst_r_r(d, s) \
	EMIT_OP_MODRM(0x85, 3, s, d) /* TEST */

#define emith_cmp_r_r(d, s) \
	EMIT_OP_MODRM(0x39, 3, s, d)

// fake teq - test equivalence - get_flags(d ^ s)
#define emith_teq_r_r(d, s) { \
	emith_push(d); \
	emith_eor_r_r(d, s); \
	emith_pop(d); \
}

#define emith_mvn_r_r(d, s) { \
	if (d != s) \
		emith_move_r_r(d, s); \
	EMIT_OP_MODRM(0xf7, 3, 2, d); /* NOT d */ \
}

#define emith_negc_r_r(d, s) { \
	int tmp_ = rcache_get_tmp(); \
	emith_move_r_imm(tmp_, 0); \
	emith_sbc_r_r(tmp_, s); \
	emith_move_r_r(d, tmp_); \
	rcache_free_tmp(tmp_); \
}

#define emith_neg_r_r(d, s) { \
	if (d != s) \
		emith_move_r_r(d, s); \
	EMIT_OP_MODRM(0xf7, 3, 3, d); /* NEG d */ \
}

// _r_r_r
#define emith_eor_r_r_r(d, s1, s2) { \
	if (d == s1) { \
		emith_eor_r_r(d, s2); \
	} else if (d == s2) { \
		emith_eor_r_r(d, s1); \
	} else { \
		emith_move_r_r(d, s1); \
		emith_eor_r_r(d, s2); \
	} \
}

// _r_r_shift
#define emith_or_r_r_lsl(d, s, lslimm) { \
	int tmp_ = rcache_get_tmp(); \
	emith_lsl(tmp_, s, lslimm); \
	emith_or_r_r(d, tmp_); \
	rcache_free_tmp(tmp_); \
}

// d != s
#define emith_eor_r_r_lsr(d, s, lsrimm) { \
	emith_push(s); \
	emith_lsr(s, s, lsrimm); \
	emith_eor_r_r(d, s); \
	emith_pop(s); \
}

// _r_imm
#define emith_move_r_imm(r, imm) { \
	EMIT_OP(0xb8 + (r)); \
	EMIT(imm, u32); \
}

#define emith_move_r_imm_s8(r, imm) \
	emith_move_r_imm(r, (u32)(signed int)(signed char)(imm))

#define emith_arith_r_imm(op, r, imm) { \
	EMIT_OP_MODRM(0x81, 3, op, r); \
	EMIT(imm, u32); \
}

// 2 - adc, 3 - sbb
#define emith_add_r_imm(r, imm) \
	emith_arith_r_imm(0, r, imm)

#define emith_or_r_imm(r, imm) \
	emith_arith_r_imm(1, r, imm)

#define emith_and_r_imm(r, imm) \
	emith_arith_r_imm(4, r, imm)

#define emith_sub_r_imm(r, imm) \
	emith_arith_r_imm(5, r, imm)

#define emith_eor_r_imm(r, imm) \
	emith_arith_r_imm(6, r, imm)

#define emith_cmp_r_imm(r, imm) \
	emith_arith_r_imm(7, r, imm)

#define emith_tst_r_imm(r, imm) { \
	EMIT_OP_MODRM(0xf7, 3, 0, r); \
	EMIT(imm, u32); \
}

// fake
#define emith_bic_r_imm(r, imm) \
	emith_arith_r_imm(4, r, ~(imm))

// fake conditionals (using SJMP instead)
#define emith_move_r_imm_c(cond, r, imm) { \
	(void)(cond); \
	emith_move_r_imm(r, imm); \
}

#define emith_add_r_imm_c(cond, r, imm) { \
	(void)(cond); \
	emith_add_r_imm(r, imm); \
}

#define emith_or_r_imm_c(cond, r, imm) { \
	(void)(cond); \
	emith_or_r_imm(r, imm); \
}

#define emith_eor_r_imm_c(cond, r, imm) { \
	(void)(cond); \
	emith_eor_r_imm(r, imm); \
}

#define emith_sub_r_imm_c(cond, r, imm) { \
	(void)(cond); \
	emith_sub_r_imm(r, imm); \
}

#define emith_bic_r_imm_c(cond, r, imm) { \
	(void)(cond); \
	emith_bic_r_imm(r, imm); \
}

// _r_r_imm
#define emith_and_r_r_imm(d, s, imm) { \
	if (d != s) \
		emith_move_r_r(d, s); \
	emith_and_r_imm(d, imm) \
}

// shift
#define emith_shift(op, d, s, cnt) { \
	if (d != s) \
		emith_move_r_r(d, s); \
	EMIT_OP_MODRM(0xc1, 3, op, d); \
	EMIT(cnt, u8); \
}

#define emith_lsl(d, s, cnt) \
	emith_shift(4, d, s, cnt)

#define emith_lsr(d, s, cnt) \
	emith_shift(5, d, s, cnt)

#define emith_asr(d, s, cnt) \
	emith_shift(7, d, s, cnt)

#define emith_rol(d, s, cnt) \
	emith_shift(0, d, s, cnt)

#define emith_ror(d, s, cnt) \
	emith_shift(1, d, s, cnt)

#define emith_rolc(r) \
	EMIT_OP_MODRM(0xd1, 3, 2, r)

#define emith_rorc(r) \
	EMIT_OP_MODRM(0xd1, 3, 3, r)

// misc
#define emith_push(r) \
	EMIT_OP(0x50 + (r))

#define emith_pop(r) \
	EMIT_OP(0x58 + (r))

#define emith_neg_r(r) \
	EMIT_OP_MODRM(0xf7, 3, 3, r)

#define emith_clear_msb(d, s, count) { \
	u32 t = (u32)-1; \
	t >>= count; \
	if (d != s) \
		emith_move_r_r(d, s); \
	emith_and_r_imm(d, t); \
}

#define emith_clear_msb_c(cond, d, s, count) { \
	(void)(cond); \
	emith_clear_msb(d, s, count); \
}

#define emith_sext(d, s, bits) { \
	emith_lsl(d, s, 32 - (bits)); \
	emith_asr(d, d, 32 - (bits)); \
}

#define emith_setc(r) { \
	EMIT_OP(0x0f); \
	EMIT_OP_MODRM(0x92, 3, 0, r); /* SETC r */ \
}

// XXX: stupid mess
#define emith_mul_(op, dlo, dhi, s1, s2) { \
	int rmr; \
	if (dlo != xAX && dhi != xAX) \
		emith_push(xAX); \
	if (dlo != xDX && dhi != xDX) \
		emith_push(xDX); \
	if ((s1) == xAX) \
		rmr = s2; \
	else if ((s2) == xAX) \
		rmr = s1; \
	else { \
		emith_move_r_r(xAX, s1); \
		rmr = s2; \
	} \
	EMIT_OP_MODRM(0xf7, 3, op, rmr); /* xMUL rmr */ \
	/* XXX: using push/pop for the case of edx->eax; eax->edx */ \
	if (dhi != xDX && dhi != -1) \
		emith_push(xDX); \
	if (dlo != xAX) \
		emith_move_r_r(dlo, xAX); \
	if (dhi != xDX && dhi != -1) \
		emith_pop(dhi); \
	if (dlo != xDX && dhi != xDX) \
		emith_pop(xDX); \
	if (dlo != xAX && dhi != xAX) \
		emith_pop(xAX); \
}

#define emith_mul_u64(dlo, dhi, s1, s2) \
	emith_mul_(4, dlo, dhi, s1, s2) /* MUL */

#define emith_mul_s64(dlo, dhi, s1, s2) \
	emith_mul_(5, dlo, dhi, s1, s2) /* IMUL */

#define emith_mul(d, s1, s2) \
	emith_mul_(4, d, -1, s1, s2)

// (dlo,dhi) += signed(s1) * signed(s2)
#define emith_mula_s64(dlo, dhi, s1, s2) { \
	emith_push(dhi); \
	emith_push(dlo); \
	emith_mul_(5, dlo, dhi, s1, s2); \
	EMIT_OP_MODRM(0x03, 0, dlo, 4); \
	EMIT_SIB(0, 4, 4); /* add dlo, [esp] */ \
	EMIT_OP_MODRM(0x13, 1, dhi, 4); \
	EMIT_SIB(0, 4, 4); \
	EMIT(4, u8); /* adc dhi, [esp+4] */ \
	emith_add_r_imm(xSP, 4*2); \
}

// "flag" instructions are the same
#define emith_subf_r_imm emith_sub_r_imm
#define emith_addf_r_r   emith_add_r_r
#define emith_subf_r_r   emith_sub_r_r
#define emith_adcf_r_r   emith_adc_r_r
#define emith_sbcf_r_r   emith_sbc_r_r
#define emith_eorf_r_r   emith_eor_r_r
#define emith_negcf_r_r  emith_negc_r_r

#define emith_lslf  emith_lsl
#define emith_lsrf  emith_lsr
#define emith_asrf  emith_asr
#define emith_rolf  emith_rol
#define emith_rorf  emith_ror
#define emith_rolcf emith_rolc
#define emith_rorcf emith_rorc

// XXX: offs is 8bit only
#define emith_ctx_read(r, offs) do { \
	EMIT_OP_MODRM(0x8b, 1, r, xBP); \
	EMIT(offs, u8); 	/* mov tmp, [ebp+#offs] */ \
} while (0)

#define emith_ctx_read_multiple(r, offs, cnt, tmpr) do { \
	int r_ = r, offs_ = offs, cnt_ = cnt;     \
	for (; cnt_ > 0; r_++, offs_ += 4, cnt_--) \
		emith_ctx_read(r_, offs_);        \
} while (0)

#define emith_ctx_write(r, offs) do { \
	EMIT_OP_MODRM(0x89, 1, r, xBP); \
	EMIT(offs, u8); 	/* mov [ebp+#offs], tmp */ \
} while (0)

#define emith_ctx_write_multiple(r, offs, cnt, tmpr) do { \
	int r_ = r, offs_ = offs, cnt_ = cnt;     \
	for (; cnt_ > 0; r_++, offs_ += 4, cnt_--) \
		emith_ctx_write(r_, offs_);       \
} while (0)

#define emith_jump(ptr) { \
	u32 disp = (u32)ptr - ((u32)tcache_ptr + 5); \
	EMIT_OP(0xe9); \
	EMIT(disp, u32); \
}

#define emith_call(ptr) { \
	u32 disp = (u32)ptr - ((u32)tcache_ptr + 5); \
	EMIT_OP(0xe8); \
	EMIT(disp, u32); \
}

#define emith_call_cond(cond, ptr) \
	emith_call(ptr)

#define emith_jump_reg(r) \
	EMIT_OP_MODRM(0xff, 3, 4, r)

#define EMITH_JMP_START(cond) { \
	u8 *cond_ptr; \
	JMP8_POS(cond_ptr)

#define EMITH_JMP_END(cond) \
	JMP8_EMIT(cond, cond_ptr); \
}

// "simple" jump (no more then a few insns)
#define EMITH_SJMP_START EMITH_JMP_START
#define EMITH_SJMP_END EMITH_JMP_END

#define host_arg2reg(rd, arg) \
	switch (arg) { \
	case 0: rd = xAX; break; \
	case 1: rd = xDX; break; \
	case 2: rd = xCX; break; \
	}

#define emith_pass_arg_r(arg, reg) { \
	int rd = 7; \
	host_arg2reg(rd, arg); \
	emith_move_r_r(rd, reg); \
}

#define emith_pass_arg_imm(arg, imm) { \
	int rd = 7; \
	host_arg2reg(rd, arg); \
	emith_move_r_imm(rd, imm); \
}

/* SH2 drc specific */
#define emith_sh2_drc_entry() { \
	emith_push(xBX);        \
	emith_push(xBP);        \
	emith_push(xSI);        \
	emith_push(xDI);        \
}

#define emith_sh2_drc_exit() {  \
	emith_pop(xDI);         \
	emith_pop(xSI);         \
	emith_pop(xBP);         \
	emith_pop(xBX);         \
	EMIT_OP(0xc3); /* ret */\
}

#define emith_sh2_test_t() { \
	int t = rcache_get_reg(SHR_SR, RC_GR_READ); \
	EMIT(0x66, u8); \
	EMIT_OP_MODRM(0xf7, 3, 0, t); \
	EMIT(0x01, u16); /* test <reg>, word 1 */ \
}

#define emith_sh2_dtbf_loop() { \
	u8 *jmp0; /* negative cycles check */            \
	u8 *jmp1; /* unsinged overflow check */          \
	int cr, rn;                                      \
	int tmp_ = rcache_get_tmp();                     \
	cr = rcache_get_reg(SHR_SR, RC_GR_RMW);          \
	rn = rcache_get_reg((op >> 8) & 0x0f, RC_GR_RMW);\
	emith_sub_r_imm(rn, 1);                          \
	emith_sub_r_imm(cr, (cycles+1) << 12);           \
	cycles = 0;                                      \
	emith_asr(tmp_, cr, 2+12);                       \
	JMP8_POS(jmp0); /* no negative cycles */         \
	emith_move_r_imm(tmp_, 0);                       \
	JMP8_EMIT(IOP_JNS, jmp0);                        \
	emith_and_r_imm(cr, 0xffe);                      \
	emith_subf_r_r(rn, tmp_);                        \
	JMP8_POS(jmp1); /* no overflow */                \
	emith_neg_r(rn); /* count left */                \
	emith_lsl(rn, rn, 2+12);                         \
	emith_or_r_r(cr, rn);                            \
	emith_or_r_imm(cr, 1);                           \
	emith_move_r_imm(rn, 0);                         \
	JMP8_EMIT(IOP_JA, jmp1);                         \
	rcache_free_tmp(tmp_);                           \
}

#define emith_write_sr(srcr) { \
	int tmp_ = rcache_get_tmp(); \
	int srr = rcache_get_reg(SHR_SR, RC_GR_RMW); \
	emith_clear_msb(tmp_, srcr, 20); \
	emith_bic_r_imm(srr, 0xfff); \
	emith_or_r_r(srr, tmp_); \
	rcache_free_tmp(tmp_); \
}

#define emith_tpop_carry(sr, is_sub) \
	emith_lsr(sr, sr, 1)

#define emith_tpush_carry(sr, is_sub) \
	emith_adc_r_r(sr, sr)

/*
 * if Q
 *   t = carry(Rn += Rm)
 * else
 *   t = carry(Rn -= Rm)
 * T ^= t
 */
#define emith_sh2_div1_step(rn, rm, sr) {         \
	u8 *jmp0, *jmp1;                          \
	int tmp_ = rcache_get_tmp();              \
	emith_eor_r_r(tmp_, tmp_);                \
	emith_tst_r_imm(sr, Q);  /* if (Q ^ M) */ \
	JMP8_POS(jmp0);          /* je do_sub */  \
	emith_add_r_r(rn, rm);                    \
	JMP8_POS(jmp1);          /* jmp done */   \
	JMP8_EMIT(IOP_JE, jmp0); /* do_sub: */    \
	emith_sub_r_r(rn, rm);                    \
	JMP8_EMIT(IOP_JMP, jmp1);/* done: */      \
	emith_setc(tmp_);                         \
	EMIT_OP_MODRM(0x31, 3, tmp_, sr); /* T = Q1 ^ Q2 */ \
	rcache_free_tmp(tmp_);                    \
}
Commit	Line	Data
3863edbd	1	/*
8b4f38f4	2	* note:
8b4f38f4	3	* temp registers must be eax-edx due to use of SETcc.
f0d7b1fa	4	* note about silly things like emith_eor_r_r_r:
8b4f38f4	5	* these are here because the compiler was designed
8b4f38f4	6	* for ARM as it's primary target.
3863edbd	7	*/
679af8a3	8	#include <stdarg.h>
679af8a3	9
f4bb5d6b	10	enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
f4bb5d6b	11
f4bb5d6b	12	#define CONTEXT_REG xBP
679af8a3	13
f0d7b1fa	14	#define IOP_JMP 0xeb
3863edbd	15	#define IOP_JO 0x70
	16	#define IOP_JNO 0x71
	17	#define IOP_JB 0x72
	18	#define IOP_JAE 0x73
80599a42	19	#define IOP_JE 0x74
	20	#define IOP_JNE 0x75
	21	#define IOP_JBE 0x76
	22	#define IOP_JA 0x77
	23	#define IOP_JS 0x78
	24	#define IOP_JNS 0x79
3863edbd	25	#define IOP_JL 0x7c
3863edbd	26	#define IOP_JGE 0x7d
80599a42	27	#define IOP_JLE 0x7e
3863edbd	28	#define IOP_JG 0x7f
80599a42	29
	30	// unified conditions (we just use rel8 jump instructions for x86)
	31	#define DCOND_EQ IOP_JE
	32	#define DCOND_NE IOP_JNE
	33	#define DCOND_MI IOP_JS // MInus
	34	#define DCOND_PL IOP_JNS // PLus or zero
3863edbd	35	#define DCOND_HI IOP_JA // higher (unsigned)
	36	#define DCOND_HS IOP_JAE // higher \|\| same (unsigned)
	37	#define DCOND_LO IOP_JB // lower (unsigned)
	38	#define DCOND_LS IOP_JBE // lower \|\| same (unsigned)
	39	#define DCOND_GE IOP_JGE // greater \|\| equal (signed)
	40	#define DCOND_GT IOP_JG // greater (signed)
	41	#define DCOND_LE IOP_JLE // less \|\| equal (signed)
	42	#define DCOND_LT IOP_JL // less (signed)
	43	#define DCOND_VS IOP_JO // oVerflow Set
	44	#define DCOND_VC IOP_JNO // oVerflow Clear
80599a42	45
679af8a3	46	#define EMIT_PTR(ptr, val, type) \
	47	(type )(ptr) = val
	48
	49	#define EMIT(val, type) { \
	50	EMIT_PTR(tcache_ptr, val, type); \
f4bb5d6b	51	tcache_ptr += sizeof(type); \
679af8a3	52	}
679af8a3	53
e898de13	54	#define EMIT_OP(op) { \
	55	COUNT_OP; \
	56	EMIT(op, u8); \
	57	}
	58
679af8a3	59	#define EMIT_MODRM(mod,r,rm) \
	60	EMIT(((mod)<<6) \| ((r)<<3) \| (rm), u8)
	61
f0d7b1fa	62	#define EMIT_SIB(scale,index,base) \
	63	EMIT(((scale)<<6) \| ((index)<<3) \| (base), u8)
	64
679af8a3	65	#define EMIT_OP_MODRM(op,mod,r,rm) { \
e898de13	66	EMIT_OP(op); \
679af8a3	67	EMIT_MODRM(mod, r, rm); \
	68	}
	69
80599a42	70	#define JMP8_POS(ptr) \
	71	ptr = tcache_ptr; \
	72	tcache_ptr += 2
	73
	74	#define JMP8_EMIT(op, ptr) \
	75	EMIT_PTR(ptr, op, u8); \
	76	EMIT_PTR(ptr + 1, (tcache_ptr - (ptr+2)), u8)
	77
3863edbd	78	// _r_r
679af8a3	79	#define emith_move_r_r(dst, src) \
	80	EMIT_OP_MODRM(0x8b, 3, dst, src)
	81
80599a42	82	#define emith_add_r_r(d, s) \
	83	EMIT_OP_MODRM(0x01, 3, s, d)
	84
	85	#define emith_sub_r_r(d, s) \
	86	EMIT_OP_MODRM(0x29, 3, s, d)
	87
3863edbd	88	#define emith_adc_r_r(d, s) \
	89	EMIT_OP_MODRM(0x11, 3, s, d)
	90
	91	#define emith_sbc_r_r(d, s) \
	92	EMIT_OP_MODRM(0x19, 3, s, d) /* SBB */
	93
80599a42	94	#define emith_or_r_r(d, s) \
	95	EMIT_OP_MODRM(0x09, 3, s, d)
	96
3863edbd	97	#define emith_and_r_r(d, s) \
	98	EMIT_OP_MODRM(0x21, 3, s, d)
	99
80599a42	100	#define emith_eor_r_r(d, s) \
3863edbd	101	EMIT_OP_MODRM(0x31, 3, s, d) /* XOR */
	102
	103	#define emith_tst_r_r(d, s) \
	104	EMIT_OP_MODRM(0x85, 3, s, d) /* TEST */
	105
	106	#define emith_cmp_r_r(d, s) \
	107	EMIT_OP_MODRM(0x39, 3, s, d)
80599a42	108
	109	// fake teq - test equivalence - get_flags(d ^ s)
	110	#define emith_teq_r_r(d, s) { \
	111	emith_push(d); \
	112	emith_eor_r_r(d, s); \
	113	emith_pop(d); \
	114	}
	115
52d759c3	116	#define emith_mvn_r_r(d, s) { \
	117	if (d != s) \
	118	emith_move_r_r(d, s); \
	119	EMIT_OP_MODRM(0xf7, 3, 2, d); /* NOT d */ \
	120	}
	121
	122	#define emith_negc_r_r(d, s) { \
	123	int tmp_ = rcache_get_tmp(); \
	124	emith_move_r_imm(tmp_, 0); \
	125	emith_sbc_r_r(tmp_, s); \
	126	emith_move_r_r(d, tmp_); \
	127	rcache_free_tmp(tmp_); \
	128	}
	129
	130	#define emith_neg_r_r(d, s) { \
	131	if (d != s) \
	132	emith_move_r_r(d, s); \
	133	EMIT_OP_MODRM(0xf7, 3, 3, d); /* NEG d */ \
	134	}
	135
3863edbd	136	// _r_r_r
3863edbd	137	#define emith_eor_r_r_r(d, s1, s2) { \
52d759c3	138	if (d == s1) { \
	139	emith_eor_r_r(d, s2); \
	140	} else if (d == s2) { \
	141	emith_eor_r_r(d, s1); \
	142	} else { \
3863edbd	143	emith_move_r_r(d, s1); \
52d759c3	144	emith_eor_r_r(d, s2); \
52d759c3	145	} \
3863edbd	146	}
3863edbd	147
f0d7b1fa	148	// _r_r_shift
f0d7b1fa	149	#define emith_or_r_r_lsl(d, s, lslimm) { \
52d759c3	150	int tmp_ = rcache_get_tmp(); \
f0d7b1fa	151	emith_lsl(tmp_, s, lslimm); \
f0d7b1fa	152	emith_or_r_r(d, tmp_); \
52d759c3	153	rcache_free_tmp(tmp_); \
3863edbd	154	}
3863edbd	155
f0d7b1fa	156	// d != s
	157	#define emith_eor_r_r_lsr(d, s, lsrimm) { \
	158	emith_push(s); \
	159	emith_lsr(s, s, lsrimm); \
	160	emith_eor_r_r(d, s); \
	161	emith_pop(s); \
	162	}
	163
80599a42	164	// _r_imm
679af8a3	165	#define emith_move_r_imm(r, imm) { \
e898de13	166	EMIT_OP(0xb8 + (r)); \
679af8a3	167	EMIT(imm, u32); \
	168	}
	169
52d759c3	170	#define emith_move_r_imm_s8(r, imm) \
	171	emith_move_r_imm(r, (u32)(signed int)(signed char)(imm))
	172
80599a42	173	#define emith_arith_r_imm(op, r, imm) { \
80599a42	174	EMIT_OP_MODRM(0x81, 3, op, r); \
679af8a3	175	EMIT(imm, u32); \
	176	}
	177
52d759c3	178	// 2 - adc, 3 - sbb
80599a42	179	#define emith_add_r_imm(r, imm) \
	180	emith_arith_r_imm(0, r, imm)
	181
	182	#define emith_or_r_imm(r, imm) \
	183	emith_arith_r_imm(1, r, imm)
	184
	185	#define emith_and_r_imm(r, imm) \
	186	emith_arith_r_imm(4, r, imm)
	187
	188	#define emith_sub_r_imm(r, imm) \
	189	emith_arith_r_imm(5, r, imm)
	190
52d759c3	191	#define emith_eor_r_imm(r, imm) \
	192	emith_arith_r_imm(6, r, imm)
	193
ed8cf79b	194	#define emith_cmp_r_imm(r, imm) \
	195	emith_arith_r_imm(7, r, imm)
	196
80599a42	197	#define emith_tst_r_imm(r, imm) { \
80599a42	198	EMIT_OP_MODRM(0xf7, 3, 0, r); \
679af8a3	199	EMIT(imm, u32); \
	200	}
	201
80599a42	202	// fake
	203	#define emith_bic_r_imm(r, imm) \
	204	emith_arith_r_imm(4, r, ~(imm))
	205
	206	// fake conditionals (using SJMP instead)
8796b7ee	207	#define emith_move_r_imm_c(cond, r, imm) { \
	208	(void)(cond); \
	209	emith_move_r_imm(r, imm); \
	210	}
	211
80599a42	212	#define emith_add_r_imm_c(cond, r, imm) { \
80599a42	213	(void)(cond); \
3863edbd	214	emith_add_r_imm(r, imm); \
80599a42	215	}
	216
	217	#define emith_or_r_imm_c(cond, r, imm) { \
	218	(void)(cond); \
3863edbd	219	emith_or_r_imm(r, imm); \
80599a42	220	}
80599a42	221
f0d7b1fa	222	#define emith_eor_r_imm_c(cond, r, imm) { \
	223	(void)(cond); \
	224	emith_eor_r_imm(r, imm); \
	225	}
	226
80599a42	227	#define emith_sub_r_imm_c(cond, r, imm) { \
80599a42	228	(void)(cond); \
3863edbd	229	emith_sub_r_imm(r, imm); \
	230	}
	231
	232	#define emith_bic_r_imm_c(cond, r, imm) { \
	233	(void)(cond); \
	234	emith_bic_r_imm(r, imm); \
80599a42	235	}
80599a42	236
52d759c3	237	// _r_r_imm
	238	#define emith_and_r_r_imm(d, s, imm) { \
	239	if (d != s) \
	240	emith_move_r_r(d, s); \
	241	emith_and_r_imm(d, imm) \
	242	}
	243
80599a42	244	// shift
	245	#define emith_shift(op, d, s, cnt) { \
	246	if (d != s) \
	247	emith_move_r_r(d, s); \
	248	EMIT_OP_MODRM(0xc1, 3, op, d); \
	249	EMIT(cnt, u8); \
	250	}
	251
80599a42	252	#define emith_lsl(d, s, cnt) \
	253	emith_shift(4, d, s, cnt)
	254
3863edbd	255	#define emith_lsr(d, s, cnt) \
	256	emith_shift(5, d, s, cnt)
	257
	258	#define emith_asr(d, s, cnt) \
	259	emith_shift(7, d, s, cnt)
	260
ed8cf79b	261	#define emith_rol(d, s, cnt) \
	262	emith_shift(0, d, s, cnt)
	263
	264	#define emith_ror(d, s, cnt) \
	265	emith_shift(1, d, s, cnt)
	266
	267	#define emith_rolc(r) \
	268	EMIT_OP_MODRM(0xd1, 3, 2, r)
	269
	270	#define emith_rorc(r) \
	271	EMIT_OP_MODRM(0xd1, 3, 3, r)
	272
80599a42	273	// misc
	274	#define emith_push(r) \
	275	EMIT_OP(0x50 + (r))
	276
	277	#define emith_pop(r) \
	278	EMIT_OP(0x58 + (r))
	279
	280	#define emith_neg_r(r) \
	281	EMIT_OP_MODRM(0xf7, 3, 3, r)
	282
	283	#define emith_clear_msb(d, s, count) { \
	284	u32 t = (u32)-1; \
	285	t >>= count; \
	286	if (d != s) \
	287	emith_move_r_r(d, s); \
	288	emith_and_r_imm(d, t); \
	289	}
	290
f0d7b1fa	291	#define emith_clear_msb_c(cond, d, s, count) { \
	292	(void)(cond); \
	293	emith_clear_msb(d, s, count); \
	294	}
	295
80599a42	296	#define emith_sext(d, s, bits) { \
	297	emith_lsl(d, s, 32 - (bits)); \
	298	emith_asr(d, d, 32 - (bits)); \
	299	}
	300
f0d7b1fa	301	#define emith_setc(r) { \
f0d7b1fa	302	EMIT_OP(0x0f); \
8b4f38f4	303	EMIT_OP_MODRM(0x92, 3, 0, r); /* SETC r */ \
f0d7b1fa	304	}
f0d7b1fa	305
80599a42	306	// XXX: stupid mess
3863edbd	307	#define emith_mul_(op, dlo, dhi, s1, s2) { \
80599a42	308	int rmr; \
3863edbd	309	if (dlo != xAX && dhi != xAX) \
80599a42	310	emith_push(xAX); \
3863edbd	311	if (dlo != xDX && dhi != xDX) \
3863edbd	312	emith_push(xDX); \
80599a42	313	if ((s1) == xAX) \
	314	rmr = s2; \
	315	else if ((s2) == xAX) \
	316	rmr = s1; \
	317	else { \
	318	emith_move_r_r(xAX, s1); \
	319	rmr = s2; \
	320	} \
3863edbd	321	EMIT_OP_MODRM(0xf7, 3, op, rmr); /* xMUL rmr */ \
	322	/* XXX: using push/pop for the case of edx->eax; eax->edx */ \
	323	if (dhi != xDX && dhi != -1) \
	324	emith_push(xDX); \
	325	if (dlo != xAX) \
	326	emith_move_r_r(dlo, xAX); \
	327	if (dhi != xDX && dhi != -1) \
	328	emith_pop(dhi); \
	329	if (dlo != xDX && dhi != xDX) \
	330	emith_pop(xDX); \
	331	if (dlo != xAX && dhi != xAX) \
80599a42	332	emith_pop(xAX); \
80599a42	333	}
80599a42	334
3863edbd	335	#define emith_mul_u64(dlo, dhi, s1, s2) \
	336	emith_mul_(4, dlo, dhi, s1, s2) /* MUL */
	337
	338	#define emith_mul_s64(dlo, dhi, s1, s2) \
	339	emith_mul_(5, dlo, dhi, s1, s2) /* IMUL */
	340
	341	#define emith_mul(d, s1, s2) \
	342	emith_mul_(4, d, -1, s1, s2)
	343
f0d7b1fa	344	// (dlo,dhi) += signed(s1) * signed(s2)
	345	#define emith_mula_s64(dlo, dhi, s1, s2) { \
	346	emith_push(dhi); \
	347	emith_push(dlo); \
	348	emith_mul_(5, dlo, dhi, s1, s2); \
	349	EMIT_OP_MODRM(0x03, 0, dlo, 4); \
	350	EMIT_SIB(0, 4, 4); /* add dlo, [esp] */ \
	351	EMIT_OP_MODRM(0x13, 1, dhi, 4); \
	352	EMIT_SIB(0, 4, 4); \
	353	EMIT(4, u8); /* adc dhi, [esp+4] */ \
	354	emith_add_r_imm(xSP, 4*2); \
	355	}
	356
80599a42	357	// "flag" instructions are the same
80599a42	358	#define emith_subf_r_imm emith_sub_r_imm
3863edbd	359	#define emith_addf_r_r emith_add_r_r
80599a42	360	#define emith_subf_r_r emith_sub_r_r
3863edbd	361	#define emith_adcf_r_r emith_adc_r_r
3863edbd	362	#define emith_sbcf_r_r emith_sbc_r_r
8796b7ee	363	#define emith_eorf_r_r emith_eor_r_r
52d759c3	364	#define emith_negcf_r_r emith_negc_r_r
3863edbd	365
ed8cf79b	366	#define emith_lslf emith_lsl
	367	#define emith_lsrf emith_lsr
	368	#define emith_asrf emith_asr
	369	#define emith_rolf emith_rol
	370	#define emith_rorf emith_ror
	371	#define emith_rolcf emith_rolc
	372	#define emith_rorcf emith_rorc
80599a42	373
679af8a3	374	// XXX: offs is 8bit only
8796b7ee	375	#define emith_ctx_read(r, offs) do { \
65c75cb0	376	EMIT_OP_MODRM(0x8b, 1, r, xBP); \
679af8a3	377	EMIT(offs, u8); /* mov tmp, [ebp+#offs] */ \
8796b7ee	378	} while (0)
679af8a3	379
8796b7ee	380	#define emith_ctx_read_multiple(r, offs, cnt, tmpr) do { \
8796b7ee	381	int r_ = r, offs_ = offs, cnt_ = cnt; \
8b4f38f4	382	for (; cnt_ > 0; r_++, offs_ += 4, cnt_--) \
8796b7ee	383	emith_ctx_read(r_, offs_); \
	384	} while (0)
	385
	386	#define emith_ctx_write(r, offs) do { \
65c75cb0	387	EMIT_OP_MODRM(0x89, 1, r, xBP); \
679af8a3	388	EMIT(offs, u8); /* mov [ebp+#offs], tmp */ \
8796b7ee	389	} while (0)
	390
	391	#define emith_ctx_write_multiple(r, offs, cnt, tmpr) do { \
	392	int r_ = r, offs_ = offs, cnt_ = cnt; \
8b4f38f4	393	for (; cnt_ > 0; r_++, offs_ += 4, cnt_--) \
8796b7ee	394	emith_ctx_write(r_, offs_); \
8796b7ee	395	} while (0)
679af8a3	396
679af8a3	397	#define emith_jump(ptr) { \
679af8a3	398	u32 disp = (u32)ptr - ((u32)tcache_ptr + 5); \
e898de13	399	EMIT_OP(0xe9); \
679af8a3	400	EMIT(disp, u32); \
	401	}
	402
	403	#define emith_call(ptr) { \
	404	u32 disp = (u32)ptr - ((u32)tcache_ptr + 5); \
e898de13	405	EMIT_OP(0xe8); \
679af8a3	406	EMIT(disp, u32); \
	407	}
	408
f0d7b1fa	409	#define emith_call_cond(cond, ptr) \
	410	emith_call(ptr)
	411
8796b7ee	412	#define emith_jump_reg(r) \
	413	EMIT_OP_MODRM(0xff, 3, 4, r)
	414
	415	#define EMITH_JMP_START(cond) { \
80599a42	416	u8 *cond_ptr; \
	417	JMP8_POS(cond_ptr)
	418
8796b7ee	419	#define EMITH_JMP_END(cond) \
80599a42	420	JMP8_EMIT(cond, cond_ptr); \
679af8a3	421	}
679af8a3	422
8796b7ee	423	// "simple" jump (no more then a few insns)
	424	#define EMITH_SJMP_START EMITH_JMP_START
	425	#define EMITH_SJMP_END EMITH_JMP_END
	426
80599a42	427	#define host_arg2reg(rd, arg) \
f4bb5d6b	428	switch (arg) { \
	429	case 0: rd = xAX; break; \
	430	case 1: rd = xDX; break; \
	431	case 2: rd = xCX; break; \
679af8a3	432	}
679af8a3	433
f4bb5d6b	434	#define emith_pass_arg_r(arg, reg) { \
f4bb5d6b	435	int rd = 7; \
80599a42	436	host_arg2reg(rd, arg); \
f4bb5d6b	437	emith_move_r_r(rd, reg); \
	438	}
	439
	440	#define emith_pass_arg_imm(arg, imm) { \
	441	int rd = 7; \
80599a42	442	host_arg2reg(rd, arg); \
f4bb5d6b	443	emith_move_r_imm(rd, imm); \
679af8a3	444	}
679af8a3	445
65c75cb0	446	/* SH2 drc specific */
8796b7ee	447	#define emith_sh2_drc_entry() { \
	448	emith_push(xBX); \
	449	emith_push(xBP); \
8b4f38f4	450	emith_push(xSI); \
8b4f38f4	451	emith_push(xDI); \
8796b7ee	452	}
	453
	454	#define emith_sh2_drc_exit() { \
8b4f38f4	455	emith_pop(xDI); \
8b4f38f4	456	emith_pop(xSI); \
8796b7ee	457	emith_pop(xBP); \
	458	emith_pop(xBX); \
	459	EMIT_OP(0xc3); /* ret */\
	460	}
	461
80599a42	462	#define emith_sh2_test_t() { \
80599a42	463	int t = rcache_get_reg(SHR_SR, RC_GR_READ); \
8b4f38f4	464	EMIT(0x66, u8); \
	465	EMIT_OP_MODRM(0xf7, 3, 0, t); \
	466	EMIT(0x01, u16); /* test <reg>, word 1 */ \
80599a42	467	}
	468
	469	#define emith_sh2_dtbf_loop() { \
	470	u8 jmp0; / negative cycles check */ \
	471	u8 jmp1; / unsinged overflow check */ \
	472	int cr, rn; \
52d759c3	473	int tmp_ = rcache_get_tmp(); \
80599a42	474	cr = rcache_get_reg(SHR_SR, RC_GR_RMW); \
	475	rn = rcache_get_reg((op >> 8) & 0x0f, RC_GR_RMW);\
	476	emith_sub_r_imm(rn, 1); \
	477	emith_sub_r_imm(cr, (cycles+1) << 12); \
	478	cycles = 0; \
52d759c3	479	emith_asr(tmp_, cr, 2+12); \
80599a42	480	JMP8_POS(jmp0); /* no negative cycles */ \
52d759c3	481	emith_move_r_imm(tmp_, 0); \
80599a42	482	JMP8_EMIT(IOP_JNS, jmp0); \
80599a42	483	emith_and_r_imm(cr, 0xffe); \
52d759c3	484	emith_subf_r_r(rn, tmp_); \
80599a42	485	JMP8_POS(jmp1); /* no overflow */ \
	486	emith_neg_r(rn); /* count left */ \
	487	emith_lsl(rn, rn, 2+12); \
	488	emith_or_r_r(cr, rn); \
	489	emith_or_r_imm(cr, 1); \
	490	emith_move_r_imm(rn, 0); \
	491	JMP8_EMIT(IOP_JA, jmp1); \
52d759c3	492	rcache_free_tmp(tmp_); \
65c75cb0	493	}
65c75cb0	494
ed8cf79b	495	#define emith_write_sr(srcr) { \
52d759c3	496	int tmp_ = rcache_get_tmp(); \
ed8cf79b	497	int srr = rcache_get_reg(SHR_SR, RC_GR_RMW); \
52d759c3	498	emith_clear_msb(tmp_, srcr, 20); \
ed8cf79b	499	emith_bic_r_imm(srr, 0xfff); \
52d759c3	500	emith_or_r_r(srr, tmp_); \
52d759c3	501	rcache_free_tmp(tmp_); \
ed8cf79b	502	}
ed8cf79b	503
8b4f38f4	504	#define emith_tpop_carry(sr, is_sub) \
	505	emith_lsr(sr, sr, 1)
	506
	507	#define emith_tpush_carry(sr, is_sub) \
	508	emith_adc_r_r(sr, sr)
ed8cf79b	509
f0d7b1fa	510	/*
	511	* if Q
	512	* t = carry(Rn += Rm)
	513	* else
	514	* t = carry(Rn -= Rm)
	515	* T ^= t
	516	*/
	517	#define emith_sh2_div1_step(rn, rm, sr) { \
	518	u8 jmp0, jmp1; \
	519	int tmp_ = rcache_get_tmp(); \
8b4f38f4	520	emith_eor_r_r(tmp_, tmp_); \
f0d7b1fa	521	emith_tst_r_imm(sr, Q); /* if (Q ^ M) */ \
	522	JMP8_POS(jmp0); /* je do_sub */ \
	523	emith_add_r_r(rn, rm); \
	524	JMP8_POS(jmp1); /* jmp done */ \
	525	JMP8_EMIT(IOP_JE, jmp0); /* do_sub: */ \
	526	emith_sub_r_r(rn, rm); \
	527	JMP8_EMIT(IOP_JMP, jmp1);/* done: */ \
	528	emith_setc(tmp_); \
8b4f38f4	529	EMIT_OP_MODRM(0x31, 3, tmp_, sr); /* T = Q1 ^ Q2 */ \
f0d7b1fa	530	rcache_free_tmp(tmp_); \
	531	}
	532