[picodrive.git] / cpu / drc / emit_x86.c

/*
 * Basic macros to emit x86 instructions and some utils
 * Copyright (C) 2008,2009,2010 notaz
 *
 * This work is licensed under the terms of MAME license.
 * See COPYING file in the top-level directory.
 *
 * note:
 *  temp registers must be eax-edx due to use of SETcc and r/w 8/16.
 * note about silly things like emith_eor_r_r_r:
 *  these are here because the compiler was designed
 *  for ARM as it's primary target.
 */
#include <stdarg.h>

enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };

#define CONTEXT_REG xBP

#define ICOND_JO  0x00
#define ICOND_JNO 0x01
#define ICOND_JB  0x02
#define ICOND_JAE 0x03
#define ICOND_JE  0x04
#define ICOND_JNE 0x05
#define ICOND_JBE 0x06
#define ICOND_JA  0x07
#define ICOND_JS  0x08
#define ICOND_JNS 0x09
#define ICOND_JL  0x0c
#define ICOND_JGE 0x0d
#define ICOND_JLE 0x0e
#define ICOND_JG  0x0f

#define IOP_JMP   0xeb

// unified conditions (we just use rel8 jump instructions for x86)
#define DCOND_EQ ICOND_JE
#define DCOND_NE ICOND_JNE
#define DCOND_MI ICOND_JS      // MInus
#define DCOND_PL ICOND_JNS     // PLus or zero
#define DCOND_HI ICOND_JA      // higher (unsigned)
#define DCOND_HS ICOND_JAE     // higher || same (unsigned)
#define DCOND_LO ICOND_JB      // lower (unsigned)
#define DCOND_LS ICOND_JBE     // lower || same (unsigned)
#define DCOND_GE ICOND_JGE     // greater || equal (signed)
#define DCOND_GT ICOND_JG      // greater (signed)
#define DCOND_LE ICOND_JLE     // less || equal (signed)
#define DCOND_LT ICOND_JL      // less (signed)
#define DCOND_VS ICOND_JO      // oVerflow Set
#define DCOND_VC ICOND_JNO     // oVerflow Clear

#define EMIT_PTR(ptr, val, type) \
	*(type *)(ptr) = val

#define EMIT(val, type) { \
	EMIT_PTR(tcache_ptr, val, type); \
	tcache_ptr += sizeof(type); \
}

#define EMIT_OP(op) { \
	COUNT_OP; \
	EMIT(op, u8); \
}

#define EMIT_MODRM(mod,r,rm) \
	EMIT(((mod)<<6) | ((r)<<3) | (rm), u8)

#define EMIT_SIB(scale,index,base) \
	EMIT(((scale)<<6) | ((index)<<3) | (base), u8)

#define EMIT_OP_MODRM(op,mod,r,rm) do { \
	EMIT_OP(op); \
	EMIT_MODRM(mod, r, rm); \
} while (0)

#define JMP8_POS(ptr) \
	ptr = tcache_ptr; \
	tcache_ptr += 2

#define JMP8_EMIT(op, ptr) \
	EMIT_PTR(ptr, 0x70|(op), u8); \
	EMIT_PTR(ptr + 1, (tcache_ptr - (ptr+2)), u8)

#define JMP8_EMIT_NC(ptr) \
	EMIT_PTR(ptr, IOP_JMP, u8); \
	EMIT_PTR(ptr + 1, (tcache_ptr - (ptr+2)), u8)

// _r_r
#define emith_move_r_r(dst, src) \
	EMIT_OP_MODRM(0x8b, 3, dst, src)

#define emith_add_r_r(d, s) \
	EMIT_OP_MODRM(0x01, 3, s, d)

#define emith_sub_r_r(d, s) \
	EMIT_OP_MODRM(0x29, 3, s, d)

#define emith_adc_r_r(d, s) \
	EMIT_OP_MODRM(0x11, 3, s, d)

#define emith_sbc_r_r(d, s) \
	EMIT_OP_MODRM(0x19, 3, s, d) /* SBB */

#define emith_or_r_r(d, s) \
	EMIT_OP_MODRM(0x09, 3, s, d)

#define emith_and_r_r(d, s) \
	EMIT_OP_MODRM(0x21, 3, s, d)

#define emith_eor_r_r(d, s) \
	EMIT_OP_MODRM(0x31, 3, s, d) /* XOR */

#define emith_tst_r_r(d, s) \
	EMIT_OP_MODRM(0x85, 3, s, d) /* TEST */

#define emith_cmp_r_r(d, s) \
	EMIT_OP_MODRM(0x39, 3, s, d)

// fake teq - test equivalence - get_flags(d ^ s)
#define emith_teq_r_r(d, s) { \
	emith_push(d); \
	emith_eor_r_r(d, s); \
	emith_pop(d); \
}

#define emith_mvn_r_r(d, s) { \
	if (d != s) \
		emith_move_r_r(d, s); \
	EMIT_OP_MODRM(0xf7, 3, 2, d); /* NOT d */ \
}

#define emith_negc_r_r(d, s) { \
	int tmp_ = rcache_get_tmp(); \
	emith_move_r_imm(tmp_, 0); \
	emith_sbc_r_r(tmp_, s); \
	emith_move_r_r(d, tmp_); \
	rcache_free_tmp(tmp_); \
}

#define emith_neg_r_r(d, s) { \
	if (d != s) \
		emith_move_r_r(d, s); \
	EMIT_OP_MODRM(0xf7, 3, 3, d); /* NEG d */ \
}

// _r_r_r
#define emith_eor_r_r_r(d, s1, s2) { \
	if (d == s1) { \
		emith_eor_r_r(d, s2); \
	} else if (d == s2) { \
		emith_eor_r_r(d, s1); \
	} else { \
		emith_move_r_r(d, s1); \
		emith_eor_r_r(d, s2); \
	} \
}

// _r_r_shift
#define emith_or_r_r_lsl(d, s, lslimm) { \
	int tmp_ = rcache_get_tmp(); \
	emith_lsl(tmp_, s, lslimm); \
	emith_or_r_r(d, tmp_); \
	rcache_free_tmp(tmp_); \
}

// d != s
#define emith_eor_r_r_lsr(d, s, lsrimm) { \
	emith_push(s); \
	emith_lsr(s, s, lsrimm); \
	emith_eor_r_r(d, s); \
	emith_pop(s); \
}

// _r_imm
#define emith_move_r_imm(r, imm) { \
	EMIT_OP(0xb8 + (r)); \
	EMIT(imm, u32); \
}

#define emith_move_r_imm_s8(r, imm) \
	emith_move_r_imm(r, (u32)(signed int)(signed char)(imm))

#define emith_arith_r_imm(op, r, imm) do { \
	EMIT_OP_MODRM(0x81, 3, op, r); \
	EMIT(imm, u32); \
} while (0)

#define emith_add_r_imm(r, imm) \
	emith_arith_r_imm(0, r, imm)

#define emith_or_r_imm(r, imm) \
	emith_arith_r_imm(1, r, imm)

#define emith_adc_r_imm(r, imm) \
	emith_arith_r_imm(2, r, imm)

#define emith_sbc_r_imm(r, imm) \
	emith_arith_r_imm(3, r, imm) // sbb

#define emith_and_r_imm(r, imm) \
	emith_arith_r_imm(4, r, imm)

#define emith_sub_r_imm(r, imm) \
	emith_arith_r_imm(5, r, imm)

#define emith_eor_r_imm(r, imm) \
	emith_arith_r_imm(6, r, imm)

#define emith_cmp_r_imm(r, imm) \
	emith_arith_r_imm(7, r, imm)

#define emith_tst_r_imm(r, imm) do { \
	EMIT_OP_MODRM(0xf7, 3, 0, r); \
	EMIT(imm, u32); \
} while (0)

// fake
#define emith_bic_r_imm(r, imm) \
	emith_arith_r_imm(4, r, ~(imm))

// fake conditionals (using SJMP instead)
#define emith_move_r_imm_c(cond, r, imm) { \
	(void)(cond); \
	emith_move_r_imm(r, imm); \
}

#define emith_add_r_imm_c(cond, r, imm) { \
	(void)(cond); \
	emith_add_r_imm(r, imm); \
}

#define emith_sub_r_imm_c(cond, r, imm) { \
	(void)(cond); \
	emith_sub_r_imm(r, imm); \
}

#define emith_or_r_imm_c(cond, r, imm) \
	emith_or_r_imm(r, imm)
#define emith_eor_r_imm_c(cond, r, imm) \
	emith_eor_r_imm(r, imm)
#define emith_bic_r_imm_c(cond, r, imm) \
	emith_bic_r_imm(r, imm)
#define emith_ror_c(cond, d, s, cnt) \
	emith_ror(d, s, cnt)

#define emith_read_r_r_offs_c(cond, r, rs, offs) \
	emith_read_r_r_offs(r, rs, offs)
#define emith_write_r_r_offs_c(cond, r, rs, offs) \
	emith_write_r_r_offs(r, rs, offs)
#define emith_read8_r_r_offs_c(cond, r, rs, offs) \
	emith_read8_r_r_offs(r, rs, offs)
#define emith_write8_r_r_offs_c(cond, r, rs, offs) \
	emith_write8_r_r_offs(r, rs, offs)
#define emith_read16_r_r_offs_c(cond, r, rs, offs) \
	emith_read16_r_r_offs(r, rs, offs)
#define emith_write16_r_r_offs_c(cond, r, rs, offs) \
	emith_write16_r_r_offs(r, rs, offs)
#define emith_jump_reg_c(cond, r) \
	emith_jump_reg(r)
#define emith_jump_ctx_c(cond, offs) \
	emith_jump_ctx(offs)
#define emith_ret_c(cond) \
	emith_ret()

// _r_r_imm
#define emith_add_r_r_imm(d, s, imm) { \
	if (d != s) \
		emith_move_r_r(d, s); \
	emith_add_r_imm(d, imm); \
}

#define emith_and_r_r_imm(d, s, imm) { \
	if (d != s) \
		emith_move_r_r(d, s); \
	emith_and_r_imm(d, imm); \
}

// shift
#define emith_shift(op, d, s, cnt) { \
	if (d != s) \
		emith_move_r_r(d, s); \
	EMIT_OP_MODRM(0xc1, 3, op, d); \
	EMIT(cnt, u8); \
}

#define emith_lsl(d, s, cnt) \
	emith_shift(4, d, s, cnt)

#define emith_lsr(d, s, cnt) \
	emith_shift(5, d, s, cnt)

#define emith_asr(d, s, cnt) \
	emith_shift(7, d, s, cnt)

#define emith_rol(d, s, cnt) \
	emith_shift(0, d, s, cnt)

#define emith_ror(d, s, cnt) \
	emith_shift(1, d, s, cnt)

#define emith_rolc(r) \
	EMIT_OP_MODRM(0xd1, 3, 2, r)

#define emith_rorc(r) \
	EMIT_OP_MODRM(0xd1, 3, 3, r)

// misc
#define emith_push(r) \
	EMIT_OP(0x50 + (r))

#define emith_push_imm(imm) { \
	EMIT_OP(0x68); \
	EMIT(imm, u32); \
}

#define emith_pop(r) \
	EMIT_OP(0x58 + (r))

#define emith_neg_r(r) \
	EMIT_OP_MODRM(0xf7, 3, 3, r)

#define emith_clear_msb(d, s, count) { \
	u32 t = (u32)-1; \
	t >>= count; \
	if (d != s) \
		emith_move_r_r(d, s); \
	emith_and_r_imm(d, t); \
}

#define emith_clear_msb_c(cond, d, s, count) { \
	(void)(cond); \
	emith_clear_msb(d, s, count); \
}

#define emith_sext(d, s, bits) { \
	emith_lsl(d, s, 32 - (bits)); \
	emith_asr(d, d, 32 - (bits)); \
}

#define emith_setc(r) { \
	EMIT_OP(0x0f); \
	EMIT_OP_MODRM(0x92, 3, 0, r); /* SETC r */ \
}

// XXX: stupid mess
#define emith_mul_(op, dlo, dhi, s1, s2) { \
	int rmr; \
	if (dlo != xAX && dhi != xAX) \
		emith_push(xAX); \
	if (dlo != xDX && dhi != xDX) \
		emith_push(xDX); \
	if ((s1) == xAX) \
		rmr = s2; \
	else if ((s2) == xAX) \
		rmr = s1; \
	else { \
		emith_move_r_r(xAX, s1); \
		rmr = s2; \
	} \
	EMIT_OP_MODRM(0xf7, 3, op, rmr); /* xMUL rmr */ \
	/* XXX: using push/pop for the case of edx->eax; eax->edx */ \
	if (dhi != xDX && dhi != -1) \
		emith_push(xDX); \
	if (dlo != xAX) \
		emith_move_r_r(dlo, xAX); \
	if (dhi != xDX && dhi != -1) \
		emith_pop(dhi); \
	if (dlo != xDX && dhi != xDX) \
		emith_pop(xDX); \
	if (dlo != xAX && dhi != xAX) \
		emith_pop(xAX); \
}

#define emith_mul_u64(dlo, dhi, s1, s2) \
	emith_mul_(4, dlo, dhi, s1, s2) /* MUL */

#define emith_mul_s64(dlo, dhi, s1, s2) \
	emith_mul_(5, dlo, dhi, s1, s2) /* IMUL */

#define emith_mul(d, s1, s2) \
	emith_mul_(4, d, -1, s1, s2)

// (dlo,dhi) += signed(s1) * signed(s2)
#define emith_mula_s64(dlo, dhi, s1, s2) { \
	emith_push(dhi); \
	emith_push(dlo); \
	emith_mul_(5, dlo, dhi, s1, s2); \
	EMIT_OP_MODRM(0x03, 0, dlo, 4); \
	EMIT_SIB(0, 4, 4); /* add dlo, [esp] */ \
	EMIT_OP_MODRM(0x13, 1, dhi, 4); \
	EMIT_SIB(0, 4, 4); \
	EMIT(4, u8); /* adc dhi, [esp+4] */ \
	emith_add_r_imm(xSP, 4*2); \
}

// "flag" instructions are the same
#define emith_subf_r_imm emith_sub_r_imm
#define emith_addf_r_r   emith_add_r_r
#define emith_subf_r_r   emith_sub_r_r
#define emith_adcf_r_r   emith_adc_r_r
#define emith_sbcf_r_r   emith_sbc_r_r
#define emith_eorf_r_r   emith_eor_r_r
#define emith_negcf_r_r  emith_negc_r_r

#define emith_lslf  emith_lsl
#define emith_lsrf  emith_lsr
#define emith_asrf  emith_asr
#define emith_rolf  emith_rol
#define emith_rorf  emith_ror
#define emith_rolcf emith_rolc
#define emith_rorcf emith_rorc

#define emith_deref_op(op, r, rs, offs) do { \
	/* mov r <-> [ebp+#offs] */ \
	if ((offs) >= 0x80) { \
		EMIT_OP_MODRM(op, 2, r, rs); \
		EMIT(offs, u32); \
	} else { \
		EMIT_OP_MODRM(op, 1, r, rs); \
		EMIT(offs, u8); \
	} \
} while (0)

#define is_abcdx(r) (xAX <= (r) && (r) <= xDX)

#define emith_read_r_r_offs(r, rs, offs) \
	emith_deref_op(0x8b, r, rs, offs)

#define emith_write_r_r_offs(r, rs, offs) \
	emith_deref_op(0x89, r, rs, offs)

// note: don't use prefixes on this
#define emith_read8_r_r_offs(r, rs, offs) do { \
	int r_ = r; \
	if (!is_abcdx(r)) \
		r_ = rcache_get_tmp(); \
	emith_deref_op(0x8a, r_, rs, offs); \
	if ((r) != r_) { \
		emith_move_r_r(r, r_); \
		rcache_free_tmp(r_); \
	} \
} while (0)

#define emith_write8_r_r_offs(r, rs, offs) do {\
	int r_ = r; \
	if (!is_abcdx(r)) { \
		r_ = rcache_get_tmp(); \
		emith_move_r_r(r_, r); \
	} \
	emith_deref_op(0x88, r_, rs, offs); \
	if ((r) != r_) \
		rcache_free_tmp(r_); \
} while (0)

#define emith_read16_r_r_offs(r, rs, offs) { \
	EMIT(0x66, u8); /* operand override */ \
	emith_read_r_r_offs(r, rs, offs); \
}

#define emith_write16_r_r_offs(r, rs, offs) { \
	EMIT(0x66, u8); \
	emith_write_r_r_offs(r, rs, offs); \
}

#define emith_ctx_read(r, offs) \
	emith_read_r_r_offs(r, CONTEXT_REG, offs)

#define emith_ctx_write(r, offs) \
	emith_write_r_r_offs(r, CONTEXT_REG, offs)

#define emith_ctx_read_multiple(r, offs, cnt, tmpr) do { \
	int r_ = r, offs_ = offs, cnt_ = cnt;     \
	for (; cnt_ > 0; r_++, offs_ += 4, cnt_--) \
		emith_ctx_read(r_, offs_);        \
} while (0)

#define emith_ctx_write_multiple(r, offs, cnt, tmpr) do { \
	int r_ = r, offs_ = offs, cnt_ = cnt;     \
	for (; cnt_ > 0; r_++, offs_ += 4, cnt_--) \
		emith_ctx_write(r_, offs_);       \
} while (0)

// assumes EBX is free
#define emith_ret_to_ctx(offs) { \
	emith_pop(xBX); \
	emith_ctx_write(xBX, offs); \
}

#define emith_jump(ptr) { \
	u32 disp = (u32)(ptr) - ((u32)tcache_ptr + 5); \
	EMIT_OP(0xe9); \
	EMIT(disp, u32); \
}

#define emith_jump_patchable(target) \
	emith_jump(target)

#define emith_jump_cond(cond, ptr) { \
	u32 disp = (u32)(ptr) - ((u32)tcache_ptr + 6); \
	EMIT(0x0f, u8); \
	EMIT_OP(0x80 | (cond)); \
	EMIT(disp, u32); \
}

#define emith_jump_cond_patchable(cond, target) \
	emith_jump_cond(cond, target)

#define emith_jump_patch(ptr, target) do { \
	u32 disp_ = (u32)(target) - ((u32)(ptr) + 4); \
	u32 offs_ = (*(u8 *)(ptr) == 0x0f) ? 2 : 1; \
	EMIT_PTR((u8 *)(ptr) + offs_, disp_ - offs_, u32); \
} while (0)

#define emith_jump_at(ptr, target) { \
	u32 disp_ = (u32)(target) - ((u32)(ptr) + 5); \
	EMIT_PTR(ptr, 0xe9, u8); \
	EMIT_PTR((u8 *)(ptr) + 1, disp_, u32); \
}

#define emith_call(ptr) { \
	u32 disp = (u32)(ptr) - ((u32)tcache_ptr + 5); \
	EMIT_OP(0xe8); \
	EMIT(disp, u32); \
}

#define emith_call_cond(cond, ptr) \
	emith_call(ptr)

#define emith_call_reg(r) \
	EMIT_OP_MODRM(0xff, 3, 2, r)

#define emith_call_ctx(offs) { \
	EMIT_OP_MODRM(0xff, 2, 2, CONTEXT_REG); \
	EMIT(offs, u32); \
}

#define emith_ret() \
	EMIT_OP(0xc3)

#define emith_jump_reg(r) \
	EMIT_OP_MODRM(0xff, 3, 4, r)

#define emith_jump_ctx(offs) { \
	EMIT_OP_MODRM(0xff, 2, 4, CONTEXT_REG); \
	EMIT(offs, u32); \
}

#define emith_push_ret()

#define emith_pop_and_ret() \
	emith_ret()

#define EMITH_JMP_START(cond) { \
	u8 *cond_ptr; \
	JMP8_POS(cond_ptr)

#define EMITH_JMP_END(cond) \
	JMP8_EMIT(cond, cond_ptr); \
}

#define EMITH_JMP3_START(cond) { \
	u8 *cond_ptr, *else_ptr; \
	JMP8_POS(cond_ptr)

#define EMITH_JMP3_MID(cond) \
	JMP8_POS(else_ptr); \
	JMP8_EMIT(cond, cond_ptr);

#define EMITH_JMP3_END() \
	JMP8_EMIT_NC(else_ptr); \
}

// "simple" jump (no more then a few insns)
// ARM will use conditional instructions here
#define EMITH_SJMP_START EMITH_JMP_START
#define EMITH_SJMP_END EMITH_JMP_END

#define EMITH_SJMP3_START EMITH_JMP3_START
#define EMITH_SJMP3_MID EMITH_JMP3_MID
#define EMITH_SJMP3_END EMITH_JMP3_END

#define emith_pass_arg_r(arg, reg) { \
	int rd = 7; \
	host_arg2reg(rd, arg); \
	emith_move_r_r(rd, reg); \
}

#define emith_pass_arg_imm(arg, imm) { \
	int rd = 7; \
	host_arg2reg(rd, arg); \
	emith_move_r_imm(rd, imm); \
}

#define host_instructions_updated(base, end)

#define host_arg2reg(rd, arg) \
	switch (arg) { \
	case 0: rd = xAX; break; \
	case 1: rd = xDX; break; \
	case 2: rd = xCX; break; \
	}

/* SH2 drc specific */
#define emith_sh2_drc_entry() { \
	emith_push(xBX);        \
	emith_push(xBP);        \
	emith_push(xSI);        \
	emith_push(xDI);        \
}

#define emith_sh2_drc_exit() {  \
	emith_pop(xDI);         \
	emith_pop(xSI);         \
	emith_pop(xBP);         \
	emith_pop(xBX);         \
	emith_ret();            \
}

// assumes EBX is free temporary
#define emith_sh2_wcall(a, tab, ret_ptr) { \
	int arg2_; \
	host_arg2reg(arg2_, 2); \
	emith_lsr(xBX, a, SH2_WRITE_SHIFT); \
	EMIT_OP_MODRM(0x8b, 0, xBX, 4); \
	EMIT_SIB(2, xBX, tab); /* mov ebx, [tab + ebx * 4] */ \
	emith_ctx_read(arg2_, offsetof(SH2, is_slave)); \
	emith_push_imm((long)(ret_ptr)); \
	emith_jump_reg(xBX); \
}

#define emith_sh2_dtbf_loop() { \
	u8 *jmp0; /* negative cycles check */            \
	u8 *jmp1; /* unsinged overflow check */          \
	int cr, rn;                                      \
	int tmp_ = rcache_get_tmp();                     \
	cr = rcache_get_reg(SHR_SR, RC_GR_RMW);          \
	rn = rcache_get_reg((op >> 8) & 0x0f, RC_GR_RMW);\
	emith_sub_r_imm(rn, 1);                          \
	emith_sub_r_imm(cr, (cycles+1) << 12);           \
	cycles = 0;                                      \
	emith_asr(tmp_, cr, 2+12);                       \
	JMP8_POS(jmp0); /* no negative cycles */         \
	emith_move_r_imm(tmp_, 0);                       \
	JMP8_EMIT(ICOND_JNS, jmp0);                      \
	emith_and_r_imm(cr, 0xffe);                      \
	emith_subf_r_r(rn, tmp_);                        \
	JMP8_POS(jmp1); /* no overflow */                \
	emith_neg_r(rn); /* count left */                \
	emith_lsl(rn, rn, 2+12);                         \
	emith_or_r_r(cr, rn);                            \
	emith_or_r_imm(cr, 1);                           \
	emith_move_r_imm(rn, 0);                         \
	JMP8_EMIT(ICOND_JA, jmp1);                       \
	rcache_free_tmp(tmp_);                           \
}

#define emith_write_sr(sr, srcr) { \
	int tmp_ = rcache_get_tmp(); \
	emith_clear_msb(tmp_, srcr, 22); \
	emith_bic_r_imm(sr, 0x3ff); \
	emith_or_r_r(sr, tmp_); \
	rcache_free_tmp(tmp_); \
}

#define emith_tpop_carry(sr, is_sub) \
	emith_lsr(sr, sr, 1)

#define emith_tpush_carry(sr, is_sub) \
	emith_adc_r_r(sr, sr)

/*
 * if Q
 *   t = carry(Rn += Rm)
 * else
 *   t = carry(Rn -= Rm)
 * T ^= t
 */
#define emith_sh2_div1_step(rn, rm, sr) {         \
	u8 *jmp0, *jmp1;                          \
	int tmp_ = rcache_get_tmp();              \
	emith_eor_r_r(tmp_, tmp_);                \
	emith_tst_r_imm(sr, Q);  /* if (Q ^ M) */ \
	JMP8_POS(jmp0);          /* je do_sub */  \
	emith_add_r_r(rn, rm);                    \
	JMP8_POS(jmp1);          /* jmp done */   \
	JMP8_EMIT(ICOND_JE, jmp0); /* do_sub: */  \
	emith_sub_r_r(rn, rm);                    \
	JMP8_EMIT_NC(jmp1);      /* done: */      \
	emith_setc(tmp_);                         \
	EMIT_OP_MODRM(0x31, 3, tmp_, sr); /* T = Q1 ^ Q2 */ \
	rcache_free_tmp(tmp_);                    \
}
Commit	Line	Data
3863edbd	1	/*
cff531af	2	* Basic macros to emit x86 instructions and some utils
	3	* Copyright (C) 2008,2009,2010 notaz
	4	*
	5	* This work is licensed under the terms of MAME license.
	6	* See COPYING file in the top-level directory.
	7	*
8b4f38f4	8	* note:
a2b8c5a5	9	* temp registers must be eax-edx due to use of SETcc and r/w 8/16.
f0d7b1fa	10	* note about silly things like emith_eor_r_r_r:
8b4f38f4	11	* these are here because the compiler was designed
8b4f38f4	12	* for ARM as it's primary target.
3863edbd	13	*/
679af8a3	14	#include <stdarg.h>
679af8a3	15
f4bb5d6b	16	enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
f4bb5d6b	17
f4bb5d6b	18	#define CONTEXT_REG xBP
679af8a3	19
18b94127	20	#define ICOND_JO 0x00
	21	#define ICOND_JNO 0x01
	22	#define ICOND_JB 0x02
	23	#define ICOND_JAE 0x03
	24	#define ICOND_JE 0x04
	25	#define ICOND_JNE 0x05
	26	#define ICOND_JBE 0x06
	27	#define ICOND_JA 0x07
	28	#define ICOND_JS 0x08
	29	#define ICOND_JNS 0x09
	30	#define ICOND_JL 0x0c
	31	#define ICOND_JGE 0x0d
	32	#define ICOND_JLE 0x0e
	33	#define ICOND_JG 0x0f
	34
	35	#define IOP_JMP 0xeb
80599a42	36
80599a42	37	// unified conditions (we just use rel8 jump instructions for x86)
18b94127	38	#define DCOND_EQ ICOND_JE
	39	#define DCOND_NE ICOND_JNE
	40	#define DCOND_MI ICOND_JS // MInus
	41	#define DCOND_PL ICOND_JNS // PLus or zero
	42	#define DCOND_HI ICOND_JA // higher (unsigned)
	43	#define DCOND_HS ICOND_JAE // higher \|\| same (unsigned)
	44	#define DCOND_LO ICOND_JB // lower (unsigned)
	45	#define DCOND_LS ICOND_JBE // lower \|\| same (unsigned)
	46	#define DCOND_GE ICOND_JGE // greater \|\| equal (signed)
	47	#define DCOND_GT ICOND_JG // greater (signed)
	48	#define DCOND_LE ICOND_JLE // less \|\| equal (signed)
	49	#define DCOND_LT ICOND_JL // less (signed)
	50	#define DCOND_VS ICOND_JO // oVerflow Set
	51	#define DCOND_VC ICOND_JNO // oVerflow Clear
80599a42	52
679af8a3	53	#define EMIT_PTR(ptr, val, type) \
	54	(type )(ptr) = val
	55
	56	#define EMIT(val, type) { \
	57	EMIT_PTR(tcache_ptr, val, type); \
f4bb5d6b	58	tcache_ptr += sizeof(type); \
679af8a3	59	}
679af8a3	60
e898de13	61	#define EMIT_OP(op) { \
	62	COUNT_OP; \
	63	EMIT(op, u8); \
	64	}
	65
679af8a3	66	#define EMIT_MODRM(mod,r,rm) \
	67	EMIT(((mod)<<6) \| ((r)<<3) \| (rm), u8)
	68
f0d7b1fa	69	#define EMIT_SIB(scale,index,base) \
	70	EMIT(((scale)<<6) \| ((index)<<3) \| (base), u8)
	71
04092e32	72	#define EMIT_OP_MODRM(op,mod,r,rm) do { \
e898de13	73	EMIT_OP(op); \
679af8a3	74	EMIT_MODRM(mod, r, rm); \
04092e32	75	} while (0)
679af8a3	76
80599a42	77	#define JMP8_POS(ptr) \
	78	ptr = tcache_ptr; \
	79	tcache_ptr += 2
	80
	81	#define JMP8_EMIT(op, ptr) \
18b94127	82	EMIT_PTR(ptr, 0x70\|(op), u8); \
	83	EMIT_PTR(ptr + 1, (tcache_ptr - (ptr+2)), u8)
	84
	85	#define JMP8_EMIT_NC(ptr) \
	86	EMIT_PTR(ptr, IOP_JMP, u8); \
80599a42	87	EMIT_PTR(ptr + 1, (tcache_ptr - (ptr+2)), u8)
80599a42	88
3863edbd	89	// _r_r
679af8a3	90	#define emith_move_r_r(dst, src) \
	91	EMIT_OP_MODRM(0x8b, 3, dst, src)
	92
80599a42	93	#define emith_add_r_r(d, s) \
	94	EMIT_OP_MODRM(0x01, 3, s, d)
	95
	96	#define emith_sub_r_r(d, s) \
	97	EMIT_OP_MODRM(0x29, 3, s, d)
	98
3863edbd	99	#define emith_adc_r_r(d, s) \
	100	EMIT_OP_MODRM(0x11, 3, s, d)
	101
	102	#define emith_sbc_r_r(d, s) \
	103	EMIT_OP_MODRM(0x19, 3, s, d) /* SBB */
	104
80599a42	105	#define emith_or_r_r(d, s) \
	106	EMIT_OP_MODRM(0x09, 3, s, d)
	107
3863edbd	108	#define emith_and_r_r(d, s) \
	109	EMIT_OP_MODRM(0x21, 3, s, d)
	110
80599a42	111	#define emith_eor_r_r(d, s) \
3863edbd	112	EMIT_OP_MODRM(0x31, 3, s, d) /* XOR */
	113
	114	#define emith_tst_r_r(d, s) \
	115	EMIT_OP_MODRM(0x85, 3, s, d) /* TEST */
	116
	117	#define emith_cmp_r_r(d, s) \
	118	EMIT_OP_MODRM(0x39, 3, s, d)
80599a42	119
	120	// fake teq - test equivalence - get_flags(d ^ s)
	121	#define emith_teq_r_r(d, s) { \
	122	emith_push(d); \
	123	emith_eor_r_r(d, s); \
	124	emith_pop(d); \
	125	}
	126
52d759c3	127	#define emith_mvn_r_r(d, s) { \
	128	if (d != s) \
	129	emith_move_r_r(d, s); \
	130	EMIT_OP_MODRM(0xf7, 3, 2, d); /* NOT d */ \
	131	}
	132
	133	#define emith_negc_r_r(d, s) { \
	134	int tmp_ = rcache_get_tmp(); \
	135	emith_move_r_imm(tmp_, 0); \
	136	emith_sbc_r_r(tmp_, s); \
	137	emith_move_r_r(d, tmp_); \
	138	rcache_free_tmp(tmp_); \
	139	}
	140
	141	#define emith_neg_r_r(d, s) { \
	142	if (d != s) \
	143	emith_move_r_r(d, s); \
	144	EMIT_OP_MODRM(0xf7, 3, 3, d); /* NEG d */ \
	145	}
	146
3863edbd	147	// _r_r_r
3863edbd	148	#define emith_eor_r_r_r(d, s1, s2) { \
52d759c3	149	if (d == s1) { \
	150	emith_eor_r_r(d, s2); \
	151	} else if (d == s2) { \
	152	emith_eor_r_r(d, s1); \
	153	} else { \
3863edbd	154	emith_move_r_r(d, s1); \
52d759c3	155	emith_eor_r_r(d, s2); \
52d759c3	156	} \
3863edbd	157	}
3863edbd	158
f0d7b1fa	159	// _r_r_shift
f0d7b1fa	160	#define emith_or_r_r_lsl(d, s, lslimm) { \
52d759c3	161	int tmp_ = rcache_get_tmp(); \
f0d7b1fa	162	emith_lsl(tmp_, s, lslimm); \
f0d7b1fa	163	emith_or_r_r(d, tmp_); \
52d759c3	164	rcache_free_tmp(tmp_); \
3863edbd	165	}
3863edbd	166
f0d7b1fa	167	// d != s
	168	#define emith_eor_r_r_lsr(d, s, lsrimm) { \
	169	emith_push(s); \
	170	emith_lsr(s, s, lsrimm); \
	171	emith_eor_r_r(d, s); \
	172	emith_pop(s); \
	173	}
	174
80599a42	175	// _r_imm
679af8a3	176	#define emith_move_r_imm(r, imm) { \
e898de13	177	EMIT_OP(0xb8 + (r)); \
679af8a3	178	EMIT(imm, u32); \
	179	}
	180
52d759c3	181	#define emith_move_r_imm_s8(r, imm) \
	182	emith_move_r_imm(r, (u32)(signed int)(signed char)(imm))
	183
18b94127	184	#define emith_arith_r_imm(op, r, imm) do { \
80599a42	185	EMIT_OP_MODRM(0x81, 3, op, r); \
679af8a3	186	EMIT(imm, u32); \
18b94127	187	} while (0)
679af8a3	188
80599a42	189	#define emith_add_r_imm(r, imm) \
	190	emith_arith_r_imm(0, r, imm)
	191
	192	#define emith_or_r_imm(r, imm) \
	193	emith_arith_r_imm(1, r, imm)
	194
5686d931	195	#define emith_adc_r_imm(r, imm) \
	196	emith_arith_r_imm(2, r, imm)
	197
	198	#define emith_sbc_r_imm(r, imm) \
	199	emith_arith_r_imm(3, r, imm) // sbb
	200
80599a42	201	#define emith_and_r_imm(r, imm) \
	202	emith_arith_r_imm(4, r, imm)
	203
	204	#define emith_sub_r_imm(r, imm) \
	205	emith_arith_r_imm(5, r, imm)
	206
52d759c3	207	#define emith_eor_r_imm(r, imm) \
	208	emith_arith_r_imm(6, r, imm)
	209
ed8cf79b	210	#define emith_cmp_r_imm(r, imm) \
	211	emith_arith_r_imm(7, r, imm)
	212
18b94127	213	#define emith_tst_r_imm(r, imm) do { \
80599a42	214	EMIT_OP_MODRM(0xf7, 3, 0, r); \
679af8a3	215	EMIT(imm, u32); \
18b94127	216	} while (0)
679af8a3	217
80599a42	218	// fake
	219	#define emith_bic_r_imm(r, imm) \
	220	emith_arith_r_imm(4, r, ~(imm))
	221
	222	// fake conditionals (using SJMP instead)
8796b7ee	223	#define emith_move_r_imm_c(cond, r, imm) { \
	224	(void)(cond); \
	225	emith_move_r_imm(r, imm); \
	226	}
	227
80599a42	228	#define emith_add_r_imm_c(cond, r, imm) { \
80599a42	229	(void)(cond); \
3863edbd	230	emith_add_r_imm(r, imm); \
80599a42	231	}
80599a42	232
80599a42	233	#define emith_sub_r_imm_c(cond, r, imm) { \
80599a42	234	(void)(cond); \
3863edbd	235	emith_sub_r_imm(r, imm); \
	236	}
	237
b081408f	238	#define emith_or_r_imm_c(cond, r, imm) \
	239	emith_or_r_imm(r, imm)
	240	#define emith_eor_r_imm_c(cond, r, imm) \
	241	emith_eor_r_imm(r, imm)
	242	#define emith_bic_r_imm_c(cond, r, imm) \
	243	emith_bic_r_imm(r, imm)
	244	#define emith_ror_c(cond, d, s, cnt) \
	245	emith_ror(d, s, cnt)
	246
	247	#define emith_read_r_r_offs_c(cond, r, rs, offs) \
	248	emith_read_r_r_offs(r, rs, offs)
	249	#define emith_write_r_r_offs_c(cond, r, rs, offs) \
	250	emith_write_r_r_offs(r, rs, offs)
	251	#define emith_read8_r_r_offs_c(cond, r, rs, offs) \
	252	emith_read8_r_r_offs(r, rs, offs)
	253	#define emith_write8_r_r_offs_c(cond, r, rs, offs) \
	254	emith_write8_r_r_offs(r, rs, offs)
	255	#define emith_read16_r_r_offs_c(cond, r, rs, offs) \
	256	emith_read16_r_r_offs(r, rs, offs)
	257	#define emith_write16_r_r_offs_c(cond, r, rs, offs) \
	258	emith_write16_r_r_offs(r, rs, offs)
	259	#define emith_jump_reg_c(cond, r) \
	260	emith_jump_reg(r)
	261	#define emith_jump_ctx_c(cond, offs) \
	262	emith_jump_ctx(offs)
	263	#define emith_ret_c(cond) \
	264	emith_ret()
e05b81fc	265
52d759c3	266	// _r_r_imm
e05b81fc	267	#define emith_add_r_r_imm(d, s, imm) { \
	268	if (d != s) \
	269	emith_move_r_r(d, s); \
	270	emith_add_r_imm(d, imm); \
	271	}
	272
52d759c3	273	#define emith_and_r_r_imm(d, s, imm) { \
	274	if (d != s) \
	275	emith_move_r_r(d, s); \
18b94127	276	emith_and_r_imm(d, imm); \
52d759c3	277	}
52d759c3	278
80599a42	279	// shift
	280	#define emith_shift(op, d, s, cnt) { \
	281	if (d != s) \
	282	emith_move_r_r(d, s); \
	283	EMIT_OP_MODRM(0xc1, 3, op, d); \
	284	EMIT(cnt, u8); \
	285	}
	286
80599a42	287	#define emith_lsl(d, s, cnt) \
	288	emith_shift(4, d, s, cnt)
	289
3863edbd	290	#define emith_lsr(d, s, cnt) \
	291	emith_shift(5, d, s, cnt)
	292
	293	#define emith_asr(d, s, cnt) \
	294	emith_shift(7, d, s, cnt)
	295
ed8cf79b	296	#define emith_rol(d, s, cnt) \
	297	emith_shift(0, d, s, cnt)
	298
	299	#define emith_ror(d, s, cnt) \
	300	emith_shift(1, d, s, cnt)
	301
	302	#define emith_rolc(r) \
	303	EMIT_OP_MODRM(0xd1, 3, 2, r)
	304
	305	#define emith_rorc(r) \
	306	EMIT_OP_MODRM(0xd1, 3, 3, r)
	307
80599a42	308	// misc
	309	#define emith_push(r) \
	310	EMIT_OP(0x50 + (r))
	311
e05b81fc	312	#define emith_push_imm(imm) { \
	313	EMIT_OP(0x68); \
	314	EMIT(imm, u32); \
	315	}
	316
80599a42	317	#define emith_pop(r) \
	318	EMIT_OP(0x58 + (r))
	319
	320	#define emith_neg_r(r) \
	321	EMIT_OP_MODRM(0xf7, 3, 3, r)
	322
	323	#define emith_clear_msb(d, s, count) { \
	324	u32 t = (u32)-1; \
	325	t >>= count; \
	326	if (d != s) \
	327	emith_move_r_r(d, s); \
	328	emith_and_r_imm(d, t); \
	329	}
	330
f0d7b1fa	331	#define emith_clear_msb_c(cond, d, s, count) { \
	332	(void)(cond); \
	333	emith_clear_msb(d, s, count); \
	334	}
	335
80599a42	336	#define emith_sext(d, s, bits) { \
	337	emith_lsl(d, s, 32 - (bits)); \
	338	emith_asr(d, d, 32 - (bits)); \
	339	}
	340
f0d7b1fa	341	#define emith_setc(r) { \
f0d7b1fa	342	EMIT_OP(0x0f); \
8b4f38f4	343	EMIT_OP_MODRM(0x92, 3, 0, r); /* SETC r */ \
f0d7b1fa	344	}
f0d7b1fa	345
80599a42	346	// XXX: stupid mess
3863edbd	347	#define emith_mul_(op, dlo, dhi, s1, s2) { \
80599a42	348	int rmr; \
3863edbd	349	if (dlo != xAX && dhi != xAX) \
80599a42	350	emith_push(xAX); \
3863edbd	351	if (dlo != xDX && dhi != xDX) \
3863edbd	352	emith_push(xDX); \
80599a42	353	if ((s1) == xAX) \
	354	rmr = s2; \
	355	else if ((s2) == xAX) \
	356	rmr = s1; \
	357	else { \
	358	emith_move_r_r(xAX, s1); \
	359	rmr = s2; \
	360	} \
3863edbd	361	EMIT_OP_MODRM(0xf7, 3, op, rmr); /* xMUL rmr */ \
	362	/* XXX: using push/pop for the case of edx->eax; eax->edx */ \
	363	if (dhi != xDX && dhi != -1) \
	364	emith_push(xDX); \
	365	if (dlo != xAX) \
	366	emith_move_r_r(dlo, xAX); \
	367	if (dhi != xDX && dhi != -1) \
	368	emith_pop(dhi); \
	369	if (dlo != xDX && dhi != xDX) \
	370	emith_pop(xDX); \
	371	if (dlo != xAX && dhi != xAX) \
80599a42	372	emith_pop(xAX); \
80599a42	373	}
80599a42	374
3863edbd	375	#define emith_mul_u64(dlo, dhi, s1, s2) \
	376	emith_mul_(4, dlo, dhi, s1, s2) /* MUL */
	377
	378	#define emith_mul_s64(dlo, dhi, s1, s2) \
	379	emith_mul_(5, dlo, dhi, s1, s2) /* IMUL */
	380
	381	#define emith_mul(d, s1, s2) \
	382	emith_mul_(4, d, -1, s1, s2)
	383
f0d7b1fa	384	// (dlo,dhi) += signed(s1) * signed(s2)
	385	#define emith_mula_s64(dlo, dhi, s1, s2) { \
	386	emith_push(dhi); \
	387	emith_push(dlo); \
	388	emith_mul_(5, dlo, dhi, s1, s2); \
	389	EMIT_OP_MODRM(0x03, 0, dlo, 4); \
	390	EMIT_SIB(0, 4, 4); /* add dlo, [esp] */ \
	391	EMIT_OP_MODRM(0x13, 1, dhi, 4); \
	392	EMIT_SIB(0, 4, 4); \
	393	EMIT(4, u8); /* adc dhi, [esp+4] */ \
	394	emith_add_r_imm(xSP, 4*2); \
	395	}
	396
80599a42	397	// "flag" instructions are the same
80599a42	398	#define emith_subf_r_imm emith_sub_r_imm
3863edbd	399	#define emith_addf_r_r emith_add_r_r
80599a42	400	#define emith_subf_r_r emith_sub_r_r
3863edbd	401	#define emith_adcf_r_r emith_adc_r_r
3863edbd	402	#define emith_sbcf_r_r emith_sbc_r_r
8796b7ee	403	#define emith_eorf_r_r emith_eor_r_r
52d759c3	404	#define emith_negcf_r_r emith_negc_r_r
3863edbd	405
ed8cf79b	406	#define emith_lslf emith_lsl
	407	#define emith_lsrf emith_lsr
	408	#define emith_asrf emith_asr
	409	#define emith_rolf emith_rol
	410	#define emith_rorf emith_ror
	411	#define emith_rolcf emith_rolc
	412	#define emith_rorcf emith_rorc
80599a42	413
b081408f	414	#define emith_deref_op(op, r, rs, offs) do { \
e05b81fc	415	/* mov r <-> [ebp+#offs] */ \
e05b81fc	416	if ((offs) >= 0x80) { \
b081408f	417	EMIT_OP_MODRM(op, 2, r, rs); \
e05b81fc	418	EMIT(offs, u32); \
e05b81fc	419	} else { \
b081408f	420	EMIT_OP_MODRM(op, 1, r, rs); \
e05b81fc	421	EMIT(offs, u8); \
e05b81fc	422	} \
8796b7ee	423	} while (0)
679af8a3	424
a2b8c5a5	425	#define is_abcdx(r) (xAX <= (r) && (r) <= xDX)
a2b8c5a5	426
04092e32	427	#define emith_read_r_r_offs(r, rs, offs) \
	428	emith_deref_op(0x8b, r, rs, offs)
	429
	430	#define emith_write_r_r_offs(r, rs, offs) \
	431	emith_deref_op(0x89, r, rs, offs)
	432
	433	// note: don't use prefixes on this
	434	#define emith_read8_r_r_offs(r, rs, offs) do { \
a2b8c5a5	435	int r_ = r; \
	436	if (!is_abcdx(r)) \
	437	r_ = rcache_get_tmp(); \
04092e32	438	emith_deref_op(0x8a, r_, rs, offs); \
a2b8c5a5	439	if ((r) != r_) { \
	440	emith_move_r_r(r, r_); \
	441	rcache_free_tmp(r_); \
	442	} \
	443	} while (0)
	444
04092e32	445	#define emith_write8_r_r_offs(r, rs, offs) do {\
a2b8c5a5	446	int r_ = r; \
	447	if (!is_abcdx(r)) { \
	448	r_ = rcache_get_tmp(); \
	449	emith_move_r_r(r_, r); \
	450	} \
04092e32	451	emith_deref_op(0x88, r_, rs, offs); \
a2b8c5a5	452	if ((r) != r_) \
	453	rcache_free_tmp(r_); \
	454	} while (0)
	455
b081408f	456	#define emith_read16_r_r_offs(r, rs, offs) { \
b081408f	457	EMIT(0x66, u8); /* operand override */ \
04092e32	458	emith_read_r_r_offs(r, rs, offs); \
b081408f	459	}
	460
	461	#define emith_write16_r_r_offs(r, rs, offs) { \
	462	EMIT(0x66, u8); \
04092e32	463	emith_write_r_r_offs(r, rs, offs); \
b081408f	464	}
b081408f	465
e05b81fc	466	#define emith_ctx_read(r, offs) \
b081408f	467	emith_read_r_r_offs(r, CONTEXT_REG, offs)
e05b81fc	468
e05b81fc	469	#define emith_ctx_write(r, offs) \
b081408f	470	emith_write_r_r_offs(r, CONTEXT_REG, offs)
e05b81fc	471
8796b7ee	472	#define emith_ctx_read_multiple(r, offs, cnt, tmpr) do { \
8796b7ee	473	int r_ = r, offs_ = offs, cnt_ = cnt; \
8b4f38f4	474	for (; cnt_ > 0; r_++, offs_ += 4, cnt_--) \
8796b7ee	475	emith_ctx_read(r_, offs_); \
	476	} while (0)
	477
8796b7ee	478	#define emith_ctx_write_multiple(r, offs, cnt, tmpr) do { \
8796b7ee	479	int r_ = r, offs_ = offs, cnt_ = cnt; \
8b4f38f4	480	for (; cnt_ > 0; r_++, offs_ += 4, cnt_--) \
8796b7ee	481	emith_ctx_write(r_, offs_); \
8796b7ee	482	} while (0)
679af8a3	483
e05b81fc	484	// assumes EBX is free
	485	#define emith_ret_to_ctx(offs) { \
	486	emith_pop(xBX); \
	487	emith_ctx_write(xBX, offs); \
	488	}
	489
679af8a3	490	#define emith_jump(ptr) { \
18b94127	491	u32 disp = (u32)(ptr) - ((u32)tcache_ptr + 5); \
e898de13	492	EMIT_OP(0xe9); \
679af8a3	493	EMIT(disp, u32); \
	494	}
	495
44e6452e	496	#define emith_jump_patchable(target) \
	497	emith_jump(target)
	498
18b94127	499	#define emith_jump_cond(cond, ptr) { \
	500	u32 disp = (u32)(ptr) - ((u32)tcache_ptr + 6); \
	501	EMIT(0x0f, u8); \
	502	EMIT_OP(0x80 \| (cond)); \
	503	EMIT(disp, u32); \
	504	}
	505
44e6452e	506	#define emith_jump_cond_patchable(cond, target) \
44e6452e	507	emith_jump_cond(cond, target)
18b94127	508
18b94127	509	#define emith_jump_patch(ptr, target) do { \
44e6452e	510	u32 disp_ = (u32)(target) - ((u32)(ptr) + 4); \
	511	u32 offs_ = ((u8 )(ptr) == 0x0f) ? 2 : 1; \
	512	EMIT_PTR((u8 *)(ptr) + offs_, disp_ - offs_, u32); \
18b94127	513	} while (0)
18b94127	514
a2b8c5a5	515	#define emith_jump_at(ptr, target) { \
	516	u32 disp_ = (u32)(target) - ((u32)(ptr) + 5); \
	517	EMIT_PTR(ptr, 0xe9, u8); \
	518	EMIT_PTR((u8 *)(ptr) + 1, disp_, u32); \
	519	}
	520
679af8a3	521	#define emith_call(ptr) { \
18b94127	522	u32 disp = (u32)(ptr) - ((u32)tcache_ptr + 5); \
e898de13	523	EMIT_OP(0xe8); \
679af8a3	524	EMIT(disp, u32); \
	525	}
	526
f0d7b1fa	527	#define emith_call_cond(cond, ptr) \
	528	emith_call(ptr)
	529
e05b81fc	530	#define emith_call_reg(r) \
	531	EMIT_OP_MODRM(0xff, 3, 2, r)
	532
	533	#define emith_call_ctx(offs) { \
b081408f	534	EMIT_OP_MODRM(0xff, 2, 2, CONTEXT_REG); \
e05b81fc	535	EMIT(offs, u32); \
	536	}
	537
	538	#define emith_ret() \
	539	EMIT_OP(0xc3)
	540
8796b7ee	541	#define emith_jump_reg(r) \
	542	EMIT_OP_MODRM(0xff, 3, 4, r)
	543
e05b81fc	544	#define emith_jump_ctx(offs) { \
b081408f	545	EMIT_OP_MODRM(0xff, 2, 4, CONTEXT_REG); \
e05b81fc	546	EMIT(offs, u32); \
	547	}
	548
a2b8c5a5	549	#define emith_push_ret()
	550
	551	#define emith_pop_and_ret() \
	552	emith_ret()
	553
8796b7ee	554	#define EMITH_JMP_START(cond) { \
80599a42	555	u8 *cond_ptr; \
	556	JMP8_POS(cond_ptr)
	557
8796b7ee	558	#define EMITH_JMP_END(cond) \
80599a42	559	JMP8_EMIT(cond, cond_ptr); \
679af8a3	560	}
679af8a3	561
b081408f	562	#define EMITH_JMP3_START(cond) { \
	563	u8 cond_ptr, else_ptr; \
	564	JMP8_POS(cond_ptr)
	565
	566	#define EMITH_JMP3_MID(cond) \
	567	JMP8_POS(else_ptr); \
	568	JMP8_EMIT(cond, cond_ptr);
	569
	570	#define EMITH_JMP3_END() \
	571	JMP8_EMIT_NC(else_ptr); \
	572	}
	573
8796b7ee	574	// "simple" jump (no more then a few insns)
b081408f	575	// ARM will use conditional instructions here
8796b7ee	576	#define EMITH_SJMP_START EMITH_JMP_START
	577	#define EMITH_SJMP_END EMITH_JMP_END
	578
b081408f	579	#define EMITH_SJMP3_START EMITH_JMP3_START
	580	#define EMITH_SJMP3_MID EMITH_JMP3_MID
	581	#define EMITH_SJMP3_END EMITH_JMP3_END
	582
f4bb5d6b	583	#define emith_pass_arg_r(arg, reg) { \
f4bb5d6b	584	int rd = 7; \
80599a42	585	host_arg2reg(rd, arg); \
f4bb5d6b	586	emith_move_r_r(rd, reg); \
	587	}
	588
	589	#define emith_pass_arg_imm(arg, imm) { \
	590	int rd = 7; \
80599a42	591	host_arg2reg(rd, arg); \
f4bb5d6b	592	emith_move_r_imm(rd, imm); \
679af8a3	593	}
679af8a3	594
a2b8c5a5	595	#define host_instructions_updated(base, end)
	596
	597	#define host_arg2reg(rd, arg) \
	598	switch (arg) { \
	599	case 0: rd = xAX; break; \
	600	case 1: rd = xDX; break; \
	601	case 2: rd = xCX; break; \
	602	}
	603
65c75cb0	604	/* SH2 drc specific */
8796b7ee	605	#define emith_sh2_drc_entry() { \
	606	emith_push(xBX); \
	607	emith_push(xBP); \
8b4f38f4	608	emith_push(xSI); \
8b4f38f4	609	emith_push(xDI); \
8796b7ee	610	}
	611
	612	#define emith_sh2_drc_exit() { \
8b4f38f4	613	emith_pop(xDI); \
8b4f38f4	614	emith_pop(xSI); \
8796b7ee	615	emith_pop(xBP); \
8796b7ee	616	emith_pop(xBX); \
e05b81fc	617	emith_ret(); \
	618	}
	619
	620	// assumes EBX is free temporary
	621	#define emith_sh2_wcall(a, tab, ret_ptr) { \
	622	int arg2_; \
	623	host_arg2reg(arg2_, 2); \
	624	emith_lsr(xBX, a, SH2_WRITE_SHIFT); \
	625	EMIT_OP_MODRM(0x8b, 0, xBX, 4); \
	626	EMIT_SIB(2, xBX, tab); /* mov ebx, [tab + ebx * 4] */ \
	627	emith_ctx_read(arg2_, offsetof(SH2, is_slave)); \
	628	emith_push_imm((long)(ret_ptr)); \
	629	emith_jump_reg(xBX); \
8796b7ee	630	}
8796b7ee	631
80599a42	632	#define emith_sh2_dtbf_loop() { \
	633	u8 jmp0; / negative cycles check */ \
	634	u8 jmp1; / unsinged overflow check */ \
	635	int cr, rn; \
52d759c3	636	int tmp_ = rcache_get_tmp(); \
80599a42	637	cr = rcache_get_reg(SHR_SR, RC_GR_RMW); \
	638	rn = rcache_get_reg((op >> 8) & 0x0f, RC_GR_RMW);\
	639	emith_sub_r_imm(rn, 1); \
	640	emith_sub_r_imm(cr, (cycles+1) << 12); \
	641	cycles = 0; \
52d759c3	642	emith_asr(tmp_, cr, 2+12); \
80599a42	643	JMP8_POS(jmp0); /* no negative cycles */ \
52d759c3	644	emith_move_r_imm(tmp_, 0); \
18b94127	645	JMP8_EMIT(ICOND_JNS, jmp0); \
80599a42	646	emith_and_r_imm(cr, 0xffe); \
52d759c3	647	emith_subf_r_r(rn, tmp_); \
80599a42	648	JMP8_POS(jmp1); /* no overflow */ \
	649	emith_neg_r(rn); /* count left */ \
	650	emith_lsl(rn, rn, 2+12); \
	651	emith_or_r_r(cr, rn); \
	652	emith_or_r_imm(cr, 1); \
	653	emith_move_r_imm(rn, 0); \
18b94127	654	JMP8_EMIT(ICOND_JA, jmp1); \
52d759c3	655	rcache_free_tmp(tmp_); \
65c75cb0	656	}
65c75cb0	657
18b94127	658	#define emith_write_sr(sr, srcr) { \
52d759c3	659	int tmp_ = rcache_get_tmp(); \
18b94127	660	emith_clear_msb(tmp_, srcr, 22); \
	661	emith_bic_r_imm(sr, 0x3ff); \
	662	emith_or_r_r(sr, tmp_); \
52d759c3	663	rcache_free_tmp(tmp_); \
ed8cf79b	664	}
ed8cf79b	665
8b4f38f4	666	#define emith_tpop_carry(sr, is_sub) \
	667	emith_lsr(sr, sr, 1)
	668
	669	#define emith_tpush_carry(sr, is_sub) \
	670	emith_adc_r_r(sr, sr)
ed8cf79b	671
f0d7b1fa	672	/*
	673	* if Q
	674	* t = carry(Rn += Rm)
	675	* else
	676	* t = carry(Rn -= Rm)
	677	* T ^= t
	678	*/
	679	#define emith_sh2_div1_step(rn, rm, sr) { \
	680	u8 jmp0, jmp1; \
	681	int tmp_ = rcache_get_tmp(); \
8b4f38f4	682	emith_eor_r_r(tmp_, tmp_); \
f0d7b1fa	683	emith_tst_r_imm(sr, Q); /* if (Q ^ M) */ \
	684	JMP8_POS(jmp0); /* je do_sub */ \
	685	emith_add_r_r(rn, rm); \
	686	JMP8_POS(jmp1); /* jmp done */ \
18b94127	687	JMP8_EMIT(ICOND_JE, jmp0); /* do_sub: */ \
f0d7b1fa	688	emith_sub_r_r(rn, rm); \
18b94127	689	JMP8_EMIT_NC(jmp1); /* done: */ \
f0d7b1fa	690	emith_setc(tmp_); \
8b4f38f4	691	EMIT_OP_MODRM(0x31, 3, tmp_, sr); /* T = Q1 ^ Q2 */ \
f0d7b1fa	692	rcache_free_tmp(tmp_); \
	693	}
	694