[picodrive.git] / cpu / drc / emit_x86.c

/*
 * note:
 *  temp registers must be eax-edx due to use of SETcc.
 * note about silly things like emith_eor_r_r_r:
 *  these are here because the compiler was designed
 *  for ARM as it's primary target.
 */
#include <stdarg.h>

enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };

#define CONTEXT_REG xBP

#define ICOND_JO  0x00
#define ICOND_JNO 0x01
#define ICOND_JB  0x02
#define ICOND_JAE 0x03
#define ICOND_JE  0x04
#define ICOND_JNE 0x05
#define ICOND_JBE 0x06
#define ICOND_JA  0x07
#define ICOND_JS  0x08
#define ICOND_JNS 0x09
#define ICOND_JL  0x0c
#define ICOND_JGE 0x0d
#define ICOND_JLE 0x0e
#define ICOND_JG  0x0f

#define IOP_JMP   0xeb

// unified conditions (we just use rel8 jump instructions for x86)
#define DCOND_EQ ICOND_JE
#define DCOND_NE ICOND_JNE
#define DCOND_MI ICOND_JS      // MInus
#define DCOND_PL ICOND_JNS     // PLus or zero
#define DCOND_HI ICOND_JA      // higher (unsigned)
#define DCOND_HS ICOND_JAE     // higher || same (unsigned)
#define DCOND_LO ICOND_JB      // lower (unsigned)
#define DCOND_LS ICOND_JBE     // lower || same (unsigned)
#define DCOND_GE ICOND_JGE     // greater || equal (signed)
#define DCOND_GT ICOND_JG      // greater (signed)
#define DCOND_LE ICOND_JLE     // less || equal (signed)
#define DCOND_LT ICOND_JL      // less (signed)
#define DCOND_VS ICOND_JO      // oVerflow Set
#define DCOND_VC ICOND_JNO     // oVerflow Clear

#define EMIT_PTR(ptr, val, type) \
	*(type *)(ptr) = val

#define EMIT(val, type) { \
	EMIT_PTR(tcache_ptr, val, type); \
	tcache_ptr += sizeof(type); \
}

#define EMIT_OP(op) { \
	COUNT_OP; \
	EMIT(op, u8); \
}

#define EMIT_MODRM(mod,r,rm) \
	EMIT(((mod)<<6) | ((r)<<3) | (rm), u8)

#define EMIT_SIB(scale,index,base) \
	EMIT(((scale)<<6) | ((index)<<3) | (base), u8)

#define EMIT_OP_MODRM(op,mod,r,rm) { \
	EMIT_OP(op); \
	EMIT_MODRM(mod, r, rm); \
}

#define JMP8_POS(ptr) \
	ptr = tcache_ptr; \
	tcache_ptr += 2

#define JMP8_EMIT(op, ptr) \
	EMIT_PTR(ptr, 0x70|(op), u8); \
	EMIT_PTR(ptr + 1, (tcache_ptr - (ptr+2)), u8)

#define JMP8_EMIT_NC(ptr) \
	EMIT_PTR(ptr, IOP_JMP, u8); \
	EMIT_PTR(ptr + 1, (tcache_ptr - (ptr+2)), u8)

// _r_r
#define emith_move_r_r(dst, src) \
	EMIT_OP_MODRM(0x8b, 3, dst, src)

#define emith_add_r_r(d, s) \
	EMIT_OP_MODRM(0x01, 3, s, d)

#define emith_sub_r_r(d, s) \
	EMIT_OP_MODRM(0x29, 3, s, d)

#define emith_adc_r_r(d, s) \
	EMIT_OP_MODRM(0x11, 3, s, d)

#define emith_sbc_r_r(d, s) \
	EMIT_OP_MODRM(0x19, 3, s, d) /* SBB */

#define emith_or_r_r(d, s) \
	EMIT_OP_MODRM(0x09, 3, s, d)

#define emith_and_r_r(d, s) \
	EMIT_OP_MODRM(0x21, 3, s, d)

#define emith_eor_r_r(d, s) \
	EMIT_OP_MODRM(0x31, 3, s, d) /* XOR */

#define emith_tst_r_r(d, s) \
	EMIT_OP_MODRM(0x85, 3, s, d) /* TEST */

#define emith_cmp_r_r(d, s) \
	EMIT_OP_MODRM(0x39, 3, s, d)

// fake teq - test equivalence - get_flags(d ^ s)
#define emith_teq_r_r(d, s) { \
	emith_push(d); \
	emith_eor_r_r(d, s); \
	emith_pop(d); \
}

#define emith_mvn_r_r(d, s) { \
	if (d != s) \
		emith_move_r_r(d, s); \
	EMIT_OP_MODRM(0xf7, 3, 2, d); /* NOT d */ \
}

#define emith_negc_r_r(d, s) { \
	int tmp_ = rcache_get_tmp(); \
	emith_move_r_imm(tmp_, 0); \
	emith_sbc_r_r(tmp_, s); \
	emith_move_r_r(d, tmp_); \
	rcache_free_tmp(tmp_); \
}

#define emith_neg_r_r(d, s) { \
	if (d != s) \
		emith_move_r_r(d, s); \
	EMIT_OP_MODRM(0xf7, 3, 3, d); /* NEG d */ \
}

// _r_r_r
#define emith_eor_r_r_r(d, s1, s2) { \
	if (d == s1) { \
		emith_eor_r_r(d, s2); \
	} else if (d == s2) { \
		emith_eor_r_r(d, s1); \
	} else { \
		emith_move_r_r(d, s1); \
		emith_eor_r_r(d, s2); \
	} \
}

// _r_r_shift
#define emith_or_r_r_lsl(d, s, lslimm) { \
	int tmp_ = rcache_get_tmp(); \
	emith_lsl(tmp_, s, lslimm); \
	emith_or_r_r(d, tmp_); \
	rcache_free_tmp(tmp_); \
}

// d != s
#define emith_eor_r_r_lsr(d, s, lsrimm) { \
	emith_push(s); \
	emith_lsr(s, s, lsrimm); \
	emith_eor_r_r(d, s); \
	emith_pop(s); \
}

// _r_imm
#define emith_move_r_imm(r, imm) { \
	EMIT_OP(0xb8 + (r)); \
	EMIT(imm, u32); \
}

#define emith_move_r_imm_s8(r, imm) \
	emith_move_r_imm(r, (u32)(signed int)(signed char)(imm))

#define emith_arith_r_imm(op, r, imm) do { \
	EMIT_OP_MODRM(0x81, 3, op, r); \
	EMIT(imm, u32); \
} while (0)

// 2 - adc, 3 - sbb
#define emith_add_r_imm(r, imm) \
	emith_arith_r_imm(0, r, imm)

#define emith_or_r_imm(r, imm) \
	emith_arith_r_imm(1, r, imm)

#define emith_and_r_imm(r, imm) \
	emith_arith_r_imm(4, r, imm)

#define emith_sub_r_imm(r, imm) \
	emith_arith_r_imm(5, r, imm)

#define emith_eor_r_imm(r, imm) \
	emith_arith_r_imm(6, r, imm)

#define emith_cmp_r_imm(r, imm) \
	emith_arith_r_imm(7, r, imm)

#define emith_tst_r_imm(r, imm) do { \
	EMIT_OP_MODRM(0xf7, 3, 0, r); \
	EMIT(imm, u32); \
} while (0)

// fake
#define emith_bic_r_imm(r, imm) \
	emith_arith_r_imm(4, r, ~(imm))

// fake conditionals (using SJMP instead)
#define emith_move_r_imm_c(cond, r, imm) { \
	(void)(cond); \
	emith_move_r_imm(r, imm); \
}

#define emith_add_r_imm_c(cond, r, imm) { \
	(void)(cond); \
	emith_add_r_imm(r, imm); \
}

#define emith_or_r_imm_c(cond, r, imm) { \
	(void)(cond); \
	emith_or_r_imm(r, imm); \
}

#define emith_eor_r_imm_c(cond, r, imm) { \
	(void)(cond); \
	emith_eor_r_imm(r, imm); \
}

#define emith_sub_r_imm_c(cond, r, imm) { \
	(void)(cond); \
	emith_sub_r_imm(r, imm); \
}

#define emith_bic_r_imm_c(cond, r, imm) { \
	(void)(cond); \
	emith_bic_r_imm(r, imm); \
}

#define emith_jump_reg_c(cond, r) emith_jump_reg(r)
#define emith_jump_ctx_c(cond, offs) emith_jump_ctx(offs)
#define emith_ret_c(cond) emith_ret()

// _r_r_imm
#define emith_add_r_r_imm(d, s, imm) { \
	if (d != s) \
		emith_move_r_r(d, s); \
	emith_add_r_imm(d, imm); \
}

#define emith_and_r_r_imm(d, s, imm) { \
	if (d != s) \
		emith_move_r_r(d, s); \
	emith_and_r_imm(d, imm); \
}

// shift
#define emith_shift(op, d, s, cnt) { \
	if (d != s) \
		emith_move_r_r(d, s); \
	EMIT_OP_MODRM(0xc1, 3, op, d); \
	EMIT(cnt, u8); \
}

#define emith_lsl(d, s, cnt) \
	emith_shift(4, d, s, cnt)

#define emith_lsr(d, s, cnt) \
	emith_shift(5, d, s, cnt)

#define emith_asr(d, s, cnt) \
	emith_shift(7, d, s, cnt)

#define emith_rol(d, s, cnt) \
	emith_shift(0, d, s, cnt)

#define emith_ror(d, s, cnt) \
	emith_shift(1, d, s, cnt)

#define emith_rolc(r) \
	EMIT_OP_MODRM(0xd1, 3, 2, r)

#define emith_rorc(r) \
	EMIT_OP_MODRM(0xd1, 3, 3, r)

// misc
#define emith_push(r) \
	EMIT_OP(0x50 + (r))

#define emith_push_imm(imm) { \
	EMIT_OP(0x68); \
	EMIT(imm, u32); \
}

#define emith_pop(r) \
	EMIT_OP(0x58 + (r))

#define emith_neg_r(r) \
	EMIT_OP_MODRM(0xf7, 3, 3, r)

#define emith_clear_msb(d, s, count) { \
	u32 t = (u32)-1; \
	t >>= count; \
	if (d != s) \
		emith_move_r_r(d, s); \
	emith_and_r_imm(d, t); \
}

#define emith_clear_msb_c(cond, d, s, count) { \
	(void)(cond); \
	emith_clear_msb(d, s, count); \
}

#define emith_sext(d, s, bits) { \
	emith_lsl(d, s, 32 - (bits)); \
	emith_asr(d, d, 32 - (bits)); \
}

#define emith_setc(r) { \
	EMIT_OP(0x0f); \
	EMIT_OP_MODRM(0x92, 3, 0, r); /* SETC r */ \
}

// XXX: stupid mess
#define emith_mul_(op, dlo, dhi, s1, s2) { \
	int rmr; \
	if (dlo != xAX && dhi != xAX) \
		emith_push(xAX); \
	if (dlo != xDX && dhi != xDX) \
		emith_push(xDX); \
	if ((s1) == xAX) \
		rmr = s2; \
	else if ((s2) == xAX) \
		rmr = s1; \
	else { \
		emith_move_r_r(xAX, s1); \
		rmr = s2; \
	} \
	EMIT_OP_MODRM(0xf7, 3, op, rmr); /* xMUL rmr */ \
	/* XXX: using push/pop for the case of edx->eax; eax->edx */ \
	if (dhi != xDX && dhi != -1) \
		emith_push(xDX); \
	if (dlo != xAX) \
		emith_move_r_r(dlo, xAX); \
	if (dhi != xDX && dhi != -1) \
		emith_pop(dhi); \
	if (dlo != xDX && dhi != xDX) \
		emith_pop(xDX); \
	if (dlo != xAX && dhi != xAX) \
		emith_pop(xAX); \
}

#define emith_mul_u64(dlo, dhi, s1, s2) \
	emith_mul_(4, dlo, dhi, s1, s2) /* MUL */

#define emith_mul_s64(dlo, dhi, s1, s2) \
	emith_mul_(5, dlo, dhi, s1, s2) /* IMUL */

#define emith_mul(d, s1, s2) \
	emith_mul_(4, d, -1, s1, s2)

// (dlo,dhi) += signed(s1) * signed(s2)
#define emith_mula_s64(dlo, dhi, s1, s2) { \
	emith_push(dhi); \
	emith_push(dlo); \
	emith_mul_(5, dlo, dhi, s1, s2); \
	EMIT_OP_MODRM(0x03, 0, dlo, 4); \
	EMIT_SIB(0, 4, 4); /* add dlo, [esp] */ \
	EMIT_OP_MODRM(0x13, 1, dhi, 4); \
	EMIT_SIB(0, 4, 4); \
	EMIT(4, u8); /* adc dhi, [esp+4] */ \
	emith_add_r_imm(xSP, 4*2); \
}

// "flag" instructions are the same
#define emith_subf_r_imm emith_sub_r_imm
#define emith_addf_r_r   emith_add_r_r
#define emith_subf_r_r   emith_sub_r_r
#define emith_adcf_r_r   emith_adc_r_r
#define emith_sbcf_r_r   emith_sbc_r_r
#define emith_eorf_r_r   emith_eor_r_r
#define emith_negcf_r_r  emith_negc_r_r

#define emith_lslf  emith_lsl
#define emith_lsrf  emith_lsr
#define emith_asrf  emith_asr
#define emith_rolf  emith_rol
#define emith_rorf  emith_ror
#define emith_rolcf emith_rolc
#define emith_rorcf emith_rorc

#define emith_ctx_op(op, r, offs) do { \
	/* mov r <-> [ebp+#offs] */ \
	if ((offs) >= 0x80) { \
		EMIT_OP_MODRM(op, 2, r, xBP); \
		EMIT(offs, u32); \
	} else { \
		EMIT_OP_MODRM(op, 1, r, xBP); \
		EMIT(offs, u8); \
	} \
} while (0)

#define emith_ctx_read(r, offs) \
	emith_ctx_op(0x8b, r, offs)

#define emith_ctx_write(r, offs) \
	emith_ctx_op(0x89, r, offs)

#define emith_ctx_read_multiple(r, offs, cnt, tmpr) do { \
	int r_ = r, offs_ = offs, cnt_ = cnt;     \
	for (; cnt_ > 0; r_++, offs_ += 4, cnt_--) \
		emith_ctx_read(r_, offs_);        \
} while (0)

#define emith_ctx_write_multiple(r, offs, cnt, tmpr) do { \
	int r_ = r, offs_ = offs, cnt_ = cnt;     \
	for (; cnt_ > 0; r_++, offs_ += 4, cnt_--) \
		emith_ctx_write(r_, offs_);       \
} while (0)

// assumes EBX is free
#define emith_ret_to_ctx(offs) { \
	emith_pop(xBX); \
	emith_ctx_write(xBX, offs); \
}

#define emith_jump(ptr) { \
	u32 disp = (u32)(ptr) - ((u32)tcache_ptr + 5); \
	EMIT_OP(0xe9); \
	EMIT(disp, u32); \
}

#define emith_jump_cond(cond, ptr) { \
	u32 disp = (u32)(ptr) - ((u32)tcache_ptr + 6); \
	EMIT(0x0f, u8); \
	EMIT_OP(0x80 | (cond)); \
	EMIT(disp, u32); \
}

#define emith_jump_patchable(cond) \
	emith_jump_cond(cond, 0)

#define emith_jump_patch(ptr, target) do { \
	u32 disp = (u32)(target) - ((u32)(ptr) + 6); \
	EMIT_PTR((u8 *)(ptr) + 2, disp, u32); \
} while (0)

#define emith_call(ptr) { \
	u32 disp = (u32)(ptr) - ((u32)tcache_ptr + 5); \
	EMIT_OP(0xe8); \
	EMIT(disp, u32); \
}

#define emith_call_cond(cond, ptr) \
	emith_call(ptr)

#define emith_call_reg(r) \
	EMIT_OP_MODRM(0xff, 3, 2, r)

#define emith_call_ctx(offs) { \
	EMIT_OP_MODRM(0xff, 2, 2, xBP); \
	EMIT(offs, u32); \
}

#define emith_ret() \
	EMIT_OP(0xc3)

#define emith_jump_reg(r) \
	EMIT_OP_MODRM(0xff, 3, 4, r)

#define emith_jump_ctx(offs) { \
	EMIT_OP_MODRM(0xff, 2, 4, xBP); \
	EMIT(offs, u32); \
}

#define EMITH_JMP_START(cond) { \
	u8 *cond_ptr; \
	JMP8_POS(cond_ptr)

#define EMITH_JMP_END(cond) \
	JMP8_EMIT(cond, cond_ptr); \
}

// "simple" jump (no more then a few insns)
#define EMITH_SJMP_START EMITH_JMP_START
#define EMITH_SJMP_END EMITH_JMP_END

#define host_arg2reg(rd, arg) \
	switch (arg) { \
	case 0: rd = xAX; break; \
	case 1: rd = xDX; break; \
	case 2: rd = xCX; break; \
	}

#define emith_pass_arg_r(arg, reg) { \
	int rd = 7; \
	host_arg2reg(rd, arg); \
	emith_move_r_r(rd, reg); \
}

#define emith_pass_arg_imm(arg, imm) { \
	int rd = 7; \
	host_arg2reg(rd, arg); \
	emith_move_r_imm(rd, imm); \
}

/* SH2 drc specific */
#define emith_sh2_drc_entry() { \
	emith_push(xBX);        \
	emith_push(xBP);        \
	emith_push(xSI);        \
	emith_push(xDI);        \
}

#define emith_sh2_drc_exit() {  \
	emith_pop(xDI);         \
	emith_pop(xSI);         \
	emith_pop(xBP);         \
	emith_pop(xBX);         \
	emith_ret();            \
}

// assumes EBX is free temporary
#define emith_sh2_wcall(a, tab, ret_ptr) { \
	int arg2_; \
	host_arg2reg(arg2_, 2); \
	emith_lsr(xBX, a, SH2_WRITE_SHIFT); \
	EMIT_OP_MODRM(0x8b, 0, xBX, 4); \
	EMIT_SIB(2, xBX, tab); /* mov ebx, [tab + ebx * 4] */ \
	emith_ctx_read(arg2_, offsetof(SH2, is_slave)); \
	emith_push_imm((long)(ret_ptr)); \
	emith_jump_reg(xBX); \
}

#define emith_sh2_dtbf_loop() { \
	u8 *jmp0; /* negative cycles check */            \
	u8 *jmp1; /* unsinged overflow check */          \
	int cr, rn;                                      \
	int tmp_ = rcache_get_tmp();                     \
	cr = rcache_get_reg(SHR_SR, RC_GR_RMW);          \
	rn = rcache_get_reg((op >> 8) & 0x0f, RC_GR_RMW);\
	emith_sub_r_imm(rn, 1);                          \
	emith_sub_r_imm(cr, (cycles+1) << 12);           \
	cycles = 0;                                      \
	emith_asr(tmp_, cr, 2+12);                       \
	JMP8_POS(jmp0); /* no negative cycles */         \
	emith_move_r_imm(tmp_, 0);                       \
	JMP8_EMIT(ICOND_JNS, jmp0);                      \
	emith_and_r_imm(cr, 0xffe);                      \
	emith_subf_r_r(rn, tmp_);                        \
	JMP8_POS(jmp1); /* no overflow */                \
	emith_neg_r(rn); /* count left */                \
	emith_lsl(rn, rn, 2+12);                         \
	emith_or_r_r(cr, rn);                            \
	emith_or_r_imm(cr, 1);                           \
	emith_move_r_imm(rn, 0);                         \
	JMP8_EMIT(ICOND_JA, jmp1);                       \
	rcache_free_tmp(tmp_);                           \
}

#define emith_write_sr(sr, srcr) { \
	int tmp_ = rcache_get_tmp(); \
	emith_clear_msb(tmp_, srcr, 22); \
	emith_bic_r_imm(sr, 0x3ff); \
	emith_or_r_r(sr, tmp_); \
	rcache_free_tmp(tmp_); \
}

#define emith_tpop_carry(sr, is_sub) \
	emith_lsr(sr, sr, 1)

#define emith_tpush_carry(sr, is_sub) \
	emith_adc_r_r(sr, sr)

/*
 * if Q
 *   t = carry(Rn += Rm)
 * else
 *   t = carry(Rn -= Rm)
 * T ^= t
 */
#define emith_sh2_div1_step(rn, rm, sr) {         \
	u8 *jmp0, *jmp1;                          \
	int tmp_ = rcache_get_tmp();              \
	emith_eor_r_r(tmp_, tmp_);                \
	emith_tst_r_imm(sr, Q);  /* if (Q ^ M) */ \
	JMP8_POS(jmp0);          /* je do_sub */  \
	emith_add_r_r(rn, rm);                    \
	JMP8_POS(jmp1);          /* jmp done */   \
	JMP8_EMIT(ICOND_JE, jmp0); /* do_sub: */  \
	emith_sub_r_r(rn, rm);                    \
	JMP8_EMIT_NC(jmp1);      /* done: */      \
	emith_setc(tmp_);                         \
	EMIT_OP_MODRM(0x31, 3, tmp_, sr); /* T = Q1 ^ Q2 */ \
	rcache_free_tmp(tmp_);                    \
}
Commit	Line	Data
3863edbd	1	/*
8b4f38f4	2	* note:
8b4f38f4	3	* temp registers must be eax-edx due to use of SETcc.
f0d7b1fa	4	* note about silly things like emith_eor_r_r_r:
8b4f38f4	5	* these are here because the compiler was designed
8b4f38f4	6	* for ARM as it's primary target.
3863edbd	7	*/
679af8a3	8	#include <stdarg.h>
679af8a3	9
f4bb5d6b	10	enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
f4bb5d6b	11
f4bb5d6b	12	#define CONTEXT_REG xBP
679af8a3	13
18b94127	14	#define ICOND_JO 0x00
	15	#define ICOND_JNO 0x01
	16	#define ICOND_JB 0x02
	17	#define ICOND_JAE 0x03
	18	#define ICOND_JE 0x04
	19	#define ICOND_JNE 0x05
	20	#define ICOND_JBE 0x06
	21	#define ICOND_JA 0x07
	22	#define ICOND_JS 0x08
	23	#define ICOND_JNS 0x09
	24	#define ICOND_JL 0x0c
	25	#define ICOND_JGE 0x0d
	26	#define ICOND_JLE 0x0e
	27	#define ICOND_JG 0x0f
	28
	29	#define IOP_JMP 0xeb
80599a42	30
80599a42	31	// unified conditions (we just use rel8 jump instructions for x86)
18b94127	32	#define DCOND_EQ ICOND_JE
	33	#define DCOND_NE ICOND_JNE
	34	#define DCOND_MI ICOND_JS // MInus
	35	#define DCOND_PL ICOND_JNS // PLus or zero
	36	#define DCOND_HI ICOND_JA // higher (unsigned)
	37	#define DCOND_HS ICOND_JAE // higher \|\| same (unsigned)
	38	#define DCOND_LO ICOND_JB // lower (unsigned)
	39	#define DCOND_LS ICOND_JBE // lower \|\| same (unsigned)
	40	#define DCOND_GE ICOND_JGE // greater \|\| equal (signed)
	41	#define DCOND_GT ICOND_JG // greater (signed)
	42	#define DCOND_LE ICOND_JLE // less \|\| equal (signed)
	43	#define DCOND_LT ICOND_JL // less (signed)
	44	#define DCOND_VS ICOND_JO // oVerflow Set
	45	#define DCOND_VC ICOND_JNO // oVerflow Clear
80599a42	46
679af8a3	47	#define EMIT_PTR(ptr, val, type) \
	48	(type )(ptr) = val
	49
	50	#define EMIT(val, type) { \
	51	EMIT_PTR(tcache_ptr, val, type); \
f4bb5d6b	52	tcache_ptr += sizeof(type); \
679af8a3	53	}
679af8a3	54
e898de13	55	#define EMIT_OP(op) { \
	56	COUNT_OP; \
	57	EMIT(op, u8); \
	58	}
	59
679af8a3	60	#define EMIT_MODRM(mod,r,rm) \
	61	EMIT(((mod)<<6) \| ((r)<<3) \| (rm), u8)
	62
f0d7b1fa	63	#define EMIT_SIB(scale,index,base) \
	64	EMIT(((scale)<<6) \| ((index)<<3) \| (base), u8)
	65
679af8a3	66	#define EMIT_OP_MODRM(op,mod,r,rm) { \
e898de13	67	EMIT_OP(op); \
679af8a3	68	EMIT_MODRM(mod, r, rm); \
	69	}
	70
80599a42	71	#define JMP8_POS(ptr) \
	72	ptr = tcache_ptr; \
	73	tcache_ptr += 2
	74
	75	#define JMP8_EMIT(op, ptr) \
18b94127	76	EMIT_PTR(ptr, 0x70\|(op), u8); \
	77	EMIT_PTR(ptr + 1, (tcache_ptr - (ptr+2)), u8)
	78
	79	#define JMP8_EMIT_NC(ptr) \
	80	EMIT_PTR(ptr, IOP_JMP, u8); \
80599a42	81	EMIT_PTR(ptr + 1, (tcache_ptr - (ptr+2)), u8)
80599a42	82
3863edbd	83	// _r_r
679af8a3	84	#define emith_move_r_r(dst, src) \
	85	EMIT_OP_MODRM(0x8b, 3, dst, src)
	86
80599a42	87	#define emith_add_r_r(d, s) \
	88	EMIT_OP_MODRM(0x01, 3, s, d)
	89
	90	#define emith_sub_r_r(d, s) \
	91	EMIT_OP_MODRM(0x29, 3, s, d)
	92
3863edbd	93	#define emith_adc_r_r(d, s) \
	94	EMIT_OP_MODRM(0x11, 3, s, d)
	95
	96	#define emith_sbc_r_r(d, s) \
	97	EMIT_OP_MODRM(0x19, 3, s, d) /* SBB */
	98
80599a42	99	#define emith_or_r_r(d, s) \
	100	EMIT_OP_MODRM(0x09, 3, s, d)
	101
3863edbd	102	#define emith_and_r_r(d, s) \
	103	EMIT_OP_MODRM(0x21, 3, s, d)
	104
80599a42	105	#define emith_eor_r_r(d, s) \
3863edbd	106	EMIT_OP_MODRM(0x31, 3, s, d) /* XOR */
	107
	108	#define emith_tst_r_r(d, s) \
	109	EMIT_OP_MODRM(0x85, 3, s, d) /* TEST */
	110
	111	#define emith_cmp_r_r(d, s) \
	112	EMIT_OP_MODRM(0x39, 3, s, d)
80599a42	113
	114	// fake teq - test equivalence - get_flags(d ^ s)
	115	#define emith_teq_r_r(d, s) { \
	116	emith_push(d); \
	117	emith_eor_r_r(d, s); \
	118	emith_pop(d); \
	119	}
	120
52d759c3	121	#define emith_mvn_r_r(d, s) { \
	122	if (d != s) \
	123	emith_move_r_r(d, s); \
	124	EMIT_OP_MODRM(0xf7, 3, 2, d); /* NOT d */ \
	125	}
	126
	127	#define emith_negc_r_r(d, s) { \
	128	int tmp_ = rcache_get_tmp(); \
	129	emith_move_r_imm(tmp_, 0); \
	130	emith_sbc_r_r(tmp_, s); \
	131	emith_move_r_r(d, tmp_); \
	132	rcache_free_tmp(tmp_); \
	133	}
	134
	135	#define emith_neg_r_r(d, s) { \
	136	if (d != s) \
	137	emith_move_r_r(d, s); \
	138	EMIT_OP_MODRM(0xf7, 3, 3, d); /* NEG d */ \
	139	}
	140
3863edbd	141	// _r_r_r
3863edbd	142	#define emith_eor_r_r_r(d, s1, s2) { \
52d759c3	143	if (d == s1) { \
	144	emith_eor_r_r(d, s2); \
	145	} else if (d == s2) { \
	146	emith_eor_r_r(d, s1); \
	147	} else { \
3863edbd	148	emith_move_r_r(d, s1); \
52d759c3	149	emith_eor_r_r(d, s2); \
52d759c3	150	} \
3863edbd	151	}
3863edbd	152
f0d7b1fa	153	// _r_r_shift
f0d7b1fa	154	#define emith_or_r_r_lsl(d, s, lslimm) { \
52d759c3	155	int tmp_ = rcache_get_tmp(); \
f0d7b1fa	156	emith_lsl(tmp_, s, lslimm); \
f0d7b1fa	157	emith_or_r_r(d, tmp_); \
52d759c3	158	rcache_free_tmp(tmp_); \
3863edbd	159	}
3863edbd	160
f0d7b1fa	161	// d != s
	162	#define emith_eor_r_r_lsr(d, s, lsrimm) { \
	163	emith_push(s); \
	164	emith_lsr(s, s, lsrimm); \
	165	emith_eor_r_r(d, s); \
	166	emith_pop(s); \
	167	}
	168
80599a42	169	// _r_imm
679af8a3	170	#define emith_move_r_imm(r, imm) { \
e898de13	171	EMIT_OP(0xb8 + (r)); \
679af8a3	172	EMIT(imm, u32); \
	173	}
	174
52d759c3	175	#define emith_move_r_imm_s8(r, imm) \
	176	emith_move_r_imm(r, (u32)(signed int)(signed char)(imm))
	177
18b94127	178	#define emith_arith_r_imm(op, r, imm) do { \
80599a42	179	EMIT_OP_MODRM(0x81, 3, op, r); \
679af8a3	180	EMIT(imm, u32); \
18b94127	181	} while (0)
679af8a3	182
52d759c3	183	// 2 - adc, 3 - sbb
80599a42	184	#define emith_add_r_imm(r, imm) \
	185	emith_arith_r_imm(0, r, imm)
	186
	187	#define emith_or_r_imm(r, imm) \
	188	emith_arith_r_imm(1, r, imm)
	189
	190	#define emith_and_r_imm(r, imm) \
	191	emith_arith_r_imm(4, r, imm)
	192
	193	#define emith_sub_r_imm(r, imm) \
	194	emith_arith_r_imm(5, r, imm)
	195
52d759c3	196	#define emith_eor_r_imm(r, imm) \
	197	emith_arith_r_imm(6, r, imm)
	198
ed8cf79b	199	#define emith_cmp_r_imm(r, imm) \
	200	emith_arith_r_imm(7, r, imm)
	201
18b94127	202	#define emith_tst_r_imm(r, imm) do { \
80599a42	203	EMIT_OP_MODRM(0xf7, 3, 0, r); \
679af8a3	204	EMIT(imm, u32); \
18b94127	205	} while (0)
679af8a3	206
80599a42	207	// fake
	208	#define emith_bic_r_imm(r, imm) \
	209	emith_arith_r_imm(4, r, ~(imm))
	210
	211	// fake conditionals (using SJMP instead)
8796b7ee	212	#define emith_move_r_imm_c(cond, r, imm) { \
	213	(void)(cond); \
	214	emith_move_r_imm(r, imm); \
	215	}
	216
80599a42	217	#define emith_add_r_imm_c(cond, r, imm) { \
80599a42	218	(void)(cond); \
3863edbd	219	emith_add_r_imm(r, imm); \
80599a42	220	}
	221
	222	#define emith_or_r_imm_c(cond, r, imm) { \
	223	(void)(cond); \
3863edbd	224	emith_or_r_imm(r, imm); \
80599a42	225	}
80599a42	226
f0d7b1fa	227	#define emith_eor_r_imm_c(cond, r, imm) { \
	228	(void)(cond); \
	229	emith_eor_r_imm(r, imm); \
	230	}
	231
80599a42	232	#define emith_sub_r_imm_c(cond, r, imm) { \
80599a42	233	(void)(cond); \
3863edbd	234	emith_sub_r_imm(r, imm); \
	235	}
	236
	237	#define emith_bic_r_imm_c(cond, r, imm) { \
	238	(void)(cond); \
	239	emith_bic_r_imm(r, imm); \
80599a42	240	}
80599a42	241
e05b81fc	242	#define emith_jump_reg_c(cond, r) emith_jump_reg(r)
	243	#define emith_jump_ctx_c(cond, offs) emith_jump_ctx(offs)
	244	#define emith_ret_c(cond) emith_ret()
	245
52d759c3	246	// _r_r_imm
e05b81fc	247	#define emith_add_r_r_imm(d, s, imm) { \
	248	if (d != s) \
	249	emith_move_r_r(d, s); \
	250	emith_add_r_imm(d, imm); \
	251	}
	252
52d759c3	253	#define emith_and_r_r_imm(d, s, imm) { \
	254	if (d != s) \
	255	emith_move_r_r(d, s); \
18b94127	256	emith_and_r_imm(d, imm); \
52d759c3	257	}
52d759c3	258
80599a42	259	// shift
	260	#define emith_shift(op, d, s, cnt) { \
	261	if (d != s) \
	262	emith_move_r_r(d, s); \
	263	EMIT_OP_MODRM(0xc1, 3, op, d); \
	264	EMIT(cnt, u8); \
	265	}
	266
80599a42	267	#define emith_lsl(d, s, cnt) \
	268	emith_shift(4, d, s, cnt)
	269
3863edbd	270	#define emith_lsr(d, s, cnt) \
	271	emith_shift(5, d, s, cnt)
	272
	273	#define emith_asr(d, s, cnt) \
	274	emith_shift(7, d, s, cnt)
	275
ed8cf79b	276	#define emith_rol(d, s, cnt) \
	277	emith_shift(0, d, s, cnt)
	278
	279	#define emith_ror(d, s, cnt) \
	280	emith_shift(1, d, s, cnt)
	281
	282	#define emith_rolc(r) \
	283	EMIT_OP_MODRM(0xd1, 3, 2, r)
	284
	285	#define emith_rorc(r) \
	286	EMIT_OP_MODRM(0xd1, 3, 3, r)
	287
80599a42	288	// misc
	289	#define emith_push(r) \
	290	EMIT_OP(0x50 + (r))
	291
e05b81fc	292	#define emith_push_imm(imm) { \
	293	EMIT_OP(0x68); \
	294	EMIT(imm, u32); \
	295	}
	296
80599a42	297	#define emith_pop(r) \
	298	EMIT_OP(0x58 + (r))
	299
	300	#define emith_neg_r(r) \
	301	EMIT_OP_MODRM(0xf7, 3, 3, r)
	302
	303	#define emith_clear_msb(d, s, count) { \
	304	u32 t = (u32)-1; \
	305	t >>= count; \
	306	if (d != s) \
	307	emith_move_r_r(d, s); \
	308	emith_and_r_imm(d, t); \
	309	}
	310
f0d7b1fa	311	#define emith_clear_msb_c(cond, d, s, count) { \
	312	(void)(cond); \
	313	emith_clear_msb(d, s, count); \
	314	}
	315
80599a42	316	#define emith_sext(d, s, bits) { \
	317	emith_lsl(d, s, 32 - (bits)); \
	318	emith_asr(d, d, 32 - (bits)); \
	319	}
	320
f0d7b1fa	321	#define emith_setc(r) { \
f0d7b1fa	322	EMIT_OP(0x0f); \
8b4f38f4	323	EMIT_OP_MODRM(0x92, 3, 0, r); /* SETC r */ \
f0d7b1fa	324	}
f0d7b1fa	325
80599a42	326	// XXX: stupid mess
3863edbd	327	#define emith_mul_(op, dlo, dhi, s1, s2) { \
80599a42	328	int rmr; \
3863edbd	329	if (dlo != xAX && dhi != xAX) \
80599a42	330	emith_push(xAX); \
3863edbd	331	if (dlo != xDX && dhi != xDX) \
3863edbd	332	emith_push(xDX); \
80599a42	333	if ((s1) == xAX) \
	334	rmr = s2; \
	335	else if ((s2) == xAX) \
	336	rmr = s1; \
	337	else { \
	338	emith_move_r_r(xAX, s1); \
	339	rmr = s2; \
	340	} \
3863edbd	341	EMIT_OP_MODRM(0xf7, 3, op, rmr); /* xMUL rmr */ \
	342	/* XXX: using push/pop for the case of edx->eax; eax->edx */ \
	343	if (dhi != xDX && dhi != -1) \
	344	emith_push(xDX); \
	345	if (dlo != xAX) \
	346	emith_move_r_r(dlo, xAX); \
	347	if (dhi != xDX && dhi != -1) \
	348	emith_pop(dhi); \
	349	if (dlo != xDX && dhi != xDX) \
	350	emith_pop(xDX); \
	351	if (dlo != xAX && dhi != xAX) \
80599a42	352	emith_pop(xAX); \
80599a42	353	}
80599a42	354
3863edbd	355	#define emith_mul_u64(dlo, dhi, s1, s2) \
	356	emith_mul_(4, dlo, dhi, s1, s2) /* MUL */
	357
	358	#define emith_mul_s64(dlo, dhi, s1, s2) \
	359	emith_mul_(5, dlo, dhi, s1, s2) /* IMUL */
	360
	361	#define emith_mul(d, s1, s2) \
	362	emith_mul_(4, d, -1, s1, s2)
	363
f0d7b1fa	364	// (dlo,dhi) += signed(s1) * signed(s2)
	365	#define emith_mula_s64(dlo, dhi, s1, s2) { \
	366	emith_push(dhi); \
	367	emith_push(dlo); \
	368	emith_mul_(5, dlo, dhi, s1, s2); \
	369	EMIT_OP_MODRM(0x03, 0, dlo, 4); \
	370	EMIT_SIB(0, 4, 4); /* add dlo, [esp] */ \
	371	EMIT_OP_MODRM(0x13, 1, dhi, 4); \
	372	EMIT_SIB(0, 4, 4); \
	373	EMIT(4, u8); /* adc dhi, [esp+4] */ \
	374	emith_add_r_imm(xSP, 4*2); \
	375	}
	376
80599a42	377	// "flag" instructions are the same
80599a42	378	#define emith_subf_r_imm emith_sub_r_imm
3863edbd	379	#define emith_addf_r_r emith_add_r_r
80599a42	380	#define emith_subf_r_r emith_sub_r_r
3863edbd	381	#define emith_adcf_r_r emith_adc_r_r
3863edbd	382	#define emith_sbcf_r_r emith_sbc_r_r
8796b7ee	383	#define emith_eorf_r_r emith_eor_r_r
52d759c3	384	#define emith_negcf_r_r emith_negc_r_r
3863edbd	385
ed8cf79b	386	#define emith_lslf emith_lsl
	387	#define emith_lsrf emith_lsr
	388	#define emith_asrf emith_asr
	389	#define emith_rolf emith_rol
	390	#define emith_rorf emith_ror
	391	#define emith_rolcf emith_rolc
	392	#define emith_rorcf emith_rorc
80599a42	393
e05b81fc	394	#define emith_ctx_op(op, r, offs) do { \
	395	/* mov r <-> [ebp+#offs] */ \
	396	if ((offs) >= 0x80) { \
	397	EMIT_OP_MODRM(op, 2, r, xBP); \
	398	EMIT(offs, u32); \
	399	} else { \
	400	EMIT_OP_MODRM(op, 1, r, xBP); \
	401	EMIT(offs, u8); \
	402	} \
8796b7ee	403	} while (0)
679af8a3	404
e05b81fc	405	#define emith_ctx_read(r, offs) \
	406	emith_ctx_op(0x8b, r, offs)
	407
	408	#define emith_ctx_write(r, offs) \
	409	emith_ctx_op(0x89, r, offs)
	410
8796b7ee	411	#define emith_ctx_read_multiple(r, offs, cnt, tmpr) do { \
8796b7ee	412	int r_ = r, offs_ = offs, cnt_ = cnt; \
8b4f38f4	413	for (; cnt_ > 0; r_++, offs_ += 4, cnt_--) \
8796b7ee	414	emith_ctx_read(r_, offs_); \
	415	} while (0)
	416
8796b7ee	417	#define emith_ctx_write_multiple(r, offs, cnt, tmpr) do { \
8796b7ee	418	int r_ = r, offs_ = offs, cnt_ = cnt; \
8b4f38f4	419	for (; cnt_ > 0; r_++, offs_ += 4, cnt_--) \
8796b7ee	420	emith_ctx_write(r_, offs_); \
8796b7ee	421	} while (0)
679af8a3	422
e05b81fc	423	// assumes EBX is free
	424	#define emith_ret_to_ctx(offs) { \
	425	emith_pop(xBX); \
	426	emith_ctx_write(xBX, offs); \
	427	}
	428
679af8a3	429	#define emith_jump(ptr) { \
18b94127	430	u32 disp = (u32)(ptr) - ((u32)tcache_ptr + 5); \
e898de13	431	EMIT_OP(0xe9); \
679af8a3	432	EMIT(disp, u32); \
	433	}
	434
18b94127	435	#define emith_jump_cond(cond, ptr) { \
	436	u32 disp = (u32)(ptr) - ((u32)tcache_ptr + 6); \
	437	EMIT(0x0f, u8); \
	438	EMIT_OP(0x80 \| (cond)); \
	439	EMIT(disp, u32); \
	440	}
	441
	442	#define emith_jump_patchable(cond) \
	443	emith_jump_cond(cond, 0)
	444
	445	#define emith_jump_patch(ptr, target) do { \
	446	u32 disp = (u32)(target) - ((u32)(ptr) + 6); \
	447	EMIT_PTR((u8 *)(ptr) + 2, disp, u32); \
	448	} while (0)
	449
679af8a3	450	#define emith_call(ptr) { \
18b94127	451	u32 disp = (u32)(ptr) - ((u32)tcache_ptr + 5); \
e898de13	452	EMIT_OP(0xe8); \
679af8a3	453	EMIT(disp, u32); \
	454	}
	455
f0d7b1fa	456	#define emith_call_cond(cond, ptr) \
	457	emith_call(ptr)
	458
e05b81fc	459	#define emith_call_reg(r) \
	460	EMIT_OP_MODRM(0xff, 3, 2, r)
	461
	462	#define emith_call_ctx(offs) { \
	463	EMIT_OP_MODRM(0xff, 2, 2, xBP); \
	464	EMIT(offs, u32); \
	465	}
	466
	467	#define emith_ret() \
	468	EMIT_OP(0xc3)
	469
8796b7ee	470	#define emith_jump_reg(r) \
	471	EMIT_OP_MODRM(0xff, 3, 4, r)
	472
e05b81fc	473	#define emith_jump_ctx(offs) { \
	474	EMIT_OP_MODRM(0xff, 2, 4, xBP); \
	475	EMIT(offs, u32); \
	476	}
	477
8796b7ee	478	#define EMITH_JMP_START(cond) { \
80599a42	479	u8 *cond_ptr; \
	480	JMP8_POS(cond_ptr)
	481
8796b7ee	482	#define EMITH_JMP_END(cond) \
80599a42	483	JMP8_EMIT(cond, cond_ptr); \
679af8a3	484	}
679af8a3	485
8796b7ee	486	// "simple" jump (no more then a few insns)
	487	#define EMITH_SJMP_START EMITH_JMP_START
	488	#define EMITH_SJMP_END EMITH_JMP_END
	489
80599a42	490	#define host_arg2reg(rd, arg) \
f4bb5d6b	491	switch (arg) { \
	492	case 0: rd = xAX; break; \
	493	case 1: rd = xDX; break; \
	494	case 2: rd = xCX; break; \
679af8a3	495	}
679af8a3	496
f4bb5d6b	497	#define emith_pass_arg_r(arg, reg) { \
f4bb5d6b	498	int rd = 7; \
80599a42	499	host_arg2reg(rd, arg); \
f4bb5d6b	500	emith_move_r_r(rd, reg); \
	501	}
	502
	503	#define emith_pass_arg_imm(arg, imm) { \
	504	int rd = 7; \
80599a42	505	host_arg2reg(rd, arg); \
f4bb5d6b	506	emith_move_r_imm(rd, imm); \
679af8a3	507	}
679af8a3	508
65c75cb0	509	/* SH2 drc specific */
8796b7ee	510	#define emith_sh2_drc_entry() { \
	511	emith_push(xBX); \
	512	emith_push(xBP); \
8b4f38f4	513	emith_push(xSI); \
8b4f38f4	514	emith_push(xDI); \
8796b7ee	515	}
	516
	517	#define emith_sh2_drc_exit() { \
8b4f38f4	518	emith_pop(xDI); \
8b4f38f4	519	emith_pop(xSI); \
8796b7ee	520	emith_pop(xBP); \
8796b7ee	521	emith_pop(xBX); \
e05b81fc	522	emith_ret(); \
	523	}
	524
	525	// assumes EBX is free temporary
	526	#define emith_sh2_wcall(a, tab, ret_ptr) { \
	527	int arg2_; \
	528	host_arg2reg(arg2_, 2); \
	529	emith_lsr(xBX, a, SH2_WRITE_SHIFT); \
	530	EMIT_OP_MODRM(0x8b, 0, xBX, 4); \
	531	EMIT_SIB(2, xBX, tab); /* mov ebx, [tab + ebx * 4] */ \
	532	emith_ctx_read(arg2_, offsetof(SH2, is_slave)); \
	533	emith_push_imm((long)(ret_ptr)); \
	534	emith_jump_reg(xBX); \
8796b7ee	535	}
8796b7ee	536
80599a42	537	#define emith_sh2_dtbf_loop() { \
	538	u8 jmp0; / negative cycles check */ \
	539	u8 jmp1; / unsinged overflow check */ \
	540	int cr, rn; \
52d759c3	541	int tmp_ = rcache_get_tmp(); \
80599a42	542	cr = rcache_get_reg(SHR_SR, RC_GR_RMW); \
	543	rn = rcache_get_reg((op >> 8) & 0x0f, RC_GR_RMW);\
	544	emith_sub_r_imm(rn, 1); \
	545	emith_sub_r_imm(cr, (cycles+1) << 12); \
	546	cycles = 0; \
52d759c3	547	emith_asr(tmp_, cr, 2+12); \
80599a42	548	JMP8_POS(jmp0); /* no negative cycles */ \
52d759c3	549	emith_move_r_imm(tmp_, 0); \
18b94127	550	JMP8_EMIT(ICOND_JNS, jmp0); \
80599a42	551	emith_and_r_imm(cr, 0xffe); \
52d759c3	552	emith_subf_r_r(rn, tmp_); \
80599a42	553	JMP8_POS(jmp1); /* no overflow */ \
	554	emith_neg_r(rn); /* count left */ \
	555	emith_lsl(rn, rn, 2+12); \
	556	emith_or_r_r(cr, rn); \
	557	emith_or_r_imm(cr, 1); \
	558	emith_move_r_imm(rn, 0); \
18b94127	559	JMP8_EMIT(ICOND_JA, jmp1); \
52d759c3	560	rcache_free_tmp(tmp_); \
65c75cb0	561	}
65c75cb0	562
18b94127	563	#define emith_write_sr(sr, srcr) { \
52d759c3	564	int tmp_ = rcache_get_tmp(); \
18b94127	565	emith_clear_msb(tmp_, srcr, 22); \
	566	emith_bic_r_imm(sr, 0x3ff); \
	567	emith_or_r_r(sr, tmp_); \
52d759c3	568	rcache_free_tmp(tmp_); \
ed8cf79b	569	}
ed8cf79b	570
8b4f38f4	571	#define emith_tpop_carry(sr, is_sub) \
	572	emith_lsr(sr, sr, 1)
	573
	574	#define emith_tpush_carry(sr, is_sub) \
	575	emith_adc_r_r(sr, sr)
ed8cf79b	576
f0d7b1fa	577	/*
	578	* if Q
	579	* t = carry(Rn += Rm)
	580	* else
	581	* t = carry(Rn -= Rm)
	582	* T ^= t
	583	*/
	584	#define emith_sh2_div1_step(rn, rm, sr) { \
	585	u8 jmp0, jmp1; \
	586	int tmp_ = rcache_get_tmp(); \
8b4f38f4	587	emith_eor_r_r(tmp_, tmp_); \
f0d7b1fa	588	emith_tst_r_imm(sr, Q); /* if (Q ^ M) */ \
	589	JMP8_POS(jmp0); /* je do_sub */ \
	590	emith_add_r_r(rn, rm); \
	591	JMP8_POS(jmp1); /* jmp done */ \
18b94127	592	JMP8_EMIT(ICOND_JE, jmp0); /* do_sub: */ \
f0d7b1fa	593	emith_sub_r_r(rn, rm); \
18b94127	594	JMP8_EMIT_NC(jmp1); /* done: */ \
f0d7b1fa	595	emith_setc(tmp_); \
8b4f38f4	596	EMIT_OP_MODRM(0x31, 3, tmp_, sr); /* T = Q1 ^ Q2 */ \
f0d7b1fa	597	rcache_free_tmp(tmp_); \
	598	}
	599