[picodrive.git] / cpu / drc / emit_x86.c

/*
 * note about silly things like emith_eor_r_r_r:
 * these are here because the compiler was designed
 * for ARM as it's primary target.
 */
#include <stdarg.h>

enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };

#define CONTEXT_REG xBP

#define IOP_JMP 0xeb
#define IOP_JO  0x70
#define IOP_JNO 0x71
#define IOP_JB  0x72
#define IOP_JAE 0x73
#define IOP_JE  0x74
#define IOP_JNE 0x75
#define IOP_JBE 0x76
#define IOP_JA  0x77
#define IOP_JS  0x78
#define IOP_JNS 0x79
#define IOP_JL  0x7c
#define IOP_JGE 0x7d
#define IOP_JLE 0x7e
#define IOP_JG  0x7f

// unified conditions (we just use rel8 jump instructions for x86)
#define DCOND_EQ IOP_JE
#define DCOND_NE IOP_JNE
#define DCOND_MI IOP_JS      // MInus
#define DCOND_PL IOP_JNS     // PLus or zero
#define DCOND_HI IOP_JA      // higher (unsigned)
#define DCOND_HS IOP_JAE     // higher || same (unsigned)
#define DCOND_LO IOP_JB      // lower (unsigned)
#define DCOND_LS IOP_JBE     // lower || same (unsigned)
#define DCOND_GE IOP_JGE     // greater || equal (signed)
#define DCOND_GT IOP_JG      // greater (signed)
#define DCOND_LE IOP_JLE     // less || equal (signed)
#define DCOND_LT IOP_JL      // less (signed)
#define DCOND_VS IOP_JO      // oVerflow Set
#define DCOND_VC IOP_JNO     // oVerflow Clear

#define EMIT_PTR(ptr, val, type) \
	*(type *)(ptr) = val

#define EMIT(val, type) { \
	EMIT_PTR(tcache_ptr, val, type); \
	tcache_ptr += sizeof(type); \
}

#define EMIT_OP(op) { \
	COUNT_OP; \
	EMIT(op, u8); \
}

#define EMIT_MODRM(mod,r,rm) \
	EMIT(((mod)<<6) | ((r)<<3) | (rm), u8)

#define EMIT_SIB(scale,index,base) \
	EMIT(((scale)<<6) | ((index)<<3) | (base), u8)

#define EMIT_OP_MODRM(op,mod,r,rm) { \
	EMIT_OP(op); \
	EMIT_MODRM(mod, r, rm); \
}

#define JMP8_POS(ptr) \
	ptr = tcache_ptr; \
	tcache_ptr += 2

#define JMP8_EMIT(op, ptr) \
	EMIT_PTR(ptr, op, u8); \
	EMIT_PTR(ptr + 1, (tcache_ptr - (ptr+2)), u8)

// _r_r
#define emith_move_r_r(dst, src) \
	EMIT_OP_MODRM(0x8b, 3, dst, src)

#define emith_add_r_r(d, s) \
	EMIT_OP_MODRM(0x01, 3, s, d)

#define emith_sub_r_r(d, s) \
	EMIT_OP_MODRM(0x29, 3, s, d)

#define emith_adc_r_r(d, s) \
	EMIT_OP_MODRM(0x11, 3, s, d)

#define emith_sbc_r_r(d, s) \
	EMIT_OP_MODRM(0x19, 3, s, d) /* SBB */

#define emith_or_r_r(d, s) \
	EMIT_OP_MODRM(0x09, 3, s, d)

#define emith_and_r_r(d, s) \
	EMIT_OP_MODRM(0x21, 3, s, d)

#define emith_eor_r_r(d, s) \
	EMIT_OP_MODRM(0x31, 3, s, d) /* XOR */

#define emith_tst_r_r(d, s) \
	EMIT_OP_MODRM(0x85, 3, s, d) /* TEST */

#define emith_cmp_r_r(d, s) \
	EMIT_OP_MODRM(0x39, 3, s, d)

// fake teq - test equivalence - get_flags(d ^ s)
#define emith_teq_r_r(d, s) { \
	emith_push(d); \
	emith_eor_r_r(d, s); \
	emith_pop(d); \
}

#define emith_mvn_r_r(d, s) { \
	if (d != s) \
		emith_move_r_r(d, s); \
	EMIT_OP_MODRM(0xf7, 3, 2, d); /* NOT d */ \
}

#define emith_negc_r_r(d, s) { \
	int tmp_ = rcache_get_tmp(); \
	emith_move_r_imm(tmp_, 0); \
	emith_sbc_r_r(tmp_, s); \
	emith_move_r_r(d, tmp_); \
	rcache_free_tmp(tmp_); \
}

#define emith_neg_r_r(d, s) { \
	if (d != s) \
		emith_move_r_r(d, s); \
	EMIT_OP_MODRM(0xf7, 3, 3, d); /* NEG d */ \
}

// _r_r_r
#define emith_eor_r_r_r(d, s1, s2) { \
	if (d == s1) { \
		emith_eor_r_r(d, s2); \
	} else if (d == s2) { \
		emith_eor_r_r(d, s1); \
	} else { \
		emith_move_r_r(d, s1); \
		emith_eor_r_r(d, s2); \
	} \
}

// _r_r_shift
#define emith_or_r_r_lsl(d, s, lslimm) { \
	int tmp_ = rcache_get_tmp(); \
	emith_lsl(tmp_, s, lslimm); \
	emith_or_r_r(d, tmp_); \
	rcache_free_tmp(tmp_); \
}

// d != s
#define emith_eor_r_r_lsr(d, s, lsrimm) { \
	emith_push(s); \
	emith_lsr(s, s, lsrimm); \
	emith_eor_r_r(d, s); \
	emith_pop(s); \
}

// _r_imm
#define emith_move_r_imm(r, imm) { \
	EMIT_OP(0xb8 + (r)); \
	EMIT(imm, u32); \
}

#define emith_move_r_imm_s8(r, imm) \
	emith_move_r_imm(r, (u32)(signed int)(signed char)(imm))

#define emith_arith_r_imm(op, r, imm) { \
	EMIT_OP_MODRM(0x81, 3, op, r); \
	EMIT(imm, u32); \
}

// 2 - adc, 3 - sbb
#define emith_add_r_imm(r, imm) \
	emith_arith_r_imm(0, r, imm)

#define emith_or_r_imm(r, imm) \
	emith_arith_r_imm(1, r, imm)

#define emith_and_r_imm(r, imm) \
	emith_arith_r_imm(4, r, imm)

#define emith_sub_r_imm(r, imm) \
	emith_arith_r_imm(5, r, imm)

#define emith_eor_r_imm(r, imm) \
	emith_arith_r_imm(6, r, imm)

#define emith_cmp_r_imm(r, imm) \
	emith_arith_r_imm(7, r, imm)

#define emith_tst_r_imm(r, imm) { \
	EMIT_OP_MODRM(0xf7, 3, 0, r); \
	EMIT(imm, u32); \
}

// fake
#define emith_bic_r_imm(r, imm) \
	emith_arith_r_imm(4, r, ~(imm))

// fake conditionals (using SJMP instead)
#define emith_add_r_imm_c(cond, r, imm) { \
	(void)(cond); \
	emith_add_r_imm(r, imm); \
}

#define emith_or_r_imm_c(cond, r, imm) { \
	(void)(cond); \
	emith_or_r_imm(r, imm); \
}

#define emith_eor_r_imm_c(cond, r, imm) { \
	(void)(cond); \
	emith_eor_r_imm(r, imm); \
}

#define emith_sub_r_imm_c(cond, r, imm) { \
	(void)(cond); \
	emith_sub_r_imm(r, imm); \
}

#define emith_bic_r_imm_c(cond, r, imm) { \
	(void)(cond); \
	emith_bic_r_imm(r, imm); \
}

// _r_r_imm
#define emith_and_r_r_imm(d, s, imm) { \
	if (d != s) \
		emith_move_r_r(d, s); \
	emith_and_r_imm(d, imm) \
}

// shift
#define emith_shift(op, d, s, cnt) { \
	if (d != s) \
		emith_move_r_r(d, s); \
	EMIT_OP_MODRM(0xc1, 3, op, d); \
	EMIT(cnt, u8); \
}

#define emith_lsl(d, s, cnt) \
	emith_shift(4, d, s, cnt)

#define emith_lsr(d, s, cnt) \
	emith_shift(5, d, s, cnt)

#define emith_asr(d, s, cnt) \
	emith_shift(7, d, s, cnt)

#define emith_rol(d, s, cnt) \
	emith_shift(0, d, s, cnt)

#define emith_ror(d, s, cnt) \
	emith_shift(1, d, s, cnt)

#define emith_rolc(r) \
	EMIT_OP_MODRM(0xd1, 3, 2, r)

#define emith_rorc(r) \
	EMIT_OP_MODRM(0xd1, 3, 3, r)

// misc
#define emith_push(r) \
	EMIT_OP(0x50 + (r))

#define emith_pop(r) \
	EMIT_OP(0x58 + (r))

#define emith_neg_r(r) \
	EMIT_OP_MODRM(0xf7, 3, 3, r)

#define emith_clear_msb(d, s, count) { \
	u32 t = (u32)-1; \
	t >>= count; \
	if (d != s) \
		emith_move_r_r(d, s); \
	emith_and_r_imm(d, t); \
}

#define emith_clear_msb_c(cond, d, s, count) { \
	(void)(cond); \
	emith_clear_msb(d, s, count); \
}

#define emith_sext(d, s, bits) { \
	emith_lsl(d, s, 32 - (bits)); \
	emith_asr(d, d, 32 - (bits)); \
}

#define emith_setc(r) { \
	EMIT_OP(0x0f); \
	EMIT(0x92, u8); \
	EMIT_MODRM(3, 0, r); /* SETC r */ \
}

// put bit0 of r0 to carry
#define emith_set_carry(r0) { \
	emith_tst_r_imm(r0, 1); /* clears C */ \
	EMITH_SJMP_START(DCOND_EQ); \
	EMIT_OP(0xf9); /* STC */ \
	EMITH_SJMP_END(DCOND_EQ); \
}

// put bit0 of r0 to carry (for subtraction)
#define emith_set_carry_sub emith_set_carry

// XXX: stupid mess
#define emith_mul_(op, dlo, dhi, s1, s2) { \
	int rmr; \
	if (dlo != xAX && dhi != xAX) \
		emith_push(xAX); \
	if (dlo != xDX && dhi != xDX) \
		emith_push(xDX); \
	if ((s1) == xAX) \
		rmr = s2; \
	else if ((s2) == xAX) \
		rmr = s1; \
	else { \
		emith_move_r_r(xAX, s1); \
		rmr = s2; \
	} \
	EMIT_OP_MODRM(0xf7, 3, op, rmr); /* xMUL rmr */ \
	/* XXX: using push/pop for the case of edx->eax; eax->edx */ \
	if (dhi != xDX && dhi != -1) \
		emith_push(xDX); \
	if (dlo != xAX) \
		emith_move_r_r(dlo, xAX); \
	if (dhi != xDX && dhi != -1) \
		emith_pop(dhi); \
	if (dlo != xDX && dhi != xDX) \
		emith_pop(xDX); \
	if (dlo != xAX && dhi != xAX) \
		emith_pop(xAX); \
}

#define emith_mul_u64(dlo, dhi, s1, s2) \
	emith_mul_(4, dlo, dhi, s1, s2) /* MUL */

#define emith_mul_s64(dlo, dhi, s1, s2) \
	emith_mul_(5, dlo, dhi, s1, s2) /* IMUL */

#define emith_mul(d, s1, s2) \
	emith_mul_(4, d, -1, s1, s2)

// (dlo,dhi) += signed(s1) * signed(s2)
#define emith_mula_s64(dlo, dhi, s1, s2) { \
	emith_push(dhi); \
	emith_push(dlo); \
	emith_mul_(5, dlo, dhi, s1, s2); \
	EMIT_OP_MODRM(0x03, 0, dlo, 4); \
	EMIT_SIB(0, 4, 4); /* add dlo, [esp] */ \
	EMIT_OP_MODRM(0x13, 1, dhi, 4); \
	EMIT_SIB(0, 4, 4); \
	EMIT(4, u8); /* adc dhi, [esp+4] */ \
	emith_add_r_imm(xSP, 4*2); \
}

// "flag" instructions are the same
#define emith_subf_r_imm emith_sub_r_imm
#define emith_addf_r_r   emith_add_r_r
#define emith_subf_r_r   emith_sub_r_r
#define emith_adcf_r_r   emith_adc_r_r
#define emith_sbcf_r_r   emith_sbc_r_r
#define emith_negcf_r_r  emith_negc_r_r

#define emith_lslf  emith_lsl
#define emith_lsrf  emith_lsr
#define emith_asrf  emith_asr
#define emith_rolf  emith_rol
#define emith_rorf  emith_ror
#define emith_rolcf emith_rolc
#define emith_rorcf emith_rorc

// XXX: offs is 8bit only
#define emith_ctx_read(r, offs) { \
	EMIT_OP_MODRM(0x8b, 1, r, xBP); \
	EMIT(offs, u8); 	/* mov tmp, [ebp+#offs] */ \
}

#define emith_ctx_write(r, offs) { \
	EMIT_OP_MODRM(0x89, 1, r, xBP); \
	EMIT(offs, u8); 	/* mov [ebp+#offs], tmp */ \
}

#define emith_jump(ptr) { \
	u32 disp = (u32)ptr - ((u32)tcache_ptr + 5); \
	EMIT_OP(0xe9); \
	EMIT(disp, u32); \
}

#define emith_call(ptr) { \
	u32 disp = (u32)ptr - ((u32)tcache_ptr + 5); \
	EMIT_OP(0xe8); \
	EMIT(disp, u32); \
}

#define emith_call_cond(cond, ptr) \
	emith_call(ptr)

// "simple" or "short" jump
#define EMITH_SJMP_START(cond) { \
	u8 *cond_ptr; \
	JMP8_POS(cond_ptr)

#define EMITH_SJMP_END(cond) \
	JMP8_EMIT(cond, cond_ptr); \
}

#define host_arg2reg(rd, arg) \
	switch (arg) { \
	case 0: rd = xAX; break; \
	case 1: rd = xDX; break; \
	case 2: rd = xCX; break; \
	}

#define emith_pass_arg_r(arg, reg) { \
	int rd = 7; \
	host_arg2reg(rd, arg); \
	emith_move_r_r(rd, reg); \
}

#define emith_pass_arg_imm(arg, imm) { \
	int rd = 7; \
	host_arg2reg(rd, arg); \
	emith_move_r_imm(rd, imm); \
}

/* SH2 drc specific */
#define emith_sh2_test_t() { \
	int t = rcache_get_reg(SHR_SR, RC_GR_READ); \
	EMIT_OP_MODRM(0xf6, 3, 0, t); \
	EMIT(0x01, u8); /* test <reg>, byte 1 */ \
}

#define emith_sh2_dtbf_loop() { \
	u8 *jmp0; /* negative cycles check */            \
	u8 *jmp1; /* unsinged overflow check */          \
	int cr, rn;                                      \
	int tmp_ = rcache_get_tmp();                     \
	cr = rcache_get_reg(SHR_SR, RC_GR_RMW);          \
	rn = rcache_get_reg((op >> 8) & 0x0f, RC_GR_RMW);\
	emith_sub_r_imm(rn, 1);                          \
	emith_sub_r_imm(cr, (cycles+1) << 12);           \
	cycles = 0;                                      \
	emith_asr(tmp_, cr, 2+12);                       \
	JMP8_POS(jmp0); /* no negative cycles */         \
	emith_move_r_imm(tmp_, 0);                       \
	JMP8_EMIT(IOP_JNS, jmp0);                        \
	emith_and_r_imm(cr, 0xffe);                      \
	emith_subf_r_r(rn, tmp_);                        \
	JMP8_POS(jmp1); /* no overflow */                \
	emith_neg_r(rn); /* count left */                \
	emith_lsl(rn, rn, 2+12);                         \
	emith_or_r_r(cr, rn);                            \
	emith_or_r_imm(cr, 1);                           \
	emith_move_r_imm(rn, 0);                         \
	JMP8_EMIT(IOP_JA, jmp1);                         \
	rcache_free_tmp(tmp_);                           \
}

#define emith_write_sr(srcr) { \
	int tmp_ = rcache_get_tmp(); \
	int srr = rcache_get_reg(SHR_SR, RC_GR_RMW); \
	emith_clear_msb(tmp_, srcr, 20); \
	emith_bic_r_imm(srr, 0xfff); \
	emith_or_r_r(srr, tmp_); \
	rcache_free_tmp(tmp_); \
}

#define emith_carry_to_t(srr, is_sub) { \
	int tmp_ = rcache_get_tmp(); \
	emith_setc(tmp_); \
	emith_bic_r_imm(srr, 1); \
	EMIT_OP_MODRM(0x08, 3, tmp_, srr); /* OR srrl, tmpl */ \
	rcache_free_tmp(tmp_); \
}

/*
 * if Q
 *   t = carry(Rn += Rm)
 * else
 *   t = carry(Rn -= Rm)
 * T ^= t
 */
#define emith_sh2_div1_step(rn, rm, sr) {         \
	u8 *jmp0, *jmp1;                          \
	int tmp_ = rcache_get_tmp();              \
	emith_tst_r_imm(sr, Q);  /* if (Q ^ M) */ \
	JMP8_POS(jmp0);          /* je do_sub */  \
	emith_add_r_r(rn, rm);                    \
	JMP8_POS(jmp1);          /* jmp done */   \
	JMP8_EMIT(IOP_JE, jmp0); /* do_sub: */    \
	emith_sub_r_r(rn, rm);                    \
	JMP8_EMIT(IOP_JMP, jmp1);/* done: */      \
	emith_setc(tmp_);                         \
	EMIT_OP_MODRM(0x30, 3, tmp_, sr); /* T = Q1 ^ Q2 (byte) */ \
	rcache_free_tmp(tmp_);                    \
}
Commit	Line	Data
3863edbd	1	/*
f0d7b1fa	2	* note about silly things like emith_eor_r_r_r:
3863edbd	3	* these are here because the compiler was designed
	4	* for ARM as it's primary target.
	5	*/
679af8a3	6	#include <stdarg.h>
679af8a3	7
f4bb5d6b	8	enum { xAX = 0, xCX, xDX, xBX, xSP, xBP, xSI, xDI };
f4bb5d6b	9
f4bb5d6b	10	#define CONTEXT_REG xBP
679af8a3	11
f0d7b1fa	12	#define IOP_JMP 0xeb
3863edbd	13	#define IOP_JO 0x70
	14	#define IOP_JNO 0x71
	15	#define IOP_JB 0x72
	16	#define IOP_JAE 0x73
80599a42	17	#define IOP_JE 0x74
	18	#define IOP_JNE 0x75
	19	#define IOP_JBE 0x76
	20	#define IOP_JA 0x77
	21	#define IOP_JS 0x78
	22	#define IOP_JNS 0x79
3863edbd	23	#define IOP_JL 0x7c
3863edbd	24	#define IOP_JGE 0x7d
80599a42	25	#define IOP_JLE 0x7e
3863edbd	26	#define IOP_JG 0x7f
80599a42	27
	28	// unified conditions (we just use rel8 jump instructions for x86)
	29	#define DCOND_EQ IOP_JE
	30	#define DCOND_NE IOP_JNE
	31	#define DCOND_MI IOP_JS // MInus
	32	#define DCOND_PL IOP_JNS // PLus or zero
3863edbd	33	#define DCOND_HI IOP_JA // higher (unsigned)
	34	#define DCOND_HS IOP_JAE // higher \|\| same (unsigned)
	35	#define DCOND_LO IOP_JB // lower (unsigned)
	36	#define DCOND_LS IOP_JBE // lower \|\| same (unsigned)
	37	#define DCOND_GE IOP_JGE // greater \|\| equal (signed)
	38	#define DCOND_GT IOP_JG // greater (signed)
	39	#define DCOND_LE IOP_JLE // less \|\| equal (signed)
	40	#define DCOND_LT IOP_JL // less (signed)
	41	#define DCOND_VS IOP_JO // oVerflow Set
	42	#define DCOND_VC IOP_JNO // oVerflow Clear
80599a42	43
679af8a3	44	#define EMIT_PTR(ptr, val, type) \
	45	(type )(ptr) = val
	46
	47	#define EMIT(val, type) { \
	48	EMIT_PTR(tcache_ptr, val, type); \
f4bb5d6b	49	tcache_ptr += sizeof(type); \
679af8a3	50	}
679af8a3	51
e898de13	52	#define EMIT_OP(op) { \
	53	COUNT_OP; \
	54	EMIT(op, u8); \
	55	}
	56
679af8a3	57	#define EMIT_MODRM(mod,r,rm) \
	58	EMIT(((mod)<<6) \| ((r)<<3) \| (rm), u8)
	59
f0d7b1fa	60	#define EMIT_SIB(scale,index,base) \
	61	EMIT(((scale)<<6) \| ((index)<<3) \| (base), u8)
	62
679af8a3	63	#define EMIT_OP_MODRM(op,mod,r,rm) { \
e898de13	64	EMIT_OP(op); \
679af8a3	65	EMIT_MODRM(mod, r, rm); \
	66	}
	67
80599a42	68	#define JMP8_POS(ptr) \
	69	ptr = tcache_ptr; \
	70	tcache_ptr += 2
	71
	72	#define JMP8_EMIT(op, ptr) \
	73	EMIT_PTR(ptr, op, u8); \
	74	EMIT_PTR(ptr + 1, (tcache_ptr - (ptr+2)), u8)
	75
3863edbd	76	// _r_r
679af8a3	77	#define emith_move_r_r(dst, src) \
	78	EMIT_OP_MODRM(0x8b, 3, dst, src)
	79
80599a42	80	#define emith_add_r_r(d, s) \
	81	EMIT_OP_MODRM(0x01, 3, s, d)
	82
	83	#define emith_sub_r_r(d, s) \
	84	EMIT_OP_MODRM(0x29, 3, s, d)
	85
3863edbd	86	#define emith_adc_r_r(d, s) \
	87	EMIT_OP_MODRM(0x11, 3, s, d)
	88
	89	#define emith_sbc_r_r(d, s) \
	90	EMIT_OP_MODRM(0x19, 3, s, d) /* SBB */
	91
80599a42	92	#define emith_or_r_r(d, s) \
	93	EMIT_OP_MODRM(0x09, 3, s, d)
	94
3863edbd	95	#define emith_and_r_r(d, s) \
	96	EMIT_OP_MODRM(0x21, 3, s, d)
	97
80599a42	98	#define emith_eor_r_r(d, s) \
3863edbd	99	EMIT_OP_MODRM(0x31, 3, s, d) /* XOR */
	100
	101	#define emith_tst_r_r(d, s) \
	102	EMIT_OP_MODRM(0x85, 3, s, d) /* TEST */
	103
	104	#define emith_cmp_r_r(d, s) \
	105	EMIT_OP_MODRM(0x39, 3, s, d)
80599a42	106
	107	// fake teq - test equivalence - get_flags(d ^ s)
	108	#define emith_teq_r_r(d, s) { \
	109	emith_push(d); \
	110	emith_eor_r_r(d, s); \
	111	emith_pop(d); \
	112	}
	113
52d759c3	114	#define emith_mvn_r_r(d, s) { \
	115	if (d != s) \
	116	emith_move_r_r(d, s); \
	117	EMIT_OP_MODRM(0xf7, 3, 2, d); /* NOT d */ \
	118	}
	119
	120	#define emith_negc_r_r(d, s) { \
	121	int tmp_ = rcache_get_tmp(); \
	122	emith_move_r_imm(tmp_, 0); \
	123	emith_sbc_r_r(tmp_, s); \
	124	emith_move_r_r(d, tmp_); \
	125	rcache_free_tmp(tmp_); \
	126	}
	127
	128	#define emith_neg_r_r(d, s) { \
	129	if (d != s) \
	130	emith_move_r_r(d, s); \
	131	EMIT_OP_MODRM(0xf7, 3, 3, d); /* NEG d */ \
	132	}
	133
3863edbd	134	// _r_r_r
3863edbd	135	#define emith_eor_r_r_r(d, s1, s2) { \
52d759c3	136	if (d == s1) { \
	137	emith_eor_r_r(d, s2); \
	138	} else if (d == s2) { \
	139	emith_eor_r_r(d, s1); \
	140	} else { \
3863edbd	141	emith_move_r_r(d, s1); \
52d759c3	142	emith_eor_r_r(d, s2); \
52d759c3	143	} \
3863edbd	144	}
3863edbd	145
f0d7b1fa	146	// _r_r_shift
f0d7b1fa	147	#define emith_or_r_r_lsl(d, s, lslimm) { \
52d759c3	148	int tmp_ = rcache_get_tmp(); \
f0d7b1fa	149	emith_lsl(tmp_, s, lslimm); \
f0d7b1fa	150	emith_or_r_r(d, tmp_); \
52d759c3	151	rcache_free_tmp(tmp_); \
3863edbd	152	}
3863edbd	153
f0d7b1fa	154	// d != s
	155	#define emith_eor_r_r_lsr(d, s, lsrimm) { \
	156	emith_push(s); \
	157	emith_lsr(s, s, lsrimm); \
	158	emith_eor_r_r(d, s); \
	159	emith_pop(s); \
	160	}
	161
80599a42	162	// _r_imm
679af8a3	163	#define emith_move_r_imm(r, imm) { \
e898de13	164	EMIT_OP(0xb8 + (r)); \
679af8a3	165	EMIT(imm, u32); \
	166	}
	167
52d759c3	168	#define emith_move_r_imm_s8(r, imm) \
	169	emith_move_r_imm(r, (u32)(signed int)(signed char)(imm))
	170
80599a42	171	#define emith_arith_r_imm(op, r, imm) { \
80599a42	172	EMIT_OP_MODRM(0x81, 3, op, r); \
679af8a3	173	EMIT(imm, u32); \
	174	}
	175
52d759c3	176	// 2 - adc, 3 - sbb
80599a42	177	#define emith_add_r_imm(r, imm) \
	178	emith_arith_r_imm(0, r, imm)
	179
	180	#define emith_or_r_imm(r, imm) \
	181	emith_arith_r_imm(1, r, imm)
	182
	183	#define emith_and_r_imm(r, imm) \
	184	emith_arith_r_imm(4, r, imm)
	185
	186	#define emith_sub_r_imm(r, imm) \
	187	emith_arith_r_imm(5, r, imm)
	188
52d759c3	189	#define emith_eor_r_imm(r, imm) \
	190	emith_arith_r_imm(6, r, imm)
	191
ed8cf79b	192	#define emith_cmp_r_imm(r, imm) \
	193	emith_arith_r_imm(7, r, imm)
	194
80599a42	195	#define emith_tst_r_imm(r, imm) { \
80599a42	196	EMIT_OP_MODRM(0xf7, 3, 0, r); \
679af8a3	197	EMIT(imm, u32); \
	198	}
	199
80599a42	200	// fake
	201	#define emith_bic_r_imm(r, imm) \
	202	emith_arith_r_imm(4, r, ~(imm))
	203
	204	// fake conditionals (using SJMP instead)
	205	#define emith_add_r_imm_c(cond, r, imm) { \
	206	(void)(cond); \
3863edbd	207	emith_add_r_imm(r, imm); \
80599a42	208	}
	209
	210	#define emith_or_r_imm_c(cond, r, imm) { \
	211	(void)(cond); \
3863edbd	212	emith_or_r_imm(r, imm); \
80599a42	213	}
80599a42	214
f0d7b1fa	215	#define emith_eor_r_imm_c(cond, r, imm) { \
	216	(void)(cond); \
	217	emith_eor_r_imm(r, imm); \
	218	}
	219
80599a42	220	#define emith_sub_r_imm_c(cond, r, imm) { \
80599a42	221	(void)(cond); \
3863edbd	222	emith_sub_r_imm(r, imm); \
	223	}
	224
	225	#define emith_bic_r_imm_c(cond, r, imm) { \
	226	(void)(cond); \
	227	emith_bic_r_imm(r, imm); \
80599a42	228	}
80599a42	229
52d759c3	230	// _r_r_imm
	231	#define emith_and_r_r_imm(d, s, imm) { \
	232	if (d != s) \
	233	emith_move_r_r(d, s); \
	234	emith_and_r_imm(d, imm) \
	235	}
	236
80599a42	237	// shift
	238	#define emith_shift(op, d, s, cnt) { \
	239	if (d != s) \
	240	emith_move_r_r(d, s); \
	241	EMIT_OP_MODRM(0xc1, 3, op, d); \
	242	EMIT(cnt, u8); \
	243	}
	244
80599a42	245	#define emith_lsl(d, s, cnt) \
	246	emith_shift(4, d, s, cnt)
	247
3863edbd	248	#define emith_lsr(d, s, cnt) \
	249	emith_shift(5, d, s, cnt)
	250
	251	#define emith_asr(d, s, cnt) \
	252	emith_shift(7, d, s, cnt)
	253
ed8cf79b	254	#define emith_rol(d, s, cnt) \
	255	emith_shift(0, d, s, cnt)
	256
	257	#define emith_ror(d, s, cnt) \
	258	emith_shift(1, d, s, cnt)
	259
	260	#define emith_rolc(r) \
	261	EMIT_OP_MODRM(0xd1, 3, 2, r)
	262
	263	#define emith_rorc(r) \
	264	EMIT_OP_MODRM(0xd1, 3, 3, r)
	265
80599a42	266	// misc
	267	#define emith_push(r) \
	268	EMIT_OP(0x50 + (r))
	269
	270	#define emith_pop(r) \
	271	EMIT_OP(0x58 + (r))
	272
	273	#define emith_neg_r(r) \
	274	EMIT_OP_MODRM(0xf7, 3, 3, r)
	275
	276	#define emith_clear_msb(d, s, count) { \
	277	u32 t = (u32)-1; \
	278	t >>= count; \
	279	if (d != s) \
	280	emith_move_r_r(d, s); \
	281	emith_and_r_imm(d, t); \
	282	}
	283
f0d7b1fa	284	#define emith_clear_msb_c(cond, d, s, count) { \
	285	(void)(cond); \
	286	emith_clear_msb(d, s, count); \
	287	}
	288
80599a42	289	#define emith_sext(d, s, bits) { \
	290	emith_lsl(d, s, 32 - (bits)); \
	291	emith_asr(d, d, 32 - (bits)); \
	292	}
	293
f0d7b1fa	294	#define emith_setc(r) { \
	295	EMIT_OP(0x0f); \
	296	EMIT(0x92, u8); \
	297	EMIT_MODRM(3, 0, r); /* SETC r */ \
	298	}
	299
3863edbd	300	// put bit0 of r0 to carry
	301	#define emith_set_carry(r0) { \
	302	emith_tst_r_imm(r0, 1); /* clears C */ \
	303	EMITH_SJMP_START(DCOND_EQ); \
	304	EMIT_OP(0xf9); /* STC */ \
	305	EMITH_SJMP_END(DCOND_EQ); \
	306	}
	307
	308	// put bit0 of r0 to carry (for subtraction)
	309	#define emith_set_carry_sub emith_set_carry
	310
80599a42	311	// XXX: stupid mess
3863edbd	312	#define emith_mul_(op, dlo, dhi, s1, s2) { \
80599a42	313	int rmr; \
3863edbd	314	if (dlo != xAX && dhi != xAX) \
80599a42	315	emith_push(xAX); \
3863edbd	316	if (dlo != xDX && dhi != xDX) \
3863edbd	317	emith_push(xDX); \
80599a42	318	if ((s1) == xAX) \
	319	rmr = s2; \
	320	else if ((s2) == xAX) \
	321	rmr = s1; \
	322	else { \
	323	emith_move_r_r(xAX, s1); \
	324	rmr = s2; \
	325	} \
3863edbd	326	EMIT_OP_MODRM(0xf7, 3, op, rmr); /* xMUL rmr */ \
	327	/* XXX: using push/pop for the case of edx->eax; eax->edx */ \
	328	if (dhi != xDX && dhi != -1) \
	329	emith_push(xDX); \
	330	if (dlo != xAX) \
	331	emith_move_r_r(dlo, xAX); \
	332	if (dhi != xDX && dhi != -1) \
	333	emith_pop(dhi); \
	334	if (dlo != xDX && dhi != xDX) \
	335	emith_pop(xDX); \
	336	if (dlo != xAX && dhi != xAX) \
80599a42	337	emith_pop(xAX); \
80599a42	338	}
80599a42	339
3863edbd	340	#define emith_mul_u64(dlo, dhi, s1, s2) \
	341	emith_mul_(4, dlo, dhi, s1, s2) /* MUL */
	342
	343	#define emith_mul_s64(dlo, dhi, s1, s2) \
	344	emith_mul_(5, dlo, dhi, s1, s2) /* IMUL */
	345
	346	#define emith_mul(d, s1, s2) \
	347	emith_mul_(4, d, -1, s1, s2)
	348
f0d7b1fa	349	// (dlo,dhi) += signed(s1) * signed(s2)
	350	#define emith_mula_s64(dlo, dhi, s1, s2) { \
	351	emith_push(dhi); \
	352	emith_push(dlo); \
	353	emith_mul_(5, dlo, dhi, s1, s2); \
	354	EMIT_OP_MODRM(0x03, 0, dlo, 4); \
	355	EMIT_SIB(0, 4, 4); /* add dlo, [esp] */ \
	356	EMIT_OP_MODRM(0x13, 1, dhi, 4); \
	357	EMIT_SIB(0, 4, 4); \
	358	EMIT(4, u8); /* adc dhi, [esp+4] */ \
	359	emith_add_r_imm(xSP, 4*2); \
	360	}
	361
80599a42	362	// "flag" instructions are the same
80599a42	363	#define emith_subf_r_imm emith_sub_r_imm
3863edbd	364	#define emith_addf_r_r emith_add_r_r
80599a42	365	#define emith_subf_r_r emith_sub_r_r
3863edbd	366	#define emith_adcf_r_r emith_adc_r_r
3863edbd	367	#define emith_sbcf_r_r emith_sbc_r_r
52d759c3	368	#define emith_negcf_r_r emith_negc_r_r
3863edbd	369
ed8cf79b	370	#define emith_lslf emith_lsl
	371	#define emith_lsrf emith_lsr
	372	#define emith_asrf emith_asr
	373	#define emith_rolf emith_rol
	374	#define emith_rorf emith_ror
	375	#define emith_rolcf emith_rolc
	376	#define emith_rorcf emith_rorc
80599a42	377
679af8a3	378	// XXX: offs is 8bit only
679af8a3	379	#define emith_ctx_read(r, offs) { \
65c75cb0	380	EMIT_OP_MODRM(0x8b, 1, r, xBP); \
679af8a3	381	EMIT(offs, u8); /* mov tmp, [ebp+#offs] */ \
	382	}
	383
	384	#define emith_ctx_write(r, offs) { \
65c75cb0	385	EMIT_OP_MODRM(0x89, 1, r, xBP); \
679af8a3	386	EMIT(offs, u8); /* mov [ebp+#offs], tmp */ \
	387	}
	388
679af8a3	389	#define emith_jump(ptr) { \
679af8a3	390	u32 disp = (u32)ptr - ((u32)tcache_ptr + 5); \
e898de13	391	EMIT_OP(0xe9); \
679af8a3	392	EMIT(disp, u32); \
	393	}
	394
	395	#define emith_call(ptr) { \
	396	u32 disp = (u32)ptr - ((u32)tcache_ptr + 5); \
e898de13	397	EMIT_OP(0xe8); \
679af8a3	398	EMIT(disp, u32); \
	399	}
	400
f0d7b1fa	401	#define emith_call_cond(cond, ptr) \
	402	emith_call(ptr)
	403
80599a42	404	// "simple" or "short" jump
	405	#define EMITH_SJMP_START(cond) { \
	406	u8 *cond_ptr; \
	407	JMP8_POS(cond_ptr)
	408
	409	#define EMITH_SJMP_END(cond) \
	410	JMP8_EMIT(cond, cond_ptr); \
679af8a3	411	}
679af8a3	412
80599a42	413	#define host_arg2reg(rd, arg) \
f4bb5d6b	414	switch (arg) { \
	415	case 0: rd = xAX; break; \
	416	case 1: rd = xDX; break; \
	417	case 2: rd = xCX; break; \
679af8a3	418	}
679af8a3	419
f4bb5d6b	420	#define emith_pass_arg_r(arg, reg) { \
f4bb5d6b	421	int rd = 7; \
80599a42	422	host_arg2reg(rd, arg); \
f4bb5d6b	423	emith_move_r_r(rd, reg); \
	424	}
	425
	426	#define emith_pass_arg_imm(arg, imm) { \
	427	int rd = 7; \
80599a42	428	host_arg2reg(rd, arg); \
f4bb5d6b	429	emith_move_r_imm(rd, imm); \
679af8a3	430	}
679af8a3	431
65c75cb0	432	/* SH2 drc specific */
80599a42	433	#define emith_sh2_test_t() { \
	434	int t = rcache_get_reg(SHR_SR, RC_GR_READ); \
	435	EMIT_OP_MODRM(0xf6, 3, 0, t); \
	436	EMIT(0x01, u8); /* test <reg>, byte 1 */ \
	437	}
	438
	439	#define emith_sh2_dtbf_loop() { \
	440	u8 jmp0; / negative cycles check */ \
	441	u8 jmp1; / unsinged overflow check */ \
	442	int cr, rn; \
52d759c3	443	int tmp_ = rcache_get_tmp(); \
80599a42	444	cr = rcache_get_reg(SHR_SR, RC_GR_RMW); \
	445	rn = rcache_get_reg((op >> 8) & 0x0f, RC_GR_RMW);\
	446	emith_sub_r_imm(rn, 1); \
	447	emith_sub_r_imm(cr, (cycles+1) << 12); \
	448	cycles = 0; \
52d759c3	449	emith_asr(tmp_, cr, 2+12); \
80599a42	450	JMP8_POS(jmp0); /* no negative cycles */ \
52d759c3	451	emith_move_r_imm(tmp_, 0); \
80599a42	452	JMP8_EMIT(IOP_JNS, jmp0); \
80599a42	453	emith_and_r_imm(cr, 0xffe); \
52d759c3	454	emith_subf_r_r(rn, tmp_); \
80599a42	455	JMP8_POS(jmp1); /* no overflow */ \
	456	emith_neg_r(rn); /* count left */ \
	457	emith_lsl(rn, rn, 2+12); \
	458	emith_or_r_r(cr, rn); \
	459	emith_or_r_imm(cr, 1); \
	460	emith_move_r_imm(rn, 0); \
	461	JMP8_EMIT(IOP_JA, jmp1); \
52d759c3	462	rcache_free_tmp(tmp_); \
65c75cb0	463	}
65c75cb0	464
ed8cf79b	465	#define emith_write_sr(srcr) { \
52d759c3	466	int tmp_ = rcache_get_tmp(); \
ed8cf79b	467	int srr = rcache_get_reg(SHR_SR, RC_GR_RMW); \
52d759c3	468	emith_clear_msb(tmp_, srcr, 20); \
ed8cf79b	469	emith_bic_r_imm(srr, 0xfff); \
52d759c3	470	emith_or_r_r(srr, tmp_); \
52d759c3	471	rcache_free_tmp(tmp_); \
ed8cf79b	472	}
	473
	474	#define emith_carry_to_t(srr, is_sub) { \
52d759c3	475	int tmp_ = rcache_get_tmp(); \
f0d7b1fa	476	emith_setc(tmp_); \
ed8cf79b	477	emith_bic_r_imm(srr, 1); \
52d759c3	478	EMIT_OP_MODRM(0x08, 3, tmp_, srr); /* OR srrl, tmpl */ \
52d759c3	479	rcache_free_tmp(tmp_); \
ed8cf79b	480	}
ed8cf79b	481
f0d7b1fa	482	/*
	483	* if Q
	484	* t = carry(Rn += Rm)
	485	* else
	486	* t = carry(Rn -= Rm)
	487	* T ^= t
	488	*/
	489	#define emith_sh2_div1_step(rn, rm, sr) { \
	490	u8 jmp0, jmp1; \
	491	int tmp_ = rcache_get_tmp(); \
	492	emith_tst_r_imm(sr, Q); /* if (Q ^ M) */ \
	493	JMP8_POS(jmp0); /* je do_sub */ \
	494	emith_add_r_r(rn, rm); \
	495	JMP8_POS(jmp1); /* jmp done */ \
	496	JMP8_EMIT(IOP_JE, jmp0); /* do_sub: */ \
	497	emith_sub_r_r(rn, rm); \
	498	JMP8_EMIT(IOP_JMP, jmp1);/* done: */ \
	499	emith_setc(tmp_); \
	500	EMIT_OP_MODRM(0x30, 3, tmp_, sr); /* T = Q1 ^ Q2 (byte) */ \
	501	rcache_free_tmp(tmp_); \
	502	}
	503