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[picodrive.git] / cpu / musashi / m68k_in.c
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cc68a136 1/*\r
2must fix:\r
3 callm\r
4 chk\r
5*/\r
6/* ======================================================================== */\r
7/* ========================= LICENSING & COPYRIGHT ======================== */\r
8/* ======================================================================== */\r
9/*\r
10 * MUSASHI\r
11 * Version 3.3\r
12 *\r
13 * A portable Motorola M680x0 processor emulation engine.\r
14 * Copyright 1998-2001 Karl Stenerud. All rights reserved.\r
15 *\r
16 * This code may be freely used for non-commercial purposes as long as this\r
17 * copyright notice remains unaltered in the source code and any binary files\r
18 * containing this code in compiled form.\r
19 *\r
20 * All other lisencing terms must be negotiated with the author\r
21 * (Karl Stenerud).\r
22 *\r
23 * The latest version of this code can be obtained at:\r
24 * http://kstenerud.cjb.net\r
25 */\r
26\r
27/* Special thanks to Bart Trzynadlowski for his insight into the\r
28 * undocumented features of this chip:\r
29 *\r
30 * http://dynarec.com/~bart/files/68knotes.txt\r
31 */\r
32\r
33\r
34/* Input file for m68kmake\r
35 * -----------------------\r
36 *\r
37 * All sections begin with 80 X's in a row followed by an end-of-line\r
38 * sequence.\r
39 * After this, m68kmake will expect to find one of the following section\r
40 * identifiers:\r
41 * M68KMAKE_PROTOTYPE_HEADER - header for opcode handler prototypes\r
42 * M68KMAKE_PROTOTYPE_FOOTER - footer for opcode handler prototypes\r
43 * M68KMAKE_TABLE_HEADER - header for opcode handler jumptable\r
44 * M68KMAKE_TABLE_FOOTER - footer for opcode handler jumptable\r
45 * M68KMAKE_TABLE_BODY - the table itself\r
46 * M68KMAKE_OPCODE_HANDLER_HEADER - header for opcode handler implementation\r
47 * M68KMAKE_OPCODE_HANDLER_FOOTER - footer for opcode handler implementation\r
48 * M68KMAKE_OPCODE_HANDLER_BODY - body section for opcode handler implementation\r
49 *\r
50 * NOTE: M68KMAKE_OPCODE_HANDLER_BODY must be last in the file and\r
51 * M68KMAKE_TABLE_BODY must be second last in the file.\r
52 *\r
53 * The M68KMAKE_OPHANDLER_BODY section contains the opcode handler\r
54 * primitives themselves. Each opcode handler begins with:\r
55 * M68KMAKE_OP(A, B, C, D)\r
56 *\r
57 * where A is the opcode handler name, B is the size of the operation,\r
58 * C denotes any special processing mode, and D denotes a specific\r
59 * addressing mode.\r
60 * For C and D where nothing is specified, use "."\r
61 *\r
62 * Example:\r
63 * M68KMAKE_OP(abcd, 8, rr, .) abcd, size 8, register to register, default EA\r
64 * M68KMAKE_OP(abcd, 8, mm, ax7) abcd, size 8, memory to memory, register X is A7\r
65 * M68KMAKE_OP(tst, 16, ., pcix) tst, size 16, PCIX addressing\r
66 *\r
67 * All opcode handler primitives end with a closing curly brace "}" at column 1\r
68 *\r
69 * NOTE: Do not place a M68KMAKE_OP() directive inside the opcode handler,\r
70 * and do not put a closing curly brace at column 1 unless it is\r
71 * marking the end of the handler!\r
72 *\r
73 * Inside the handler, m68kmake will recognize M68KMAKE_GET_OPER_xx_xx,\r
74 * M68KMAKE_GET_EA_xx_xx, and M68KMAKE_CC directives, and create multiple\r
75 * opcode handlers to handle variations in the opcode handler.\r
76 * Note: M68KMAKE_CC will only be interpreted in condition code opcodes.\r
77 * As well, M68KMAKE_GET_EA_xx_xx and M68KMAKE_GET_OPER_xx_xx will only\r
78 * be interpreted on instructions where the corresponding table entry\r
79 * specifies multiple effective addressing modes.\r
80 * Example:\r
81 * clr 32 . . 0100001010...... A+-DXWL... U U U 12 6 4\r
82 *\r
83 * This table entry says that the clr.l opcde has 7 variations (A+-DXWL).\r
84 * It is run in user or supervisor mode for all CPUs, and uses 12 cycles for\r
85 * 68000, 6 cycles for 68010, and 4 cycles for 68020.\r
86 */\r
87\r
88XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\r
89M68KMAKE_PROTOTYPE_HEADER\r
90\r
91#ifndef M68KOPS__HEADER\r
92#define M68KOPS__HEADER\r
93\r
94/* ======================================================================== */\r
95/* ============================ OPCODE HANDLERS =========================== */\r
96/* ======================================================================== */\r
97\r
98\r
99\r
100XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\r
101M68KMAKE_PROTOTYPE_FOOTER\r
102\r
103\r
104/* Build the opcode handler table */\r
105void m68ki_build_opcode_table(void);\r
106\r
107extern void (*m68ki_instruction_jump_table[0x10000])(void); /* opcode handler jump table */\r
108extern unsigned char m68ki_cycles[][0x10000];\r
109\r
110\r
111/* ======================================================================== */\r
112/* ============================== END OF FILE ============================= */\r
113/* ======================================================================== */\r
114\r
115#endif /* M68KOPS__HEADER */\r
116\r
117\r
118\r
119XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\r
120M68KMAKE_TABLE_HEADER\r
121\r
122/* ======================================================================== */\r
123/* ========================= OPCODE TABLE BUILDER ========================= */\r
124/* ======================================================================== */\r
125\r
126#include "m68kops.h"\r
127\r
128#define NUM_CPU_TYPES 4\r
129\r
130void (*m68ki_instruction_jump_table[0x10000])(void); /* opcode handler jump table */\r
131unsigned char m68ki_cycles[NUM_CPU_TYPES][0x10000]; /* Cycles used by CPU type */\r
132\r
133/* This is used to generate the opcode handler jump table */\r
134typedef struct\r
135{\r
136 void (*opcode_handler)(void); /* handler function */\r
137 unsigned int mask; /* mask on opcode */\r
138 unsigned int match; /* what to match after masking */\r
139 unsigned char cycles[NUM_CPU_TYPES]; /* cycles each cpu type takes */\r
140} opcode_handler_struct;\r
141\r
142\r
143/* Opcode handler table */\r
144static opcode_handler_struct m68k_opcode_handler_table[] =\r
145{\r
146/* function mask match 000 010 020 040 */\r
147\r
148\r
149\r
150XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\r
151M68KMAKE_TABLE_FOOTER\r
152\r
153 {0, 0, 0, {0, 0, 0, 0}}\r
154};\r
155\r
156\r
157/* Build the opcode handler jump table */\r
158void m68ki_build_opcode_table(void)\r
159{\r
160 opcode_handler_struct *ostruct;\r
161 int instr;\r
162 int i;\r
163 int j;\r
164 int k;\r
165\r
166 for(i = 0; i < 0x10000; i++)\r
167 {\r
168 /* default to illegal */\r
169 m68ki_instruction_jump_table[i] = m68k_op_illegal;\r
170 for(k=0;k<NUM_CPU_TYPES;k++)\r
171 m68ki_cycles[k][i] = 0;\r
172 }\r
173\r
174 ostruct = m68k_opcode_handler_table;\r
175 while(ostruct->mask != 0xff00)\r
176 {\r
177 for(i = 0;i < 0x10000;i++)\r
178 {\r
179 if((i & ostruct->mask) == ostruct->match)\r
180 {\r
181 m68ki_instruction_jump_table[i] = ostruct->opcode_handler;\r
182 for(k=0;k<NUM_CPU_TYPES;k++)\r
183 m68ki_cycles[k][i] = ostruct->cycles[k];\r
184 }\r
185 }\r
186 ostruct++;\r
187 }\r
188 while(ostruct->mask == 0xff00)\r
189 {\r
190 for(i = 0;i <= 0xff;i++)\r
191 {\r
192 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;\r
193 for(k=0;k<NUM_CPU_TYPES;k++)\r
194 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];\r
195 }\r
196 ostruct++;\r
197 }\r
198 while(ostruct->mask == 0xf1f8)\r
199 {\r
200 for(i = 0;i < 8;i++)\r
201 {\r
202 for(j = 0;j < 8;j++)\r
203 {\r
204 instr = ostruct->match | (i << 9) | j;\r
205 m68ki_instruction_jump_table[instr] = ostruct->opcode_handler;\r
206 for(k=0;k<NUM_CPU_TYPES;k++)\r
207 m68ki_cycles[k][instr] = ostruct->cycles[k];\r
208 }\r
209 }\r
210 ostruct++;\r
211 }\r
212 while(ostruct->mask == 0xfff0)\r
213 {\r
214 for(i = 0;i <= 0x0f;i++)\r
215 {\r
216 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;\r
217 for(k=0;k<NUM_CPU_TYPES;k++)\r
218 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];\r
219 }\r
220 ostruct++;\r
221 }\r
222 while(ostruct->mask == 0xf1ff)\r
223 {\r
224 for(i = 0;i <= 0x07;i++)\r
225 {\r
226 m68ki_instruction_jump_table[ostruct->match | (i << 9)] = ostruct->opcode_handler;\r
227 for(k=0;k<NUM_CPU_TYPES;k++)\r
228 m68ki_cycles[k][ostruct->match | (i << 9)] = ostruct->cycles[k];\r
229 }\r
230 ostruct++;\r
231 }\r
232 while(ostruct->mask == 0xfff8)\r
233 {\r
234 for(i = 0;i <= 0x07;i++)\r
235 {\r
236 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;\r
237 for(k=0;k<NUM_CPU_TYPES;k++)\r
238 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];\r
239 }\r
240 ostruct++;\r
241 }\r
242 while(ostruct->mask == 0xffff)\r
243 {\r
244 m68ki_instruction_jump_table[ostruct->match] = ostruct->opcode_handler;\r
245 for(k=0;k<NUM_CPU_TYPES;k++)\r
246 m68ki_cycles[k][ostruct->match] = ostruct->cycles[k];\r
247 ostruct++;\r
248 }\r
249}\r
250\r
251\r
252/* ======================================================================== */\r
253/* ============================== END OF FILE ============================= */\r
254/* ======================================================================== */\r
255\r
256\r
257\r
258XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\r
259M68KMAKE_OPCODE_HANDLER_HEADER\r
260\r
261#include "m68kcpu.h"\r
262\r
263/* ======================================================================== */\r
264/* ========================= INSTRUCTION HANDLERS ========================= */\r
265/* ======================================================================== */\r
266\r
267\r
268\r
269XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\r
270M68KMAKE_OPCODE_HANDLER_FOOTER\r
271\r
272/* ======================================================================== */\r
273/* ============================== END OF FILE ============================= */\r
274/* ======================================================================== */\r
275\r
276\r
277\r
278XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\r
279M68KMAKE_TABLE_BODY\r
280\r
281The following table is arranged as follows:\r
282\r
283name: Opcode mnemonic\r
284\r
285size: Operation size\r
286\r
287spec proc: Special processing mode:\r
288 .: normal\r
289 s: static operand\r
290 r: register operand\r
291 rr: register to register\r
292 mm: memory to memory\r
293 er: effective address to register\r
294 re: register to effective address\r
295 dd: data register to data register\r
296 da: data register to address register\r
297 aa: address register to address register\r
298 cr: control register to register\r
299 rc: register to control register\r
300 toc: to condition code register\r
301 tos: to status register\r
302 tou: to user stack pointer\r
303 frc: from condition code register\r
304 frs: from status register\r
305 fru: from user stack pointer\r
306 * for move.x, the special processing mode is a specific\r
307 destination effective addressing mode.\r
308\r
309spec ea: Specific effective addressing mode:\r
310 .: normal\r
311 i: immediate\r
312 d: data register\r
313 a: address register\r
314 ai: address register indirect\r
315 pi: address register indirect with postincrement\r
316 pd: address register indirect with predecrement\r
317 di: address register indirect with displacement\r
318 ix: address register indirect with index\r
319 aw: absolute word address\r
320 al: absolute long address\r
321 pcdi: program counter relative with displacement\r
322 pcix: program counter relative with index\r
323 a7: register specified in instruction is A7\r
324 ax7: register field X of instruction is A7\r
325 ay7: register field Y of instruction is A7\r
326 axy7: register fields X and Y of instruction are A7\r
327\r
328bit pattern: Pattern to recognize this opcode. "." means don't care.\r
329\r
330allowed ea: List of allowed addressing modes:\r
331 .: not present\r
332 A: address register indirect\r
333 +: ARI (address register indirect) with postincrement\r
334 -: ARI with predecrement\r
335 D: ARI with displacement\r
336 X: ARI with index\r
337 W: absolute word address\r
338 L: absolute long address\r
339 d: program counter indirect with displacement\r
340 x: program counter indirect with index\r
341 I: immediate\r
342mode: CPU operating mode for each cpu type. U = user or supervisor,\r
343 S = supervisor only, "." = opcode not present.\r
344\r
345cpu cycles: Base number of cycles required to execute this opcode on the\r
346 specified CPU type.\r
347 Use "." if CPU does not have this opcode.\r
348\r
349\r
350\r
351 spec spec allowed ea mode cpu cycles\r
352name size proc ea bit pattern A+-DXWLdxI 0 1 2 4 000 010 020 040 comments\r
353====== ==== ==== ==== ================ ========== = = = = === === === === =============\r
354M68KMAKE_TABLE_START\r
3551010 0 . . 1010............ .......... U U U U 4 4 4 4\r
3561111 0 . . 1111............ .......... U U U U 4 4 4 4\r
357abcd 8 rr . 1100...100000... .......... U U U U 6 6 4 4\r
358abcd 8 mm ax7 1100111100001... .......... U U U U 18 18 16 16\r
359abcd 8 mm ay7 1100...100001111 .......... U U U U 18 18 16 16\r
360abcd 8 mm axy7 1100111100001111 .......... U U U U 18 18 16 16\r
361abcd 8 mm . 1100...100001... .......... U U U U 18 18 16 16\r
362add 8 er d 1101...000000... .......... U U U U 4 4 2 2\r
363add 8 er . 1101...000...... A+-DXWLdxI U U U U 4 4 2 2\r
364add 16 er d 1101...001000... .......... U U U U 4 4 2 2\r
365add 16 er a 1101...001001... .......... U U U U 4 4 2 2\r
366add 16 er . 1101...001...... A+-DXWLdxI U U U U 4 4 2 2\r
367add 32 er d 1101...010000... .......... U U U U 6 6 2 2\r
368add 32 er a 1101...010001... .......... U U U U 6 6 2 2\r
369add 32 er . 1101...010...... A+-DXWLdxI U U U U 6 6 2 2\r
370add 8 re . 1101...100...... A+-DXWL... U U U U 8 8 4 4\r
371add 16 re . 1101...101...... A+-DXWL... U U U U 8 8 4 4\r
372add 32 re . 1101...110...... A+-DXWL... U U U U 12 12 4 4\r
373adda 16 . d 1101...011000... .......... U U U U 8 8 2 2\r
374adda 16 . a 1101...011001... .......... U U U U 8 8 2 2\r
375adda 16 . . 1101...011...... A+-DXWLdxI U U U U 8 8 2 2\r
376adda 32 . d 1101...111000... .......... U U U U 6 6 2 2\r
377adda 32 . a 1101...111001... .......... U U U U 6 6 2 2\r
378adda 32 . . 1101...111...... A+-DXWLdxI U U U U 6 6 2 2\r
379addi 8 . d 0000011000000... .......... U U U U 8 8 2 2\r
380addi 8 . . 0000011000...... A+-DXWL... U U U U 12 12 4 4\r
381addi 16 . d 0000011001000... .......... U U U U 8 8 2 2\r
382addi 16 . . 0000011001...... A+-DXWL... U U U U 12 12 4 4\r
383addi 32 . d 0000011010000... .......... U U U U 16 14 2 2\r
384addi 32 . . 0000011010...... A+-DXWL... U U U U 20 20 4 4\r
385addq 8 . d 0101...000000... .......... U U U U 4 4 2 2\r
386addq 8 . . 0101...000...... A+-DXWL... U U U U 8 8 4 4\r
387addq 16 . d 0101...001000... .......... U U U U 4 4 2 2\r
388addq 16 . a 0101...001001... .......... U U U U 4 4 2 2\r
389addq 16 . . 0101...001...... A+-DXWL... U U U U 8 8 4 4\r
390addq 32 . d 0101...010000... .......... U U U U 8 8 2 2\r
391addq 32 . a 0101...010001... .......... U U U U 8 8 2 2\r
392addq 32 . . 0101...010...... A+-DXWL... U U U U 12 12 4 4\r
393addx 8 rr . 1101...100000... .......... U U U U 4 4 2 2\r
394addx 16 rr . 1101...101000... .......... U U U U 4 4 2 2\r
395addx 32 rr . 1101...110000... .......... U U U U 8 6 2 2\r
396addx 8 mm ax7 1101111100001... .......... U U U U 18 18 12 12\r
397addx 8 mm ay7 1101...100001111 .......... U U U U 18 18 12 12\r
398addx 8 mm axy7 1101111100001111 .......... U U U U 18 18 12 12\r
399addx 8 mm . 1101...100001... .......... U U U U 18 18 12 12\r
400addx 16 mm . 1101...101001... .......... U U U U 18 18 12 12\r
401addx 32 mm . 1101...110001... .......... U U U U 30 30 12 12\r
402and 8 er d 1100...000000... .......... U U U U 4 4 2 2\r
403and 8 er . 1100...000...... A+-DXWLdxI U U U U 4 4 2 2\r
404and 16 er d 1100...001000... .......... U U U U 4 4 2 2\r
405and 16 er . 1100...001...... A+-DXWLdxI U U U U 4 4 2 2\r
406and 32 er d 1100...010000... .......... U U U U 6 6 2 2\r
407and 32 er . 1100...010...... A+-DXWLdxI U U U U 6 6 2 2\r
408and 8 re . 1100...100...... A+-DXWL... U U U U 8 8 4 4\r
409and 16 re . 1100...101...... A+-DXWL... U U U U 8 8 4 4\r
410and 32 re . 1100...110...... A+-DXWL... U U U U 12 12 4 4\r
411andi 16 toc . 0000001000111100 .......... U U U U 20 16 12 12\r
412andi 16 tos . 0000001001111100 .......... S S S S 20 16 12 12\r
413andi 8 . d 0000001000000... .......... U U U U 8 8 2 2\r
414andi 8 . . 0000001000...... A+-DXWL... U U U U 12 12 4 4\r
415andi 16 . d 0000001001000... .......... U U U U 8 8 2 2\r
416andi 16 . . 0000001001...... A+-DXWL... U U U U 12 12 4 4\r
417andi 32 . d 0000001010000... .......... U U U U 14 14 2 2\r
418andi 32 . . 0000001010...... A+-DXWL... U U U U 20 20 4 4\r
419asr 8 s . 1110...000000... .......... U U U U 6 6 6 6\r
420asr 16 s . 1110...001000... .......... U U U U 6 6 6 6\r
421asr 32 s . 1110...010000... .......... U U U U 8 8 6 6\r
422asr 8 r . 1110...000100... .......... U U U U 6 6 6 6\r
423asr 16 r . 1110...001100... .......... U U U U 6 6 6 6\r
424asr 32 r . 1110...010100... .......... U U U U 8 8 6 6\r
425asr 16 . . 1110000011...... A+-DXWL... U U U U 8 8 5 5\r
426asl 8 s . 1110...100000... .......... U U U U 6 6 8 8\r
427asl 16 s . 1110...101000... .......... U U U U 6 6 8 8\r
428asl 32 s . 1110...110000... .......... U U U U 8 8 8 8\r
429asl 8 r . 1110...100100... .......... U U U U 6 6 8 8\r
430asl 16 r . 1110...101100... .......... U U U U 6 6 8 8\r
431asl 32 r . 1110...110100... .......... U U U U 8 8 8 8\r
432asl 16 . . 1110000111...... A+-DXWL... U U U U 8 8 6 6\r
433bcc 8 . . 0110............ .......... U U U U 10 10 6 6\r
434bcc 16 . . 0110....00000000 .......... U U U U 10 10 6 6\r
435bcc 32 . . 0110....11111111 .......... U U U U 10 10 6 6\r
436bchg 8 r . 0000...101...... A+-DXWL... U U U U 8 8 4 4\r
437bchg 32 r d 0000...101000... .......... U U U U 8 8 4 4\r
438bchg 8 s . 0000100001...... A+-DXWL... U U U U 12 12 4 4\r
439bchg 32 s d 0000100001000... .......... U U U U 12 12 4 4\r
440bclr 8 r . 0000...110...... A+-DXWL... U U U U 8 10 4 4\r
441bclr 32 r d 0000...110000... .......... U U U U 10 10 4 4\r
442bclr 8 s . 0000100010...... A+-DXWL... U U U U 12 12 4 4\r
443bclr 32 s d 0000100010000... .......... U U U U 14 14 4 4\r
444bfchg 32 . d 1110101011000... .......... . . U U . . 12 12 timing not quite correct\r
445bfchg 32 . . 1110101011...... A..DXWL... . . U U . . 20 20\r
446bfclr 32 . d 1110110011000... .......... . . U U . . 12 12\r
447bfclr 32 . . 1110110011...... A..DXWL... . . U U . . 20 20\r
448bfexts 32 . d 1110101111000... .......... . . U U . . 8 8\r
449bfexts 32 . . 1110101111...... A..DXWLdx. . . U U . . 15 15\r
450bfextu 32 . d 1110100111000... .......... . . U U . . 8 8\r
451bfextu 32 . . 1110100111...... A..DXWLdx. . . U U . . 15 15\r
452bfffo 32 . d 1110110111000... .......... . . U U . . 18 18\r
453bfffo 32 . . 1110110111...... A..DXWLdx. . . U U . . 28 28\r
454bfins 32 . d 1110111111000... .......... . . U U . . 10 10\r
455bfins 32 . . 1110111111...... A..DXWL... . . U U . . 17 17\r
456bfset 32 . d 1110111011000... .......... . . U U . . 12 12\r
457bfset 32 . . 1110111011...... A..DXWL... . . U U . . 20 20\r
458bftst 32 . d 1110100011000... .......... . . U U . . 6 6\r
459bftst 32 . . 1110100011...... A..DXWLdx. . . U U . . 13 13\r
460bkpt 0 . . 0100100001001... .......... . U U U . 10 10 10\r
461bra 8 . . 01100000........ .......... U U U U 10 10 10 10\r
462bra 16 . . 0110000000000000 .......... U U U U 10 10 10 10\r
463bra 32 . . 0110000011111111 .......... U U U U 10 10 10 10\r
464bset 32 r d 0000...111000... .......... U U U U 8 8 4 4\r
465bset 8 r . 0000...111...... A+-DXWL... U U U U 8 8 4 4\r
466bset 8 s . 0000100011...... A+-DXWL... U U U U 12 12 4 4\r
467bset 32 s d 0000100011000... .......... U U U U 12 12 4 4\r
468bsr 8 . . 01100001........ .......... U U U U 18 18 7 7\r
469bsr 16 . . 0110000100000000 .......... U U U U 18 18 7 7\r
470bsr 32 . . 0110000111111111 .......... U U U U 18 18 7 7\r
471btst 8 r . 0000...100...... A+-DXWLdxI U U U U 4 4 4 4\r
472btst 32 r d 0000...100000... .......... U U U U 6 6 4 4\r
473btst 8 s . 0000100000...... A+-DXWLdx. U U U U 8 8 4 4\r
474btst 32 s d 0000100000000... .......... U U U U 10 10 4 4\r
475callm 32 . . 0000011011...... A..DXWLdx. . . U U . . 60 60 not properly emulated\r
476cas 8 . . 0000101011...... A+-DXWL... . . U U . . 12 12\r
477cas 16 . . 0000110011...... A+-DXWL... . . U U . . 12 12\r
478cas 32 . . 0000111011...... A+-DXWL... . . U U . . 12 12\r
479cas2 16 . . 0000110011111100 .......... . . U U . . 12 12\r
480cas2 32 . . 0000111011111100 .......... . . U U . . 12 12\r
481chk 16 . d 0100...110000... .......... U U U U 10 8 8 8\r
482chk 16 . . 0100...110...... A+-DXWLdxI U U U U 10 8 8 8\r
483chk 32 . d 0100...100000... .......... . . U U . . 8 8\r
484chk 32 . . 0100...100...... A+-DXWLdxI . . U U . . 8 8\r
485chk2cmp2 8 . pcdi 0000000011111010 .......... . . U U . . 23 23\r
486chk2cmp2 8 . pcix 0000000011111011 .......... . . U U . . 23 23\r
487chk2cmp2 8 . . 0000000011...... A..DXWL... . . U U . . 18 18\r
488chk2cmp2 16 . pcdi 0000001011111010 .......... . . U U . . 23 23\r
489chk2cmp2 16 . pcix 0000001011111011 .......... . . U U . . 23 23\r
490chk2cmp2 16 . . 0000001011...... A..DXWL... . . U U . . 18 18\r
491chk2cmp2 32 . pcdi 0000010011111010 .......... . . U U . . 23 23\r
492chk2cmp2 32 . pcix 0000010011111011 .......... . . U U . . 23 23\r
493chk2cmp2 32 . . 0000010011...... A..DXWL... . . U U . . 18 18\r
494clr 8 . d 0100001000000... .......... U U U U 4 4 2 2\r
495clr 8 . . 0100001000...... A+-DXWL... U U U U 6 4 4 4 notaz hack: changed 000 cycles 8 -> 6 like in starscream for Fatal Rewind\r
496clr 16 . d 0100001001000... .......... U U U U 4 4 2 2\r
497clr 16 . . 0100001001...... A+-DXWL... U U U U 6 4 4 4 ditto\r
498clr 32 . d 0100001010000... .......... U U U U 6 6 2 2\r
499clr 32 . . 0100001010...... A+-DXWL... U U U U 12 6 4 4\r
500cmp 8 . d 1011...000000... .......... U U U U 4 4 2 2\r
501cmp 8 . . 1011...000...... A+-DXWLdxI U U U U 4 4 2 2\r
502cmp 16 . d 1011...001000... .......... U U U U 4 4 2 2\r
503cmp 16 . a 1011...001001... .......... U U U U 4 4 2 2\r
504cmp 16 . . 1011...001...... A+-DXWLdxI U U U U 4 4 2 2\r
505cmp 32 . d 1011...010000... .......... U U U U 6 6 2 2\r
506cmp 32 . a 1011...010001... .......... U U U U 6 6 2 2\r
507cmp 32 . . 1011...010...... A+-DXWLdxI U U U U 6 6 2 2\r
508cmpa 16 . d 1011...011000... .......... U U U U 6 6 4 4\r
509cmpa 16 . a 1011...011001... .......... U U U U 6 6 4 4\r
510cmpa 16 . . 1011...011...... A+-DXWLdxI U U U U 6 6 4 4\r
511cmpa 32 . d 1011...111000... .......... U U U U 6 6 4 4\r
512cmpa 32 . a 1011...111001... .......... U U U U 6 6 4 4\r
513cmpa 32 . . 1011...111...... A+-DXWLdxI U U U U 6 6 4 4\r
514cmpi 8 . d 0000110000000... .......... U U U U 8 8 2 2\r
515cmpi 8 . . 0000110000...... A+-DXWL... U U U U 8 8 2 2\r
516cmpi 8 . pcdi 0000110000111010 .......... . . U U . . 7 7\r
517cmpi 8 . pcix 0000110000111011 .......... . . U U . . 9 9\r
518cmpi 16 . d 0000110001000... .......... U U U U 8 8 2 2\r
519cmpi 16 . . 0000110001...... A+-DXWL... U U U U 8 8 2 2\r
520cmpi 16 . pcdi 0000110001111010 .......... . . U U . . 7 7\r
521cmpi 16 . pcix 0000110001111011 .......... . . U U . . 9 9\r
522cmpi 32 . d 0000110010000... .......... U U U U 14 12 2 2\r
523cmpi 32 . . 0000110010...... A+-DXWL... U U U U 12 12 2 2\r
524cmpi 32 . pcdi 0000110010111010 .......... . . U U . . 7 7\r
525cmpi 32 . pcix 0000110010111011 .......... . . U U . . 9 9\r
526cmpm 8 . ax7 1011111100001... .......... U U U U 12 12 9 9\r
527cmpm 8 . ay7 1011...100001111 .......... U U U U 12 12 9 9\r
528cmpm 8 . axy7 1011111100001111 .......... U U U U 12 12 9 9\r
529cmpm 8 . . 1011...100001... .......... U U U U 12 12 9 9\r
530cmpm 16 . . 1011...101001... .......... U U U U 12 12 9 9\r
531cmpm 32 . . 1011...110001... .......... U U U U 20 20 9 9\r
532cpbcc 32 . . 1111...01....... .......... . . U . . . 4 . unemulated\r
533cpdbcc 32 . . 1111...001001... .......... . . U . . . 4 . unemulated\r
534cpgen 32 . . 1111...000...... .......... . . U . . . 4 . unemulated\r
535cpscc 32 . . 1111...001...... .......... . . U . . . 4 . unemulated\r
536cptrapcc 32 . . 1111...001111... .......... . . U . . . 4 . unemulated\r
537dbt 16 . . 0101000011001... .......... U U U U 12 12 6 6\r
538dbf 16 . . 0101000111001... .......... U U U U 12 12 6 6\r
539dbcc 16 . . 0101....11001... .......... U U U U 12 12 6 6\r
540divs 16 . d 1000...111000... .......... U U U U 158 122 56 56\r
541divs 16 . . 1000...111...... A+-DXWLdxI U U U U 158 122 56 56\r
542divu 16 . d 1000...011000... .......... U U U U 140 108 44 44\r
543divu 16 . . 1000...011...... A+-DXWLdxI U U U U 140 108 44 44\r
544divl 32 . d 0100110001000... .......... . . U U . . 84 84\r
545divl 32 . . 0100110001...... A+-DXWLdxI . . U U . . 84 84\r
546eor 8 . d 1011...100000... .......... U U U U 4 4 2 2\r
547eor 8 . . 1011...100...... A+-DXWL... U U U U 8 8 4 4\r
548eor 16 . d 1011...101000... .......... U U U U 4 4 2 2\r
549eor 16 . . 1011...101...... A+-DXWL... U U U U 8 8 4 4\r
550eor 32 . d 1011...110000... .......... U U U U 8 6 2 2\r
551eor 32 . . 1011...110...... A+-DXWL... U U U U 12 12 4 4\r
552eori 16 toc . 0000101000111100 .......... U U U U 20 16 12 12\r
553eori 16 tos . 0000101001111100 .......... S S S S 20 16 12 12\r
554eori 8 . d 0000101000000... .......... U U U U 8 8 2 2\r
555eori 8 . . 0000101000...... A+-DXWL... U U U U 12 12 4 4\r
556eori 16 . d 0000101001000... .......... U U U U 8 8 2 2\r
557eori 16 . . 0000101001...... A+-DXWL... U U U U 12 12 4 4\r
558eori 32 . d 0000101010000... .......... U U U U 16 14 2 2\r
559eori 32 . . 0000101010...... A+-DXWL... U U U U 20 20 4 4\r
560exg 32 dd . 1100...101000... .......... U U U U 6 6 2 2\r
561exg 32 aa . 1100...101001... .......... U U U U 6 6 2 2\r
562exg 32 da . 1100...110001... .......... U U U U 6 6 2 2\r
563ext 16 . . 0100100010000... .......... U U U U 4 4 4 4\r
564ext 32 . . 0100100011000... .......... U U U U 4 4 4 4\r
565extb 32 . . 0100100111000... .......... . . U U . . 4 4\r
566illegal 0 . . 0100101011111100 .......... U U U U 4 4 4 4\r
567jmp 32 . . 0100111011...... A..DXWLdx. U U U U 4 4 0 0\r
568jsr 32 . . 0100111010...... A..DXWLdx. U U U U 12 12 0 0\r
569lea 32 . . 0100...111...... A..DXWLdx. U U U U 0 0 2 2\r
570link 16 . a7 0100111001010111 .......... U U U U 16 16 5 5\r
571link 16 . . 0100111001010... .......... U U U U 16 16 5 5\r
572link 32 . a7 0100100000001111 .......... . . U U . . 6 6\r
573link 32 . . 0100100000001... .......... . . U U . . 6 6\r
574lsr 8 s . 1110...000001... .......... U U U U 6 6 4 4\r
575lsr 16 s . 1110...001001... .......... U U U U 6 6 4 4\r
576lsr 32 s . 1110...010001... .......... U U U U 8 8 4 4\r
577lsr 8 r . 1110...000101... .......... U U U U 6 6 6 6\r
578lsr 16 r . 1110...001101... .......... U U U U 6 6 6 6\r
579lsr 32 r . 1110...010101... .......... U U U U 8 8 6 6\r
580lsr 16 . . 1110001011...... A+-DXWL... U U U U 8 8 5 5\r
581lsl 8 s . 1110...100001... .......... U U U U 6 6 4 4\r
582lsl 16 s . 1110...101001... .......... U U U U 6 6 4 4\r
583lsl 32 s . 1110...110001... .......... U U U U 8 8 4 4\r
584lsl 8 r . 1110...100101... .......... U U U U 6 6 6 6\r
585lsl 16 r . 1110...101101... .......... U U U U 6 6 6 6\r
586lsl 32 r . 1110...110101... .......... U U U U 8 8 6 6\r
587lsl 16 . . 1110001111...... A+-DXWL... U U U U 8 8 5 5\r
588move 8 d d 0001...000000... .......... U U U U 4 4 2 2\r
589move 8 d . 0001...000...... A+-DXWLdxI U U U U 4 4 2 2\r
590move 8 ai d 0001...010000... .......... U U U U 8 8 4 4\r
591move 8 ai . 0001...010...... A+-DXWLdxI U U U U 8 8 4 4\r
592move 8 pi d 0001...011000... .......... U U U U 8 8 4 4\r
593move 8 pi . 0001...011...... A+-DXWLdxI U U U U 8 8 4 4\r
594move 8 pi7 d 0001111011000... .......... U U U U 8 8 4 4\r
595move 8 pi7 . 0001111011...... A+-DXWLdxI U U U U 8 8 4 4\r
596move 8 pd d 0001...100000... .......... U U U U 8 8 5 5\r
597move 8 pd . 0001...100...... A+-DXWLdxI U U U U 8 8 5 5\r
598move 8 pd7 d 0001111100000... .......... U U U U 8 8 5 5\r
599move 8 pd7 . 0001111100...... A+-DXWLdxI U U U U 8 8 5 5\r
600move 8 di d 0001...101000... .......... U U U U 12 12 5 5\r
601move 8 di . 0001...101...... A+-DXWLdxI U U U U 12 12 5 5\r
602move 8 ix d 0001...110000... .......... U U U U 14 14 7 7\r
603move 8 ix . 0001...110...... A+-DXWLdxI U U U U 14 14 7 7\r
604move 8 aw d 0001000111000... .......... U U U U 12 12 4 4\r
605move 8 aw . 0001000111...... A+-DXWLdxI U U U U 12 12 4 4\r
606move 8 al d 0001001111000... .......... U U U U 16 16 6 6\r
607move 8 al . 0001001111...... A+-DXWLdxI U U U U 16 16 6 6\r
608move 16 d d 0011...000000... .......... U U U U 4 4 2 2\r
609move 16 d a 0011...000001... .......... U U U U 4 4 2 2\r
610move 16 d . 0011...000...... A+-DXWLdxI U U U U 4 4 2 2\r
611move 16 ai d 0011...010000... .......... U U U U 8 8 4 4\r
612move 16 ai a 0011...010001... .......... U U U U 8 8 4 4\r
613move 16 ai . 0011...010...... A+-DXWLdxI U U U U 8 8 4 4\r
614move 16 pi d 0011...011000... .......... U U U U 8 8 4 4\r
615move 16 pi a 0011...011001... .......... U U U U 8 8 4 4\r
616move 16 pi . 0011...011...... A+-DXWLdxI U U U U 8 8 4 4\r
617move 16 pd d 0011...100000... .......... U U U U 8 8 5 5\r
618move 16 pd a 0011...100001... .......... U U U U 8 8 5 5\r
619move 16 pd . 0011...100...... A+-DXWLdxI U U U U 8 8 5 5\r
620move 16 di d 0011...101000... .......... U U U U 12 12 5 5\r
621move 16 di a 0011...101001... .......... U U U U 12 12 5 5\r
622move 16 di . 0011...101...... A+-DXWLdxI U U U U 12 12 5 5\r
623move 16 ix d 0011...110000... .......... U U U U 14 14 7 7\r
624move 16 ix a 0011...110001... .......... U U U U 14 14 7 7\r
625move 16 ix . 0011...110...... A+-DXWLdxI U U U U 14 14 7 7\r
626move 16 aw d 0011000111000... .......... U U U U 12 12 4 4\r
627move 16 aw a 0011000111001... .......... U U U U 12 12 4 4\r
628move 16 aw . 0011000111...... A+-DXWLdxI U U U U 12 12 4 4\r
629move 16 al d 0011001111000... .......... U U U U 16 16 6 6\r
630move 16 al a 0011001111001... .......... U U U U 16 16 6 6\r
631move 16 al . 0011001111...... A+-DXWLdxI U U U U 16 16 6 6\r
632move 32 d d 0010...000000... .......... U U U U 4 4 2 2\r
633move 32 d a 0010...000001... .......... U U U U 4 4 2 2\r
634move 32 d . 0010...000...... A+-DXWLdxI U U U U 4 4 2 2\r
635move 32 ai d 0010...010000... .......... U U U U 12 12 4 4\r
636move 32 ai a 0010...010001... .......... U U U U 12 12 4 4\r
637move 32 ai . 0010...010...... A+-DXWLdxI U U U U 12 12 4 4\r
638move 32 pi d 0010...011000... .......... U U U U 12 12 4 4\r
639move 32 pi a 0010...011001... .......... U U U U 12 12 4 4\r
640move 32 pi . 0010...011...... A+-DXWLdxI U U U U 12 12 4 4\r
641move 32 pd d 0010...100000... .......... U U U U 12 14 5 5\r
642move 32 pd a 0010...100001... .......... U U U U 12 14 5 5\r
643move 32 pd . 0010...100...... A+-DXWLdxI U U U U 12 14 5 5\r
644move 32 di d 0010...101000... .......... U U U U 16 16 5 5\r
645move 32 di a 0010...101001... .......... U U U U 16 16 5 5\r
646move 32 di . 0010...101...... A+-DXWLdxI U U U U 16 16 5 5\r
647move 32 ix d 0010...110000... .......... U U U U 18 18 7 7\r
648move 32 ix a 0010...110001... .......... U U U U 18 18 7 7\r
649move 32 ix . 0010...110...... A+-DXWLdxI U U U U 18 18 7 7\r
650move 32 aw d 0010000111000... .......... U U U U 16 16 4 4\r
651move 32 aw a 0010000111001... .......... U U U U 16 16 4 4\r
652move 32 aw . 0010000111...... A+-DXWLdxI U U U U 16 16 4 4\r
653move 32 al d 0010001111000... .......... U U U U 20 20 6 6\r
654move 32 al a 0010001111001... .......... U U U U 20 20 6 6\r
655move 32 al . 0010001111...... A+-DXWLdxI U U U U 20 20 6 6\r
656movea 16 . d 0011...001000... .......... U U U U 4 4 2 2\r
657movea 16 . a 0011...001001... .......... U U U U 4 4 2 2\r
658movea 16 . . 0011...001...... A+-DXWLdxI U U U U 4 4 2 2\r
659movea 32 . d 0010...001000... .......... U U U U 4 4 2 2\r
660movea 32 . a 0010...001001... .......... U U U U 4 4 2 2\r
661movea 32 . . 0010...001...... A+-DXWLdxI U U U U 4 4 2 2\r
662move 16 frc d 0100001011000... .......... . U U U . 4 4 4\r
663move 16 frc . 0100001011...... A+-DXWL... . U U U . 8 4 4\r
664move 16 toc d 0100010011000... .......... U U U U 12 12 4 4\r
665move 16 toc . 0100010011...... A+-DXWLdxI U U U U 12 12 4 4\r
666move 16 frs d 0100000011000... .......... U S S S 6 4 8 8 U only for 000\r
667move 16 frs . 0100000011...... A+-DXWL... U S S S 8 8 8 8 U only for 000\r
668move 16 tos d 0100011011000... .......... S S S S 12 12 8 8\r
669move 16 tos . 0100011011...... A+-DXWLdxI S S S S 12 12 8 8\r
670move 32 fru . 0100111001101... .......... S S S S 4 6 2 2\r
671move 32 tou . 0100111001100... .......... S S S S 4 6 2 2\r
672movec 32 cr . 0100111001111010 .......... . S S S . 12 6 6\r
673movec 32 rc . 0100111001111011 .......... . S S S . 10 12 12\r
674movem 16 re pd 0100100010100... .......... U U U U 8 8 4 4\r
675movem 16 re . 0100100010...... A..DXWL... U U U U 8 8 4 4\r
676movem 32 re pd 0100100011100... .......... U U U U 8 8 4 4\r
677movem 32 re . 0100100011...... A..DXWL... U U U U 8 8 4 4\r
678movem 16 er pi 0100110010011... .......... U U U U 12 12 8 8\r
679movem 16 er pcdi 0100110010111010 .......... U U U U 16 16 9 9\r
680movem 16 er pcix 0100110010111011 .......... U U U U 18 18 11 11\r
681movem 16 er . 0100110010...... A..DXWL... U U U U 12 12 8 8\r
682movem 32 er pi 0100110011011... .......... U U U U 12 12 8 8\r
683movem 32 er pcdi 0100110011111010 .......... U U U U 16 16 9 9\r
684movem 32 er pcix 0100110011111011 .......... U U U U 18 18 11 11\r
685movem 32 er . 0100110011...... A..DXWL... U U U U 12 12 8 8\r
686movep 16 er . 0000...100001... .......... U U U U 16 16 12 12\r
687movep 32 er . 0000...101001... .......... U U U U 24 24 18 18\r
688movep 16 re . 0000...110001... .......... U U U U 16 16 11 11\r
689movep 32 re . 0000...111001... .......... U U U U 24 24 17 17\r
690moveq 32 . . 0111...0........ .......... U U U U 4 4 2 2\r
691moves 8 . . 0000111000...... A+-DXWL... . S S S . 14 5 5\r
692moves 16 . . 0000111001...... A+-DXWL... . S S S . 14 5 5\r
693moves 32 . . 0000111010...... A+-DXWL... . S S S . 16 5 5\r
694move16 32 . . 1111011000100... .......... . . . U . . . 4 TODO: correct timing\r
695muls 16 . d 1100...111000... .......... U U U U 54 32 27 27\r
696muls 16 . . 1100...111...... A+-DXWLdxI U U U U 54 32 27 27\r
697mulu 16 . d 1100...011000... .......... U U U U 54 30 27 27\r
698mulu 16 . . 1100...011...... A+-DXWLdxI U U U U 54 30 27 27\r
699mull 32 . d 0100110000000... .......... . . U U . . 43 43\r
700mull 32 . . 0100110000...... A+-DXWLdxI . . U U . . 43 43\r
701nbcd 8 . d 0100100000000... .......... U U U U 6 6 6 6\r
702nbcd 8 . . 0100100000...... A+-DXWL... U U U U 8 8 6 6\r
703neg 8 . d 0100010000000... .......... U U U U 4 4 2 2\r
704neg 8 . . 0100010000...... A+-DXWL... U U U U 8 8 4 4\r
705neg 16 . d 0100010001000... .......... U U U U 4 4 2 2\r
706neg 16 . . 0100010001...... A+-DXWL... U U U U 8 8 4 4\r
707neg 32 . d 0100010010000... .......... U U U U 6 6 2 2\r
708neg 32 . . 0100010010...... A+-DXWL... U U U U 12 12 4 4\r
709negx 8 . d 0100000000000... .......... U U U U 4 4 2 2\r
710negx 8 . . 0100000000...... A+-DXWL... U U U U 8 8 4 4\r
711negx 16 . d 0100000001000... .......... U U U U 4 4 2 2\r
712negx 16 . . 0100000001...... A+-DXWL... U U U U 8 8 4 4\r
713negx 32 . d 0100000010000... .......... U U U U 6 6 2 2\r
714negx 32 . . 0100000010...... A+-DXWL... U U U U 12 12 4 4\r
715nop 0 . . 0100111001110001 .......... U U U U 4 4 2 2\r
716not 8 . d 0100011000000... .......... U U U U 4 4 2 2\r
717not 8 . . 0100011000...... A+-DXWL... U U U U 8 8 4 4\r
718not 16 . d 0100011001000... .......... U U U U 4 4 2 2\r
719not 16 . . 0100011001...... A+-DXWL... U U U U 8 8 4 4\r
720not 32 . d 0100011010000... .......... U U U U 6 6 2 2\r
721not 32 . . 0100011010...... A+-DXWL... U U U U 12 12 4 4\r
722or 8 er d 1000...000000... .......... U U U U 4 4 2 2\r
723or 8 er . 1000...000...... A+-DXWLdxI U U U U 4 4 2 2\r
724or 16 er d 1000...001000... .......... U U U U 4 4 2 2\r
725or 16 er . 1000...001...... A+-DXWLdxI U U U U 4 4 2 2\r
726or 32 er d 1000...010000... .......... U U U U 6 6 2 2\r
727or 32 er . 1000...010...... A+-DXWLdxI U U U U 6 6 2 2\r
728or 8 re . 1000...100...... A+-DXWL... U U U U 8 8 4 4\r
729or 16 re . 1000...101...... A+-DXWL... U U U U 8 8 4 4\r
730or 32 re . 1000...110...... A+-DXWL... U U U U 12 12 4 4\r
731ori 16 toc . 0000000000111100 .......... U U U U 20 16 12 12\r
732ori 16 tos . 0000000001111100 .......... S S S S 20 16 12 12\r
733ori 8 . d 0000000000000... .......... U U U U 8 8 2 2\r
734ori 8 . . 0000000000...... A+-DXWL... U U U U 12 12 4 4\r
735ori 16 . d 0000000001000... .......... U U U U 8 8 2 2\r
736ori 16 . . 0000000001...... A+-DXWL... U U U U 12 12 4 4\r
737ori 32 . d 0000000010000... .......... U U U U 16 14 2 2\r
738ori 32 . . 0000000010...... A+-DXWL... U U U U 20 20 4 4\r
739pack 16 rr . 1000...101000... .......... . . U U . . 6 6\r
740pack 16 mm ax7 1000111101001... .......... . . U U . . 13 13\r
741pack 16 mm ay7 1000...101001111 .......... . . U U . . 13 13\r
742pack 16 mm axy7 1000111101001111 .......... . . U U . . 13 13\r
743pack 16 mm . 1000...101001... .......... . . U U . . 13 13\r
744pea 32 . . 0100100001...... A..DXWLdx. U U U U 6 6 5 5\r
745pflush 32 . . 1111010100011000 .......... . . . S . . . 4 TODO: correct timing\r
746reset 0 . . 0100111001110000 .......... S S S S 0 0 0 0\r
747ror 8 s . 1110...000011... .......... U U U U 6 6 8 8\r
748ror 16 s . 1110...001011... .......... U U U U 6 6 8 8\r
749ror 32 s . 1110...010011... .......... U U U U 8 8 8 8\r
750ror 8 r . 1110...000111... .......... U U U U 6 6 8 8\r
751ror 16 r . 1110...001111... .......... U U U U 6 6 8 8\r
752ror 32 r . 1110...010111... .......... U U U U 8 8 8 8\r
753ror 16 . . 1110011011...... A+-DXWL... U U U U 8 8 7 7\r
754rol 8 s . 1110...100011... .......... U U U U 6 6 8 8\r
755rol 16 s . 1110...101011... .......... U U U U 6 6 8 8\r
756rol 32 s . 1110...110011... .......... U U U U 8 8 8 8\r
757rol 8 r . 1110...100111... .......... U U U U 6 6 8 8\r
758rol 16 r . 1110...101111... .......... U U U U 6 6 8 8\r
759rol 32 r . 1110...110111... .......... U U U U 8 8 8 8\r
760rol 16 . . 1110011111...... A+-DXWL... U U U U 8 8 7 7\r
761roxr 8 s . 1110...000010... .......... U U U U 6 6 12 12\r
762roxr 16 s . 1110...001010... .......... U U U U 6 6 12 12\r
763roxr 32 s . 1110...010010... .......... U U U U 8 8 12 12\r
764roxr 8 r . 1110...000110... .......... U U U U 6 6 12 12\r
765roxr 16 r . 1110...001110... .......... U U U U 6 6 12 12\r
766roxr 32 r . 1110...010110... .......... U U U U 8 8 12 12\r
767roxr 16 . . 1110010011...... A+-DXWL... U U U U 8 8 5 5\r
768roxl 8 s . 1110...100010... .......... U U U U 6 6 12 12\r
769roxl 16 s . 1110...101010... .......... U U U U 6 6 12 12\r
770roxl 32 s . 1110...110010... .......... U U U U 8 8 12 12\r
771roxl 8 r . 1110...100110... .......... U U U U 6 6 12 12\r
772roxl 16 r . 1110...101110... .......... U U U U 6 6 12 12\r
773roxl 32 r . 1110...110110... .......... U U U U 8 8 12 12\r
774roxl 16 . . 1110010111...... A+-DXWL... U U U U 8 8 5 5\r
775rtd 32 . . 0100111001110100 .......... . U U U . 16 10 10\r
776rte 32 . . 0100111001110011 .......... S S S S 20 24 20 20 bus fault not emulated\r
777rtm 32 . . 000001101100.... .......... . . U U . . 19 19 not properly emulated\r
778rtr 32 . . 0100111001110111 .......... U U U U 20 20 14 14\r
779rts 32 . . 0100111001110101 .......... U U U U 16 16 10 10\r
780sbcd 8 rr . 1000...100000... .......... U U U U 6 6 4 4\r
781sbcd 8 mm ax7 1000111100001... .......... U U U U 18 18 16 16\r
782sbcd 8 mm ay7 1000...100001111 .......... U U U U 18 18 16 16\r
783sbcd 8 mm axy7 1000111100001111 .......... U U U U 18 18 16 16\r
784sbcd 8 mm . 1000...100001... .......... U U U U 18 18 16 16\r
785st 8 . d 0101000011000... .......... U U U U 6 4 4 4\r
786st 8 . . 0101000011...... A+-DXWL... U U U U 8 8 6 6\r
787sf 8 . d 0101000111000... .......... U U U U 4 4 4 4\r
788sf 8 . . 0101000111...... A+-DXWL... U U U U 8 8 6 6\r
789scc 8 . d 0101....11000... .......... U U U U 4 4 4 4\r
790scc 8 . . 0101....11...... A+-DXWL... U U U U 8 8 6 6\r
791stop 0 . . 0100111001110010 .......... S S S S 4 4 8 8\r
792sub 8 er d 1001...000000... .......... U U U U 4 4 2 2\r
793sub 8 er . 1001...000...... A+-DXWLdxI U U U U 4 4 2 2\r
794sub 16 er d 1001...001000... .......... U U U U 4 4 2 2\r
795sub 16 er a 1001...001001... .......... U U U U 4 4 2 2\r
796sub 16 er . 1001...001...... A+-DXWLdxI U U U U 4 4 2 2\r
797sub 32 er d 1001...010000... .......... U U U U 6 6 2 2\r
798sub 32 er a 1001...010001... .......... U U U U 6 6 2 2\r
799sub 32 er . 1001...010...... A+-DXWLdxI U U U U 6 6 2 2\r
800sub 8 re . 1001...100...... A+-DXWL... U U U U 8 8 4 4\r
801sub 16 re . 1001...101...... A+-DXWL... U U U U 8 8 4 4\r
802sub 32 re . 1001...110...... A+-DXWL... U U U U 12 12 4 4\r
803suba 16 . d 1001...011000... .......... U U U U 8 8 2 2\r
804suba 16 . a 1001...011001... .......... U U U U 8 8 2 2\r
805suba 16 . . 1001...011...... A+-DXWLdxI U U U U 8 8 2 2\r
806suba 32 . d 1001...111000... .......... U U U U 6 6 2 2\r
807suba 32 . a 1001...111001... .......... U U U U 6 6 2 2\r
808suba 32 . . 1001...111...... A+-DXWLdxI U U U U 6 6 2 2\r
809subi 8 . d 0000010000000... .......... U U U U 8 8 2 2\r
810subi 8 . . 0000010000...... A+-DXWL... U U U U 12 12 4 4\r
811subi 16 . d 0000010001000... .......... U U U U 8 8 2 2\r
812subi 16 . . 0000010001...... A+-DXWL... U U U U 12 12 4 4\r
813subi 32 . d 0000010010000... .......... U U U U 16 14 2 2\r
814subi 32 . . 0000010010...... A+-DXWL... U U U U 20 20 4 4\r
815subq 8 . d 0101...100000... .......... U U U U 4 4 2 2\r
816subq 8 . . 0101...100...... A+-DXWL... U U U U 8 8 4 4\r
817subq 16 . d 0101...101000... .......... U U U U 4 4 2 2\r
818subq 16 . a 0101...101001... .......... U U U U 8 4 2 2\r
819subq 16 . . 0101...101...... A+-DXWL... U U U U 8 8 4 4\r
820subq 32 . d 0101...110000... .......... U U U U 8 8 2 2\r
821subq 32 . a 0101...110001... .......... U U U U 8 8 2 2\r
822subq 32 . . 0101...110...... A+-DXWL... U U U U 12 12 4 4\r
823subx 8 rr . 1001...100000... .......... U U U U 4 4 2 2\r
824subx 16 rr . 1001...101000... .......... U U U U 4 4 2 2\r
825subx 32 rr . 1001...110000... .......... U U U U 8 6 2 2\r
826subx 8 mm ax7 1001111100001... .......... U U U U 18 18 12 12\r
827subx 8 mm ay7 1001...100001111 .......... U U U U 18 18 12 12\r
828subx 8 mm axy7 1001111100001111 .......... U U U U 18 18 12 12\r
829subx 8 mm . 1001...100001... .......... U U U U 18 18 12 12\r
830subx 16 mm . 1001...101001... .......... U U U U 18 18 12 12\r
831subx 32 mm . 1001...110001... .......... U U U U 30 30 12 12\r
832swap 32 . . 0100100001000... .......... U U U U 4 4 4 4\r
833tas 8 . d 0100101011000... .......... U U U U 4 4 4 4\r
834tas 8 . . 0100101011...... A+-DXWL... U U U U 14 14 12 12\r
835trap 0 . . 010011100100.... .......... U U U U 4 4 4 4\r
836trapt 0 . . 0101000011111100 .......... . . U U . . 4 4\r
837trapt 16 . . 0101000011111010 .......... . . U U . . 6 6\r
838trapt 32 . . 0101000011111011 .......... . . U U . . 8 8\r
839trapf 0 . . 0101000111111100 .......... . . U U . . 4 4\r
840trapf 16 . . 0101000111111010 .......... . . U U . . 6 6\r
841trapf 32 . . 0101000111111011 .......... . . U U . . 8 8\r
842trapcc 0 . . 0101....11111100 .......... . . U U . . 4 4\r
843trapcc 16 . . 0101....11111010 .......... . . U U . . 6 6\r
844trapcc 32 . . 0101....11111011 .......... . . U U . . 8 8\r
845trapv 0 . . 0100111001110110 .......... U U U U 4 4 4 4\r
846tst 8 . d 0100101000000... .......... U U U U 4 4 2 2\r
847tst 8 . . 0100101000...... A+-DXWL... U U U U 4 4 2 2\r
848tst 8 . pcdi 0100101000111010 .......... . . U U . . 7 7\r
849tst 8 . pcix 0100101000111011 .......... . . U U . . 9 9\r
850tst 8 . i 0100101000111100 .......... . . U U . . 6 6\r
851tst 16 . d 0100101001000... .......... U U U U 4 4 2 2\r
852tst 16 . a 0100101001001... .......... . . U U . . 2 2\r
853tst 16 . . 0100101001...... A+-DXWL... U U U U 4 4 2 2\r
854tst 16 . pcdi 0100101001111010 .......... . . U U . . 7 7\r
855tst 16 . pcix 0100101001111011 .......... . . U U . . 9 9\r
856tst 16 . i 0100101001111100 .......... . . U U . . 6 6\r
857tst 32 . d 0100101010000... .......... U U U U 4 4 2 2\r
858tst 32 . a 0100101010001... .......... . . U U . . 2 2\r
859tst 32 . . 0100101010...... A+-DXWL... U U U U 4 4 2 2\r
860tst 32 . pcdi 0100101010111010 .......... . . U U . . 7 7\r
861tst 32 . pcix 0100101010111011 .......... . . U U . . 9 9\r
862tst 32 . i 0100101010111100 .......... . . U U . . 6 6\r
863unlk 32 . a7 0100111001011111 .......... U U U U 12 12 6 6\r
864unlk 32 . . 0100111001011... .......... U U U U 12 12 6 6\r
865unpk 16 rr . 1000...110000... .......... . . U U . . 8 8\r
866unpk 16 mm ax7 1000111110001... .......... . . U U . . 13 13\r
867unpk 16 mm ay7 1000...110001111 .......... . . U U . . 13 13\r
868unpk 16 mm axy7 1000111110001111 .......... . . U U . . 13 13\r
869unpk 16 mm . 1000...110001... .......... . . U U . . 13 13\r
870\r
871\r
872\r
873XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\r
874M68KMAKE_OPCODE_HANDLER_BODY\r
875\r
876M68KMAKE_OP(1010, 0, ., .)\r
877{\r
878 m68ki_exception_1010();\r
879}\r
880\r
881\r
882M68KMAKE_OP(1111, 0, ., .)\r
883{\r
884 m68ki_exception_1111();\r
885}\r
886\r
887\r
888M68KMAKE_OP(abcd, 8, rr, .)\r
889{\r
890 uint* r_dst = &DX;\r
891 uint src = DY;\r
892 uint dst = *r_dst;\r
893 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();\r
894\r
895 FLAG_V = ~res; /* Undefined V behavior */\r
896\r
897 if(res > 9)\r
898 res += 6;\r
899 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);\r
900 FLAG_X = FLAG_C = (res > 0x99) << 8;\r
901 if(FLAG_C)\r
902 res -= 0xa0;\r
903\r
904 FLAG_V &= res; /* Undefined V behavior part II */\r
905 FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
906\r
907 res = MASK_OUT_ABOVE_8(res);\r
908 FLAG_Z |= res;\r
909\r
910 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
911}\r
912\r
913\r
914M68KMAKE_OP(abcd, 8, mm, ax7)\r
915{\r
916 uint src = OPER_AY_PD_8();\r
917 uint ea = EA_A7_PD_8();\r
918 uint dst = m68ki_read_8(ea);\r
919 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();\r
920\r
921 FLAG_V = ~res; /* Undefined V behavior */\r
922\r
923 if(res > 9)\r
924 res += 6;\r
925 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);\r
926 FLAG_X = FLAG_C = (res > 0x99) << 8;\r
927 if(FLAG_C)\r
928 res -= 0xa0;\r
929\r
930 FLAG_V &= res; /* Undefined V behavior part II */\r
931 FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
932\r
933 res = MASK_OUT_ABOVE_8(res);\r
934 FLAG_Z |= res;\r
935\r
936 m68ki_write_8(ea, res);\r
937}\r
938\r
939\r
940M68KMAKE_OP(abcd, 8, mm, ay7)\r
941{\r
942 uint src = OPER_A7_PD_8();\r
943 uint ea = EA_AX_PD_8();\r
944 uint dst = m68ki_read_8(ea);\r
945 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();\r
946\r
947 FLAG_V = ~res; /* Undefined V behavior */\r
948\r
949 if(res > 9)\r
950 res += 6;\r
951 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);\r
952 FLAG_X = FLAG_C = (res > 0x99) << 8;\r
953 if(FLAG_C)\r
954 res -= 0xa0;\r
955\r
956 FLAG_V &= res; /* Undefined V behavior part II */\r
957 FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
958\r
959 res = MASK_OUT_ABOVE_8(res);\r
960 FLAG_Z |= res;\r
961\r
962 m68ki_write_8(ea, res);\r
963}\r
964\r
965\r
966M68KMAKE_OP(abcd, 8, mm, axy7)\r
967{\r
968 uint src = OPER_A7_PD_8();\r
969 uint ea = EA_A7_PD_8();\r
970 uint dst = m68ki_read_8(ea);\r
971 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();\r
972\r
973 FLAG_V = ~res; /* Undefined V behavior */\r
974\r
975 if(res > 9)\r
976 res += 6;\r
977 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);\r
978 FLAG_X = FLAG_C = (res > 0x99) << 8;\r
979 if(FLAG_C)\r
980 res -= 0xa0;\r
981\r
982 FLAG_V &= res; /* Undefined V behavior part II */\r
983 FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
984\r
985 res = MASK_OUT_ABOVE_8(res);\r
986 FLAG_Z |= res;\r
987\r
988 m68ki_write_8(ea, res);\r
989}\r
990\r
991\r
992M68KMAKE_OP(abcd, 8, mm, .)\r
993{\r
994 uint src = OPER_AY_PD_8();\r
995 uint ea = EA_AX_PD_8();\r
996 uint dst = m68ki_read_8(ea);\r
997 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();\r
998\r
999 FLAG_V = ~res; /* Undefined V behavior */\r
1000\r
1001 if(res > 9)\r
1002 res += 6;\r
1003 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);\r
1004 FLAG_X = FLAG_C = (res > 0x99) << 8;\r
1005 if(FLAG_C)\r
1006 res -= 0xa0;\r
1007\r
1008 FLAG_V &= res; /* Undefined V behavior part II */\r
1009 FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
1010\r
1011 res = MASK_OUT_ABOVE_8(res);\r
1012 FLAG_Z |= res;\r
1013\r
1014 m68ki_write_8(ea, res);\r
1015}\r
1016\r
1017\r
1018M68KMAKE_OP(add, 8, er, d)\r
1019{\r
1020 uint* r_dst = &DX;\r
1021 uint src = MASK_OUT_ABOVE_8(DY);\r
1022 uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
1023 uint res = src + dst;\r
1024\r
1025 FLAG_N = NFLAG_8(res);\r
1026 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1027 FLAG_X = FLAG_C = CFLAG_8(res);\r
1028 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
1029\r
1030 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;\r
1031}\r
1032\r
1033\r
1034M68KMAKE_OP(add, 8, er, .)\r
1035{\r
1036 uint* r_dst = &DX;\r
1037 uint src = M68KMAKE_GET_OPER_AY_8;\r
1038 uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
1039 uint res = src + dst;\r
1040\r
1041 FLAG_N = NFLAG_8(res);\r
1042 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1043 FLAG_X = FLAG_C = CFLAG_8(res);\r
1044 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
1045\r
1046 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;\r
1047}\r
1048\r
1049\r
1050M68KMAKE_OP(add, 16, er, d)\r
1051{\r
1052 uint* r_dst = &DX;\r
1053 uint src = MASK_OUT_ABOVE_16(DY);\r
1054 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
1055 uint res = src + dst;\r
1056\r
1057 FLAG_N = NFLAG_16(res);\r
1058 FLAG_V = VFLAG_ADD_16(src, dst, res);\r
1059 FLAG_X = FLAG_C = CFLAG_16(res);\r
1060 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
1061\r
1062 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
1063}\r
1064\r
1065\r
1066M68KMAKE_OP(add, 16, er, a)\r
1067{\r
1068 uint* r_dst = &DX;\r
1069 uint src = MASK_OUT_ABOVE_16(AY);\r
1070 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
1071 uint res = src + dst;\r
1072\r
1073 FLAG_N = NFLAG_16(res);\r
1074 FLAG_V = VFLAG_ADD_16(src, dst, res);\r
1075 FLAG_X = FLAG_C = CFLAG_16(res);\r
1076 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
1077\r
1078 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
1079}\r
1080\r
1081\r
1082M68KMAKE_OP(add, 16, er, .)\r
1083{\r
1084 uint* r_dst = &DX;\r
1085 uint src = M68KMAKE_GET_OPER_AY_16;\r
1086 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
1087 uint res = src + dst;\r
1088\r
1089 FLAG_N = NFLAG_16(res);\r
1090 FLAG_V = VFLAG_ADD_16(src, dst, res);\r
1091 FLAG_X = FLAG_C = CFLAG_16(res);\r
1092 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
1093\r
1094 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
1095}\r
1096\r
1097\r
1098M68KMAKE_OP(add, 32, er, d)\r
1099{\r
1100 uint* r_dst = &DX;\r
1101 uint src = DY;\r
1102 uint dst = *r_dst;\r
1103 uint res = src + dst;\r
1104\r
1105 FLAG_N = NFLAG_32(res);\r
1106 FLAG_V = VFLAG_ADD_32(src, dst, res);\r
1107 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
1108 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
1109\r
1110 *r_dst = FLAG_Z;\r
1111}\r
1112\r
1113\r
1114M68KMAKE_OP(add, 32, er, a)\r
1115{\r
1116 uint* r_dst = &DX;\r
1117 uint src = AY;\r
1118 uint dst = *r_dst;\r
1119 uint res = src + dst;\r
1120\r
1121 FLAG_N = NFLAG_32(res);\r
1122 FLAG_V = VFLAG_ADD_32(src, dst, res);\r
1123 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
1124 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
1125\r
1126 *r_dst = FLAG_Z;\r
1127}\r
1128\r
1129\r
1130M68KMAKE_OP(add, 32, er, .)\r
1131{\r
1132 uint* r_dst = &DX;\r
1133 uint src = M68KMAKE_GET_OPER_AY_32;\r
1134 uint dst = *r_dst;\r
1135 uint res = src + dst;\r
1136\r
1137 FLAG_N = NFLAG_32(res);\r
1138 FLAG_V = VFLAG_ADD_32(src, dst, res);\r
1139 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
1140 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
1141\r
1142 *r_dst = FLAG_Z;\r
1143}\r
1144\r
1145\r
1146M68KMAKE_OP(add, 8, re, .)\r
1147{\r
1148 uint ea = M68KMAKE_GET_EA_AY_8;\r
1149 uint src = MASK_OUT_ABOVE_8(DX);\r
1150 uint dst = m68ki_read_8(ea);\r
1151 uint res = src + dst;\r
1152\r
1153 FLAG_N = NFLAG_8(res);\r
1154 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1155 FLAG_X = FLAG_C = CFLAG_8(res);\r
1156 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
1157\r
1158 m68ki_write_8(ea, FLAG_Z);\r
1159}\r
1160\r
1161\r
1162M68KMAKE_OP(add, 16, re, .)\r
1163{\r
1164 uint ea = M68KMAKE_GET_EA_AY_16;\r
1165 uint src = MASK_OUT_ABOVE_16(DX);\r
1166 uint dst = m68ki_read_16(ea);\r
1167 uint res = src + dst;\r
1168\r
1169 FLAG_N = NFLAG_16(res);\r
1170 FLAG_V = VFLAG_ADD_16(src, dst, res);\r
1171 FLAG_X = FLAG_C = CFLAG_16(res);\r
1172 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
1173\r
1174 m68ki_write_16(ea, FLAG_Z);\r
1175}\r
1176\r
1177\r
1178M68KMAKE_OP(add, 32, re, .)\r
1179{\r
1180 uint ea = M68KMAKE_GET_EA_AY_32;\r
1181 uint src = DX;\r
1182 uint dst = m68ki_read_32(ea);\r
1183 uint res = src + dst;\r
1184\r
1185 FLAG_N = NFLAG_32(res);\r
1186 FLAG_V = VFLAG_ADD_32(src, dst, res);\r
1187 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
1188 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
1189\r
1190 m68ki_write_32(ea, FLAG_Z);\r
1191}\r
1192\r
1193\r
1194M68KMAKE_OP(adda, 16, ., d)\r
1195{\r
1196 uint* r_dst = &AX;\r
1197\r
1198 *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(DY));\r
1199}\r
1200\r
1201\r
1202M68KMAKE_OP(adda, 16, ., a)\r
1203{\r
1204 uint* r_dst = &AX;\r
1205\r
1206 *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(AY));\r
1207}\r
1208\r
1209\r
1210M68KMAKE_OP(adda, 16, ., .)\r
1211{\r
1212 uint* r_dst = &AX;\r
1213\r
1214 *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(M68KMAKE_GET_OPER_AY_16));\r
1215}\r
1216\r
1217\r
1218M68KMAKE_OP(adda, 32, ., d)\r
1219{\r
1220 uint* r_dst = &AX;\r
1221\r
1222 *r_dst = MASK_OUT_ABOVE_32(*r_dst + DY);\r
1223}\r
1224\r
1225\r
1226M68KMAKE_OP(adda, 32, ., a)\r
1227{\r
1228 uint* r_dst = &AX;\r
1229\r
1230 *r_dst = MASK_OUT_ABOVE_32(*r_dst + AY);\r
1231}\r
1232\r
1233\r
1234M68KMAKE_OP(adda, 32, ., .)\r
1235{\r
1236 uint* r_dst = &AX;\r
1237\r
1238 *r_dst = MASK_OUT_ABOVE_32(*r_dst + M68KMAKE_GET_OPER_AY_32);\r
1239}\r
1240\r
1241\r
1242M68KMAKE_OP(addi, 8, ., d)\r
1243{\r
1244 uint* r_dst = &DY;\r
1245 uint src = OPER_I_8();\r
1246 uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
1247 uint res = src + dst;\r
1248\r
1249 FLAG_N = NFLAG_8(res);\r
1250 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1251 FLAG_X = FLAG_C = CFLAG_8(res);\r
1252 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
1253\r
1254 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;\r
1255}\r
1256\r
1257\r
1258M68KMAKE_OP(addi, 8, ., .)\r
1259{\r
1260 uint src = OPER_I_8();\r
1261 uint ea = M68KMAKE_GET_EA_AY_8;\r
1262 uint dst = m68ki_read_8(ea);\r
1263 uint res = src + dst;\r
1264\r
1265 FLAG_N = NFLAG_8(res);\r
1266 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1267 FLAG_X = FLAG_C = CFLAG_8(res);\r
1268 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
1269\r
1270 m68ki_write_8(ea, FLAG_Z);\r
1271}\r
1272\r
1273\r
1274M68KMAKE_OP(addi, 16, ., d)\r
1275{\r
1276 uint* r_dst = &DY;\r
1277 uint src = OPER_I_16();\r
1278 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
1279 uint res = src + dst;\r
1280\r
1281 FLAG_N = NFLAG_16(res);\r
1282 FLAG_V = VFLAG_ADD_16(src, dst, res);\r
1283 FLAG_X = FLAG_C = CFLAG_16(res);\r
1284 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
1285\r
1286 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
1287}\r
1288\r
1289\r
1290M68KMAKE_OP(addi, 16, ., .)\r
1291{\r
1292 uint src = OPER_I_16();\r
1293 uint ea = M68KMAKE_GET_EA_AY_16;\r
1294 uint dst = m68ki_read_16(ea);\r
1295 uint res = src + dst;\r
1296\r
1297 FLAG_N = NFLAG_16(res);\r
1298 FLAG_V = VFLAG_ADD_16(src, dst, res);\r
1299 FLAG_X = FLAG_C = CFLAG_16(res);\r
1300 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
1301\r
1302 m68ki_write_16(ea, FLAG_Z);\r
1303}\r
1304\r
1305\r
1306M68KMAKE_OP(addi, 32, ., d)\r
1307{\r
1308 uint* r_dst = &DY;\r
1309 uint src = OPER_I_32();\r
1310 uint dst = *r_dst;\r
1311 uint res = src + dst;\r
1312\r
1313 FLAG_N = NFLAG_32(res);\r
1314 FLAG_V = VFLAG_ADD_32(src, dst, res);\r
1315 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
1316 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
1317\r
1318 *r_dst = FLAG_Z;\r
1319}\r
1320\r
1321\r
1322M68KMAKE_OP(addi, 32, ., .)\r
1323{\r
1324 uint src = OPER_I_32();\r
1325 uint ea = M68KMAKE_GET_EA_AY_32;\r
1326 uint dst = m68ki_read_32(ea);\r
1327 uint res = src + dst;\r
1328\r
1329 FLAG_N = NFLAG_32(res);\r
1330 FLAG_V = VFLAG_ADD_32(src, dst, res);\r
1331 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
1332 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
1333\r
1334 m68ki_write_32(ea, FLAG_Z);\r
1335}\r
1336\r
1337\r
1338M68KMAKE_OP(addq, 8, ., d)\r
1339{\r
1340 uint* r_dst = &DY;\r
1341 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
1342 uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
1343 uint res = src + dst;\r
1344\r
1345 FLAG_N = NFLAG_8(res);\r
1346 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1347 FLAG_X = FLAG_C = CFLAG_8(res);\r
1348 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
1349\r
1350 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;\r
1351}\r
1352\r
1353\r
1354M68KMAKE_OP(addq, 8, ., .)\r
1355{\r
1356 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
1357 uint ea = M68KMAKE_GET_EA_AY_8;\r
1358 uint dst = m68ki_read_8(ea);\r
1359 uint res = src + dst;\r
1360\r
1361 FLAG_N = NFLAG_8(res);\r
1362 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1363 FLAG_X = FLAG_C = CFLAG_8(res);\r
1364 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
1365\r
1366 m68ki_write_8(ea, FLAG_Z);\r
1367}\r
1368\r
1369\r
1370M68KMAKE_OP(addq, 16, ., d)\r
1371{\r
1372 uint* r_dst = &DY;\r
1373 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
1374 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
1375 uint res = src + dst;\r
1376\r
1377 FLAG_N = NFLAG_16(res);\r
1378 FLAG_V = VFLAG_ADD_16(src, dst, res);\r
1379 FLAG_X = FLAG_C = CFLAG_16(res);\r
1380 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
1381\r
1382 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
1383}\r
1384\r
1385\r
1386M68KMAKE_OP(addq, 16, ., a)\r
1387{\r
1388 uint* r_dst = &AY;\r
1389\r
1390 *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1);\r
1391}\r
1392\r
1393\r
1394M68KMAKE_OP(addq, 16, ., .)\r
1395{\r
1396 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
1397 uint ea = M68KMAKE_GET_EA_AY_16;\r
1398 uint dst = m68ki_read_16(ea);\r
1399 uint res = src + dst;\r
1400\r
1401 FLAG_N = NFLAG_16(res);\r
1402 FLAG_V = VFLAG_ADD_16(src, dst, res);\r
1403 FLAG_X = FLAG_C = CFLAG_16(res);\r
1404 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
1405\r
1406 m68ki_write_16(ea, FLAG_Z);\r
1407}\r
1408\r
1409\r
1410M68KMAKE_OP(addq, 32, ., d)\r
1411{\r
1412 uint* r_dst = &DY;\r
1413 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
1414 uint dst = *r_dst;\r
1415 uint res = src + dst;\r
1416\r
1417 FLAG_N = NFLAG_32(res);\r
1418 FLAG_V = VFLAG_ADD_32(src, dst, res);\r
1419 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
1420 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
1421\r
1422 *r_dst = FLAG_Z;\r
1423}\r
1424\r
1425\r
1426M68KMAKE_OP(addq, 32, ., a)\r
1427{\r
1428 uint* r_dst = &AY;\r
1429\r
1430 *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1);\r
1431}\r
1432\r
1433\r
1434M68KMAKE_OP(addq, 32, ., .)\r
1435{\r
1436 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
1437 uint ea = M68KMAKE_GET_EA_AY_32;\r
1438 uint dst = m68ki_read_32(ea);\r
1439 uint res = src + dst;\r
1440\r
1441\r
1442 FLAG_N = NFLAG_32(res);\r
1443 FLAG_V = VFLAG_ADD_32(src, dst, res);\r
1444 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
1445 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
1446\r
1447 m68ki_write_32(ea, FLAG_Z);\r
1448}\r
1449\r
1450\r
1451M68KMAKE_OP(addx, 8, rr, .)\r
1452{\r
1453 uint* r_dst = &DX;\r
1454 uint src = MASK_OUT_ABOVE_8(DY);\r
1455 uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
1456 uint res = src + dst + XFLAG_AS_1();\r
1457\r
1458 FLAG_N = NFLAG_8(res);\r
1459 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1460 FLAG_X = FLAG_C = CFLAG_8(res);\r
1461\r
1462 res = MASK_OUT_ABOVE_8(res);\r
1463 FLAG_Z |= res;\r
1464\r
1465 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
1466}\r
1467\r
1468\r
1469M68KMAKE_OP(addx, 16, rr, .)\r
1470{\r
1471 uint* r_dst = &DX;\r
1472 uint src = MASK_OUT_ABOVE_16(DY);\r
1473 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
1474 uint res = src + dst + XFLAG_AS_1();\r
1475\r
1476 FLAG_N = NFLAG_16(res);\r
1477 FLAG_V = VFLAG_ADD_16(src, dst, res);\r
1478 FLAG_X = FLAG_C = CFLAG_16(res);\r
1479\r
1480 res = MASK_OUT_ABOVE_16(res);\r
1481 FLAG_Z |= res;\r
1482\r
1483 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
1484}\r
1485\r
1486\r
1487M68KMAKE_OP(addx, 32, rr, .)\r
1488{\r
1489 uint* r_dst = &DX;\r
1490 uint src = DY;\r
1491 uint dst = *r_dst;\r
1492 uint res = src + dst + XFLAG_AS_1();\r
1493\r
1494 FLAG_N = NFLAG_32(res);\r
1495 FLAG_V = VFLAG_ADD_32(src, dst, res);\r
1496 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
1497\r
1498 res = MASK_OUT_ABOVE_32(res);\r
1499 FLAG_Z |= res;\r
1500\r
1501 *r_dst = res;\r
1502}\r
1503\r
1504\r
1505M68KMAKE_OP(addx, 8, mm, ax7)\r
1506{\r
1507 uint src = OPER_AY_PD_8();\r
1508 uint ea = EA_A7_PD_8();\r
1509 uint dst = m68ki_read_8(ea);\r
1510 uint res = src + dst + XFLAG_AS_1();\r
1511\r
1512 FLAG_N = NFLAG_8(res);\r
1513 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1514 FLAG_X = FLAG_C = CFLAG_8(res);\r
1515\r
1516 res = MASK_OUT_ABOVE_8(res);\r
1517 FLAG_Z |= res;\r
1518\r
1519 m68ki_write_8(ea, res);\r
1520}\r
1521\r
1522\r
1523M68KMAKE_OP(addx, 8, mm, ay7)\r
1524{\r
1525 uint src = OPER_A7_PD_8();\r
1526 uint ea = EA_AX_PD_8();\r
1527 uint dst = m68ki_read_8(ea);\r
1528 uint res = src + dst + XFLAG_AS_1();\r
1529\r
1530 FLAG_N = NFLAG_8(res);\r
1531 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1532 FLAG_X = FLAG_C = CFLAG_8(res);\r
1533\r
1534 res = MASK_OUT_ABOVE_8(res);\r
1535 FLAG_Z |= res;\r
1536\r
1537 m68ki_write_8(ea, res);\r
1538}\r
1539\r
1540\r
1541M68KMAKE_OP(addx, 8, mm, axy7)\r
1542{\r
1543 uint src = OPER_A7_PD_8();\r
1544 uint ea = EA_A7_PD_8();\r
1545 uint dst = m68ki_read_8(ea);\r
1546 uint res = src + dst + XFLAG_AS_1();\r
1547\r
1548 FLAG_N = NFLAG_8(res);\r
1549 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1550 FLAG_X = FLAG_C = CFLAG_8(res);\r
1551\r
1552 res = MASK_OUT_ABOVE_8(res);\r
1553 FLAG_Z |= res;\r
1554\r
1555 m68ki_write_8(ea, res);\r
1556}\r
1557\r
1558\r
1559M68KMAKE_OP(addx, 8, mm, .)\r
1560{\r
1561 uint src = OPER_AY_PD_8();\r
1562 uint ea = EA_AX_PD_8();\r
1563 uint dst = m68ki_read_8(ea);\r
1564 uint res = src + dst + XFLAG_AS_1();\r
1565\r
1566 FLAG_N = NFLAG_8(res);\r
1567 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1568 FLAG_X = FLAG_C = CFLAG_8(res);\r
1569\r
1570 res = MASK_OUT_ABOVE_8(res);\r
1571 FLAG_Z |= res;\r
1572\r
1573 m68ki_write_8(ea, res);\r
1574}\r
1575\r
1576\r
1577M68KMAKE_OP(addx, 16, mm, .)\r
1578{\r
1579 uint src = OPER_AY_PD_16();\r
1580 uint ea = EA_AX_PD_16();\r
1581 uint dst = m68ki_read_16(ea);\r
1582 uint res = src + dst + XFLAG_AS_1();\r
1583\r
1584 FLAG_N = NFLAG_16(res);\r
1585 FLAG_V = VFLAG_ADD_16(src, dst, res);\r
1586 FLAG_X = FLAG_C = CFLAG_16(res);\r
1587\r
1588 res = MASK_OUT_ABOVE_16(res);\r
1589 FLAG_Z |= res;\r
1590\r
1591 m68ki_write_16(ea, res);\r
1592}\r
1593\r
1594\r
1595M68KMAKE_OP(addx, 32, mm, .)\r
1596{\r
1597 uint src = OPER_AY_PD_32();\r
1598 uint ea = EA_AX_PD_32();\r
1599 uint dst = m68ki_read_32(ea);\r
1600 uint res = src + dst + XFLAG_AS_1();\r
1601\r
1602 FLAG_N = NFLAG_32(res);\r
1603 FLAG_V = VFLAG_ADD_32(src, dst, res);\r
1604 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
1605\r
1606 res = MASK_OUT_ABOVE_32(res);\r
1607 FLAG_Z |= res;\r
1608\r
1609 m68ki_write_32(ea, res);\r
1610}\r
1611\r
1612\r
1613M68KMAKE_OP(and, 8, er, d)\r
1614{\r
1615 FLAG_Z = MASK_OUT_ABOVE_8(DX &= (DY | 0xffffff00));\r
1616\r
1617 FLAG_N = NFLAG_8(FLAG_Z);\r
1618 FLAG_C = CFLAG_CLEAR;\r
1619 FLAG_V = VFLAG_CLEAR;\r
1620}\r
1621\r
1622\r
1623M68KMAKE_OP(and, 8, er, .)\r
1624{\r
1625 FLAG_Z = MASK_OUT_ABOVE_8(DX &= (M68KMAKE_GET_OPER_AY_8 | 0xffffff00));\r
1626\r
1627 FLAG_N = NFLAG_8(FLAG_Z);\r
1628 FLAG_C = CFLAG_CLEAR;\r
1629 FLAG_V = VFLAG_CLEAR;\r
1630}\r
1631\r
1632\r
1633M68KMAKE_OP(and, 16, er, d)\r
1634{\r
1635 FLAG_Z = MASK_OUT_ABOVE_16(DX &= (DY | 0xffff0000));\r
1636\r
1637 FLAG_N = NFLAG_16(FLAG_Z);\r
1638 FLAG_C = CFLAG_CLEAR;\r
1639 FLAG_V = VFLAG_CLEAR;\r
1640}\r
1641\r
1642\r
1643M68KMAKE_OP(and, 16, er, .)\r
1644{\r
1645 FLAG_Z = MASK_OUT_ABOVE_16(DX &= (M68KMAKE_GET_OPER_AY_16 | 0xffff0000));\r
1646\r
1647 FLAG_N = NFLAG_16(FLAG_Z);\r
1648 FLAG_C = CFLAG_CLEAR;\r
1649 FLAG_V = VFLAG_CLEAR;\r
1650}\r
1651\r
1652\r
1653M68KMAKE_OP(and, 32, er, d)\r
1654{\r
1655 FLAG_Z = DX &= DY;\r
1656\r
1657 FLAG_N = NFLAG_32(FLAG_Z);\r
1658 FLAG_C = CFLAG_CLEAR;\r
1659 FLAG_V = VFLAG_CLEAR;\r
1660}\r
1661\r
1662\r
1663M68KMAKE_OP(and, 32, er, .)\r
1664{\r
1665 FLAG_Z = DX &= M68KMAKE_GET_OPER_AY_32;\r
1666\r
1667 FLAG_N = NFLAG_32(FLAG_Z);\r
1668 FLAG_C = CFLAG_CLEAR;\r
1669 FLAG_V = VFLAG_CLEAR;\r
1670}\r
1671\r
1672\r
1673M68KMAKE_OP(and, 8, re, .)\r
1674{\r
1675 uint ea = M68KMAKE_GET_EA_AY_8;\r
1676 uint res = DX & m68ki_read_8(ea);\r
1677\r
1678 FLAG_N = NFLAG_8(res);\r
1679 FLAG_C = CFLAG_CLEAR;\r
1680 FLAG_V = VFLAG_CLEAR;\r
1681 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
1682\r
1683 m68ki_write_8(ea, FLAG_Z);\r
1684}\r
1685\r
1686\r
1687M68KMAKE_OP(and, 16, re, .)\r
1688{\r
1689 uint ea = M68KMAKE_GET_EA_AY_16;\r
1690 uint res = DX & m68ki_read_16(ea);\r
1691\r
1692 FLAG_N = NFLAG_16(res);\r
1693 FLAG_C = CFLAG_CLEAR;\r
1694 FLAG_V = VFLAG_CLEAR;\r
1695 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
1696\r
1697 m68ki_write_16(ea, FLAG_Z);\r
1698}\r
1699\r
1700\r
1701M68KMAKE_OP(and, 32, re, .)\r
1702{\r
1703 uint ea = M68KMAKE_GET_EA_AY_32;\r
1704 uint res = DX & m68ki_read_32(ea);\r
1705\r
1706 FLAG_N = NFLAG_32(res);\r
1707 FLAG_Z = res;\r
1708 FLAG_C = CFLAG_CLEAR;\r
1709 FLAG_V = VFLAG_CLEAR;\r
1710\r
1711 m68ki_write_32(ea, res);\r
1712}\r
1713\r
1714\r
1715M68KMAKE_OP(andi, 8, ., d)\r
1716{\r
1717 FLAG_Z = MASK_OUT_ABOVE_8(DY &= (OPER_I_8() | 0xffffff00));\r
1718\r
1719 FLAG_N = NFLAG_8(FLAG_Z);\r
1720 FLAG_C = CFLAG_CLEAR;\r
1721 FLAG_V = VFLAG_CLEAR;\r
1722}\r
1723\r
1724\r
1725M68KMAKE_OP(andi, 8, ., .)\r
1726{\r
1727 uint src = OPER_I_8();\r
1728 uint ea = M68KMAKE_GET_EA_AY_8;\r
1729 uint res = src & m68ki_read_8(ea);\r
1730\r
1731 FLAG_N = NFLAG_8(res);\r
1732 FLAG_Z = res;\r
1733 FLAG_C = CFLAG_CLEAR;\r
1734 FLAG_V = VFLAG_CLEAR;\r
1735\r
1736 m68ki_write_8(ea, res);\r
1737}\r
1738\r
1739\r
1740M68KMAKE_OP(andi, 16, ., d)\r
1741{\r
1742 FLAG_Z = MASK_OUT_ABOVE_16(DY &= (OPER_I_16() | 0xffff0000));\r
1743\r
1744 FLAG_N = NFLAG_16(FLAG_Z);\r
1745 FLAG_C = CFLAG_CLEAR;\r
1746 FLAG_V = VFLAG_CLEAR;\r
1747}\r
1748\r
1749\r
1750M68KMAKE_OP(andi, 16, ., .)\r
1751{\r
1752 uint src = OPER_I_16();\r
1753 uint ea = M68KMAKE_GET_EA_AY_16;\r
1754 uint res = src & m68ki_read_16(ea);\r
1755\r
1756 FLAG_N = NFLAG_16(res);\r
1757 FLAG_Z = res;\r
1758 FLAG_C = CFLAG_CLEAR;\r
1759 FLAG_V = VFLAG_CLEAR;\r
1760\r
1761 m68ki_write_16(ea, res);\r
1762}\r
1763\r
1764\r
1765M68KMAKE_OP(andi, 32, ., d)\r
1766{\r
1767 FLAG_Z = DY &= (OPER_I_32());\r
1768\r
1769 FLAG_N = NFLAG_32(FLAG_Z);\r
1770 FLAG_C = CFLAG_CLEAR;\r
1771 FLAG_V = VFLAG_CLEAR;\r
1772}\r
1773\r
1774\r
1775M68KMAKE_OP(andi, 32, ., .)\r
1776{\r
1777 uint src = OPER_I_32();\r
1778 uint ea = M68KMAKE_GET_EA_AY_32;\r
1779 uint res = src & m68ki_read_32(ea);\r
1780\r
1781 FLAG_N = NFLAG_32(res);\r
1782 FLAG_Z = res;\r
1783 FLAG_C = CFLAG_CLEAR;\r
1784 FLAG_V = VFLAG_CLEAR;\r
1785\r
1786 m68ki_write_32(ea, res);\r
1787}\r
1788\r
1789\r
1790M68KMAKE_OP(andi, 16, toc, .)\r
1791{\r
1792 m68ki_set_ccr(m68ki_get_ccr() & OPER_I_16());\r
1793}\r
1794\r
1795\r
1796M68KMAKE_OP(andi, 16, tos, .)\r
1797{\r
1798 if(FLAG_S)\r
1799 {\r
1800 uint src = OPER_I_16();\r
1801 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
1802 m68ki_set_sr(m68ki_get_sr() & src);\r
1803 return;\r
1804 }\r
1805 m68ki_exception_privilege_violation();\r
1806}\r
1807\r
1808\r
1809M68KMAKE_OP(asr, 8, s, .)\r
1810{\r
1811 uint* r_dst = &DY;\r
1812 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
1813 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
1814 uint res = src >> shift;\r
1815\r
1816 if(shift != 0)\r
1817 USE_CYCLES(shift<<CYC_SHIFT);\r
1818\r
1819 if(GET_MSB_8(src))\r
1820 res |= m68ki_shift_8_table[shift];\r
1821\r
1822 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
1823\r
1824 FLAG_N = NFLAG_8(res);\r
1825 FLAG_Z = res;\r
1826 FLAG_V = VFLAG_CLEAR;\r
1827 FLAG_X = FLAG_C = src << (9-shift);\r
1828}\r
1829\r
1830\r
1831M68KMAKE_OP(asr, 16, s, .)\r
1832{\r
1833 uint* r_dst = &DY;\r
1834 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
1835 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
1836 uint res = src >> shift;\r
1837\r
1838 if(shift != 0)\r
1839 USE_CYCLES(shift<<CYC_SHIFT);\r
1840\r
1841 if(GET_MSB_16(src))\r
1842 res |= m68ki_shift_16_table[shift];\r
1843\r
1844 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
1845\r
1846 FLAG_N = NFLAG_16(res);\r
1847 FLAG_Z = res;\r
1848 FLAG_V = VFLAG_CLEAR;\r
1849 FLAG_X = FLAG_C = src << (9-shift);\r
1850}\r
1851\r
1852\r
1853M68KMAKE_OP(asr, 32, s, .)\r
1854{\r
1855 uint* r_dst = &DY;\r
1856 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
1857 uint src = *r_dst;\r
1858 uint res = src >> shift;\r
1859\r
1860 if(shift != 0)\r
1861 USE_CYCLES(shift<<CYC_SHIFT);\r
1862\r
1863 if(GET_MSB_32(src))\r
1864 res |= m68ki_shift_32_table[shift];\r
1865\r
1866 *r_dst = res;\r
1867\r
1868 FLAG_N = NFLAG_32(res);\r
1869 FLAG_Z = res;\r
1870 FLAG_V = VFLAG_CLEAR;\r
1871 FLAG_X = FLAG_C = src << (9-shift);\r
1872}\r
1873\r
1874\r
1875M68KMAKE_OP(asr, 8, r, .)\r
1876{\r
1877 uint* r_dst = &DY;\r
1878 uint shift = DX & 0x3f;\r
1879 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
1880 uint res = src >> shift;\r
1881\r
1882 if(shift != 0)\r
1883 {\r
1884 USE_CYCLES(shift<<CYC_SHIFT);\r
1885\r
1886 if(shift < 8)\r
1887 {\r
1888 if(GET_MSB_8(src))\r
1889 res |= m68ki_shift_8_table[shift];\r
1890\r
1891 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
1892\r
1893 FLAG_X = FLAG_C = src << (9-shift);\r
1894 FLAG_N = NFLAG_8(res);\r
1895 FLAG_Z = res;\r
1896 FLAG_V = VFLAG_CLEAR;\r
1897 return;\r
1898 }\r
1899\r
1900 if(GET_MSB_8(src))\r
1901 {\r
1902 *r_dst |= 0xff;\r
1903 FLAG_C = CFLAG_SET;\r
1904 FLAG_X = XFLAG_SET;\r
1905 FLAG_N = NFLAG_SET;\r
1906 FLAG_Z = ZFLAG_CLEAR;\r
1907 FLAG_V = VFLAG_CLEAR;\r
1908 return;\r
1909 }\r
1910\r
1911 *r_dst &= 0xffffff00;\r
1912 FLAG_C = CFLAG_CLEAR;\r
1913 FLAG_X = XFLAG_CLEAR;\r
1914 FLAG_N = NFLAG_CLEAR;\r
1915 FLAG_Z = ZFLAG_SET;\r
1916 FLAG_V = VFLAG_CLEAR;\r
1917 return;\r
1918 }\r
1919\r
1920 FLAG_C = CFLAG_CLEAR;\r
1921 FLAG_N = NFLAG_8(src);\r
1922 FLAG_Z = src;\r
1923 FLAG_V = VFLAG_CLEAR;\r
1924}\r
1925\r
1926\r
1927M68KMAKE_OP(asr, 16, r, .)\r
1928{\r
1929 uint* r_dst = &DY;\r
1930 uint shift = DX & 0x3f;\r
1931 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
1932 uint res = src >> shift;\r
1933\r
1934 if(shift != 0)\r
1935 {\r
1936 USE_CYCLES(shift<<CYC_SHIFT);\r
1937\r
1938 if(shift < 16)\r
1939 {\r
1940 if(GET_MSB_16(src))\r
1941 res |= m68ki_shift_16_table[shift];\r
1942\r
1943 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
1944\r
1945 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;\r
1946 FLAG_N = NFLAG_16(res);\r
1947 FLAG_Z = res;\r
1948 FLAG_V = VFLAG_CLEAR;\r
1949 return;\r
1950 }\r
1951\r
1952 if(GET_MSB_16(src))\r
1953 {\r
1954 *r_dst |= 0xffff;\r
1955 FLAG_C = CFLAG_SET;\r
1956 FLAG_X = XFLAG_SET;\r
1957 FLAG_N = NFLAG_SET;\r
1958 FLAG_Z = ZFLAG_CLEAR;\r
1959 FLAG_V = VFLAG_CLEAR;\r
1960 return;\r
1961 }\r
1962\r
1963 *r_dst &= 0xffff0000;\r
1964 FLAG_C = CFLAG_CLEAR;\r
1965 FLAG_X = XFLAG_CLEAR;\r
1966 FLAG_N = NFLAG_CLEAR;\r
1967 FLAG_Z = ZFLAG_SET;\r
1968 FLAG_V = VFLAG_CLEAR;\r
1969 return;\r
1970 }\r
1971\r
1972 FLAG_C = CFLAG_CLEAR;\r
1973 FLAG_N = NFLAG_16(src);\r
1974 FLAG_Z = src;\r
1975 FLAG_V = VFLAG_CLEAR;\r
1976}\r
1977\r
1978\r
1979M68KMAKE_OP(asr, 32, r, .)\r
1980{\r
1981 uint* r_dst = &DY;\r
1982 uint shift = DX & 0x3f;\r
1983 uint src = *r_dst;\r
1984 uint res = src >> shift;\r
1985\r
1986 if(shift != 0)\r
1987 {\r
1988 USE_CYCLES(shift<<CYC_SHIFT);\r
1989\r
1990 if(shift < 32)\r
1991 {\r
1992 if(GET_MSB_32(src))\r
1993 res |= m68ki_shift_32_table[shift];\r
1994\r
1995 *r_dst = res;\r
1996\r
1997 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;\r
1998 FLAG_N = NFLAG_32(res);\r
1999 FLAG_Z = res;\r
2000 FLAG_V = VFLAG_CLEAR;\r
2001 return;\r
2002 }\r
2003\r
2004 if(GET_MSB_32(src))\r
2005 {\r
2006 *r_dst = 0xffffffff;\r
2007 FLAG_C = CFLAG_SET;\r
2008 FLAG_X = XFLAG_SET;\r
2009 FLAG_N = NFLAG_SET;\r
2010 FLAG_Z = ZFLAG_CLEAR;\r
2011 FLAG_V = VFLAG_CLEAR;\r
2012 return;\r
2013 }\r
2014\r
2015 *r_dst = 0;\r
2016 FLAG_C = CFLAG_CLEAR;\r
2017 FLAG_X = XFLAG_CLEAR;\r
2018 FLAG_N = NFLAG_CLEAR;\r
2019 FLAG_Z = ZFLAG_SET;\r
2020 FLAG_V = VFLAG_CLEAR;\r
2021 return;\r
2022 }\r
2023\r
2024 FLAG_C = CFLAG_CLEAR;\r
2025 FLAG_N = NFLAG_32(src);\r
2026 FLAG_Z = src;\r
2027 FLAG_V = VFLAG_CLEAR;\r
2028}\r
2029\r
2030\r
2031M68KMAKE_OP(asr, 16, ., .)\r
2032{\r
2033 uint ea = M68KMAKE_GET_EA_AY_16;\r
2034 uint src = m68ki_read_16(ea);\r
2035 uint res = src >> 1;\r
2036\r
2037 if(GET_MSB_16(src))\r
2038 res |= 0x8000;\r
2039\r
2040 m68ki_write_16(ea, res);\r
2041\r
2042 FLAG_N = NFLAG_16(res);\r
2043 FLAG_Z = res;\r
2044 FLAG_V = VFLAG_CLEAR;\r
2045 FLAG_C = FLAG_X = src << 8;\r
2046}\r
2047\r
2048\r
2049M68KMAKE_OP(asl, 8, s, .)\r
2050{\r
2051 uint* r_dst = &DY;\r
2052 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
2053 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
2054 uint res = MASK_OUT_ABOVE_8(src << shift);\r
2055\r
2056 if(shift != 0)\r
2057 USE_CYCLES(shift<<CYC_SHIFT);\r
2058\r
2059 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
2060\r
2061 FLAG_X = FLAG_C = src << shift;\r
2062 FLAG_N = NFLAG_8(res);\r
2063 FLAG_Z = res;\r
2064 src &= m68ki_shift_8_table[shift + 1];\r
2065 FLAG_V = (!(src == 0 || (src == m68ki_shift_8_table[shift + 1] && shift < 8)))<<7;\r
2066}\r
2067\r
2068\r
2069M68KMAKE_OP(asl, 16, s, .)\r
2070{\r
2071 uint* r_dst = &DY;\r
2072 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
2073 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
2074 uint res = MASK_OUT_ABOVE_16(src << shift);\r
2075\r
2076 if(shift != 0)\r
2077 USE_CYCLES(shift<<CYC_SHIFT);\r
2078\r
2079 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
2080\r
2081 FLAG_N = NFLAG_16(res);\r
2082 FLAG_Z = res;\r
2083 FLAG_X = FLAG_C = src >> (8-shift);\r
2084 src &= m68ki_shift_16_table[shift + 1];\r
2085 FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7;\r
2086}\r
2087\r
2088\r
2089M68KMAKE_OP(asl, 32, s, .)\r
2090{\r
2091 uint* r_dst = &DY;\r
2092 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
2093 uint src = *r_dst;\r
2094 uint res = MASK_OUT_ABOVE_32(src << shift);\r
2095\r
2096 if(shift != 0)\r
2097 USE_CYCLES(shift<<CYC_SHIFT);\r
2098\r
2099 *r_dst = res;\r
2100\r
2101 FLAG_N = NFLAG_32(res);\r
2102 FLAG_Z = res;\r
2103 FLAG_X = FLAG_C = src >> (24-shift);\r
2104 src &= m68ki_shift_32_table[shift + 1];\r
2105 FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7;\r
2106}\r
2107\r
2108\r
2109M68KMAKE_OP(asl, 8, r, .)\r
2110{\r
2111 uint* r_dst = &DY;\r
2112 uint shift = DX & 0x3f;\r
2113 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
2114 uint res = MASK_OUT_ABOVE_8(src << shift);\r
2115\r
2116 if(shift != 0)\r
2117 {\r
2118 USE_CYCLES(shift<<CYC_SHIFT);\r
2119\r
2120 if(shift < 8)\r
2121 {\r
2122 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
2123 FLAG_X = FLAG_C = src << shift;\r
2124 FLAG_N = NFLAG_8(res);\r
2125 FLAG_Z = res;\r
2126 src &= m68ki_shift_8_table[shift + 1];\r
2127 FLAG_V = (!(src == 0 || src == m68ki_shift_8_table[shift + 1]))<<7;\r
2128 return;\r
2129 }\r
2130\r
2131 *r_dst &= 0xffffff00;\r
2132 FLAG_X = FLAG_C = ((shift == 8 ? src & 1 : 0))<<8;\r
2133 FLAG_N = NFLAG_CLEAR;\r
2134 FLAG_Z = ZFLAG_SET;\r
2135 FLAG_V = (!(src == 0))<<7;\r
2136 return;\r
2137 }\r
2138\r
2139 FLAG_C = CFLAG_CLEAR;\r
2140 FLAG_N = NFLAG_8(src);\r
2141 FLAG_Z = src;\r
2142 FLAG_V = VFLAG_CLEAR;\r
2143}\r
2144\r
2145\r
2146M68KMAKE_OP(asl, 16, r, .)\r
2147{\r
2148 uint* r_dst = &DY;\r
2149 uint shift = DX & 0x3f;\r
2150 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
2151 uint res = MASK_OUT_ABOVE_16(src << shift);\r
2152\r
2153 if(shift != 0)\r
2154 {\r
2155 USE_CYCLES(shift<<CYC_SHIFT);\r
2156\r
2157 if(shift < 16)\r
2158 {\r
2159 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
2160 FLAG_X = FLAG_C = (src << shift) >> 8;\r
2161 FLAG_N = NFLAG_16(res);\r
2162 FLAG_Z = res;\r
2163 src &= m68ki_shift_16_table[shift + 1];\r
2164 FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7;\r
2165 return;\r
2166 }\r
2167\r
2168 *r_dst &= 0xffff0000;\r
2169 FLAG_X = FLAG_C = ((shift == 16 ? src & 1 : 0))<<8;\r
2170 FLAG_N = NFLAG_CLEAR;\r
2171 FLAG_Z = ZFLAG_SET;\r
2172 FLAG_V = (!(src == 0))<<7;\r
2173 return;\r
2174 }\r
2175\r
2176 FLAG_C = CFLAG_CLEAR;\r
2177 FLAG_N = NFLAG_16(src);\r
2178 FLAG_Z = src;\r
2179 FLAG_V = VFLAG_CLEAR;\r
2180}\r
2181\r
2182\r
2183M68KMAKE_OP(asl, 32, r, .)\r
2184{\r
2185 uint* r_dst = &DY;\r
2186 uint shift = DX & 0x3f;\r
2187 uint src = *r_dst;\r
2188 uint res = MASK_OUT_ABOVE_32(src << shift);\r
2189\r
2190 if(shift != 0)\r
2191 {\r
2192 USE_CYCLES(shift<<CYC_SHIFT);\r
2193\r
2194 if(shift < 32)\r
2195 {\r
2196 *r_dst = res;\r
2197 FLAG_X = FLAG_C = (src >> (32 - shift)) << 8;\r
2198 FLAG_N = NFLAG_32(res);\r
2199 FLAG_Z = res;\r
2200 src &= m68ki_shift_32_table[shift + 1];\r
2201 FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7;\r
2202 return;\r
2203 }\r
2204\r
2205 *r_dst = 0;\r
2206 FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8;\r
2207 FLAG_N = NFLAG_CLEAR;\r
2208 FLAG_Z = ZFLAG_SET;\r
2209 FLAG_V = (!(src == 0))<<7;\r
2210 return;\r
2211 }\r
2212\r
2213 FLAG_C = CFLAG_CLEAR;\r
2214 FLAG_N = NFLAG_32(src);\r
2215 FLAG_Z = src;\r
2216 FLAG_V = VFLAG_CLEAR;\r
2217}\r
2218\r
2219\r
2220M68KMAKE_OP(asl, 16, ., .)\r
2221{\r
2222 uint ea = M68KMAKE_GET_EA_AY_16;\r
2223 uint src = m68ki_read_16(ea);\r
2224 uint res = MASK_OUT_ABOVE_16(src << 1);\r
2225\r
2226 m68ki_write_16(ea, res);\r
2227\r
2228 FLAG_N = NFLAG_16(res);\r
2229 FLAG_Z = res;\r
2230 FLAG_X = FLAG_C = src >> 7;\r
2231 src &= 0xc000;\r
2232 FLAG_V = (!(src == 0 || src == 0xc000))<<7;\r
2233}\r
2234\r
2235\r
2236M68KMAKE_OP(bcc, 8, ., .)\r
2237{\r
2238 if(M68KMAKE_CC)\r
2239 {\r
2240 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
2241 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));\r
2242 return;\r
2243 }\r
2244 USE_CYCLES(CYC_BCC_NOTAKE_B);\r
2245}\r
2246\r
2247\r
2248M68KMAKE_OP(bcc, 16, ., .)\r
2249{\r
2250 if(M68KMAKE_CC)\r
2251 {\r
2252 uint offset = OPER_I_16();\r
2253 REG_PC -= 2;\r
2254 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
2255 m68ki_branch_16(offset);\r
2256 return;\r
2257 }\r
2258 REG_PC += 2;\r
2259 USE_CYCLES(CYC_BCC_NOTAKE_W);\r
2260}\r
2261\r
2262\r
2263M68KMAKE_OP(bcc, 32, ., .)\r
2264{\r
2265 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2266 {\r
2267 if(M68KMAKE_CC)\r
2268 {\r
2269 uint offset = OPER_I_32();\r
2270 REG_PC -= 4;\r
2271 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
2272 m68ki_branch_32(offset);\r
2273 return;\r
2274 }\r
2275 REG_PC += 4;\r
2276 return;\r
2277 }\r
2278 else\r
2279 {\r
2280 if(M68KMAKE_CC)\r
2281 {\r
2282 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
2283 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));\r
2284 return;\r
2285 }\r
2286 USE_CYCLES(CYC_BCC_NOTAKE_B);\r
2287 }\r
2288}\r
2289\r
2290\r
2291M68KMAKE_OP(bchg, 32, r, d)\r
2292{\r
2293 uint* r_dst = &DY;\r
2294 uint mask = 1 << (DX & 0x1f);\r
2295\r
2296 FLAG_Z = *r_dst & mask;\r
2297 *r_dst ^= mask;\r
2298}\r
2299\r
2300\r
2301M68KMAKE_OP(bchg, 8, r, .)\r
2302{\r
2303 uint ea = M68KMAKE_GET_EA_AY_8;\r
2304 uint src = m68ki_read_8(ea);\r
2305 uint mask = 1 << (DX & 7);\r
2306\r
2307 FLAG_Z = src & mask;\r
2308 m68ki_write_8(ea, src ^ mask);\r
2309}\r
2310\r
2311\r
2312M68KMAKE_OP(bchg, 32, s, d)\r
2313{\r
2314 uint* r_dst = &DY;\r
2315 uint mask = 1 << (OPER_I_8() & 0x1f);\r
2316\r
2317 FLAG_Z = *r_dst & mask;\r
2318 *r_dst ^= mask;\r
2319}\r
2320\r
2321\r
2322M68KMAKE_OP(bchg, 8, s, .)\r
2323{\r
2324 uint mask = 1 << (OPER_I_8() & 7);\r
2325 uint ea = M68KMAKE_GET_EA_AY_8;\r
2326 uint src = m68ki_read_8(ea);\r
2327\r
2328 FLAG_Z = src & mask;\r
2329 m68ki_write_8(ea, src ^ mask);\r
2330}\r
2331\r
2332\r
2333M68KMAKE_OP(bclr, 32, r, d)\r
2334{\r
2335 uint* r_dst = &DY;\r
2336 uint mask = 1 << (DX & 0x1f);\r
2337\r
2338 FLAG_Z = *r_dst & mask;\r
2339 *r_dst &= ~mask;\r
2340}\r
2341\r
2342\r
2343M68KMAKE_OP(bclr, 8, r, .)\r
2344{\r
2345 uint ea = M68KMAKE_GET_EA_AY_8;\r
2346 uint src = m68ki_read_8(ea);\r
2347 uint mask = 1 << (DX & 7);\r
2348\r
2349 FLAG_Z = src & mask;\r
2350 m68ki_write_8(ea, src & ~mask);\r
2351}\r
2352\r
2353\r
2354M68KMAKE_OP(bclr, 32, s, d)\r
2355{\r
2356 uint* r_dst = &DY;\r
2357 uint mask = 1 << (OPER_I_8() & 0x1f);\r
2358\r
2359 FLAG_Z = *r_dst & mask;\r
2360 *r_dst &= ~mask;\r
2361}\r
2362\r
2363\r
2364M68KMAKE_OP(bclr, 8, s, .)\r
2365{\r
2366 uint mask = 1 << (OPER_I_8() & 7);\r
2367 uint ea = M68KMAKE_GET_EA_AY_8;\r
2368 uint src = m68ki_read_8(ea);\r
2369\r
2370 FLAG_Z = src & mask;\r
2371 m68ki_write_8(ea, src & ~mask);\r
2372}\r
2373\r
2374\r
2375M68KMAKE_OP(bfchg, 32, ., d)\r
2376{\r
2377 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2378 {\r
2379 uint word2 = OPER_I_16();\r
2380 uint offset = (word2>>6)&31;\r
2381 uint width = word2;\r
2382 uint* data = &DY;\r
2383 uint64 mask;\r
2384\r
2385\r
2386 if(BIT_B(word2))\r
2387 offset = REG_D[offset&7];\r
2388 if(BIT_5(word2))\r
2389 width = REG_D[width&7];\r
2390\r
2391 offset &= 31;\r
2392 width = ((width-1) & 31) + 1;\r
2393\r
2394 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
2395 mask = ROR_32(mask, offset);\r
2396\r
2397 FLAG_N = NFLAG_32(*data<<offset);\r
2398 FLAG_Z = *data & mask;\r
2399 FLAG_V = VFLAG_CLEAR;\r
2400 FLAG_C = CFLAG_CLEAR;\r
2401\r
2402 *data ^= mask;\r
2403\r
2404 return;\r
2405 }\r
2406 m68ki_exception_illegal();\r
2407}\r
2408\r
2409\r
2410M68KMAKE_OP(bfchg, 32, ., .)\r
2411{\r
2412 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2413 {\r
2414 uint word2 = OPER_I_16();\r
2415 sint offset = (word2>>6)&31;\r
2416 uint width = word2;\r
2417 uint mask_base;\r
2418 uint data_long;\r
2419 uint mask_long;\r
2420 uint data_byte = 0;\r
2421 uint mask_byte = 0;\r
2422 uint ea = M68KMAKE_GET_EA_AY_8;\r
2423\r
2424\r
2425 if(BIT_B(word2))\r
2426 offset = MAKE_INT_32(REG_D[offset&7]);\r
2427 if(BIT_5(word2))\r
2428 width = REG_D[width&7];\r
2429\r
2430 /* Offset is signed so we have to use ugly math =( */\r
2431 ea += offset / 8;\r
2432 offset %= 8;\r
2433 if(offset < 0)\r
2434 {\r
2435 offset += 8;\r
2436 ea--;\r
2437 }\r
2438 width = ((width-1) & 31) + 1;\r
2439\r
2440 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
2441 mask_long = mask_base >> offset;\r
2442\r
2443 data_long = m68ki_read_32(ea);\r
2444 FLAG_N = NFLAG_32(data_long << offset);\r
2445 FLAG_Z = data_long & mask_long;\r
2446 FLAG_V = VFLAG_CLEAR;\r
2447 FLAG_C = CFLAG_CLEAR;\r
2448\r
2449 m68ki_write_32(ea, data_long ^ mask_long);\r
2450\r
2451 if((width + offset) > 32)\r
2452 {\r
2453 mask_byte = MASK_OUT_ABOVE_8(mask_base);\r
2454 data_byte = m68ki_read_8(ea+4);\r
2455 FLAG_Z |= (data_byte & mask_byte);\r
2456 m68ki_write_8(ea+4, data_byte ^ mask_byte);\r
2457 }\r
2458 return;\r
2459 }\r
2460 m68ki_exception_illegal();\r
2461}\r
2462\r
2463\r
2464M68KMAKE_OP(bfclr, 32, ., d)\r
2465{\r
2466 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2467 {\r
2468 uint word2 = OPER_I_16();\r
2469 uint offset = (word2>>6)&31;\r
2470 uint width = word2;\r
2471 uint* data = &DY;\r
2472 uint64 mask;\r
2473\r
2474\r
2475 if(BIT_B(word2))\r
2476 offset = REG_D[offset&7];\r
2477 if(BIT_5(word2))\r
2478 width = REG_D[width&7];\r
2479\r
2480\r
2481 offset &= 31;\r
2482 width = ((width-1) & 31) + 1;\r
2483\r
2484\r
2485 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
2486 mask = ROR_32(mask, offset);\r
2487\r
2488 FLAG_N = NFLAG_32(*data<<offset);\r
2489 FLAG_Z = *data & mask;\r
2490 FLAG_V = VFLAG_CLEAR;\r
2491 FLAG_C = CFLAG_CLEAR;\r
2492\r
2493 *data &= ~mask;\r
2494\r
2495 return;\r
2496 }\r
2497 m68ki_exception_illegal();\r
2498}\r
2499\r
2500\r
2501M68KMAKE_OP(bfclr, 32, ., .)\r
2502{\r
2503 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2504 {\r
2505 uint word2 = OPER_I_16();\r
2506 sint offset = (word2>>6)&31;\r
2507 uint width = word2;\r
2508 uint mask_base;\r
2509 uint data_long;\r
2510 uint mask_long;\r
2511 uint data_byte = 0;\r
2512 uint mask_byte = 0;\r
2513 uint ea = M68KMAKE_GET_EA_AY_8;\r
2514\r
2515\r
2516 if(BIT_B(word2))\r
2517 offset = MAKE_INT_32(REG_D[offset&7]);\r
2518 if(BIT_5(word2))\r
2519 width = REG_D[width&7];\r
2520\r
2521 /* Offset is signed so we have to use ugly math =( */\r
2522 ea += offset / 8;\r
2523 offset %= 8;\r
2524 if(offset < 0)\r
2525 {\r
2526 offset += 8;\r
2527 ea--;\r
2528 }\r
2529 width = ((width-1) & 31) + 1;\r
2530\r
2531 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
2532 mask_long = mask_base >> offset;\r
2533\r
2534 data_long = m68ki_read_32(ea);\r
2535 FLAG_N = NFLAG_32(data_long << offset);\r
2536 FLAG_Z = data_long & mask_long;\r
2537 FLAG_V = VFLAG_CLEAR;\r
2538 FLAG_C = CFLAG_CLEAR;\r
2539\r
2540 m68ki_write_32(ea, data_long & ~mask_long);\r
2541\r
2542 if((width + offset) > 32)\r
2543 {\r
2544 mask_byte = MASK_OUT_ABOVE_8(mask_base);\r
2545 data_byte = m68ki_read_8(ea+4);\r
2546 FLAG_Z |= (data_byte & mask_byte);\r
2547 m68ki_write_8(ea+4, data_byte & ~mask_byte);\r
2548 }\r
2549 return;\r
2550 }\r
2551 m68ki_exception_illegal();\r
2552}\r
2553\r
2554\r
2555M68KMAKE_OP(bfexts, 32, ., d)\r
2556{\r
2557 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2558 {\r
2559 uint word2 = OPER_I_16();\r
2560 uint offset = (word2>>6)&31;\r
2561 uint width = word2;\r
2562 uint64 data = DY;\r
2563\r
2564\r
2565 if(BIT_B(word2))\r
2566 offset = REG_D[offset&7];\r
2567 if(BIT_5(word2))\r
2568 width = REG_D[width&7];\r
2569\r
2570 offset &= 31;\r
2571 width = ((width-1) & 31) + 1;\r
2572\r
2573 data = ROL_32(data, offset);\r
2574 FLAG_N = NFLAG_32(data);\r
2575 data = MAKE_INT_32(data) >> (32 - width);\r
2576\r
2577 FLAG_Z = data;\r
2578 FLAG_V = VFLAG_CLEAR;\r
2579 FLAG_C = CFLAG_CLEAR;\r
2580\r
2581 REG_D[(word2>>12)&7] = data;\r
2582\r
2583 return;\r
2584 }\r
2585 m68ki_exception_illegal();\r
2586}\r
2587\r
2588\r
2589M68KMAKE_OP(bfexts, 32, ., .)\r
2590{\r
2591 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2592 {\r
2593 uint word2 = OPER_I_16();\r
2594 sint offset = (word2>>6)&31;\r
2595 uint width = word2;\r
2596 uint data;\r
2597 uint ea = M68KMAKE_GET_EA_AY_8;\r
2598\r
2599\r
2600 if(BIT_B(word2))\r
2601 offset = MAKE_INT_32(REG_D[offset&7]);\r
2602 if(BIT_5(word2))\r
2603 width = REG_D[width&7];\r
2604\r
2605 /* Offset is signed so we have to use ugly math =( */\r
2606 ea += offset / 8;\r
2607 offset %= 8;\r
2608 if(offset < 0)\r
2609 {\r
2610 offset += 8;\r
2611 ea--;\r
2612 }\r
2613 width = ((width-1) & 31) + 1;\r
2614\r
2615 data = m68ki_read_32(ea);\r
2616\r
2617 data = MASK_OUT_ABOVE_32(data<<offset);\r
2618\r
2619 if((offset+width) > 32)\r
2620 data |= (m68ki_read_8(ea+4) << offset) >> 8;\r
2621\r
2622 FLAG_N = NFLAG_32(data);\r
2623 data = MAKE_INT_32(data) >> (32 - width);\r
2624\r
2625 FLAG_Z = data;\r
2626 FLAG_V = VFLAG_CLEAR;\r
2627 FLAG_C = CFLAG_CLEAR;\r
2628\r
2629 REG_D[(word2 >> 12) & 7] = data;\r
2630\r
2631 return;\r
2632 }\r
2633 m68ki_exception_illegal();\r
2634}\r
2635\r
2636\r
2637M68KMAKE_OP(bfextu, 32, ., d)\r
2638{\r
2639 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2640 {\r
2641 uint word2 = OPER_I_16();\r
2642 uint offset = (word2>>6)&31;\r
2643 uint width = word2;\r
2644 uint64 data = DY;\r
2645\r
2646\r
2647 if(BIT_B(word2))\r
2648 offset = REG_D[offset&7];\r
2649 if(BIT_5(word2))\r
2650 width = REG_D[width&7];\r
2651\r
2652 offset &= 31;\r
2653 width = ((width-1) & 31) + 1;\r
2654\r
2655 data = ROL_32(data, offset);\r
2656 FLAG_N = NFLAG_32(data);\r
2657 data >>= 32 - width;\r
2658\r
2659 FLAG_Z = data;\r
2660 FLAG_V = VFLAG_CLEAR;\r
2661 FLAG_C = CFLAG_CLEAR;\r
2662\r
2663 REG_D[(word2>>12)&7] = data;\r
2664\r
2665 return;\r
2666 }\r
2667 m68ki_exception_illegal();\r
2668}\r
2669\r
2670\r
2671M68KMAKE_OP(bfextu, 32, ., .)\r
2672{\r
2673 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2674 {\r
2675 uint word2 = OPER_I_16();\r
2676 sint offset = (word2>>6)&31;\r
2677 uint width = word2;\r
2678 uint data;\r
2679 uint ea = M68KMAKE_GET_EA_AY_8;\r
2680\r
2681\r
2682 if(BIT_B(word2))\r
2683 offset = MAKE_INT_32(REG_D[offset&7]);\r
2684 if(BIT_5(word2))\r
2685 width = REG_D[width&7];\r
2686\r
2687 /* Offset is signed so we have to use ugly math =( */\r
2688 ea += offset / 8;\r
2689 offset %= 8;\r
2690 if(offset < 0)\r
2691 {\r
2692 offset += 8;\r
2693 ea--;\r
2694 }\r
2695 width = ((width-1) & 31) + 1;\r
2696\r
2697 data = m68ki_read_32(ea);\r
2698 data = MASK_OUT_ABOVE_32(data<<offset);\r
2699\r
2700 if((offset+width) > 32)\r
2701 data |= (m68ki_read_8(ea+4) << offset) >> 8;\r
2702\r
2703 FLAG_N = NFLAG_32(data);\r
2704 data >>= (32 - width);\r
2705\r
2706 FLAG_Z = data;\r
2707 FLAG_V = VFLAG_CLEAR;\r
2708 FLAG_C = CFLAG_CLEAR;\r
2709\r
2710 REG_D[(word2 >> 12) & 7] = data;\r
2711\r
2712 return;\r
2713 }\r
2714 m68ki_exception_illegal();\r
2715}\r
2716\r
2717\r
2718M68KMAKE_OP(bfffo, 32, ., d)\r
2719{\r
2720 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2721 {\r
2722 uint word2 = OPER_I_16();\r
2723 uint offset = (word2>>6)&31;\r
2724 uint width = word2;\r
2725 uint64 data = DY;\r
2726 uint bit;\r
2727\r
2728\r
2729 if(BIT_B(word2))\r
2730 offset = REG_D[offset&7];\r
2731 if(BIT_5(word2))\r
2732 width = REG_D[width&7];\r
2733\r
2734 offset &= 31;\r
2735 width = ((width-1) & 31) + 1;\r
2736\r
2737 data = ROL_32(data, offset);\r
2738 FLAG_N = NFLAG_32(data);\r
2739 data >>= 32 - width;\r
2740\r
2741 FLAG_Z = data;\r
2742 FLAG_V = VFLAG_CLEAR;\r
2743 FLAG_C = CFLAG_CLEAR;\r
2744\r
2745 for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)\r
2746 offset++;\r
2747\r
2748 REG_D[(word2>>12)&7] = offset;\r
2749\r
2750 return;\r
2751 }\r
2752 m68ki_exception_illegal();\r
2753}\r
2754\r
2755\r
2756M68KMAKE_OP(bfffo, 32, ., .)\r
2757{\r
2758 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2759 {\r
2760 uint word2 = OPER_I_16();\r
2761 sint offset = (word2>>6)&31;\r
2762 sint local_offset;\r
2763 uint width = word2;\r
2764 uint data;\r
2765 uint bit;\r
2766 uint ea = M68KMAKE_GET_EA_AY_8;\r
2767\r
2768\r
2769 if(BIT_B(word2))\r
2770 offset = MAKE_INT_32(REG_D[offset&7]);\r
2771 if(BIT_5(word2))\r
2772 width = REG_D[width&7];\r
2773\r
2774 /* Offset is signed so we have to use ugly math =( */\r
2775 ea += offset / 8;\r
2776 local_offset = offset % 8;\r
2777 if(local_offset < 0)\r
2778 {\r
2779 local_offset += 8;\r
2780 ea--;\r
2781 }\r
2782 width = ((width-1) & 31) + 1;\r
2783\r
2784 data = m68ki_read_32(ea);\r
2785 data = MASK_OUT_ABOVE_32(data<<local_offset);\r
2786\r
2787 if((local_offset+width) > 32)\r
2788 data |= (m68ki_read_8(ea+4) << local_offset) >> 8;\r
2789\r
2790 FLAG_N = NFLAG_32(data);\r
2791 data >>= (32 - width);\r
2792\r
2793 FLAG_Z = data;\r
2794 FLAG_V = VFLAG_CLEAR;\r
2795 FLAG_C = CFLAG_CLEAR;\r
2796\r
2797 for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)\r
2798 offset++;\r
2799\r
2800 REG_D[(word2>>12)&7] = offset;\r
2801\r
2802 return;\r
2803 }\r
2804 m68ki_exception_illegal();\r
2805}\r
2806\r
2807\r
2808M68KMAKE_OP(bfins, 32, ., d)\r
2809{\r
2810 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2811 {\r
2812 uint word2 = OPER_I_16();\r
2813 uint offset = (word2>>6)&31;\r
2814 uint width = word2;\r
2815 uint* data = &DY;\r
2816 uint64 mask;\r
2817 uint64 insert = REG_D[(word2>>12)&7];\r
2818\r
2819\r
2820 if(BIT_B(word2))\r
2821 offset = REG_D[offset&7];\r
2822 if(BIT_5(word2))\r
2823 width = REG_D[width&7];\r
2824\r
2825\r
2826 offset &= 31;\r
2827 width = ((width-1) & 31) + 1;\r
2828\r
2829\r
2830 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
2831 mask = ROR_32(mask, offset);\r
2832\r
2833 insert = MASK_OUT_ABOVE_32(insert << (32 - width));\r
2834 FLAG_N = NFLAG_32(insert);\r
2835 FLAG_Z = insert;\r
2836 insert = ROR_32(insert, offset);\r
2837\r
2838 FLAG_V = VFLAG_CLEAR;\r
2839 FLAG_C = CFLAG_CLEAR;\r
2840\r
2841 *data &= ~mask;\r
2842 *data |= insert;\r
2843\r
2844 return;\r
2845 }\r
2846 m68ki_exception_illegal();\r
2847}\r
2848\r
2849\r
2850M68KMAKE_OP(bfins, 32, ., .)\r
2851{\r
2852 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2853 {\r
2854 uint word2 = OPER_I_16();\r
2855 sint offset = (word2>>6)&31;\r
2856 uint width = word2;\r
2857 uint insert_base = REG_D[(word2>>12)&7];\r
2858 uint insert_long;\r
2859 uint insert_byte;\r
2860 uint mask_base;\r
2861 uint data_long;\r
2862 uint mask_long;\r
2863 uint data_byte = 0;\r
2864 uint mask_byte = 0;\r
2865 uint ea = M68KMAKE_GET_EA_AY_8;\r
2866\r
2867\r
2868 if(BIT_B(word2))\r
2869 offset = MAKE_INT_32(REG_D[offset&7]);\r
2870 if(BIT_5(word2))\r
2871 width = REG_D[width&7];\r
2872\r
2873 /* Offset is signed so we have to use ugly math =( */\r
2874 ea += offset / 8;\r
2875 offset %= 8;\r
2876 if(offset < 0)\r
2877 {\r
2878 offset += 8;\r
2879 ea--;\r
2880 }\r
2881 width = ((width-1) & 31) + 1;\r
2882\r
2883 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
2884 mask_long = mask_base >> offset;\r
2885\r
2886 insert_base = MASK_OUT_ABOVE_32(insert_base << (32 - width));\r
2887 FLAG_N = NFLAG_32(insert_base);\r
2888 FLAG_Z = insert_base;\r
2889 insert_long = insert_base >> offset;\r
2890\r
2891 data_long = m68ki_read_32(ea);\r
2892 FLAG_V = VFLAG_CLEAR;\r
2893 FLAG_C = CFLAG_CLEAR;\r
2894\r
2895 m68ki_write_32(ea, (data_long & ~mask_long) | insert_long);\r
2896\r
2897 if((width + offset) > 32)\r
2898 {\r
2899 mask_byte = MASK_OUT_ABOVE_8(mask_base);\r
2900 insert_byte = MASK_OUT_ABOVE_8(insert_base);\r
2901 data_byte = m68ki_read_8(ea+4);\r
2902 FLAG_Z |= (data_byte & mask_byte);\r
2903 m68ki_write_8(ea+4, (data_byte & ~mask_byte) | insert_byte);\r
2904 }\r
2905 return;\r
2906 }\r
2907 m68ki_exception_illegal();\r
2908}\r
2909\r
2910\r
2911M68KMAKE_OP(bfset, 32, ., d)\r
2912{\r
2913 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2914 {\r
2915 uint word2 = OPER_I_16();\r
2916 uint offset = (word2>>6)&31;\r
2917 uint width = word2;\r
2918 uint* data = &DY;\r
2919 uint64 mask;\r
2920\r
2921\r
2922 if(BIT_B(word2))\r
2923 offset = REG_D[offset&7];\r
2924 if(BIT_5(word2))\r
2925 width = REG_D[width&7];\r
2926\r
2927\r
2928 offset &= 31;\r
2929 width = ((width-1) & 31) + 1;\r
2930\r
2931\r
2932 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
2933 mask = ROR_32(mask, offset);\r
2934\r
2935 FLAG_N = NFLAG_32(*data<<offset);\r
2936 FLAG_Z = *data & mask;\r
2937 FLAG_V = VFLAG_CLEAR;\r
2938 FLAG_C = CFLAG_CLEAR;\r
2939\r
2940 *data |= mask;\r
2941\r
2942 return;\r
2943 }\r
2944 m68ki_exception_illegal();\r
2945}\r
2946\r
2947\r
2948M68KMAKE_OP(bfset, 32, ., .)\r
2949{\r
2950 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2951 {\r
2952 uint word2 = OPER_I_16();\r
2953 sint offset = (word2>>6)&31;\r
2954 uint width = word2;\r
2955 uint mask_base;\r
2956 uint data_long;\r
2957 uint mask_long;\r
2958 uint data_byte = 0;\r
2959 uint mask_byte = 0;\r
2960 uint ea = M68KMAKE_GET_EA_AY_8;\r
2961\r
2962\r
2963 if(BIT_B(word2))\r
2964 offset = MAKE_INT_32(REG_D[offset&7]);\r
2965 if(BIT_5(word2))\r
2966 width = REG_D[width&7];\r
2967\r
2968 /* Offset is signed so we have to use ugly math =( */\r
2969 ea += offset / 8;\r
2970 offset %= 8;\r
2971 if(offset < 0)\r
2972 {\r
2973 offset += 8;\r
2974 ea--;\r
2975 }\r
2976 width = ((width-1) & 31) + 1;\r
2977\r
2978\r
2979 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
2980 mask_long = mask_base >> offset;\r
2981\r
2982 data_long = m68ki_read_32(ea);\r
2983 FLAG_N = NFLAG_32(data_long << offset);\r
2984 FLAG_Z = data_long & mask_long;\r
2985 FLAG_V = VFLAG_CLEAR;\r
2986 FLAG_C = CFLAG_CLEAR;\r
2987\r
2988 m68ki_write_32(ea, data_long | mask_long);\r
2989\r
2990 if((width + offset) > 32)\r
2991 {\r
2992 mask_byte = MASK_OUT_ABOVE_8(mask_base);\r
2993 data_byte = m68ki_read_8(ea+4);\r
2994 FLAG_Z |= (data_byte & mask_byte);\r
2995 m68ki_write_8(ea+4, data_byte | mask_byte);\r
2996 }\r
2997 return;\r
2998 }\r
2999 m68ki_exception_illegal();\r
3000}\r
3001\r
3002\r
3003M68KMAKE_OP(bftst, 32, ., d)\r
3004{\r
3005 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3006 {\r
3007 uint word2 = OPER_I_16();\r
3008 uint offset = (word2>>6)&31;\r
3009 uint width = word2;\r
3010 uint* data = &DY;\r
3011 uint64 mask;\r
3012\r
3013\r
3014 if(BIT_B(word2))\r
3015 offset = REG_D[offset&7];\r
3016 if(BIT_5(word2))\r
3017 width = REG_D[width&7];\r
3018\r
3019\r
3020 offset &= 31;\r
3021 width = ((width-1) & 31) + 1;\r
3022\r
3023\r
3024 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
3025 mask = ROR_32(mask, offset);\r
3026\r
3027 FLAG_N = NFLAG_32(*data<<offset);\r
3028 FLAG_Z = *data & mask;\r
3029 FLAG_V = VFLAG_CLEAR;\r
3030 FLAG_C = CFLAG_CLEAR;\r
3031\r
3032 return;\r
3033 }\r
3034 m68ki_exception_illegal();\r
3035}\r
3036\r
3037\r
3038M68KMAKE_OP(bftst, 32, ., .)\r
3039{\r
3040 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3041 {\r
3042 uint word2 = OPER_I_16();\r
3043 sint offset = (word2>>6)&31;\r
3044 uint width = word2;\r
3045 uint mask_base;\r
3046 uint data_long;\r
3047 uint mask_long;\r
3048 uint data_byte = 0;\r
3049 uint mask_byte = 0;\r
3050 uint ea = M68KMAKE_GET_EA_AY_8;\r
3051\r
3052 if(BIT_B(word2))\r
3053 offset = MAKE_INT_32(REG_D[offset&7]);\r
3054 if(BIT_5(word2))\r
3055 width = REG_D[width&7];\r
3056\r
3057 /* Offset is signed so we have to use ugly math =( */\r
3058 ea += offset / 8;\r
3059 offset %= 8;\r
3060 if(offset < 0)\r
3061 {\r
3062 offset += 8;\r
3063 ea--;\r
3064 }\r
3065 width = ((width-1) & 31) + 1;\r
3066\r
3067\r
3068 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
3069 mask_long = mask_base >> offset;\r
3070\r
3071 data_long = m68ki_read_32(ea);\r
3072 FLAG_N = ((data_long & (0x80000000 >> offset))<<offset)>>24;\r
3073 FLAG_Z = data_long & mask_long;\r
3074 FLAG_V = VFLAG_CLEAR;\r
3075 FLAG_C = CFLAG_CLEAR;\r
3076\r
3077 if((width + offset) > 32)\r
3078 {\r
3079 mask_byte = MASK_OUT_ABOVE_8(mask_base);\r
3080 data_byte = m68ki_read_8(ea+4);\r
3081 FLAG_Z |= (data_byte & mask_byte);\r
3082 }\r
3083 return;\r
3084 }\r
3085 m68ki_exception_illegal();\r
3086}\r
3087\r
3088\r
3089M68KMAKE_OP(bkpt, 0, ., .)\r
3090{\r
3091 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))\r
3092 {\r
3093 m68ki_bkpt_ack(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE) ? REG_IR & 7 : 0); /* auto-disable (see m68kcpu.h) */\r
3094 }\r
3095 m68ki_exception_illegal();\r
3096}\r
3097\r
3098\r
3099M68KMAKE_OP(bra, 8, ., .)\r
3100{\r
3101 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3102 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));\r
3103// if(REG_PC == REG_PPC)\r
3104// USE_ALL_CYCLES();\r
3105}\r
3106\r
3107\r
3108M68KMAKE_OP(bra, 16, ., .)\r
3109{\r
3110 uint offset = OPER_I_16();\r
3111 REG_PC -= 2;\r
3112 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3113 m68ki_branch_16(offset);\r
3114// if(REG_PC == REG_PPC)\r
3115// USE_ALL_CYCLES();\r
3116}\r
3117\r
3118\r
3119M68KMAKE_OP(bra, 32, ., .)\r
3120{\r
3121 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3122 {\r
3123 uint offset = OPER_I_32();\r
3124 REG_PC -= 4;\r
3125 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3126 m68ki_branch_32(offset);\r
3127 if(REG_PC == REG_PPC)\r
3128 USE_ALL_CYCLES();\r
3129 return;\r
3130 }\r
3131 else\r
3132 {\r
3133 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3134 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));\r
3135// if(REG_PC == REG_PPC)\r
3136// USE_ALL_CYCLES();\r
3137 }\r
3138}\r
3139\r
3140\r
3141M68KMAKE_OP(bset, 32, r, d)\r
3142{\r
3143 uint* r_dst = &DY;\r
3144 uint mask = 1 << (DX & 0x1f);\r
3145\r
3146 FLAG_Z = *r_dst & mask;\r
3147 *r_dst |= mask;\r
3148}\r
3149\r
3150\r
3151M68KMAKE_OP(bset, 8, r, .)\r
3152{\r
3153 uint ea = M68KMAKE_GET_EA_AY_8;\r
3154 uint src = m68ki_read_8(ea);\r
3155 uint mask = 1 << (DX & 7);\r
3156\r
3157 FLAG_Z = src & mask;\r
3158 m68ki_write_8(ea, src | mask);\r
3159}\r
3160\r
3161\r
3162M68KMAKE_OP(bset, 32, s, d)\r
3163{\r
3164 uint* r_dst = &DY;\r
3165 uint mask = 1 << (OPER_I_8() & 0x1f);\r
3166\r
3167 FLAG_Z = *r_dst & mask;\r
3168 *r_dst |= mask;\r
3169}\r
3170\r
3171\r
3172M68KMAKE_OP(bset, 8, s, .)\r
3173{\r
3174 uint mask = 1 << (OPER_I_8() & 7);\r
3175 uint ea = M68KMAKE_GET_EA_AY_8;\r
3176 uint src = m68ki_read_8(ea);\r
3177\r
3178 FLAG_Z = src & mask;\r
3179 m68ki_write_8(ea, src | mask);\r
3180}\r
3181\r
3182\r
3183M68KMAKE_OP(bsr, 8, ., .)\r
3184{\r
3185 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3186 m68ki_push_32(REG_PC);\r
3187 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));\r
3188}\r
3189\r
3190\r
3191M68KMAKE_OP(bsr, 16, ., .)\r
3192{\r
3193 uint offset = OPER_I_16();\r
3194 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3195 m68ki_push_32(REG_PC);\r
3196 REG_PC -= 2;\r
3197 m68ki_branch_16(offset);\r
3198}\r
3199\r
3200\r
3201M68KMAKE_OP(bsr, 32, ., .)\r
3202{\r
3203 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3204 {\r
3205 uint offset = OPER_I_32();\r
3206 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3207 m68ki_push_32(REG_PC);\r
3208 REG_PC -= 4;\r
3209 m68ki_branch_32(offset);\r
3210 return;\r
3211 }\r
3212 else\r
3213 {\r
3214 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3215 m68ki_push_32(REG_PC);\r
3216 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));\r
3217 }\r
3218}\r
3219\r
3220\r
3221M68KMAKE_OP(btst, 32, r, d)\r
3222{\r
3223 FLAG_Z = DY & (1 << (DX & 0x1f));\r
3224}\r
3225\r
3226\r
3227M68KMAKE_OP(btst, 8, r, .)\r
3228{\r
3229 FLAG_Z = M68KMAKE_GET_OPER_AY_8 & (1 << (DX & 7));\r
3230}\r
3231\r
3232\r
3233M68KMAKE_OP(btst, 32, s, d)\r
3234{\r
3235 FLAG_Z = DY & (1 << (OPER_I_8() & 0x1f));\r
3236}\r
3237\r
3238\r
3239M68KMAKE_OP(btst, 8, s, .)\r
3240{\r
3241 uint bit = OPER_I_8() & 7;\r
3242\r
3243 FLAG_Z = M68KMAKE_GET_OPER_AY_8 & (1 << bit);\r
3244}\r
3245\r
3246\r
3247M68KMAKE_OP(callm, 32, ., .)\r
3248{\r
3249 /* note: watch out for pcrelative modes */\r
3250 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))\r
3251 {\r
3252 uint ea = M68KMAKE_GET_EA_AY_32;\r
3253\r
3254 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3255 REG_PC += 2;\r
3256(void)ea; /* just to avoid an 'unused variable' warning */\r
3257 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",\r
3258 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,\r
3259 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));\r
3260 return;\r
3261 }\r
3262 m68ki_exception_illegal();\r
3263}\r
3264\r
3265\r
3266M68KMAKE_OP(cas, 8, ., .)\r
3267{\r
3268 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3269 {\r
3270 uint word2 = OPER_I_16();\r
3271 uint ea = M68KMAKE_GET_EA_AY_8;\r
3272 uint dest = m68ki_read_8(ea);\r
3273 uint* compare = &REG_D[word2 & 7];\r
3274 uint res = dest - MASK_OUT_ABOVE_8(*compare);\r
3275\r
3276 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3277 FLAG_N = NFLAG_8(res);\r
3278 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
3279 FLAG_V = VFLAG_SUB_8(*compare, dest, res);\r
3280 FLAG_C = CFLAG_8(res);\r
3281\r
3282 if(COND_NE())\r
3283 *compare = MASK_OUT_BELOW_8(*compare) | dest;\r
3284 else\r
3285 {\r
3286 USE_CYCLES(3);\r
3287 m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7]));\r
3288 }\r
3289 return;\r
3290 }\r
3291 m68ki_exception_illegal();\r
3292}\r
3293\r
3294\r
3295M68KMAKE_OP(cas, 16, ., .)\r
3296{\r
3297 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3298 {\r
3299 uint word2 = OPER_I_16();\r
3300 uint ea = M68KMAKE_GET_EA_AY_16;\r
3301 uint dest = m68ki_read_16(ea);\r
3302 uint* compare = &REG_D[word2 & 7];\r
3303 uint res = dest - MASK_OUT_ABOVE_16(*compare);\r
3304\r
3305 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3306 FLAG_N = NFLAG_16(res);\r
3307 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
3308 FLAG_V = VFLAG_SUB_16(*compare, dest, res);\r
3309 FLAG_C = CFLAG_16(res);\r
3310\r
3311 if(COND_NE())\r
3312 *compare = MASK_OUT_BELOW_16(*compare) | dest;\r
3313 else\r
3314 {\r
3315 USE_CYCLES(3);\r
3316 m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7]));\r
3317 }\r
3318 return;\r
3319 }\r
3320 m68ki_exception_illegal();\r
3321}\r
3322\r
3323\r
3324M68KMAKE_OP(cas, 32, ., .)\r
3325{\r
3326 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3327 {\r
3328 uint word2 = OPER_I_16();\r
3329 uint ea = M68KMAKE_GET_EA_AY_32;\r
3330 uint dest = m68ki_read_32(ea);\r
3331 uint* compare = &REG_D[word2 & 7];\r
3332 uint res = dest - *compare;\r
3333\r
3334 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3335 FLAG_N = NFLAG_32(res);\r
3336 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
3337 FLAG_V = VFLAG_SUB_32(*compare, dest, res);\r
3338 FLAG_C = CFLAG_SUB_32(*compare, dest, res);\r
3339\r
3340 if(COND_NE())\r
3341 *compare = dest;\r
3342 else\r
3343 {\r
3344 USE_CYCLES(3);\r
3345 m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]);\r
3346 }\r
3347 return;\r
3348 }\r
3349 m68ki_exception_illegal();\r
3350}\r
3351\r
3352\r
3353M68KMAKE_OP(cas2, 16, ., .)\r
3354{\r
3355 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3356 {\r
3357 uint word2 = OPER_I_32();\r
3358 uint* compare1 = &REG_D[(word2 >> 16) & 7];\r
3359 uint ea1 = REG_DA[(word2 >> 28) & 15];\r
3360 uint dest1 = m68ki_read_16(ea1);\r
3361 uint res1 = dest1 - MASK_OUT_ABOVE_16(*compare1);\r
3362 uint* compare2 = &REG_D[word2 & 7];\r
3363 uint ea2 = REG_DA[(word2 >> 12) & 15];\r
3364 uint dest2 = m68ki_read_16(ea2);\r
3365 uint res2;\r
3366\r
3367 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3368 FLAG_N = NFLAG_16(res1);\r
3369 FLAG_Z = MASK_OUT_ABOVE_16(res1);\r
3370 FLAG_V = VFLAG_SUB_16(*compare1, dest1, res1);\r
3371 FLAG_C = CFLAG_16(res1);\r
3372\r
3373 if(COND_EQ())\r
3374 {\r
3375 res2 = dest2 - MASK_OUT_ABOVE_16(*compare2);\r
3376\r
3377 FLAG_N = NFLAG_16(res2);\r
3378 FLAG_Z = MASK_OUT_ABOVE_16(res2);\r
3379 FLAG_V = VFLAG_SUB_16(*compare2, dest2, res2);\r
3380 FLAG_C = CFLAG_16(res2);\r
3381\r
3382 if(COND_EQ())\r
3383 {\r
3384 USE_CYCLES(3);\r
3385 m68ki_write_16(ea1, REG_D[(word2 >> 22) & 7]);\r
3386 m68ki_write_16(ea2, REG_D[(word2 >> 6) & 7]);\r
3387 return;\r
3388 }\r
3389 }\r
3390 *compare1 = BIT_1F(word2) ? MAKE_INT_16(dest1) : MASK_OUT_BELOW_16(*compare1) | dest1;\r
3391 *compare2 = BIT_F(word2) ? MAKE_INT_16(dest2) : MASK_OUT_BELOW_16(*compare2) | dest2;\r
3392 return;\r
3393 }\r
3394 m68ki_exception_illegal();\r
3395}\r
3396\r
3397\r
3398M68KMAKE_OP(cas2, 32, ., .)\r
3399{\r
3400 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3401 {\r
3402 uint word2 = OPER_I_32();\r
3403 uint* compare1 = &REG_D[(word2 >> 16) & 7];\r
3404 uint ea1 = REG_DA[(word2 >> 28) & 15];\r
3405 uint dest1 = m68ki_read_32(ea1);\r
3406 uint res1 = dest1 - *compare1;\r
3407 uint* compare2 = &REG_D[word2 & 7];\r
3408 uint ea2 = REG_DA[(word2 >> 12) & 15];\r
3409 uint dest2 = m68ki_read_32(ea2);\r
3410 uint res2;\r
3411\r
3412 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3413 FLAG_N = NFLAG_32(res1);\r
3414 FLAG_Z = MASK_OUT_ABOVE_32(res1);\r
3415 FLAG_V = VFLAG_SUB_32(*compare1, dest1, res1);\r
3416 FLAG_C = CFLAG_SUB_32(*compare1, dest1, res1);\r
3417\r
3418 if(COND_EQ())\r
3419 {\r
3420 res2 = dest2 - *compare2;\r
3421\r
3422 FLAG_N = NFLAG_32(res2);\r
3423 FLAG_Z = MASK_OUT_ABOVE_32(res2);\r
3424 FLAG_V = VFLAG_SUB_32(*compare2, dest2, res2);\r
3425 FLAG_C = CFLAG_SUB_32(*compare2, dest2, res2);\r
3426\r
3427 if(COND_EQ())\r
3428 {\r
3429 USE_CYCLES(3);\r
3430 m68ki_write_32(ea1, REG_D[(word2 >> 22) & 7]);\r
3431 m68ki_write_32(ea2, REG_D[(word2 >> 6) & 7]);\r
3432 return;\r
3433 }\r
3434 }\r
3435 *compare1 = dest1;\r
3436 *compare2 = dest2;\r
3437 return;\r
3438 }\r
3439 m68ki_exception_illegal();\r
3440}\r
3441\r
3442\r
3443M68KMAKE_OP(chk, 16, ., d)\r
3444{\r
3445 sint src = MAKE_INT_16(DX);\r
3446 sint bound = MAKE_INT_16(DY);\r
3447\r
3448 FLAG_Z = ZFLAG_16(src); /* Undocumented */\r
3449 FLAG_V = VFLAG_CLEAR; /* Undocumented */\r
3450 FLAG_C = CFLAG_CLEAR; /* Undocumented */\r
3451\r
3452 if(src >= 0 && src <= bound)\r
3453 {\r
3454 return;\r
3455 }\r
3456 FLAG_N = (src < 0)<<7;\r
3457 m68ki_exception_trap(EXCEPTION_CHK);\r
3458}\r
3459\r
3460\r
3461M68KMAKE_OP(chk, 16, ., .)\r
3462{\r
3463 sint src = MAKE_INT_16(DX);\r
3464 sint bound = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);\r
3465\r
3466 FLAG_Z = ZFLAG_16(src); /* Undocumented */\r
3467 FLAG_V = VFLAG_CLEAR; /* Undocumented */\r
3468 FLAG_C = CFLAG_CLEAR; /* Undocumented */\r
3469\r
3470 if(src >= 0 && src <= bound)\r
3471 {\r
3472 return;\r
3473 }\r
3474 FLAG_N = (src < 0)<<7;\r
3475 m68ki_exception_trap(EXCEPTION_CHK);\r
3476}\r
3477\r
3478\r
3479M68KMAKE_OP(chk, 32, ., d)\r
3480{\r
3481 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3482 {\r
3483 sint src = MAKE_INT_32(DX);\r
3484 sint bound = MAKE_INT_32(DY);\r
3485\r
3486 FLAG_Z = ZFLAG_32(src); /* Undocumented */\r
3487 FLAG_V = VFLAG_CLEAR; /* Undocumented */\r
3488 FLAG_C = CFLAG_CLEAR; /* Undocumented */\r
3489\r
3490 if(src >= 0 && src <= bound)\r
3491 {\r
3492 return;\r
3493 }\r
3494 FLAG_N = (src < 0)<<7;\r
3495 m68ki_exception_trap(EXCEPTION_CHK);\r
3496 return;\r
3497 }\r
3498 m68ki_exception_illegal();\r
3499}\r
3500\r
3501\r
3502M68KMAKE_OP(chk, 32, ., .)\r
3503{\r
3504 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3505 {\r
3506 sint src = MAKE_INT_32(DX);\r
3507 sint bound = MAKE_INT_32(M68KMAKE_GET_OPER_AY_32);\r
3508\r
3509 FLAG_Z = ZFLAG_32(src); /* Undocumented */\r
3510 FLAG_V = VFLAG_CLEAR; /* Undocumented */\r
3511 FLAG_C = CFLAG_CLEAR; /* Undocumented */\r
3512\r
3513 if(src >= 0 && src <= bound)\r
3514 {\r
3515 return;\r
3516 }\r
3517 FLAG_N = (src < 0)<<7;\r
3518 m68ki_exception_trap(EXCEPTION_CHK);\r
3519 return;\r
3520 }\r
3521 m68ki_exception_illegal();\r
3522}\r
3523\r
3524\r
3525M68KMAKE_OP(chk2cmp2, 8, ., pcdi)\r
3526{\r
3527 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3528 {\r
3529 uint word2 = OPER_I_16();\r
3530 uint compare = REG_DA[(word2 >> 12) & 15]&0xff;\r
3531 uint ea = EA_PCDI_8();\r
3532 uint lower_bound = m68ki_read_pcrel_8(ea);\r
3533 uint upper_bound = m68ki_read_pcrel_8(ea + 1);\r
3534\r
3535 if(!BIT_F(word2))\r
3536 FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound);\r
3537 else\r
3538 FLAG_C = compare - lower_bound;\r
3539 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));\r
3540 if(COND_CS())\r
3541 {\r
3542 if(BIT_B(word2))\r
3543 m68ki_exception_trap(EXCEPTION_CHK);\r
3544 return;\r
3545 }\r
3546\r
3547 FLAG_C = upper_bound - compare;\r
3548 if(COND_CS() && BIT_B(word2))\r
3549 m68ki_exception_trap(EXCEPTION_CHK);\r
3550 return;\r
3551 }\r
3552 m68ki_exception_illegal();\r
3553}\r
3554\r
3555\r
3556M68KMAKE_OP(chk2cmp2, 8, ., pcix)\r
3557{\r
3558 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3559 {\r
3560 uint word2 = OPER_I_16();\r
3561 uint compare = REG_DA[(word2 >> 12) & 15]&0xff;\r
3562 uint ea = EA_PCIX_8();\r
3563 uint lower_bound = m68ki_read_pcrel_8(ea);\r
3564 uint upper_bound = m68ki_read_pcrel_8(ea + 1);\r
3565\r
3566 if(!BIT_F(word2))\r
3567 FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound);\r
3568 else\r
3569 FLAG_C = compare - lower_bound;\r
3570 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));\r
3571 if(COND_CS())\r
3572 {\r
3573 if(BIT_B(word2))\r
3574 m68ki_exception_trap(EXCEPTION_CHK);\r
3575 return;\r
3576 }\r
3577\r
3578 FLAG_C = upper_bound - compare;\r
3579 if(COND_CS() && BIT_B(word2))\r
3580 m68ki_exception_trap(EXCEPTION_CHK);\r
3581 return;\r
3582 }\r
3583 m68ki_exception_illegal();\r
3584}\r
3585\r
3586\r
3587M68KMAKE_OP(chk2cmp2, 8, ., .)\r
3588{\r
3589 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3590 {\r
3591 uint word2 = OPER_I_16();\r
3592 uint compare = REG_DA[(word2 >> 12) & 15]&0xff;\r
3593 uint ea = M68KMAKE_GET_EA_AY_8;\r
3594 uint lower_bound = m68ki_read_8(ea);\r
3595 uint upper_bound = m68ki_read_8(ea + 1);\r
3596\r
3597 if(!BIT_F(word2))\r
3598 FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound);\r
3599 else\r
3600 FLAG_C = compare - lower_bound;\r
3601 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));\r
3602 if(COND_CS())\r
3603 {\r
3604 if(BIT_B(word2))\r
3605 m68ki_exception_trap(EXCEPTION_CHK);\r
3606 return;\r
3607 }\r
3608\r
3609 FLAG_C = upper_bound - compare;\r
3610 if(COND_CS() && BIT_B(word2))\r
3611 m68ki_exception_trap(EXCEPTION_CHK);\r
3612 return;\r
3613 }\r
3614 m68ki_exception_illegal();\r
3615}\r
3616\r
3617\r
3618M68KMAKE_OP(chk2cmp2, 16, ., pcdi)\r
3619{\r
3620 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3621 {\r
3622 uint word2 = OPER_I_16();\r
3623 uint compare = REG_DA[(word2 >> 12) & 15]&0xffff;\r
3624 uint ea = EA_PCDI_16();\r
3625 uint lower_bound = m68ki_read_pcrel_16(ea);\r
3626 uint upper_bound = m68ki_read_pcrel_16(ea + 2);\r
3627\r
3628 if(!BIT_F(word2))\r
3629 FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound);\r
3630 else\r
3631 FLAG_C = compare - lower_bound;\r
3632 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));\r
3633 FLAG_C = CFLAG_16(FLAG_C);\r
3634 if(COND_CS())\r
3635 {\r
3636 if(BIT_B(word2))\r
3637 m68ki_exception_trap(EXCEPTION_CHK);\r
3638 return;\r
3639 }\r
3640\r
3641 if(!BIT_F(word2))\r
3642 FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare);\r
3643 else\r
3644 FLAG_C = upper_bound - compare;\r
3645 FLAG_C = CFLAG_16(FLAG_C);\r
3646 if(COND_CS() && BIT_B(word2))\r
3647 m68ki_exception_trap(EXCEPTION_CHK);\r
3648 return;\r
3649 }\r
3650 m68ki_exception_illegal();\r
3651}\r
3652\r
3653\r
3654M68KMAKE_OP(chk2cmp2, 16, ., pcix)\r
3655{\r
3656 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3657 {\r
3658 uint word2 = OPER_I_16();\r
3659 uint compare = REG_DA[(word2 >> 12) & 15]&0xffff;\r
3660 uint ea = EA_PCIX_16();\r
3661 uint lower_bound = m68ki_read_pcrel_16(ea);\r
3662 uint upper_bound = m68ki_read_pcrel_16(ea + 2);\r
3663\r
3664 if(!BIT_F(word2))\r
3665 FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound);\r
3666 else\r
3667 FLAG_C = compare - lower_bound;\r
3668 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));\r
3669 FLAG_C = CFLAG_16(FLAG_C);\r
3670 if(COND_CS())\r
3671 {\r
3672 if(BIT_B(word2))\r
3673 m68ki_exception_trap(EXCEPTION_CHK);\r
3674 return;\r
3675 }\r
3676\r
3677 if(!BIT_F(word2))\r
3678 FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare);\r
3679 else\r
3680 FLAG_C = upper_bound - compare;\r
3681 FLAG_C = CFLAG_16(FLAG_C);\r
3682 if(COND_CS() && BIT_B(word2))\r
3683 m68ki_exception_trap(EXCEPTION_CHK);\r
3684 return;\r
3685 }\r
3686 m68ki_exception_illegal();\r
3687}\r
3688\r
3689\r
3690M68KMAKE_OP(chk2cmp2, 16, ., .)\r
3691{\r
3692 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3693 {\r
3694 uint word2 = OPER_I_16();\r
3695 uint compare = REG_DA[(word2 >> 12) & 15]&0xffff;\r
3696 uint ea = M68KMAKE_GET_EA_AY_16;\r
3697 uint lower_bound = m68ki_read_16(ea);\r
3698 uint upper_bound = m68ki_read_16(ea + 2);\r
3699\r
3700 if(!BIT_F(word2))\r
3701 FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound);\r
3702 else\r
3703 FLAG_C = compare - lower_bound;\r
3704\r
3705 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));\r
3706 FLAG_C = CFLAG_16(FLAG_C);\r
3707 if(COND_CS())\r
3708 {\r
3709 if(BIT_B(word2))\r
3710 m68ki_exception_trap(EXCEPTION_CHK);\r
3711 return;\r
3712 }\r
3713 if(!BIT_F(word2))\r
3714 FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare);\r
3715 else\r
3716 FLAG_C = upper_bound - compare;\r
3717\r
3718 FLAG_C = CFLAG_16(FLAG_C);\r
3719 if(COND_CS() && BIT_B(word2))\r
3720 m68ki_exception_trap(EXCEPTION_CHK);\r
3721 return;\r
3722 }\r
3723 m68ki_exception_illegal();\r
3724}\r
3725\r
3726\r
3727M68KMAKE_OP(chk2cmp2, 32, ., pcdi)\r
3728{\r
3729 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3730 {\r
3731 uint word2 = OPER_I_16();\r
3732 uint compare = REG_DA[(word2 >> 12) & 15];\r
3733 uint ea = EA_PCDI_32();\r
3734 uint lower_bound = m68ki_read_pcrel_32(ea);\r
3735 uint upper_bound = m68ki_read_pcrel_32(ea + 4);\r
3736\r
3737 FLAG_C = compare - lower_bound;\r
3738 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));\r
3739 FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);\r
3740 if(COND_CS())\r
3741 {\r
3742 if(BIT_B(word2))\r
3743 m68ki_exception_trap(EXCEPTION_CHK);\r
3744 return;\r
3745 }\r
3746\r
3747 FLAG_C = upper_bound - compare;\r
3748 FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);\r
3749 if(COND_CS() && BIT_B(word2))\r
3750 m68ki_exception_trap(EXCEPTION_CHK);\r
3751 return;\r
3752 }\r
3753 m68ki_exception_illegal();\r
3754}\r
3755\r
3756\r
3757M68KMAKE_OP(chk2cmp2, 32, ., pcix)\r
3758{\r
3759 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3760 {\r
3761 uint word2 = OPER_I_16();\r
3762 uint compare = REG_DA[(word2 >> 12) & 15];\r
3763 uint ea = EA_PCIX_32();\r
3764 uint lower_bound = m68ki_read_pcrel_32(ea);\r
3765 uint upper_bound = m68ki_read_pcrel_32(ea + 4);\r
3766\r
3767 FLAG_C = compare - lower_bound;\r
3768 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));\r
3769 FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);\r
3770 if(COND_CS())\r
3771 {\r
3772 if(BIT_B(word2))\r
3773 m68ki_exception_trap(EXCEPTION_CHK);\r
3774 return;\r
3775 }\r
3776\r
3777 FLAG_C = upper_bound - compare;\r
3778 FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);\r
3779 if(COND_CS() && BIT_B(word2))\r
3780 m68ki_exception_trap(EXCEPTION_CHK);\r
3781 return;\r
3782 }\r
3783 m68ki_exception_illegal();\r
3784}\r
3785\r
3786\r
3787M68KMAKE_OP(chk2cmp2, 32, ., .)\r
3788{\r
3789 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3790 {\r
3791 uint word2 = OPER_I_16();\r
3792 uint compare = REG_DA[(word2 >> 12) & 15];\r
3793 uint ea = M68KMAKE_GET_EA_AY_32;\r
3794 uint lower_bound = m68ki_read_32(ea);\r
3795 uint upper_bound = m68ki_read_32(ea + 4);\r
3796\r
3797 FLAG_C = compare - lower_bound;\r
3798 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));\r
3799 FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);\r
3800 if(COND_CS())\r
3801 {\r
3802 if(BIT_B(word2))\r
3803 m68ki_exception_trap(EXCEPTION_CHK);\r
3804 return;\r
3805 }\r
3806\r
3807 FLAG_C = upper_bound - compare;\r
3808 FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);\r
3809 if(COND_CS() && BIT_B(word2))\r
3810 m68ki_exception_trap(EXCEPTION_CHK);\r
3811 return;\r
3812 }\r
3813 m68ki_exception_illegal();\r
3814}\r
3815\r
3816\r
3817M68KMAKE_OP(clr, 8, ., d)\r
3818{\r
3819 DY &= 0xffffff00;\r
3820\r
3821 FLAG_N = NFLAG_CLEAR;\r
3822 FLAG_V = VFLAG_CLEAR;\r
3823 FLAG_C = CFLAG_CLEAR;\r
3824 FLAG_Z = ZFLAG_SET;\r
3825}\r
3826\r
3827\r
3828M68KMAKE_OP(clr, 8, ., .)\r
3829{\r
3830 m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0);\r
3831\r
3832 FLAG_N = NFLAG_CLEAR;\r
3833 FLAG_V = VFLAG_CLEAR;\r
3834 FLAG_C = CFLAG_CLEAR;\r
3835 FLAG_Z = ZFLAG_SET;\r
3836}\r
3837\r
3838\r
3839M68KMAKE_OP(clr, 16, ., d)\r
3840{\r
3841 DY &= 0xffff0000;\r
3842\r
3843 FLAG_N = NFLAG_CLEAR;\r
3844 FLAG_V = VFLAG_CLEAR;\r
3845 FLAG_C = CFLAG_CLEAR;\r
3846 FLAG_Z = ZFLAG_SET;\r
3847}\r
3848\r
3849\r
3850M68KMAKE_OP(clr, 16, ., .)\r
3851{\r
3852 m68ki_write_16(M68KMAKE_GET_EA_AY_16, 0);\r
3853\r
3854 FLAG_N = NFLAG_CLEAR;\r
3855 FLAG_V = VFLAG_CLEAR;\r
3856 FLAG_C = CFLAG_CLEAR;\r
3857 FLAG_Z = ZFLAG_SET;\r
3858}\r
3859\r
3860\r
3861M68KMAKE_OP(clr, 32, ., d)\r
3862{\r
3863 DY = 0;\r
3864\r
3865 FLAG_N = NFLAG_CLEAR;\r
3866 FLAG_V = VFLAG_CLEAR;\r
3867 FLAG_C = CFLAG_CLEAR;\r
3868 FLAG_Z = ZFLAG_SET;\r
3869}\r
3870\r
3871\r
3872M68KMAKE_OP(clr, 32, ., .)\r
3873{\r
3874 m68ki_write_32(M68KMAKE_GET_EA_AY_32, 0);\r
3875\r
3876 FLAG_N = NFLAG_CLEAR;\r
3877 FLAG_V = VFLAG_CLEAR;\r
3878 FLAG_C = CFLAG_CLEAR;\r
3879 FLAG_Z = ZFLAG_SET;\r
3880}\r
3881\r
3882\r
3883M68KMAKE_OP(cmp, 8, ., d)\r
3884{\r
3885 uint src = MASK_OUT_ABOVE_8(DY);\r
3886 uint dst = MASK_OUT_ABOVE_8(DX);\r
3887 uint res = dst - src;\r
3888\r
3889 FLAG_N = NFLAG_8(res);\r
3890 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
3891 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
3892 FLAG_C = CFLAG_8(res);\r
3893}\r
3894\r
3895\r
3896M68KMAKE_OP(cmp, 8, ., .)\r
3897{\r
3898 uint src = M68KMAKE_GET_OPER_AY_8;\r
3899 uint dst = MASK_OUT_ABOVE_8(DX);\r
3900 uint res = dst - src;\r
3901\r
3902 FLAG_N = NFLAG_8(res);\r
3903 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
3904 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
3905 FLAG_C = CFLAG_8(res);\r
3906}\r
3907\r
3908\r
3909M68KMAKE_OP(cmp, 16, ., d)\r
3910{\r
3911 uint src = MASK_OUT_ABOVE_16(DY);\r
3912 uint dst = MASK_OUT_ABOVE_16(DX);\r
3913 uint res = dst - src;\r
3914\r
3915 FLAG_N = NFLAG_16(res);\r
3916 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
3917 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
3918 FLAG_C = CFLAG_16(res);\r
3919}\r
3920\r
3921\r
3922M68KMAKE_OP(cmp, 16, ., a)\r
3923{\r
3924 uint src = MASK_OUT_ABOVE_16(AY);\r
3925 uint dst = MASK_OUT_ABOVE_16(DX);\r
3926 uint res = dst - src;\r
3927\r
3928 FLAG_N = NFLAG_16(res);\r
3929 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
3930 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
3931 FLAG_C = CFLAG_16(res);\r
3932}\r
3933\r
3934\r
3935M68KMAKE_OP(cmp, 16, ., .)\r
3936{\r
3937 uint src = M68KMAKE_GET_OPER_AY_16;\r
3938 uint dst = MASK_OUT_ABOVE_16(DX);\r
3939 uint res = dst - src;\r
3940\r
3941 FLAG_N = NFLAG_16(res);\r
3942 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
3943 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
3944 FLAG_C = CFLAG_16(res);\r
3945}\r
3946\r
3947\r
3948M68KMAKE_OP(cmp, 32, ., d)\r
3949{\r
3950 uint src = DY;\r
3951 uint dst = DX;\r
3952 uint res = dst - src;\r
3953\r
3954 FLAG_N = NFLAG_32(res);\r
3955 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
3956 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
3957 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
3958}\r
3959\r
3960\r
3961M68KMAKE_OP(cmp, 32, ., a)\r
3962{\r
3963 uint src = AY;\r
3964 uint dst = DX;\r
3965 uint res = dst - src;\r
3966\r
3967 FLAG_N = NFLAG_32(res);\r
3968 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
3969 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
3970 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
3971}\r
3972\r
3973\r
3974M68KMAKE_OP(cmp, 32, ., .)\r
3975{\r
3976 uint src = M68KMAKE_GET_OPER_AY_32;\r
3977 uint dst = DX;\r
3978 uint res = dst - src;\r
3979\r
3980 FLAG_N = NFLAG_32(res);\r
3981 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
3982 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
3983 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
3984}\r
3985\r
3986\r
3987M68KMAKE_OP(cmpa, 16, ., d)\r
3988{\r
3989 uint src = MAKE_INT_16(DY);\r
3990 uint dst = AX;\r
3991 uint res = dst - src;\r
3992\r
3993 FLAG_N = NFLAG_32(res);\r
3994 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
3995 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
3996 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
3997}\r
3998\r
3999\r
4000M68KMAKE_OP(cmpa, 16, ., a)\r
4001{\r
4002 uint src = MAKE_INT_16(AY);\r
4003 uint dst = AX;\r
4004 uint res = dst - src;\r
4005\r
4006 FLAG_N = NFLAG_32(res);\r
4007 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4008 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4009 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4010}\r
4011\r
4012\r
4013M68KMAKE_OP(cmpa, 16, ., .)\r
4014{\r
4015 uint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);\r
4016 uint dst = AX;\r
4017 uint res = dst - src;\r
4018\r
4019 FLAG_N = NFLAG_32(res);\r
4020 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4021 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4022 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4023}\r
4024\r
4025\r
4026M68KMAKE_OP(cmpa, 32, ., d)\r
4027{\r
4028 uint src = DY;\r
4029 uint dst = AX;\r
4030 uint res = dst - src;\r
4031\r
4032 FLAG_N = NFLAG_32(res);\r
4033 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4034 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4035 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4036}\r
4037\r
4038\r
4039M68KMAKE_OP(cmpa, 32, ., a)\r
4040{\r
4041 uint src = AY;\r
4042 uint dst = AX;\r
4043 uint res = dst - src;\r
4044\r
4045 FLAG_N = NFLAG_32(res);\r
4046 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4047 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4048 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4049}\r
4050\r
4051\r
4052M68KMAKE_OP(cmpa, 32, ., .)\r
4053{\r
4054 uint src = M68KMAKE_GET_OPER_AY_32;\r
4055 uint dst = AX;\r
4056 uint res = dst - src;\r
4057\r
4058 FLAG_N = NFLAG_32(res);\r
4059 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4060 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4061 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4062}\r
4063\r
4064\r
4065M68KMAKE_OP(cmpi, 8, ., d)\r
4066{\r
4067 uint src = OPER_I_8();\r
4068 uint dst = MASK_OUT_ABOVE_8(DY);\r
4069 uint res = dst - src;\r
4070\r
4071 FLAG_N = NFLAG_8(res);\r
4072 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
4073 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
4074 FLAG_C = CFLAG_8(res);\r
4075}\r
4076\r
4077\r
4078M68KMAKE_OP(cmpi, 8, ., .)\r
4079{\r
4080 uint src = OPER_I_8();\r
4081 uint dst = M68KMAKE_GET_OPER_AY_8;\r
4082 uint res = dst - src;\r
4083\r
4084 FLAG_N = NFLAG_8(res);\r
4085 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
4086 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
4087 FLAG_C = CFLAG_8(res);\r
4088}\r
4089\r
4090\r
4091M68KMAKE_OP(cmpi, 8, ., pcdi)\r
4092{\r
4093 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4094 {\r
4095 uint src = OPER_I_8();\r
4096 uint dst = OPER_PCDI_8();\r
4097 uint res = dst - src;\r
4098\r
4099 FLAG_N = NFLAG_8(res);\r
4100 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
4101 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
4102 FLAG_C = CFLAG_8(res);\r
4103 return;\r
4104 }\r
4105 m68ki_exception_illegal();\r
4106}\r
4107\r
4108\r
4109M68KMAKE_OP(cmpi, 8, ., pcix)\r
4110{\r
4111 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4112 {\r
4113 uint src = OPER_I_8();\r
4114 uint dst = OPER_PCIX_8();\r
4115 uint res = dst - src;\r
4116\r
4117 FLAG_N = NFLAG_8(res);\r
4118 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
4119 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
4120 FLAG_C = CFLAG_8(res);\r
4121 return;\r
4122 }\r
4123 m68ki_exception_illegal();\r
4124}\r
4125\r
4126\r
4127M68KMAKE_OP(cmpi, 16, ., d)\r
4128{\r
4129 uint src = OPER_I_16();\r
4130 uint dst = MASK_OUT_ABOVE_16(DY);\r
4131 uint res = dst - src;\r
4132\r
4133 FLAG_N = NFLAG_16(res);\r
4134 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
4135 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
4136 FLAG_C = CFLAG_16(res);\r
4137}\r
4138\r
4139\r
4140M68KMAKE_OP(cmpi, 16, ., .)\r
4141{\r
4142 uint src = OPER_I_16();\r
4143 uint dst = M68KMAKE_GET_OPER_AY_16;\r
4144 uint res = dst - src;\r
4145\r
4146 FLAG_N = NFLAG_16(res);\r
4147 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
4148 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
4149 FLAG_C = CFLAG_16(res);\r
4150}\r
4151\r
4152\r
4153M68KMAKE_OP(cmpi, 16, ., pcdi)\r
4154{\r
4155 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4156 {\r
4157 uint src = OPER_I_16();\r
4158 uint dst = OPER_PCDI_16();\r
4159 uint res = dst - src;\r
4160\r
4161 FLAG_N = NFLAG_16(res);\r
4162 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
4163 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
4164 FLAG_C = CFLAG_16(res);\r
4165 return;\r
4166 }\r
4167 m68ki_exception_illegal();\r
4168}\r
4169\r
4170\r
4171M68KMAKE_OP(cmpi, 16, ., pcix)\r
4172{\r
4173 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4174 {\r
4175 uint src = OPER_I_16();\r
4176 uint dst = OPER_PCIX_16();\r
4177 uint res = dst - src;\r
4178\r
4179 FLAG_N = NFLAG_16(res);\r
4180 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
4181 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
4182 FLAG_C = CFLAG_16(res);\r
4183 return;\r
4184 }\r
4185 m68ki_exception_illegal();\r
4186}\r
4187\r
4188\r
4189M68KMAKE_OP(cmpi, 32, ., d)\r
4190{\r
4191 uint src = OPER_I_32();\r
4192 uint dst = DY;\r
4193 uint res = dst - src;\r
4194\r
4195 m68ki_cmpild_callback(src, REG_IR & 7); /* auto-disable (see m68kcpu.h) */\r
4196\r
4197 FLAG_N = NFLAG_32(res);\r
4198 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4199 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4200 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4201}\r
4202\r
4203\r
4204M68KMAKE_OP(cmpi, 32, ., .)\r
4205{\r
4206 uint src = OPER_I_32();\r
4207 uint dst = M68KMAKE_GET_OPER_AY_32;\r
4208 uint res = dst - src;\r
4209\r
4210 FLAG_N = NFLAG_32(res);\r
4211 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4212 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4213 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4214}\r
4215\r
4216\r
4217M68KMAKE_OP(cmpi, 32, ., pcdi)\r
4218{\r
4219 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4220 {\r
4221 uint src = OPER_I_32();\r
4222 uint dst = OPER_PCDI_32();\r
4223 uint res = dst - src;\r
4224\r
4225 FLAG_N = NFLAG_32(res);\r
4226 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4227 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4228 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4229 return;\r
4230 }\r
4231 m68ki_exception_illegal();\r
4232}\r
4233\r
4234\r
4235M68KMAKE_OP(cmpi, 32, ., pcix)\r
4236{\r
4237 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4238 {\r
4239 uint src = OPER_I_32();\r
4240 uint dst = OPER_PCIX_32();\r
4241 uint res = dst - src;\r
4242\r
4243 FLAG_N = NFLAG_32(res);\r
4244 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4245 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4246 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4247 return;\r
4248 }\r
4249 m68ki_exception_illegal();\r
4250}\r
4251\r
4252\r
4253M68KMAKE_OP(cmpm, 8, ., ax7)\r
4254{\r
4255 uint src = OPER_AY_PI_8();\r
4256 uint dst = OPER_A7_PI_8();\r
4257 uint res = dst - src;\r
4258\r
4259 FLAG_N = NFLAG_8(res);\r
4260 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
4261 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
4262 FLAG_C = CFLAG_8(res);\r
4263}\r
4264\r
4265\r
4266M68KMAKE_OP(cmpm, 8, ., ay7)\r
4267{\r
4268 uint src = OPER_A7_PI_8();\r
4269 uint dst = OPER_AX_PI_8();\r
4270 uint res = dst - src;\r
4271\r
4272 FLAG_N = NFLAG_8(res);\r
4273 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
4274 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
4275 FLAG_C = CFLAG_8(res);\r
4276}\r
4277\r
4278\r
4279M68KMAKE_OP(cmpm, 8, ., axy7)\r
4280{\r
4281 uint src = OPER_A7_PI_8();\r
4282 uint dst = OPER_A7_PI_8();\r
4283 uint res = dst - src;\r
4284\r
4285 FLAG_N = NFLAG_8(res);\r
4286 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
4287 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
4288 FLAG_C = CFLAG_8(res);\r
4289}\r
4290\r
4291\r
4292M68KMAKE_OP(cmpm, 8, ., .)\r
4293{\r
4294 uint src = OPER_AY_PI_8();\r
4295 uint dst = OPER_AX_PI_8();\r
4296 uint res = dst - src;\r
4297\r
4298 FLAG_N = NFLAG_8(res);\r
4299 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
4300 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
4301 FLAG_C = CFLAG_8(res);\r
4302}\r
4303\r
4304\r
4305M68KMAKE_OP(cmpm, 16, ., .)\r
4306{\r
4307 uint src = OPER_AY_PI_16();\r
4308 uint dst = OPER_AX_PI_16();\r
4309 uint res = dst - src;\r
4310\r
4311 FLAG_N = NFLAG_16(res);\r
4312 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
4313 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
4314 FLAG_C = CFLAG_16(res);\r
4315}\r
4316\r
4317\r
4318M68KMAKE_OP(cmpm, 32, ., .)\r
4319{\r
4320 uint src = OPER_AY_PI_32();\r
4321 uint dst = OPER_AX_PI_32();\r
4322 uint res = dst - src;\r
4323\r
4324 FLAG_N = NFLAG_32(res);\r
4325 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4326 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4327 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4328}\r
4329\r
4330\r
4331M68KMAKE_OP(cpbcc, 32, ., .)\r
4332{\r
4333 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4334 {\r
4335 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",\r
4336 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,\r
4337 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));\r
4338 return;\r
4339 }\r
4340 m68ki_exception_1111();\r
4341}\r
4342\r
4343\r
4344M68KMAKE_OP(cpdbcc, 32, ., .)\r
4345{\r
4346 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4347 {\r
4348 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",\r
4349 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,\r
4350 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));\r
4351 return;\r
4352 }\r
4353 m68ki_exception_1111();\r
4354}\r
4355\r
4356\r
4357M68KMAKE_OP(cpgen, 32, ., .)\r
4358{\r
4359 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4360 {\r
4361 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",\r
4362 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,\r
4363 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));\r
4364 return;\r
4365 }\r
4366 m68ki_exception_1111();\r
4367}\r
4368\r
4369\r
4370M68KMAKE_OP(cpscc, 32, ., .)\r
4371{\r
4372 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4373 {\r
4374 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",\r
4375 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,\r
4376 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));\r
4377 return;\r
4378 }\r
4379 m68ki_exception_1111();\r
4380}\r
4381\r
4382\r
4383M68KMAKE_OP(cptrapcc, 32, ., .)\r
4384{\r
4385 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4386 {\r
4387 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",\r
4388 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,\r
4389 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));\r
4390 return;\r
4391 }\r
4392 m68ki_exception_1111();\r
4393}\r
4394\r
4395\r
4396M68KMAKE_OP(dbt, 16, ., .)\r
4397{\r
4398 REG_PC += 2;\r
4399}\r
4400\r
4401\r
4402M68KMAKE_OP(dbf, 16, ., .)\r
4403{\r
4404 uint* r_dst = &DY;\r
4405 uint res = MASK_OUT_ABOVE_16(*r_dst - 1);\r
4406\r
4407 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
4408 if(res != 0xffff)\r
4409 {\r
4410 uint offset = OPER_I_16();\r
4411 REG_PC -= 2;\r
4412 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
4413 m68ki_branch_16(offset);\r
4414 USE_CYCLES(CYC_DBCC_F_NOEXP);\r
4415 return;\r
4416 }\r
4417 REG_PC += 2;\r
4418 USE_CYCLES(CYC_DBCC_F_EXP);\r
4419}\r
4420\r
4421\r
4422M68KMAKE_OP(dbcc, 16, ., .)\r
4423{\r
4424 if(M68KMAKE_NOT_CC)\r
4425 {\r
4426 uint* r_dst = &DY;\r
4427 uint res = MASK_OUT_ABOVE_16(*r_dst - 1);\r
4428\r
4429 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
4430 if(res != 0xffff)\r
4431 {\r
4432 uint offset = OPER_I_16();\r
4433 REG_PC -= 2;\r
4434 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
4435 m68ki_branch_16(offset);\r
4436 USE_CYCLES(CYC_DBCC_F_NOEXP);\r
4437 return;\r
4438 }\r
4439 REG_PC += 2;\r
4440 USE_CYCLES(CYC_DBCC_F_EXP);\r
4441 return;\r
4442 }\r
4443 REG_PC += 2;\r
4444}\r
4445\r
4446\r
4447M68KMAKE_OP(divs, 16, ., d)\r
4448{\r
4449 uint* r_dst = &DX;\r
4450 sint src = MAKE_INT_16(DY);\r
4451 sint quotient;\r
4452 sint remainder;\r
4453\r
4454 if(src != 0)\r
4455 {\r
4456 if((uint32)*r_dst == 0x80000000 && src == -1)\r
4457 {\r
4458 FLAG_Z = 0;\r
4459 FLAG_N = NFLAG_CLEAR;\r
4460 FLAG_V = VFLAG_CLEAR;\r
4461 FLAG_C = CFLAG_CLEAR;\r
4462 *r_dst = 0;\r
4463 return;\r
4464 }\r
4465\r
4466 quotient = MAKE_INT_32(*r_dst) / src;\r
4467 remainder = MAKE_INT_32(*r_dst) % src;\r
4468\r
4469 if(quotient == MAKE_INT_16(quotient))\r
4470 {\r
4471 FLAG_Z = quotient;\r
4472 FLAG_N = NFLAG_16(quotient);\r
4473 FLAG_V = VFLAG_CLEAR;\r
4474 FLAG_C = CFLAG_CLEAR;\r
4475 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));\r
4476 return;\r
4477 }\r
4478 FLAG_V = VFLAG_SET;\r
4479 return;\r
4480 }\r
4481 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);\r
4482}\r
4483\r
4484\r
4485M68KMAKE_OP(divs, 16, ., .)\r
4486{\r
4487 uint* r_dst = &DX;\r
4488 sint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);\r
4489 sint quotient;\r
4490 sint remainder;\r
4491\r
4492 if(src != 0)\r
4493 {\r
4494 if((uint32)*r_dst == 0x80000000 && src == -1)\r
4495 {\r
4496 FLAG_Z = 0;\r
4497 FLAG_N = NFLAG_CLEAR;\r
4498 FLAG_V = VFLAG_CLEAR;\r
4499 FLAG_C = CFLAG_CLEAR;\r
4500 *r_dst = 0;\r
4501 return;\r
4502 }\r
4503\r
4504 quotient = MAKE_INT_32(*r_dst) / src;\r
4505 remainder = MAKE_INT_32(*r_dst) % src;\r
4506\r
4507 if(quotient == MAKE_INT_16(quotient))\r
4508 {\r
4509 FLAG_Z = quotient;\r
4510 FLAG_N = NFLAG_16(quotient);\r
4511 FLAG_V = VFLAG_CLEAR;\r
4512 FLAG_C = CFLAG_CLEAR;\r
4513 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));\r
4514 return;\r
4515 }\r
4516 FLAG_V = VFLAG_SET;\r
4517 return;\r
4518 }\r
4519 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);\r
4520}\r
4521\r
4522\r
4523M68KMAKE_OP(divu, 16, ., d)\r
4524{\r
4525 uint* r_dst = &DX;\r
4526 uint src = MASK_OUT_ABOVE_16(DY);\r
4527\r
4528 if(src != 0)\r
4529 {\r
4530 uint quotient = *r_dst / src;\r
4531 uint remainder = *r_dst % src;\r
4532\r
4533 if(quotient < 0x10000)\r
4534 {\r
4535 FLAG_Z = quotient;\r
4536 FLAG_N = NFLAG_16(quotient);\r
4537 FLAG_V = VFLAG_CLEAR;\r
4538 FLAG_C = CFLAG_CLEAR;\r
4539 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));\r
4540 return;\r
4541 }\r
4542 FLAG_V = VFLAG_SET;\r
4543 return;\r
4544 }\r
4545 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);\r
4546}\r
4547\r
4548\r
4549M68KMAKE_OP(divu, 16, ., .)\r
4550{\r
4551 uint* r_dst = &DX;\r
4552 uint src = M68KMAKE_GET_OPER_AY_16;\r
4553\r
4554 if(src != 0)\r
4555 {\r
4556 uint quotient = *r_dst / src;\r
4557 uint remainder = *r_dst % src;\r
4558\r
4559 if(quotient < 0x10000)\r
4560 {\r
4561 FLAG_Z = quotient;\r
4562 FLAG_N = NFLAG_16(quotient);\r
4563 FLAG_V = VFLAG_CLEAR;\r
4564 FLAG_C = CFLAG_CLEAR;\r
4565 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));\r
4566 return;\r
4567 }\r
4568 FLAG_V = VFLAG_SET;\r
4569 return;\r
4570 }\r
4571 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);\r
4572}\r
4573\r
4574\r
4575M68KMAKE_OP(divl, 32, ., d)\r
4576{\r
4577#if M68K_USE_64_BIT\r
4578\r
4579 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4580 {\r
4581 uint word2 = OPER_I_16();\r
4582 uint64 divisor = DY;\r
4583 uint64 dividend = 0;\r
4584 uint64 quotient = 0;\r
4585 uint64 remainder = 0;\r
4586\r
4587 if(divisor != 0)\r
4588 {\r
4589 if(BIT_A(word2)) /* 64 bit */\r
4590 {\r
4591 dividend = REG_D[word2 & 7];\r
4592 dividend <<= 32;\r
4593 dividend |= REG_D[(word2 >> 12) & 7];\r
4594\r
4595 if(BIT_B(word2)) /* signed */\r
4596 {\r
4597 quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor));\r
4598 remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));\r
4599 if((sint64)quotient != (sint64)((sint32)quotient))\r
4600 {\r
4601 FLAG_V = VFLAG_SET;\r
4602 return;\r
4603 }\r
4604 }\r
4605 else /* unsigned */\r
4606 {\r
4607 quotient = dividend / divisor;\r
4608 if(quotient > 0xffffffff)\r
4609 {\r
4610 FLAG_V = VFLAG_SET;\r
4611 return;\r
4612 }\r
4613 remainder = dividend % divisor;\r
4614 }\r
4615 }\r
4616 else /* 32 bit */\r
4617 {\r
4618 dividend = REG_D[(word2 >> 12) & 7];\r
4619 if(BIT_B(word2)) /* signed */\r
4620 {\r
4621 quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));\r
4622 remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));\r
4623 }\r
4624 else /* unsigned */\r
4625 {\r
4626 quotient = dividend / divisor;\r
4627 remainder = dividend % divisor;\r
4628 }\r
4629 }\r
4630\r
4631 REG_D[word2 & 7] = remainder;\r
4632 REG_D[(word2 >> 12) & 7] = quotient;\r
4633\r
4634 FLAG_N = NFLAG_32(quotient);\r
4635 FLAG_Z = quotient;\r
4636 FLAG_V = VFLAG_CLEAR;\r
4637 FLAG_C = CFLAG_CLEAR;\r
4638 return;\r
4639 }\r
4640 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);\r
4641 return;\r
4642 }\r
4643 m68ki_exception_illegal();\r
4644\r
4645#else\r
4646\r
4647 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4648 {\r
4649 uint word2 = OPER_I_16();\r
4650 uint divisor = DY;\r
4651 uint dividend_hi = REG_D[word2 & 7];\r
4652 uint dividend_lo = REG_D[(word2 >> 12) & 7];\r
4653 uint quotient = 0;\r
4654 uint remainder = 0;\r
4655 uint dividend_neg = 0;\r
4656 uint divisor_neg = 0;\r
4657 sint i;\r
4658 uint overflow;\r
4659\r
4660 if(divisor != 0)\r
4661 {\r
4662 /* quad / long : long quotient, long remainder */\r
4663 if(BIT_A(word2))\r
4664 {\r
4665 if(BIT_B(word2)) /* signed */\r
4666 {\r
4667 /* special case in signed divide */\r
4668 if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)\r
4669 {\r
4670 REG_D[word2 & 7] = 0;\r
4671 REG_D[(word2 >> 12) & 7] = 0x80000000;\r
4672\r
4673 FLAG_N = NFLAG_SET;\r
4674 FLAG_Z = ZFLAG_CLEAR;\r
4675 FLAG_V = VFLAG_CLEAR;\r
4676 FLAG_C = CFLAG_CLEAR;\r
4677 return;\r
4678 }\r
4679 if(GET_MSB_32(dividend_hi))\r
4680 {\r
4681 dividend_neg = 1;\r
4682 dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));\r
4683 dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);\r
4684 }\r
4685 if(GET_MSB_32(divisor))\r
4686 {\r
4687 divisor_neg = 1;\r
4688 divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);\r
4689\r
4690 }\r
4691 }\r
4692\r
4693 /* if the upper long is greater than the divisor, we're overflowing. */\r
4694 if(dividend_hi >= divisor)\r
4695 {\r
4696 FLAG_V = VFLAG_SET;\r
4697 return;\r
4698 }\r
4699\r
4700 for(i = 31; i >= 0; i--)\r
4701 {\r
4702 quotient <<= 1;\r
4703 remainder = (remainder << 1) + ((dividend_hi >> i) & 1);\r
4704 if(remainder >= divisor)\r
4705 {\r
4706 remainder -= divisor;\r
4707 quotient++;\r
4708 }\r
4709 }\r
4710 for(i = 31; i >= 0; i--)\r
4711 {\r
4712 quotient <<= 1;\r
4713 overflow = GET_MSB_32(remainder);\r
4714 remainder = (remainder << 1) + ((dividend_lo >> i) & 1);\r
4715 if(remainder >= divisor || overflow)\r
4716 {\r
4717 remainder -= divisor;\r
4718 quotient++;\r
4719 }\r
4720 }\r
4721\r
4722 if(BIT_B(word2)) /* signed */\r
4723 {\r
4724 if(quotient > 0x7fffffff)\r
4725 {\r
4726 FLAG_V = VFLAG_SET;\r
4727 return;\r
4728 }\r
4729 if(dividend_neg)\r
4730 {\r
4731 remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);\r
4732 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);\r
4733 }\r
4734 if(divisor_neg)\r
4735 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);\r
4736 }\r
4737\r
4738 REG_D[word2 & 7] = remainder;\r
4739 REG_D[(word2 >> 12) & 7] = quotient;\r
4740\r
4741 FLAG_N = NFLAG_32(quotient);\r
4742 FLAG_Z = quotient;\r
4743 FLAG_V = VFLAG_CLEAR;\r
4744 FLAG_C = CFLAG_CLEAR;\r
4745 return;\r
4746 }\r
4747\r
4748 /* long / long: long quotient, maybe long remainder */\r
4749 if(BIT_B(word2)) /* signed */\r
4750 {\r
4751 /* Special case in divide */\r
4752 if(dividend_lo == 0x80000000 && divisor == 0xffffffff)\r
4753 {\r
4754 FLAG_N = NFLAG_SET;\r
4755 FLAG_Z = ZFLAG_CLEAR;\r
4756 FLAG_V = VFLAG_CLEAR;\r
4757 FLAG_C = CFLAG_CLEAR;\r
4758 REG_D[(word2 >> 12) & 7] = 0x80000000;\r
4759 REG_D[word2 & 7] = 0;\r
4760 return;\r
4761 }\r
4762 REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);\r
4763 quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);\r
4764 }\r
4765 else\r
4766 {\r
4767 REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);\r
4768 quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);\r
4769 }\r
4770\r
4771 FLAG_N = NFLAG_32(quotient);\r
4772 FLAG_Z = quotient;\r
4773 FLAG_V = VFLAG_CLEAR;\r
4774 FLAG_C = CFLAG_CLEAR;\r
4775 return;\r
4776 }\r
4777 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);\r
4778 return;\r
4779 }\r
4780 m68ki_exception_illegal();\r
4781\r
4782#endif\r
4783}\r
4784\r
4785\r
4786M68KMAKE_OP(divl, 32, ., .)\r
4787{\r
4788#if M68K_USE_64_BIT\r
4789\r
4790 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4791 {\r
4792 uint word2 = OPER_I_16();\r
4793 uint64 divisor = M68KMAKE_GET_OPER_AY_32;\r
4794 uint64 dividend = 0;\r
4795 uint64 quotient = 0;\r
4796 uint64 remainder = 0;\r
4797\r
4798 if(divisor != 0)\r
4799 {\r
4800 if(BIT_A(word2)) /* 64 bit */\r
4801 {\r
4802 dividend = REG_D[word2 & 7];\r
4803 dividend <<= 32;\r
4804 dividend |= REG_D[(word2 >> 12) & 7];\r
4805\r
4806 if(BIT_B(word2)) /* signed */\r
4807 {\r
4808 quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor));\r
4809 remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));\r
4810 if((sint64)quotient != (sint64)((sint32)quotient))\r
4811 {\r
4812 FLAG_V = VFLAG_SET;\r
4813 return;\r
4814 }\r
4815 }\r
4816 else /* unsigned */\r
4817 {\r
4818 quotient = dividend / divisor;\r
4819 if(quotient > 0xffffffff)\r
4820 {\r
4821 FLAG_V = VFLAG_SET;\r
4822 return;\r
4823 }\r
4824 remainder = dividend % divisor;\r
4825 }\r
4826 }\r
4827 else /* 32 bit */\r
4828 {\r
4829 dividend = REG_D[(word2 >> 12) & 7];\r
4830 if(BIT_B(word2)) /* signed */\r
4831 {\r
4832 quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));\r
4833 remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));\r
4834 }\r
4835 else /* unsigned */\r
4836 {\r
4837 quotient = dividend / divisor;\r
4838 remainder = dividend % divisor;\r
4839 }\r
4840 }\r
4841\r
4842 REG_D[word2 & 7] = remainder;\r
4843 REG_D[(word2 >> 12) & 7] = quotient;\r
4844\r
4845 FLAG_N = NFLAG_32(quotient);\r
4846 FLAG_Z = quotient;\r
4847 FLAG_V = VFLAG_CLEAR;\r
4848 FLAG_C = CFLAG_CLEAR;\r
4849 return;\r
4850 }\r
4851 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);\r
4852 return;\r
4853 }\r
4854 m68ki_exception_illegal();\r
4855\r
4856#else\r
4857\r
4858 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4859 {\r
4860 uint word2 = OPER_I_16();\r
4861 uint divisor = M68KMAKE_GET_OPER_AY_32;\r
4862 uint dividend_hi = REG_D[word2 & 7];\r
4863 uint dividend_lo = REG_D[(word2 >> 12) & 7];\r
4864 uint quotient = 0;\r
4865 uint remainder = 0;\r
4866 uint dividend_neg = 0;\r
4867 uint divisor_neg = 0;\r
4868 sint i;\r
4869 uint overflow;\r
4870\r
4871 if(divisor != 0)\r
4872 {\r
4873 /* quad / long : long quotient, long remainder */\r
4874 if(BIT_A(word2))\r
4875 {\r
4876 if(BIT_B(word2)) /* signed */\r
4877 {\r
4878 /* special case in signed divide */\r
4879 if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)\r
4880 {\r
4881 REG_D[word2 & 7] = 0;\r
4882 REG_D[(word2 >> 12) & 7] = 0x80000000;\r
4883\r
4884 FLAG_N = NFLAG_SET;\r
4885 FLAG_Z = ZFLAG_CLEAR;\r
4886 FLAG_V = VFLAG_CLEAR;\r
4887 FLAG_C = CFLAG_CLEAR;\r
4888 return;\r
4889 }\r
4890 if(GET_MSB_32(dividend_hi))\r
4891 {\r
4892 dividend_neg = 1;\r
4893 dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));\r
4894 dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);\r
4895 }\r
4896 if(GET_MSB_32(divisor))\r
4897 {\r
4898 divisor_neg = 1;\r
4899 divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);\r
4900\r
4901 }\r
4902 }\r
4903\r
4904 /* if the upper long is greater than the divisor, we're overflowing. */\r
4905 if(dividend_hi >= divisor)\r
4906 {\r
4907 FLAG_V = VFLAG_SET;\r
4908 return;\r
4909 }\r
4910\r
4911 for(i = 31; i >= 0; i--)\r
4912 {\r
4913 quotient <<= 1;\r
4914 remainder = (remainder << 1) + ((dividend_hi >> i) & 1);\r
4915 if(remainder >= divisor)\r
4916 {\r
4917 remainder -= divisor;\r
4918 quotient++;\r
4919 }\r
4920 }\r
4921 for(i = 31; i >= 0; i--)\r
4922 {\r
4923 quotient <<= 1;\r
4924 overflow = GET_MSB_32(remainder);\r
4925 remainder = (remainder << 1) + ((dividend_lo >> i) & 1);\r
4926 if(remainder >= divisor || overflow)\r
4927 {\r
4928 remainder -= divisor;\r
4929 quotient++;\r
4930 }\r
4931 }\r
4932\r
4933 if(BIT_B(word2)) /* signed */\r
4934 {\r
4935 if(quotient > 0x7fffffff)\r
4936 {\r
4937 FLAG_V = VFLAG_SET;\r
4938 return;\r
4939 }\r
4940 if(dividend_neg)\r
4941 {\r
4942 remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);\r
4943 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);\r
4944 }\r
4945 if(divisor_neg)\r
4946 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);\r
4947 }\r
4948\r
4949 REG_D[word2 & 7] = remainder;\r
4950 REG_D[(word2 >> 12) & 7] = quotient;\r
4951\r
4952 FLAG_N = NFLAG_32(quotient);\r
4953 FLAG_Z = quotient;\r
4954 FLAG_V = VFLAG_CLEAR;\r
4955 FLAG_C = CFLAG_CLEAR;\r
4956 return;\r
4957 }\r
4958\r
4959 /* long / long: long quotient, maybe long remainder */\r
4960 if(BIT_B(word2)) /* signed */\r
4961 {\r
4962 /* Special case in divide */\r
4963 if(dividend_lo == 0x80000000 && divisor == 0xffffffff)\r
4964 {\r
4965 FLAG_N = NFLAG_SET;\r
4966 FLAG_Z = ZFLAG_CLEAR;\r
4967 FLAG_V = VFLAG_CLEAR;\r
4968 FLAG_C = CFLAG_CLEAR;\r
4969 REG_D[(word2 >> 12) & 7] = 0x80000000;\r
4970 REG_D[word2 & 7] = 0;\r
4971 return;\r
4972 }\r
4973 REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);\r
4974 quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);\r
4975 }\r
4976 else\r
4977 {\r
4978 REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);\r
4979 quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);\r
4980 }\r
4981\r
4982 FLAG_N = NFLAG_32(quotient);\r
4983 FLAG_Z = quotient;\r
4984 FLAG_V = VFLAG_CLEAR;\r
4985 FLAG_C = CFLAG_CLEAR;\r
4986 return;\r
4987 }\r
4988 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);\r
4989 return;\r
4990 }\r
4991 m68ki_exception_illegal();\r
4992\r
4993#endif\r
4994}\r
4995\r
4996\r
4997M68KMAKE_OP(eor, 8, ., d)\r
4998{\r
4999 uint res = MASK_OUT_ABOVE_8(DY ^= MASK_OUT_ABOVE_8(DX));\r
5000\r
5001 FLAG_N = NFLAG_8(res);\r
5002 FLAG_Z = res;\r
5003 FLAG_C = CFLAG_CLEAR;\r
5004 FLAG_V = VFLAG_CLEAR;\r
5005}\r
5006\r
5007\r
5008M68KMAKE_OP(eor, 8, ., .)\r
5009{\r
5010 uint ea = M68KMAKE_GET_EA_AY_8;\r
5011 uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));\r
5012\r
5013 m68ki_write_8(ea, res);\r
5014\r
5015 FLAG_N = NFLAG_8(res);\r
5016 FLAG_Z = res;\r
5017 FLAG_C = CFLAG_CLEAR;\r
5018 FLAG_V = VFLAG_CLEAR;\r
5019}\r
5020\r
5021\r
5022M68KMAKE_OP(eor, 16, ., d)\r
5023{\r
5024 uint res = MASK_OUT_ABOVE_16(DY ^= MASK_OUT_ABOVE_16(DX));\r
5025\r
5026 FLAG_N = NFLAG_16(res);\r
5027 FLAG_Z = res;\r
5028 FLAG_C = CFLAG_CLEAR;\r
5029 FLAG_V = VFLAG_CLEAR;\r
5030}\r
5031\r
5032\r
5033M68KMAKE_OP(eor, 16, ., .)\r
5034{\r
5035 uint ea = M68KMAKE_GET_EA_AY_16;\r
5036 uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea));\r
5037\r
5038 m68ki_write_16(ea, res);\r
5039\r
5040 FLAG_N = NFLAG_16(res);\r
5041 FLAG_Z = res;\r
5042 FLAG_C = CFLAG_CLEAR;\r
5043 FLAG_V = VFLAG_CLEAR;\r
5044}\r
5045\r
5046\r
5047M68KMAKE_OP(eor, 32, ., d)\r
5048{\r
5049 uint res = DY ^= DX;\r
5050\r
5051 FLAG_N = NFLAG_32(res);\r
5052 FLAG_Z = res;\r
5053 FLAG_C = CFLAG_CLEAR;\r
5054 FLAG_V = VFLAG_CLEAR;\r
5055}\r
5056\r
5057\r
5058M68KMAKE_OP(eor, 32, ., .)\r
5059{\r
5060 uint ea = M68KMAKE_GET_EA_AY_32;\r
5061 uint res = DX ^ m68ki_read_32(ea);\r
5062\r
5063 m68ki_write_32(ea, res);\r
5064\r
5065 FLAG_N = NFLAG_32(res);\r
5066 FLAG_Z = res;\r
5067 FLAG_C = CFLAG_CLEAR;\r
5068 FLAG_V = VFLAG_CLEAR;\r
5069}\r
5070\r
5071\r
5072M68KMAKE_OP(eori, 8, ., d)\r
5073{\r
5074 uint res = MASK_OUT_ABOVE_8(DY ^= OPER_I_8());\r
5075\r
5076 FLAG_N = NFLAG_8(res);\r
5077 FLAG_Z = res;\r
5078 FLAG_C = CFLAG_CLEAR;\r
5079 FLAG_V = VFLAG_CLEAR;\r
5080}\r
5081\r
5082\r
5083M68KMAKE_OP(eori, 8, ., .)\r
5084{\r
5085 uint src = OPER_I_8();\r
5086 uint ea = M68KMAKE_GET_EA_AY_8;\r
5087 uint res = src ^ m68ki_read_8(ea);\r
5088\r
5089 m68ki_write_8(ea, res);\r
5090\r
5091 FLAG_N = NFLAG_8(res);\r
5092 FLAG_Z = res;\r
5093 FLAG_C = CFLAG_CLEAR;\r
5094 FLAG_V = VFLAG_CLEAR;\r
5095}\r
5096\r
5097\r
5098M68KMAKE_OP(eori, 16, ., d)\r
5099{\r
5100 uint res = MASK_OUT_ABOVE_16(DY ^= OPER_I_16());\r
5101\r
5102 FLAG_N = NFLAG_16(res);\r
5103 FLAG_Z = res;\r
5104 FLAG_C = CFLAG_CLEAR;\r
5105 FLAG_V = VFLAG_CLEAR;\r
5106}\r
5107\r
5108\r
5109M68KMAKE_OP(eori, 16, ., .)\r
5110{\r
5111 uint src = OPER_I_16();\r
5112 uint ea = M68KMAKE_GET_EA_AY_16;\r
5113 uint res = src ^ m68ki_read_16(ea);\r
5114\r
5115 m68ki_write_16(ea, res);\r
5116\r
5117 FLAG_N = NFLAG_16(res);\r
5118 FLAG_Z = res;\r
5119 FLAG_C = CFLAG_CLEAR;\r
5120 FLAG_V = VFLAG_CLEAR;\r
5121}\r
5122\r
5123\r
5124M68KMAKE_OP(eori, 32, ., d)\r
5125{\r
5126 uint res = DY ^= OPER_I_32();\r
5127\r
5128 FLAG_N = NFLAG_32(res);\r
5129 FLAG_Z = res;\r
5130 FLAG_C = CFLAG_CLEAR;\r
5131 FLAG_V = VFLAG_CLEAR;\r
5132}\r
5133\r
5134\r
5135M68KMAKE_OP(eori, 32, ., .)\r
5136{\r
5137 uint src = OPER_I_32();\r
5138 uint ea = M68KMAKE_GET_EA_AY_32;\r
5139 uint res = src ^ m68ki_read_32(ea);\r
5140\r
5141 m68ki_write_32(ea, res);\r
5142\r
5143 FLAG_N = NFLAG_32(res);\r
5144 FLAG_Z = res;\r
5145 FLAG_C = CFLAG_CLEAR;\r
5146 FLAG_V = VFLAG_CLEAR;\r
5147}\r
5148\r
5149\r
5150M68KMAKE_OP(eori, 16, toc, .)\r
5151{\r
5152 m68ki_set_ccr(m68ki_get_ccr() ^ OPER_I_16());\r
5153}\r
5154\r
5155\r
5156M68KMAKE_OP(eori, 16, tos, .)\r
5157{\r
5158 if(FLAG_S)\r
5159 {\r
5160 uint src = OPER_I_16();\r
5161 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
5162 m68ki_set_sr(m68ki_get_sr() ^ src);\r
5163 return;\r
5164 }\r
5165 m68ki_exception_privilege_violation();\r
5166}\r
5167\r
5168\r
5169M68KMAKE_OP(exg, 32, dd, .)\r
5170{\r
5171 uint* reg_a = &DX;\r
5172 uint* reg_b = &DY;\r
5173 uint tmp = *reg_a;\r
5174 *reg_a = *reg_b;\r
5175 *reg_b = tmp;\r
5176}\r
5177\r
5178\r
5179M68KMAKE_OP(exg, 32, aa, .)\r
5180{\r
5181 uint* reg_a = &AX;\r
5182 uint* reg_b = &AY;\r
5183 uint tmp = *reg_a;\r
5184 *reg_a = *reg_b;\r
5185 *reg_b = tmp;\r
5186}\r
5187\r
5188\r
5189M68KMAKE_OP(exg, 32, da, .)\r
5190{\r
5191 uint* reg_a = &DX;\r
5192 uint* reg_b = &AY;\r
5193 uint tmp = *reg_a;\r
5194 *reg_a = *reg_b;\r
5195 *reg_b = tmp;\r
5196}\r
5197\r
5198\r
5199M68KMAKE_OP(ext, 16, ., .)\r
5200{\r
5201 uint* r_dst = &DY;\r
5202\r
5203 *r_dst = MASK_OUT_BELOW_16(*r_dst) | MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xff00 : 0);\r
5204\r
5205 FLAG_N = NFLAG_16(*r_dst);\r
5206 FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);\r
5207 FLAG_V = VFLAG_CLEAR;\r
5208 FLAG_C = CFLAG_CLEAR;\r
5209}\r
5210\r
5211\r
5212M68KMAKE_OP(ext, 32, ., .)\r
5213{\r
5214 uint* r_dst = &DY;\r
5215\r
5216 *r_dst = MASK_OUT_ABOVE_16(*r_dst) | (GET_MSB_16(*r_dst) ? 0xffff0000 : 0);\r
5217\r
5218 FLAG_N = NFLAG_32(*r_dst);\r
5219 FLAG_Z = *r_dst;\r
5220 FLAG_V = VFLAG_CLEAR;\r
5221 FLAG_C = CFLAG_CLEAR;\r
5222}\r
5223\r
5224\r
5225M68KMAKE_OP(extb, 32, ., .)\r
5226{\r
5227 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
5228 {\r
5229 uint* r_dst = &DY;\r
5230\r
5231 *r_dst = MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xffffff00 : 0);\r
5232\r
5233 FLAG_N = NFLAG_32(*r_dst);\r
5234 FLAG_Z = *r_dst;\r
5235 FLAG_V = VFLAG_CLEAR;\r
5236 FLAG_C = CFLAG_CLEAR;\r
5237 return;\r
5238 }\r
5239 m68ki_exception_illegal();\r
5240}\r
5241\r
5242\r
5243M68KMAKE_OP(illegal, 0, ., .)\r
5244{\r
5245 m68ki_exception_illegal();\r
5246}\r
5247\r
5248M68KMAKE_OP(jmp, 32, ., .)\r
5249{\r
5250 m68ki_jump(M68KMAKE_GET_EA_AY_32);\r
5251 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
5252 if(REG_PC == REG_PPC)\r
5253 USE_ALL_CYCLES();\r
5254}\r
5255\r
5256\r
5257M68KMAKE_OP(jsr, 32, ., .)\r
5258{\r
5259 uint ea = M68KMAKE_GET_EA_AY_32;\r
5260 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
5261 m68ki_push_32(MAKE_INT_24(REG_PC)); // notaz: Cyclone can't handle 32bit PC and I neet to debug it\r
5262 m68ki_jump(ea);\r
5263}\r
5264\r
5265\r
5266M68KMAKE_OP(lea, 32, ., .)\r
5267{\r
5268 AX = M68KMAKE_GET_EA_AY_32;\r
5269}\r
5270\r
5271\r
5272M68KMAKE_OP(link, 16, ., a7)\r
5273{\r
5274 REG_A[7] -= 4;\r
5275 m68ki_write_32(REG_A[7], REG_A[7]);\r
5276 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));\r
5277}\r
5278\r
5279\r
5280M68KMAKE_OP(link, 16, ., .)\r
5281{\r
5282 uint* r_dst = &AY;\r
5283\r
5284 m68ki_push_32(*r_dst);\r
5285 *r_dst = REG_A[7];\r
5286 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));\r
5287}\r
5288\r
5289\r
5290M68KMAKE_OP(link, 32, ., a7)\r
5291{\r
5292 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
5293 {\r
5294 REG_A[7] -= 4;\r
5295 m68ki_write_32(REG_A[7], REG_A[7]);\r
5296 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32());\r
5297 return;\r
5298 }\r
5299 m68ki_exception_illegal();\r
5300}\r
5301\r
5302\r
5303M68KMAKE_OP(link, 32, ., .)\r
5304{\r
5305 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
5306 {\r
5307 uint* r_dst = &AY;\r
5308\r
5309 m68ki_push_32(*r_dst);\r
5310 *r_dst = REG_A[7];\r
5311 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32());\r
5312 return;\r
5313 }\r
5314 m68ki_exception_illegal();\r
5315}\r
5316\r
5317\r
5318M68KMAKE_OP(lsr, 8, s, .)\r
5319{\r
5320 uint* r_dst = &DY;\r
5321 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
5322 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
5323 uint res = src >> shift;\r
5324\r
5325 if(shift != 0)\r
5326 USE_CYCLES(shift<<CYC_SHIFT);\r
5327\r
5328 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
5329\r
5330 FLAG_N = NFLAG_CLEAR;\r
5331 FLAG_Z = res;\r
5332 FLAG_X = FLAG_C = src << (9-shift);\r
5333 FLAG_V = VFLAG_CLEAR;\r
5334}\r
5335\r
5336\r
5337M68KMAKE_OP(lsr, 16, s, .)\r
5338{\r
5339 uint* r_dst = &DY;\r
5340 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
5341 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
5342 uint res = src >> shift;\r
5343\r
5344 if(shift != 0)\r
5345 USE_CYCLES(shift<<CYC_SHIFT);\r
5346\r
5347 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
5348\r
5349 FLAG_N = NFLAG_CLEAR;\r
5350 FLAG_Z = res;\r
5351 FLAG_X = FLAG_C = src << (9-shift);\r
5352 FLAG_V = VFLAG_CLEAR;\r
5353}\r
5354\r
5355\r
5356M68KMAKE_OP(lsr, 32, s, .)\r
5357{\r
5358 uint* r_dst = &DY;\r
5359 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
5360 uint src = *r_dst;\r
5361 uint res = src >> shift;\r
5362\r
5363 if(shift != 0)\r
5364 USE_CYCLES(shift<<CYC_SHIFT);\r
5365\r
5366 *r_dst = res;\r
5367\r
5368 FLAG_N = NFLAG_CLEAR;\r
5369 FLAG_Z = res;\r
5370 FLAG_X = FLAG_C = src << (9-shift);\r
5371 FLAG_V = VFLAG_CLEAR;\r
5372}\r
5373\r
5374\r
5375M68KMAKE_OP(lsr, 8, r, .)\r
5376{\r
5377 uint* r_dst = &DY;\r
5378 uint shift = DX & 0x3f;\r
5379 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
5380 uint res = src >> shift;\r
5381\r
5382 if(shift != 0)\r
5383 {\r
5384 USE_CYCLES(shift<<CYC_SHIFT);\r
5385\r
5386 if(shift <= 8)\r
5387 {\r
5388 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
5389 FLAG_X = FLAG_C = src << (9-shift);\r
5390 FLAG_N = NFLAG_CLEAR;\r
5391 FLAG_Z = res;\r
5392 FLAG_V = VFLAG_CLEAR;\r
5393 return;\r
5394 }\r
5395\r
5396 *r_dst &= 0xffffff00;\r
5397 FLAG_X = XFLAG_CLEAR;\r
5398 FLAG_C = CFLAG_CLEAR;\r
5399 FLAG_N = NFLAG_CLEAR;\r
5400 FLAG_Z = ZFLAG_SET;\r
5401 FLAG_V = VFLAG_CLEAR;\r
5402 return;\r
5403 }\r
5404\r
5405 FLAG_C = CFLAG_CLEAR;\r
5406 FLAG_N = NFLAG_8(src);\r
5407 FLAG_Z = src;\r
5408 FLAG_V = VFLAG_CLEAR;\r
5409}\r
5410\r
5411\r
5412M68KMAKE_OP(lsr, 16, r, .)\r
5413{\r
5414 uint* r_dst = &DY;\r
5415 uint shift = DX & 0x3f;\r
5416 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
5417 uint res = src >> shift;\r
5418\r
5419 if(shift != 0)\r
5420 {\r
5421 USE_CYCLES(shift<<CYC_SHIFT);\r
5422\r
5423 if(shift <= 16)\r
5424 {\r
5425 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
5426 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;\r
5427 FLAG_N = NFLAG_CLEAR;\r
5428 FLAG_Z = res;\r
5429 FLAG_V = VFLAG_CLEAR;\r
5430 return;\r
5431 }\r
5432\r
5433 *r_dst &= 0xffff0000;\r
5434 FLAG_X = XFLAG_CLEAR;\r
5435 FLAG_C = CFLAG_CLEAR;\r
5436 FLAG_N = NFLAG_CLEAR;\r
5437 FLAG_Z = ZFLAG_SET;\r
5438 FLAG_V = VFLAG_CLEAR;\r
5439 return;\r
5440 }\r
5441\r
5442 FLAG_C = CFLAG_CLEAR;\r
5443 FLAG_N = NFLAG_16(src);\r
5444 FLAG_Z = src;\r
5445 FLAG_V = VFLAG_CLEAR;\r
5446}\r
5447\r
5448\r
5449M68KMAKE_OP(lsr, 32, r, .)\r
5450{\r
5451 uint* r_dst = &DY;\r
5452 uint shift = DX & 0x3f;\r
5453 uint src = *r_dst;\r
5454 uint res = src >> shift;\r
5455\r
5456 if(shift != 0)\r
5457 {\r
5458 USE_CYCLES(shift<<CYC_SHIFT);\r
5459\r
5460 if(shift < 32)\r
5461 {\r
5462 *r_dst = res;\r
5463 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;\r
5464 FLAG_N = NFLAG_CLEAR;\r
5465 FLAG_Z = res;\r
5466 FLAG_V = VFLAG_CLEAR;\r
5467 return;\r
5468 }\r
5469\r
5470 *r_dst = 0;\r
5471 FLAG_X = FLAG_C = (shift == 32 ? GET_MSB_32(src)>>23 : 0);\r
5472 FLAG_N = NFLAG_CLEAR;\r
5473 FLAG_Z = ZFLAG_SET;\r
5474 FLAG_V = VFLAG_CLEAR;\r
5475 return;\r
5476 }\r
5477\r
5478 FLAG_C = CFLAG_CLEAR;\r
5479 FLAG_N = NFLAG_32(src);\r
5480 FLAG_Z = src;\r
5481 FLAG_V = VFLAG_CLEAR;\r
5482}\r
5483\r
5484\r
5485M68KMAKE_OP(lsr, 16, ., .)\r
5486{\r
5487 uint ea = M68KMAKE_GET_EA_AY_16;\r
5488 uint src = m68ki_read_16(ea);\r
5489 uint res = src >> 1;\r
5490\r
5491 m68ki_write_16(ea, res);\r
5492\r
5493 FLAG_N = NFLAG_CLEAR;\r
5494 FLAG_Z = res;\r
5495 FLAG_C = FLAG_X = src << 8;\r
5496 FLAG_V = VFLAG_CLEAR;\r
5497}\r
5498\r
5499\r
5500M68KMAKE_OP(lsl, 8, s, .)\r
5501{\r
5502 uint* r_dst = &DY;\r
5503 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
5504 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
5505 uint res = MASK_OUT_ABOVE_8(src << shift);\r
5506\r
5507 if(shift != 0)\r
5508 USE_CYCLES(shift<<CYC_SHIFT);\r
5509\r
5510 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
5511\r
5512 FLAG_N = NFLAG_8(res);\r
5513 FLAG_Z = res;\r
5514 FLAG_X = FLAG_C = src << shift;\r
5515 FLAG_V = VFLAG_CLEAR;\r
5516}\r
5517\r
5518\r
5519M68KMAKE_OP(lsl, 16, s, .)\r
5520{\r
5521 uint* r_dst = &DY;\r
5522 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
5523 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
5524 uint res = MASK_OUT_ABOVE_16(src << shift);\r
5525\r
5526 if(shift != 0)\r
5527 USE_CYCLES(shift<<CYC_SHIFT);\r
5528\r
5529 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
5530\r
5531 FLAG_N = NFLAG_16(res);\r
5532 FLAG_Z = res;\r
5533 FLAG_X = FLAG_C = src >> (8-shift);\r
5534 FLAG_V = VFLAG_CLEAR;\r
5535}\r
5536\r
5537\r
5538M68KMAKE_OP(lsl, 32, s, .)\r
5539{\r
5540 uint* r_dst = &DY;\r
5541 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
5542 uint src = *r_dst;\r
5543 uint res = MASK_OUT_ABOVE_32(src << shift);\r
5544\r
5545 if(shift != 0)\r
5546 USE_CYCLES(shift<<CYC_SHIFT);\r
5547\r
5548 *r_dst = res;\r
5549\r
5550 FLAG_N = NFLAG_32(res);\r
5551 FLAG_Z = res;\r
5552 FLAG_X = FLAG_C = src >> (24-shift);\r
5553 FLAG_V = VFLAG_CLEAR;\r
5554}\r
5555\r
5556\r
5557M68KMAKE_OP(lsl, 8, r, .)\r
5558{\r
5559 uint* r_dst = &DY;\r
5560 uint shift = DX & 0x3f;\r
5561 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
5562 uint res = MASK_OUT_ABOVE_8(src << shift);\r
5563\r
5564 if(shift != 0)\r
5565 {\r
5566 USE_CYCLES(shift<<CYC_SHIFT);\r
5567\r
5568 if(shift <= 8)\r
5569 {\r
5570 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
5571 FLAG_X = FLAG_C = src << shift;\r
5572 FLAG_N = NFLAG_8(res);\r
5573 FLAG_Z = res;\r
5574 FLAG_V = VFLAG_CLEAR;\r
5575 return;\r
5576 }\r
5577\r
5578 *r_dst &= 0xffffff00;\r
5579 FLAG_X = XFLAG_CLEAR;\r
5580 FLAG_C = CFLAG_CLEAR;\r
5581 FLAG_N = NFLAG_CLEAR;\r
5582 FLAG_Z = ZFLAG_SET;\r
5583 FLAG_V = VFLAG_CLEAR;\r
5584 return;\r
5585 }\r
5586\r
5587 FLAG_C = CFLAG_CLEAR;\r
5588 FLAG_N = NFLAG_8(src);\r
5589 FLAG_Z = src;\r
5590 FLAG_V = VFLAG_CLEAR;\r
5591}\r
5592\r
5593\r
5594M68KMAKE_OP(lsl, 16, r, .)\r
5595{\r
5596 uint* r_dst = &DY;\r
5597 uint shift = DX & 0x3f;\r
5598 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
5599 uint res = MASK_OUT_ABOVE_16(src << shift);\r
5600\r
5601 if(shift != 0)\r
5602 {\r
5603 USE_CYCLES(shift<<CYC_SHIFT);\r
5604\r
5605 if(shift <= 16)\r
5606 {\r
5607 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
5608 FLAG_X = FLAG_C = (src << shift) >> 8;\r
5609 FLAG_N = NFLAG_16(res);\r
5610 FLAG_Z = res;\r
5611 FLAG_V = VFLAG_CLEAR;\r
5612 return;\r
5613 }\r
5614\r
5615 *r_dst &= 0xffff0000;\r
5616 FLAG_X = XFLAG_CLEAR;\r
5617 FLAG_C = CFLAG_CLEAR;\r
5618 FLAG_N = NFLAG_CLEAR;\r
5619 FLAG_Z = ZFLAG_SET;\r
5620 FLAG_V = VFLAG_CLEAR;\r
5621 return;\r
5622 }\r
5623\r
5624 FLAG_C = CFLAG_CLEAR;\r
5625 FLAG_N = NFLAG_16(src);\r
5626 FLAG_Z = src;\r
5627 FLAG_V = VFLAG_CLEAR;\r
5628}\r
5629\r
5630\r
5631M68KMAKE_OP(lsl, 32, r, .)\r
5632{\r
5633 uint* r_dst = &DY;\r
5634 uint shift = DX & 0x3f;\r
5635 uint src = *r_dst;\r
5636 uint res = MASK_OUT_ABOVE_32(src << shift);\r
5637\r
5638 if(shift != 0)\r
5639 {\r
5640 USE_CYCLES(shift<<CYC_SHIFT);\r
5641\r
5642 if(shift < 32)\r
5643 {\r
5644 *r_dst = res;\r
5645 FLAG_X = FLAG_C = (src >> (32 - shift)) << 8;\r
5646 FLAG_N = NFLAG_32(res);\r
5647 FLAG_Z = res;\r
5648 FLAG_V = VFLAG_CLEAR;\r
5649 return;\r
5650 }\r
5651\r
5652 *r_dst = 0;\r
5653 FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8;\r
5654 FLAG_N = NFLAG_CLEAR;\r
5655 FLAG_Z = ZFLAG_SET;\r
5656 FLAG_V = VFLAG_CLEAR;\r
5657 return;\r
5658 }\r
5659\r
5660 FLAG_C = CFLAG_CLEAR;\r
5661 FLAG_N = NFLAG_32(src);\r
5662 FLAG_Z = src;\r
5663 FLAG_V = VFLAG_CLEAR;\r
5664}\r
5665\r
5666\r
5667M68KMAKE_OP(lsl, 16, ., .)\r
5668{\r
5669 uint ea = M68KMAKE_GET_EA_AY_16;\r
5670 uint src = m68ki_read_16(ea);\r
5671 uint res = MASK_OUT_ABOVE_16(src << 1);\r
5672\r
5673 m68ki_write_16(ea, res);\r
5674\r
5675 FLAG_N = NFLAG_16(res);\r
5676 FLAG_Z = res;\r
5677 FLAG_X = FLAG_C = src >> 7;\r
5678 FLAG_V = VFLAG_CLEAR;\r
5679}\r
5680\r
5681\r
5682M68KMAKE_OP(move, 8, d, d)\r
5683{\r
5684 uint res = MASK_OUT_ABOVE_8(DY);\r
5685 uint* r_dst = &DX;\r
5686\r
5687 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
5688\r
5689 FLAG_N = NFLAG_8(res);\r
5690 FLAG_Z = res;\r
5691 FLAG_V = VFLAG_CLEAR;\r
5692 FLAG_C = CFLAG_CLEAR;\r
5693}\r
5694\r
5695\r
5696M68KMAKE_OP(move, 8, d, .)\r
5697{\r
5698 uint res = M68KMAKE_GET_OPER_AY_8;\r
5699 uint* r_dst = &DX;\r
5700\r
5701 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
5702\r
5703 FLAG_N = NFLAG_8(res);\r
5704 FLAG_Z = res;\r
5705 FLAG_V = VFLAG_CLEAR;\r
5706 FLAG_C = CFLAG_CLEAR;\r
5707}\r
5708\r
5709\r
5710M68KMAKE_OP(move, 8, ai, d)\r
5711{\r
5712 uint res = MASK_OUT_ABOVE_8(DY);\r
5713 uint ea = EA_AX_AI_8();\r
5714\r
5715 m68ki_write_8(ea, res);\r
5716\r
5717 FLAG_N = NFLAG_8(res);\r
5718 FLAG_Z = res;\r
5719 FLAG_V = VFLAG_CLEAR;\r
5720 FLAG_C = CFLAG_CLEAR;\r
5721}\r
5722\r
5723\r
5724M68KMAKE_OP(move, 8, ai, .)\r
5725{\r
5726 uint res = M68KMAKE_GET_OPER_AY_8;\r
5727 uint ea = EA_AX_AI_8();\r
5728\r
5729 m68ki_write_8(ea, res);\r
5730\r
5731 FLAG_N = NFLAG_8(res);\r
5732 FLAG_Z = res;\r
5733 FLAG_V = VFLAG_CLEAR;\r
5734 FLAG_C = CFLAG_CLEAR;\r
5735}\r
5736\r
5737\r
5738M68KMAKE_OP(move, 8, pi7, d)\r
5739{\r
5740 uint res = MASK_OUT_ABOVE_8(DY);\r
5741 uint ea = EA_A7_PI_8();\r
5742\r
5743 m68ki_write_8(ea, res);\r
5744\r
5745 FLAG_N = NFLAG_8(res);\r
5746 FLAG_Z = res;\r
5747 FLAG_V = VFLAG_CLEAR;\r
5748 FLAG_C = CFLAG_CLEAR;\r
5749}\r
5750\r
5751\r
5752M68KMAKE_OP(move, 8, pi, d)\r
5753{\r
5754 uint res = MASK_OUT_ABOVE_8(DY);\r
5755 uint ea = EA_AX_PI_8();\r
5756\r
5757 m68ki_write_8(ea, res);\r
5758\r
5759 FLAG_N = NFLAG_8(res);\r
5760 FLAG_Z = res;\r
5761 FLAG_V = VFLAG_CLEAR;\r
5762 FLAG_C = CFLAG_CLEAR;\r
5763}\r
5764\r
5765\r
5766M68KMAKE_OP(move, 8, pi7, .)\r
5767{\r
5768 uint res = M68KMAKE_GET_OPER_AY_8;\r
5769 uint ea = EA_A7_PI_8();\r
5770\r
5771 m68ki_write_8(ea, res);\r
5772\r
5773 FLAG_N = NFLAG_8(res);\r
5774 FLAG_Z = res;\r
5775 FLAG_V = VFLAG_CLEAR;\r
5776 FLAG_C = CFLAG_CLEAR;\r
5777}\r
5778\r
5779\r
5780M68KMAKE_OP(move, 8, pi, .)\r
5781{\r
5782 uint res = M68KMAKE_GET_OPER_AY_8;\r
5783 uint ea = EA_AX_PI_8();\r
5784\r
5785 m68ki_write_8(ea, res);\r
5786\r
5787 FLAG_N = NFLAG_8(res);\r
5788 FLAG_Z = res;\r
5789 FLAG_V = VFLAG_CLEAR;\r
5790 FLAG_C = CFLAG_CLEAR;\r
5791}\r
5792\r
5793\r
5794M68KMAKE_OP(move, 8, pd7, d)\r
5795{\r
5796 uint res = MASK_OUT_ABOVE_8(DY);\r
5797 uint ea = EA_A7_PD_8();\r
5798\r
5799 m68ki_write_8(ea, res);\r
5800\r
5801 FLAG_N = NFLAG_8(res);\r
5802 FLAG_Z = res;\r
5803 FLAG_V = VFLAG_CLEAR;\r
5804 FLAG_C = CFLAG_CLEAR;\r
5805}\r
5806\r
5807\r
5808M68KMAKE_OP(move, 8, pd, d)\r
5809{\r
5810 uint res = MASK_OUT_ABOVE_8(DY);\r
5811 uint ea = EA_AX_PD_8();\r
5812\r
5813 m68ki_write_8(ea, res);\r
5814\r
5815 FLAG_N = NFLAG_8(res);\r
5816 FLAG_Z = res;\r
5817 FLAG_V = VFLAG_CLEAR;\r
5818 FLAG_C = CFLAG_CLEAR;\r
5819}\r
5820\r
5821\r
5822M68KMAKE_OP(move, 8, pd7, .)\r
5823{\r
5824 uint res = M68KMAKE_GET_OPER_AY_8;\r
5825 uint ea = EA_A7_PD_8();\r
5826\r
5827 m68ki_write_8(ea, res);\r
5828\r
5829 FLAG_N = NFLAG_8(res);\r
5830 FLAG_Z = res;\r
5831 FLAG_V = VFLAG_CLEAR;\r
5832 FLAG_C = CFLAG_CLEAR;\r
5833}\r
5834\r
5835\r
5836M68KMAKE_OP(move, 8, pd, .)\r
5837{\r
5838 uint res = M68KMAKE_GET_OPER_AY_8;\r
5839 uint ea = EA_AX_PD_8();\r
5840\r
5841 m68ki_write_8(ea, res);\r
5842\r
5843 FLAG_N = NFLAG_8(res);\r
5844 FLAG_Z = res;\r
5845 FLAG_V = VFLAG_CLEAR;\r
5846 FLAG_C = CFLAG_CLEAR;\r
5847}\r
5848\r
5849\r
5850M68KMAKE_OP(move, 8, di, d)\r
5851{\r
5852 uint res = MASK_OUT_ABOVE_8(DY);\r
5853 uint ea = EA_AX_DI_8();\r
5854\r
5855 m68ki_write_8(ea, res);\r
5856\r
5857 FLAG_N = NFLAG_8(res);\r
5858 FLAG_Z = res;\r
5859 FLAG_V = VFLAG_CLEAR;\r
5860 FLAG_C = CFLAG_CLEAR;\r
5861}\r
5862\r
5863\r
5864M68KMAKE_OP(move, 8, di, .)\r
5865{\r
5866 uint res = M68KMAKE_GET_OPER_AY_8;\r
5867 uint ea = EA_AX_DI_8();\r
5868\r
5869 m68ki_write_8(ea, res);\r
5870\r
5871 FLAG_N = NFLAG_8(res);\r
5872 FLAG_Z = res;\r
5873 FLAG_V = VFLAG_CLEAR;\r
5874 FLAG_C = CFLAG_CLEAR;\r
5875}\r
5876\r
5877\r
5878M68KMAKE_OP(move, 8, ix, d)\r
5879{\r
5880 uint res = MASK_OUT_ABOVE_8(DY);\r
5881 uint ea = EA_AX_IX_8();\r
5882\r
5883 m68ki_write_8(ea, res);\r
5884\r
5885 FLAG_N = NFLAG_8(res);\r
5886 FLAG_Z = res;\r
5887 FLAG_V = VFLAG_CLEAR;\r
5888 FLAG_C = CFLAG_CLEAR;\r
5889}\r
5890\r
5891\r
5892M68KMAKE_OP(move, 8, ix, .)\r
5893{\r
5894 uint res = M68KMAKE_GET_OPER_AY_8;\r
5895 uint ea = EA_AX_IX_8();\r
5896\r
5897 m68ki_write_8(ea, res);\r
5898\r
5899 FLAG_N = NFLAG_8(res);\r
5900 FLAG_Z = res;\r
5901 FLAG_V = VFLAG_CLEAR;\r
5902 FLAG_C = CFLAG_CLEAR;\r
5903}\r
5904\r
5905\r
5906M68KMAKE_OP(move, 8, aw, d)\r
5907{\r
5908 uint res = MASK_OUT_ABOVE_8(DY);\r
5909 uint ea = EA_AW_8();\r
5910\r
5911 m68ki_write_8(ea, res);\r
5912\r
5913 FLAG_N = NFLAG_8(res);\r
5914 FLAG_Z = res;\r
5915 FLAG_V = VFLAG_CLEAR;\r
5916 FLAG_C = CFLAG_CLEAR;\r
5917}\r
5918\r
5919\r
5920M68KMAKE_OP(move, 8, aw, .)\r
5921{\r
5922 uint res = M68KMAKE_GET_OPER_AY_8;\r
5923 uint ea = EA_AW_8();\r
5924\r
5925 m68ki_write_8(ea, res);\r
5926\r
5927 FLAG_N = NFLAG_8(res);\r
5928 FLAG_Z = res;\r
5929 FLAG_V = VFLAG_CLEAR;\r
5930 FLAG_C = CFLAG_CLEAR;\r
5931}\r
5932\r
5933\r
5934M68KMAKE_OP(move, 8, al, d)\r
5935{\r
5936 uint res = MASK_OUT_ABOVE_8(DY);\r
5937 uint ea = EA_AL_8();\r
5938\r
5939 m68ki_write_8(ea, res);\r
5940\r
5941 FLAG_N = NFLAG_8(res);\r
5942 FLAG_Z = res;\r
5943 FLAG_V = VFLAG_CLEAR;\r
5944 FLAG_C = CFLAG_CLEAR;\r
5945}\r
5946\r
5947\r
5948M68KMAKE_OP(move, 8, al, .)\r
5949{\r
5950 uint res = M68KMAKE_GET_OPER_AY_8;\r
5951 uint ea = EA_AL_8();\r
5952\r
5953 m68ki_write_8(ea, res);\r
5954\r
5955 FLAG_N = NFLAG_8(res);\r
5956 FLAG_Z = res;\r
5957 FLAG_V = VFLAG_CLEAR;\r
5958 FLAG_C = CFLAG_CLEAR;\r
5959}\r
5960\r
5961\r
5962M68KMAKE_OP(move, 16, d, d)\r
5963{\r
5964 uint res = MASK_OUT_ABOVE_16(DY);\r
5965 uint* r_dst = &DX;\r
5966\r
5967 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
5968\r
5969 FLAG_N = NFLAG_16(res);\r
5970 FLAG_Z = res;\r
5971 FLAG_V = VFLAG_CLEAR;\r
5972 FLAG_C = CFLAG_CLEAR;\r
5973}\r
5974\r
5975\r
5976M68KMAKE_OP(move, 16, d, a)\r
5977{\r
5978 uint res = MASK_OUT_ABOVE_16(AY);\r
5979 uint* r_dst = &DX;\r
5980\r
5981 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
5982\r
5983 FLAG_N = NFLAG_16(res);\r
5984 FLAG_Z = res;\r
5985 FLAG_V = VFLAG_CLEAR;\r
5986 FLAG_C = CFLAG_CLEAR;\r
5987}\r
5988\r
5989\r
5990M68KMAKE_OP(move, 16, d, .)\r
5991{\r
5992 uint res = M68KMAKE_GET_OPER_AY_16;\r
5993 uint* r_dst = &DX;\r
5994\r
5995 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
5996\r
5997 FLAG_N = NFLAG_16(res);\r
5998 FLAG_Z = res;\r
5999 FLAG_V = VFLAG_CLEAR;\r
6000 FLAG_C = CFLAG_CLEAR;\r
6001}\r
6002\r
6003\r
6004M68KMAKE_OP(move, 16, ai, d)\r
6005{\r
6006 uint res = MASK_OUT_ABOVE_16(DY);\r
6007 uint ea = EA_AX_AI_16();\r
6008\r
6009 m68ki_write_16(ea, res);\r
6010\r
6011 FLAG_N = NFLAG_16(res);\r
6012 FLAG_Z = res;\r
6013 FLAG_V = VFLAG_CLEAR;\r
6014 FLAG_C = CFLAG_CLEAR;\r
6015}\r
6016\r
6017\r
6018M68KMAKE_OP(move, 16, ai, a)\r
6019{\r
6020 uint res = MASK_OUT_ABOVE_16(AY);\r
6021 uint ea = EA_AX_AI_16();\r
6022\r
6023 m68ki_write_16(ea, res);\r
6024\r
6025 FLAG_N = NFLAG_16(res);\r
6026 FLAG_Z = res;\r
6027 FLAG_V = VFLAG_CLEAR;\r
6028 FLAG_C = CFLAG_CLEAR;\r
6029}\r
6030\r
6031\r
6032M68KMAKE_OP(move, 16, ai, .)\r
6033{\r
6034 uint res = M68KMAKE_GET_OPER_AY_16;\r
6035 uint ea = EA_AX_AI_16();\r
6036\r
6037 m68ki_write_16(ea, res);\r
6038\r
6039 FLAG_N = NFLAG_16(res);\r
6040 FLAG_Z = res;\r
6041 FLAG_V = VFLAG_CLEAR;\r
6042 FLAG_C = CFLAG_CLEAR;\r
6043}\r
6044\r
6045\r
6046M68KMAKE_OP(move, 16, pi, d)\r
6047{\r
6048 uint res = MASK_OUT_ABOVE_16(DY);\r
6049 uint ea = EA_AX_PI_16();\r
6050\r
6051 m68ki_write_16(ea, res);\r
6052\r
6053 FLAG_N = NFLAG_16(res);\r
6054 FLAG_Z = res;\r
6055 FLAG_V = VFLAG_CLEAR;\r
6056 FLAG_C = CFLAG_CLEAR;\r
6057}\r
6058\r
6059\r
6060M68KMAKE_OP(move, 16, pi, a)\r
6061{\r
6062 uint res = MASK_OUT_ABOVE_16(AY);\r
6063 uint ea = EA_AX_PI_16();\r
6064\r
6065 m68ki_write_16(ea, res);\r
6066\r
6067 FLAG_N = NFLAG_16(res);\r
6068 FLAG_Z = res;\r
6069 FLAG_V = VFLAG_CLEAR;\r
6070 FLAG_C = CFLAG_CLEAR;\r
6071}\r
6072\r
6073\r
6074M68KMAKE_OP(move, 16, pi, .)\r
6075{\r
6076 uint res = M68KMAKE_GET_OPER_AY_16;\r
6077 uint ea = EA_AX_PI_16();\r
6078\r
6079 m68ki_write_16(ea, res);\r
6080\r
6081 FLAG_N = NFLAG_16(res);\r
6082 FLAG_Z = res;\r
6083 FLAG_V = VFLAG_CLEAR;\r
6084 FLAG_C = CFLAG_CLEAR;\r
6085}\r
6086\r
6087\r
6088M68KMAKE_OP(move, 16, pd, d)\r
6089{\r
6090 uint res = MASK_OUT_ABOVE_16(DY);\r
6091 uint ea = EA_AX_PD_16();\r
6092\r
6093 m68ki_write_16(ea, res);\r
6094\r
6095 FLAG_N = NFLAG_16(res);\r
6096 FLAG_Z = res;\r
6097 FLAG_V = VFLAG_CLEAR;\r
6098 FLAG_C = CFLAG_CLEAR;\r
6099}\r
6100\r
6101\r
6102M68KMAKE_OP(move, 16, pd, a)\r
6103{\r
6104 uint res = MASK_OUT_ABOVE_16(AY);\r
6105 uint ea = EA_AX_PD_16();\r
6106\r
6107 m68ki_write_16(ea, res);\r
6108\r
6109 FLAG_N = NFLAG_16(res);\r
6110 FLAG_Z = res;\r
6111 FLAG_V = VFLAG_CLEAR;\r
6112 FLAG_C = CFLAG_CLEAR;\r
6113}\r
6114\r
6115\r
6116M68KMAKE_OP(move, 16, pd, .)\r
6117{\r
6118 uint res = M68KMAKE_GET_OPER_AY_16;\r
6119 uint ea = EA_AX_PD_16();\r
6120\r
6121 m68ki_write_16(ea, res);\r
6122\r
6123 FLAG_N = NFLAG_16(res);\r
6124 FLAG_Z = res;\r
6125 FLAG_V = VFLAG_CLEAR;\r
6126 FLAG_C = CFLAG_CLEAR;\r
6127}\r
6128\r
6129\r
6130M68KMAKE_OP(move, 16, di, d)\r
6131{\r
6132 uint res = MASK_OUT_ABOVE_16(DY);\r
6133 uint ea = EA_AX_DI_16();\r
6134\r
6135 m68ki_write_16(ea, res);\r
6136\r
6137 FLAG_N = NFLAG_16(res);\r
6138 FLAG_Z = res;\r
6139 FLAG_V = VFLAG_CLEAR;\r
6140 FLAG_C = CFLAG_CLEAR;\r
6141}\r
6142\r
6143\r
6144M68KMAKE_OP(move, 16, di, a)\r
6145{\r
6146 uint res = MASK_OUT_ABOVE_16(AY);\r
6147 uint ea = EA_AX_DI_16();\r
6148\r
6149 m68ki_write_16(ea, res);\r
6150\r
6151 FLAG_N = NFLAG_16(res);\r
6152 FLAG_Z = res;\r
6153 FLAG_V = VFLAG_CLEAR;\r
6154 FLAG_C = CFLAG_CLEAR;\r
6155}\r
6156\r
6157\r
6158M68KMAKE_OP(move, 16, di, .)\r
6159{\r
6160 uint res = M68KMAKE_GET_OPER_AY_16;\r
6161 uint ea = EA_AX_DI_16();\r
6162\r
6163 m68ki_write_16(ea, res);\r
6164\r
6165 FLAG_N = NFLAG_16(res);\r
6166 FLAG_Z = res;\r
6167 FLAG_V = VFLAG_CLEAR;\r
6168 FLAG_C = CFLAG_CLEAR;\r
6169}\r
6170\r
6171\r
6172M68KMAKE_OP(move, 16, ix, d)\r
6173{\r
6174 uint res = MASK_OUT_ABOVE_16(DY);\r
6175 uint ea = EA_AX_IX_16();\r
6176\r
6177 m68ki_write_16(ea, res);\r
6178\r
6179 FLAG_N = NFLAG_16(res);\r
6180 FLAG_Z = res;\r
6181 FLAG_V = VFLAG_CLEAR;\r
6182 FLAG_C = CFLAG_CLEAR;\r
6183}\r
6184\r
6185\r
6186M68KMAKE_OP(move, 16, ix, a)\r
6187{\r
6188 uint res = MASK_OUT_ABOVE_16(AY);\r
6189 uint ea = EA_AX_IX_16();\r
6190\r
6191 m68ki_write_16(ea, res);\r
6192\r
6193 FLAG_N = NFLAG_16(res);\r
6194 FLAG_Z = res;\r
6195 FLAG_V = VFLAG_CLEAR;\r
6196 FLAG_C = CFLAG_CLEAR;\r
6197}\r
6198\r
6199\r
6200M68KMAKE_OP(move, 16, ix, .)\r
6201{\r
6202 uint res = M68KMAKE_GET_OPER_AY_16;\r
6203 uint ea = EA_AX_IX_16();\r
6204\r
6205 m68ki_write_16(ea, res);\r
6206\r
6207 FLAG_N = NFLAG_16(res);\r
6208 FLAG_Z = res;\r
6209 FLAG_V = VFLAG_CLEAR;\r
6210 FLAG_C = CFLAG_CLEAR;\r
6211}\r
6212\r
6213\r
6214M68KMAKE_OP(move, 16, aw, d)\r
6215{\r
6216 uint res = MASK_OUT_ABOVE_16(DY);\r
6217 uint ea = EA_AW_16();\r
6218\r
6219 m68ki_write_16(ea, res);\r
6220\r
6221 FLAG_N = NFLAG_16(res);\r
6222 FLAG_Z = res;\r
6223 FLAG_V = VFLAG_CLEAR;\r
6224 FLAG_C = CFLAG_CLEAR;\r
6225}\r
6226\r
6227\r
6228M68KMAKE_OP(move, 16, aw, a)\r
6229{\r
6230 uint res = MASK_OUT_ABOVE_16(AY);\r
6231 uint ea = EA_AW_16();\r
6232\r
6233 m68ki_write_16(ea, res);\r
6234\r
6235 FLAG_N = NFLAG_16(res);\r
6236 FLAG_Z = res;\r
6237 FLAG_V = VFLAG_CLEAR;\r
6238 FLAG_C = CFLAG_CLEAR;\r
6239}\r
6240\r
6241\r
6242M68KMAKE_OP(move, 16, aw, .)\r
6243{\r
6244 uint res = M68KMAKE_GET_OPER_AY_16;\r
6245 uint ea = EA_AW_16();\r
6246\r
6247 m68ki_write_16(ea, res);\r
6248\r
6249 FLAG_N = NFLAG_16(res);\r
6250 FLAG_Z = res;\r
6251 FLAG_V = VFLAG_CLEAR;\r
6252 FLAG_C = CFLAG_CLEAR;\r
6253}\r
6254\r
6255\r
6256M68KMAKE_OP(move, 16, al, d)\r
6257{\r
6258 uint res = MASK_OUT_ABOVE_16(DY);\r
6259 uint ea = EA_AL_16();\r
6260\r
6261 m68ki_write_16(ea, res);\r
6262\r
6263 FLAG_N = NFLAG_16(res);\r
6264 FLAG_Z = res;\r
6265 FLAG_V = VFLAG_CLEAR;\r
6266 FLAG_C = CFLAG_CLEAR;\r
6267}\r
6268\r
6269\r
6270M68KMAKE_OP(move, 16, al, a)\r
6271{\r
6272 uint res = MASK_OUT_ABOVE_16(AY);\r
6273 uint ea = EA_AL_16();\r
6274\r
6275 m68ki_write_16(ea, res);\r
6276\r
6277 FLAG_N = NFLAG_16(res);\r
6278 FLAG_Z = res;\r
6279 FLAG_V = VFLAG_CLEAR;\r
6280 FLAG_C = CFLAG_CLEAR;\r
6281}\r
6282\r
6283\r
6284M68KMAKE_OP(move, 16, al, .)\r
6285{\r
6286 uint res = M68KMAKE_GET_OPER_AY_16;\r
6287 uint ea = EA_AL_16();\r
6288\r
6289 m68ki_write_16(ea, res);\r
6290\r
6291 FLAG_N = NFLAG_16(res);\r
6292 FLAG_Z = res;\r
6293 FLAG_V = VFLAG_CLEAR;\r
6294 FLAG_C = CFLAG_CLEAR;\r
6295}\r
6296\r
6297\r
6298M68KMAKE_OP(move, 32, d, d)\r
6299{\r
6300 uint res = DY;\r
6301 uint* r_dst = &DX;\r
6302\r
6303 *r_dst = res;\r
6304\r
6305 FLAG_N = NFLAG_32(res);\r
6306 FLAG_Z = res;\r
6307 FLAG_V = VFLAG_CLEAR;\r
6308 FLAG_C = CFLAG_CLEAR;\r
6309}\r
6310\r
6311\r
6312M68KMAKE_OP(move, 32, d, a)\r
6313{\r
6314 uint res = AY;\r
6315 uint* r_dst = &DX;\r
6316\r
6317 *r_dst = res;\r
6318\r
6319 FLAG_N = NFLAG_32(res);\r
6320 FLAG_Z = res;\r
6321 FLAG_V = VFLAG_CLEAR;\r
6322 FLAG_C = CFLAG_CLEAR;\r
6323}\r
6324\r
6325\r
6326M68KMAKE_OP(move, 32, d, .)\r
6327{\r
6328 uint res = M68KMAKE_GET_OPER_AY_32;\r
6329 uint* r_dst = &DX;\r
6330\r
6331 *r_dst = res;\r
6332\r
6333 FLAG_N = NFLAG_32(res);\r
6334 FLAG_Z = res;\r
6335 FLAG_V = VFLAG_CLEAR;\r
6336 FLAG_C = CFLAG_CLEAR;\r
6337}\r
6338\r
6339\r
6340M68KMAKE_OP(move, 32, ai, d)\r
6341{\r
6342 uint res = DY;\r
6343 uint ea = EA_AX_AI_32();\r
6344\r
6345 m68ki_write_32(ea, res);\r
6346\r
6347 FLAG_N = NFLAG_32(res);\r
6348 FLAG_Z = res;\r
6349 FLAG_V = VFLAG_CLEAR;\r
6350 FLAG_C = CFLAG_CLEAR;\r
6351}\r
6352\r
6353\r
6354M68KMAKE_OP(move, 32, ai, a)\r
6355{\r
6356 uint res = AY;\r
6357 uint ea = EA_AX_AI_32();\r
6358\r
6359 m68ki_write_32(ea, res);\r
6360\r
6361 FLAG_N = NFLAG_32(res);\r
6362 FLAG_Z = res;\r
6363 FLAG_V = VFLAG_CLEAR;\r
6364 FLAG_C = CFLAG_CLEAR;\r
6365}\r
6366\r
6367\r
6368M68KMAKE_OP(move, 32, ai, .)\r
6369{\r
6370 uint res = M68KMAKE_GET_OPER_AY_32;\r
6371 uint ea = EA_AX_AI_32();\r
6372\r
6373 m68ki_write_32(ea, res);\r
6374\r
6375 FLAG_N = NFLAG_32(res);\r
6376 FLAG_Z = res;\r
6377 FLAG_V = VFLAG_CLEAR;\r
6378 FLAG_C = CFLAG_CLEAR;\r
6379}\r
6380\r
6381\r
6382M68KMAKE_OP(move, 32, pi, d)\r
6383{\r
6384 uint res = DY;\r
6385 uint ea = EA_AX_PI_32();\r
6386\r
6387 m68ki_write_32(ea, res);\r
6388\r
6389 FLAG_N = NFLAG_32(res);\r
6390 FLAG_Z = res;\r
6391 FLAG_V = VFLAG_CLEAR;\r
6392 FLAG_C = CFLAG_CLEAR;\r
6393}\r
6394\r
6395\r
6396M68KMAKE_OP(move, 32, pi, a)\r
6397{\r
6398 uint res = AY;\r
6399 uint ea = EA_AX_PI_32();\r
6400\r
6401 m68ki_write_32(ea, res);\r
6402\r
6403 FLAG_N = NFLAG_32(res);\r
6404 FLAG_Z = res;\r
6405 FLAG_V = VFLAG_CLEAR;\r
6406 FLAG_C = CFLAG_CLEAR;\r
6407}\r
6408\r
6409\r
6410M68KMAKE_OP(move, 32, pi, .)\r
6411{\r
6412 uint res = M68KMAKE_GET_OPER_AY_32;\r
6413 uint ea = EA_AX_PI_32();\r
6414\r
6415 m68ki_write_32(ea, res);\r
6416\r
6417 FLAG_N = NFLAG_32(res);\r
6418 FLAG_Z = res;\r
6419 FLAG_V = VFLAG_CLEAR;\r
6420 FLAG_C = CFLAG_CLEAR;\r
6421}\r
6422\r
6423\r
6424M68KMAKE_OP(move, 32, pd, d)\r
6425{\r
6426 uint res = DY;\r
6427 uint ea = EA_AX_PD_32();\r
6428\r
6429 m68ki_write_32(ea, res);\r
6430\r
6431 FLAG_N = NFLAG_32(res);\r
6432 FLAG_Z = res;\r
6433 FLAG_V = VFLAG_CLEAR;\r
6434 FLAG_C = CFLAG_CLEAR;\r
6435}\r
6436\r
6437\r
6438M68KMAKE_OP(move, 32, pd, a)\r
6439{\r
6440 uint res = AY;\r
6441 uint ea = EA_AX_PD_32();\r
6442\r
6443 m68ki_write_32(ea, res);\r
6444\r
6445 FLAG_N = NFLAG_32(res);\r
6446 FLAG_Z = res;\r
6447 FLAG_V = VFLAG_CLEAR;\r
6448 FLAG_C = CFLAG_CLEAR;\r
6449}\r
6450\r
6451\r
6452M68KMAKE_OP(move, 32, pd, .)\r
6453{\r
6454 uint res = M68KMAKE_GET_OPER_AY_32;\r
6455 uint ea = EA_AX_PD_32();\r
6456\r
6457 m68ki_write_32(ea, res);\r
6458\r
6459 FLAG_N = NFLAG_32(res);\r
6460 FLAG_Z = res;\r
6461 FLAG_V = VFLAG_CLEAR;\r
6462 FLAG_C = CFLAG_CLEAR;\r
6463}\r
6464\r
6465\r
6466M68KMAKE_OP(move, 32, di, d)\r
6467{\r
6468 uint res = DY;\r
6469 uint ea = EA_AX_DI_32();\r
6470\r
6471 m68ki_write_32(ea, res);\r
6472\r
6473 FLAG_N = NFLAG_32(res);\r
6474 FLAG_Z = res;\r
6475 FLAG_V = VFLAG_CLEAR;\r
6476 FLAG_C = CFLAG_CLEAR;\r
6477}\r
6478\r
6479\r
6480M68KMAKE_OP(move, 32, di, a)\r
6481{\r
6482 uint res = AY;\r
6483 uint ea = EA_AX_DI_32();\r
6484\r
6485 m68ki_write_32(ea, res);\r
6486\r
6487 FLAG_N = NFLAG_32(res);\r
6488 FLAG_Z = res;\r
6489 FLAG_V = VFLAG_CLEAR;\r
6490 FLAG_C = CFLAG_CLEAR;\r
6491}\r
6492\r
6493\r
6494M68KMAKE_OP(move, 32, di, .)\r
6495{\r
6496 uint res = M68KMAKE_GET_OPER_AY_32;\r
6497 uint ea = EA_AX_DI_32();\r
6498\r
6499 m68ki_write_32(ea, res);\r
6500\r
6501 FLAG_N = NFLAG_32(res);\r
6502 FLAG_Z = res;\r
6503 FLAG_V = VFLAG_CLEAR;\r
6504 FLAG_C = CFLAG_CLEAR;\r
6505}\r
6506\r
6507\r
6508M68KMAKE_OP(move, 32, ix, d)\r
6509{\r
6510 uint res = DY;\r
6511 uint ea = EA_AX_IX_32();\r
6512\r
6513 m68ki_write_32(ea, res);\r
6514\r
6515 FLAG_N = NFLAG_32(res);\r
6516 FLAG_Z = res;\r
6517 FLAG_V = VFLAG_CLEAR;\r
6518 FLAG_C = CFLAG_CLEAR;\r
6519}\r
6520\r
6521\r
6522M68KMAKE_OP(move, 32, ix, a)\r
6523{\r
6524 uint res = AY;\r
6525 uint ea = EA_AX_IX_32();\r
6526\r
6527 m68ki_write_32(ea, res);\r
6528\r
6529 FLAG_N = NFLAG_32(res);\r
6530 FLAG_Z = res;\r
6531 FLAG_V = VFLAG_CLEAR;\r
6532 FLAG_C = CFLAG_CLEAR;\r
6533}\r
6534\r
6535\r
6536M68KMAKE_OP(move, 32, ix, .)\r
6537{\r
6538 uint res = M68KMAKE_GET_OPER_AY_32;\r
6539 uint ea = EA_AX_IX_32();\r
6540\r
6541 m68ki_write_32(ea, res);\r
6542\r
6543 FLAG_N = NFLAG_32(res);\r
6544 FLAG_Z = res;\r
6545 FLAG_V = VFLAG_CLEAR;\r
6546 FLAG_C = CFLAG_CLEAR;\r
6547}\r
6548\r
6549\r
6550M68KMAKE_OP(move, 32, aw, d)\r
6551{\r
6552 uint res = DY;\r
6553 uint ea = EA_AW_32();\r
6554\r
6555 m68ki_write_32(ea, res);\r
6556\r
6557 FLAG_N = NFLAG_32(res);\r
6558 FLAG_Z = res;\r
6559 FLAG_V = VFLAG_CLEAR;\r
6560 FLAG_C = CFLAG_CLEAR;\r
6561}\r
6562\r
6563\r
6564M68KMAKE_OP(move, 32, aw, a)\r
6565{\r
6566 uint res = AY;\r
6567 uint ea = EA_AW_32();\r
6568\r
6569 m68ki_write_32(ea, res);\r
6570\r
6571 FLAG_N = NFLAG_32(res);\r
6572 FLAG_Z = res;\r
6573 FLAG_V = VFLAG_CLEAR;\r
6574 FLAG_C = CFLAG_CLEAR;\r
6575}\r
6576\r
6577\r
6578M68KMAKE_OP(move, 32, aw, .)\r
6579{\r
6580 uint res = M68KMAKE_GET_OPER_AY_32;\r
6581 uint ea = EA_AW_32();\r
6582\r
6583 m68ki_write_32(ea, res);\r
6584\r
6585 FLAG_N = NFLAG_32(res);\r
6586 FLAG_Z = res;\r
6587 FLAG_V = VFLAG_CLEAR;\r
6588 FLAG_C = CFLAG_CLEAR;\r
6589}\r
6590\r
6591\r
6592M68KMAKE_OP(move, 32, al, d)\r
6593{\r
6594 uint res = DY;\r
6595 uint ea = EA_AL_32();\r
6596\r
6597 m68ki_write_32(ea, res);\r
6598\r
6599 FLAG_N = NFLAG_32(res);\r
6600 FLAG_Z = res;\r
6601 FLAG_V = VFLAG_CLEAR;\r
6602 FLAG_C = CFLAG_CLEAR;\r
6603}\r
6604\r
6605\r
6606M68KMAKE_OP(move, 32, al, a)\r
6607{\r
6608 uint res = AY;\r
6609 uint ea = EA_AL_32();\r
6610\r
6611 m68ki_write_32(ea, res);\r
6612\r
6613 FLAG_N = NFLAG_32(res);\r
6614 FLAG_Z = res;\r
6615 FLAG_V = VFLAG_CLEAR;\r
6616 FLAG_C = CFLAG_CLEAR;\r
6617}\r
6618\r
6619\r
6620M68KMAKE_OP(move, 32, al, .)\r
6621{\r
6622 uint res = M68KMAKE_GET_OPER_AY_32;\r
6623 uint ea = EA_AL_32();\r
6624\r
6625 m68ki_write_32(ea, res);\r
6626\r
6627 FLAG_N = NFLAG_32(res);\r
6628 FLAG_Z = res;\r
6629 FLAG_V = VFLAG_CLEAR;\r
6630 FLAG_C = CFLAG_CLEAR;\r
6631}\r
6632\r
6633\r
6634M68KMAKE_OP(movea, 16, ., d)\r
6635{\r
6636 AX = MAKE_INT_16(DY);\r
6637}\r
6638\r
6639\r
6640M68KMAKE_OP(movea, 16, ., a)\r
6641{\r
6642 AX = MAKE_INT_16(AY);\r
6643}\r
6644\r
6645\r
6646M68KMAKE_OP(movea, 16, ., .)\r
6647{\r
6648 AX = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);\r
6649}\r
6650\r
6651\r
6652M68KMAKE_OP(movea, 32, ., d)\r
6653{\r
6654 AX = DY;\r
6655}\r
6656\r
6657\r
6658M68KMAKE_OP(movea, 32, ., a)\r
6659{\r
6660 AX = AY;\r
6661}\r
6662\r
6663\r
6664M68KMAKE_OP(movea, 32, ., .)\r
6665{\r
6666 AX = M68KMAKE_GET_OPER_AY_32;\r
6667}\r
6668\r
6669\r
6670M68KMAKE_OP(move, 16, frc, d)\r
6671{\r
6672 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))\r
6673 {\r
6674 DY = MASK_OUT_BELOW_16(DY) | m68ki_get_ccr();\r
6675 return;\r
6676 }\r
6677 m68ki_exception_illegal();\r
6678}\r
6679\r
6680\r
6681M68KMAKE_OP(move, 16, frc, .)\r
6682{\r
6683 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))\r
6684 {\r
6685 m68ki_write_16(M68KMAKE_GET_EA_AY_16, m68ki_get_ccr());\r
6686 return;\r
6687 }\r
6688 m68ki_exception_illegal();\r
6689}\r
6690\r
6691\r
6692M68KMAKE_OP(move, 16, toc, d)\r
6693{\r
6694 m68ki_set_ccr(DY);\r
6695}\r
6696\r
6697\r
6698M68KMAKE_OP(move, 16, toc, .)\r
6699{\r
6700 m68ki_set_ccr(M68KMAKE_GET_OPER_AY_16);\r
6701}\r
6702\r
6703\r
6704M68KMAKE_OP(move, 16, frs, d)\r
6705{\r
6706 if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */\r
6707 {\r
6708 DY = MASK_OUT_BELOW_16(DY) | m68ki_get_sr();\r
6709 return;\r
6710 }\r
6711 m68ki_exception_privilege_violation();\r
6712}\r
6713\r
6714\r
6715M68KMAKE_OP(move, 16, frs, .)\r
6716{\r
6717 if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */\r
6718 {\r
6719 uint ea = M68KMAKE_GET_EA_AY_16;\r
6720 m68ki_write_16(ea, m68ki_get_sr());\r
6721 return;\r
6722 }\r
6723 m68ki_exception_privilege_violation();\r
6724}\r
6725\r
6726\r
6727M68KMAKE_OP(move, 16, tos, d)\r
6728{\r
6729 if(FLAG_S)\r
6730 {\r
6731 m68ki_set_sr(DY);\r
6732 return;\r
6733 }\r
6734 m68ki_exception_privilege_violation();\r
6735}\r
6736\r
6737\r
6738M68KMAKE_OP(move, 16, tos, .)\r
6739{\r
6740 if(FLAG_S)\r
6741 {\r
6742 uint new_sr = M68KMAKE_GET_OPER_AY_16;\r
6743 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
6744 m68ki_set_sr(new_sr);\r
6745 return;\r
6746 }\r
6747 m68ki_exception_privilege_violation();\r
6748}\r
6749\r
6750\r
6751M68KMAKE_OP(move, 32, fru, .)\r
6752{\r
6753 if(FLAG_S)\r
6754 {\r
6755 AY = REG_USP;\r
6756 return;\r
6757 }\r
6758 m68ki_exception_privilege_violation();\r
6759}\r
6760\r
6761\r
6762M68KMAKE_OP(move, 32, tou, .)\r
6763{\r
6764 if(FLAG_S)\r
6765 {\r
6766 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
6767 REG_USP = AY;\r
6768 return;\r
6769 }\r
6770 m68ki_exception_privilege_violation();\r
6771}\r
6772\r
6773\r
6774M68KMAKE_OP(movec, 32, cr, .)\r
6775{\r
6776 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))\r
6777 {\r
6778 if(FLAG_S)\r
6779 {\r
6780 uint word2 = OPER_I_16();\r
6781\r
6782 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
6783 switch (word2 & 0xfff)\r
6784 {\r
6785 case 0x000: /* SFC */\r
6786 REG_DA[(word2 >> 12) & 15] = REG_SFC;\r
6787 return;\r
6788 case 0x001: /* DFC */\r
6789 REG_DA[(word2 >> 12) & 15] = REG_DFC;\r
6790 return;\r
6791 case 0x002: /* CACR */\r
6792 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
6793 {\r
6794 REG_DA[(word2 >> 12) & 15] = REG_CACR;\r
6795 return;\r
6796 }\r
6797 return;\r
6798 case 0x800: /* USP */\r
6799 REG_DA[(word2 >> 12) & 15] = REG_USP;\r
6800 return;\r
6801 case 0x801: /* VBR */\r
6802 REG_DA[(word2 >> 12) & 15] = REG_VBR;\r
6803 return;\r
6804 case 0x802: /* CAAR */\r
6805 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
6806 {\r
6807 REG_DA[(word2 >> 12) & 15] = REG_CAAR;\r
6808 return;\r
6809 }\r
6810 m68ki_exception_illegal();\r
6811 break;\r
6812 case 0x803: /* MSP */\r
6813 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
6814 {\r
6815 REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_SP : REG_MSP;\r
6816 return;\r
6817 }\r
6818 m68ki_exception_illegal();\r
6819 return;\r
6820 case 0x804: /* ISP */\r
6821 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
6822 {\r
6823 REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_ISP : REG_SP;\r
6824 return;\r
6825 }\r
6826 m68ki_exception_illegal();\r
6827 return;\r
6828 case 0x003: /* TC */\r
6829 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
6830 {\r
6831 /* TODO */\r
6832 return;\r
6833 }\r
6834 m68ki_exception_illegal();\r
6835 return;\r
6836 case 0x004: /* ITT0 */\r
6837 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
6838 {\r
6839 /* TODO */\r
6840 return;\r
6841 }\r
6842 m68ki_exception_illegal();\r
6843 return;\r
6844 case 0x005: /* ITT1 */\r
6845 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
6846 {\r
6847 /* TODO */\r
6848 return;\r
6849 }\r
6850 m68ki_exception_illegal();\r
6851 return;\r
6852 case 0x006: /* DTT0 */\r
6853 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
6854 {\r
6855 /* TODO */\r
6856 return;\r
6857 }\r
6858 m68ki_exception_illegal();\r
6859 return;\r
6860 case 0x007: /* DTT1 */\r
6861 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
6862 {\r
6863 /* TODO */\r
6864 return;\r
6865 }\r
6866 m68ki_exception_illegal();\r
6867 return;\r
6868 case 0x805: /* MMUSR */\r
6869 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
6870 {\r
6871 /* TODO */\r
6872 return;\r
6873 }\r
6874 m68ki_exception_illegal();\r
6875 return;\r
6876 case 0x806: /* URP */\r
6877 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
6878 {\r
6879 /* TODO */\r
6880 return;\r
6881 }\r
6882 m68ki_exception_illegal();\r
6883 return;\r
6884 case 0x807: /* SRP */\r
6885 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
6886 {\r
6887 /* TODO */\r
6888 return;\r
6889 }\r
6890 m68ki_exception_illegal();\r
6891 return;\r
6892 default:\r
6893 m68ki_exception_illegal();\r
6894 return;\r
6895 }\r
6896 }\r
6897 m68ki_exception_privilege_violation();\r
6898 return;\r
6899 }\r
6900 m68ki_exception_illegal();\r
6901}\r
6902\r
6903\r
6904M68KMAKE_OP(movec, 32, rc, .)\r
6905{\r
6906 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))\r
6907 {\r
6908 if(FLAG_S)\r
6909 {\r
6910 uint word2 = OPER_I_16();\r
6911\r
6912 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
6913 switch (word2 & 0xfff)\r
6914 {\r
6915 case 0x000: /* SFC */\r
6916 REG_SFC = REG_DA[(word2 >> 12) & 15] & 7;\r
6917 return;\r
6918 case 0x001: /* DFC */\r
6919 REG_DFC = REG_DA[(word2 >> 12) & 15] & 7;\r
6920 return;\r
6921 case 0x002: /* CACR */\r
6922 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
6923 {\r
6924 REG_CACR = REG_DA[(word2 >> 12) & 15];\r
6925 return;\r
6926 }\r
6927 m68ki_exception_illegal();\r
6928 return;\r
6929 case 0x800: /* USP */\r
6930 REG_USP = REG_DA[(word2 >> 12) & 15];\r
6931 return;\r
6932 case 0x801: /* VBR */\r
6933 REG_VBR = REG_DA[(word2 >> 12) & 15];\r
6934 return;\r
6935 case 0x802: /* CAAR */\r
6936 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
6937 {\r
6938 REG_CAAR = REG_DA[(word2 >> 12) & 15];\r
6939 return;\r
6940 }\r
6941 m68ki_exception_illegal();\r
6942 return;\r
6943 case 0x803: /* MSP */\r
6944 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
6945 {\r
6946 /* we are in supervisor mode so just check for M flag */\r
6947 if(!FLAG_M)\r
6948 {\r
6949 REG_MSP = REG_DA[(word2 >> 12) & 15];\r
6950 return;\r
6951 }\r
6952 REG_SP = REG_DA[(word2 >> 12) & 15];\r
6953 return;\r
6954 }\r
6955 m68ki_exception_illegal();\r
6956 return;\r
6957 case 0x804: /* ISP */\r
6958 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
6959 {\r
6960 if(!FLAG_M)\r
6961 {\r
6962 REG_SP = REG_DA[(word2 >> 12) & 15];\r
6963 return;\r
6964 }\r
6965 REG_ISP = REG_DA[(word2 >> 12) & 15];\r
6966 return;\r
6967 }\r
6968 m68ki_exception_illegal();\r
6969 return;\r
6970 case 0x003: /* TC */\r
6971 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
6972 {\r
6973 /* TODO */\r
6974 return;\r
6975 }\r
6976 m68ki_exception_illegal();\r
6977 return;\r
6978 case 0x004: /* ITT0 */\r
6979 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
6980 {\r
6981 /* TODO */\r
6982 return;\r
6983 }\r
6984 m68ki_exception_illegal();\r
6985 return;\r
6986 case 0x005: /* ITT1 */\r
6987 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
6988 {\r
6989 /* TODO */\r
6990 return;\r
6991 }\r
6992 m68ki_exception_illegal();\r
6993 return;\r
6994 case 0x006: /* DTT0 */\r
6995 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
6996 {\r
6997 /* TODO */\r
6998 return;\r
6999 }\r
7000 m68ki_exception_illegal();\r
7001 return;\r
7002 case 0x007: /* DTT1 */\r
7003 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
7004 {\r
7005 /* TODO */\r
7006 return;\r
7007 }\r
7008 m68ki_exception_illegal();\r
7009 return;\r
7010 case 0x805: /* MMUSR */\r
7011 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
7012 {\r
7013 /* TODO */\r
7014 return;\r
7015 }\r
7016 m68ki_exception_illegal();\r
7017 return;\r
7018 case 0x806: /* URP */\r
7019 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
7020 {\r
7021 /* TODO */\r
7022 return;\r
7023 }\r
7024 m68ki_exception_illegal();\r
7025 return;\r
7026 case 0x807: /* SRP */\r
7027 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
7028 {\r
7029 /* TODO */\r
7030 return;\r
7031 }\r
7032 m68ki_exception_illegal();\r
7033 return;\r
7034 default:\r
7035 m68ki_exception_illegal();\r
7036 return;\r
7037 }\r
7038 }\r
7039 m68ki_exception_privilege_violation();\r
7040 return;\r
7041 }\r
7042 m68ki_exception_illegal();\r
7043}\r
7044\r
7045\r
7046M68KMAKE_OP(movem, 16, re, pd)\r
7047{\r
7048 uint i = 0;\r
7049 uint register_list = OPER_I_16();\r
7050 uint ea = AY;\r
7051 uint count = 0;\r
7052\r
7053 for(; i < 16; i++)\r
7054 if(register_list & (1 << i))\r
7055 {\r
7056 ea -= 2;\r
7057 m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[15-i]));\r
7058 count++;\r
7059 }\r
7060 AY = ea;\r
7061\r
7062 USE_CYCLES(count<<CYC_MOVEM_W);\r
7063}\r
7064\r
7065\r
7066M68KMAKE_OP(movem, 16, re, .)\r
7067{\r
7068 uint i = 0;\r
7069 uint register_list = OPER_I_16();\r
7070 uint ea = M68KMAKE_GET_EA_AY_16;\r
7071 uint count = 0;\r
7072\r
7073 for(; i < 16; i++)\r
7074 if(register_list & (1 << i))\r
7075 {\r
7076 m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[i]));\r
7077 ea += 2;\r
7078 count++;\r
7079 }\r
7080\r
7081 USE_CYCLES(count<<CYC_MOVEM_W);\r
7082}\r
7083\r
7084\r
7085M68KMAKE_OP(movem, 32, re, pd)\r
7086{\r
7087 uint i = 0;\r
7088 uint register_list = OPER_I_16();\r
7089 uint ea = AY;\r
7090 uint count = 0;\r
7091\r
7092 for(; i < 16; i++)\r
7093 if(register_list & (1 << i))\r
7094 {\r
7095 ea -= 4;\r
7096 m68ki_write_32(ea, REG_DA[15-i]);\r
7097 count++;\r
7098 }\r
7099 AY = ea;\r
7100\r
7101 USE_CYCLES(count<<CYC_MOVEM_L);\r
7102}\r
7103\r
7104\r
7105M68KMAKE_OP(movem, 32, re, .)\r
7106{\r
7107 uint i = 0;\r
7108 uint register_list = OPER_I_16();\r
7109 uint ea = M68KMAKE_GET_EA_AY_32;\r
7110 uint count = 0;\r
7111\r
7112 for(; i < 16; i++)\r
7113 if(register_list & (1 << i))\r
7114 {\r
7115 m68ki_write_32(ea, REG_DA[i]);\r
7116 ea += 4;\r
7117 count++;\r
7118 }\r
7119\r
7120 USE_CYCLES(count<<CYC_MOVEM_L);\r
7121}\r
7122\r
7123\r
7124M68KMAKE_OP(movem, 16, er, pi)\r
7125{\r
7126 uint i = 0;\r
7127 uint register_list = OPER_I_16();\r
7128 uint ea = AY;\r
7129 uint count = 0;\r
7130\r
7131 for(; i < 16; i++)\r
7132 if(register_list & (1 << i))\r
7133 {\r
7134 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));\r
7135 ea += 2;\r
7136 count++;\r
7137 }\r
7138 AY = ea;\r
7139\r
7140 USE_CYCLES(count<<CYC_MOVEM_W);\r
7141}\r
7142\r
7143\r
7144M68KMAKE_OP(movem, 16, er, pcdi)\r
7145{\r
7146 uint i = 0;\r
7147 uint register_list = OPER_I_16();\r
7148 uint ea = EA_PCDI_16();\r
7149 uint count = 0;\r
7150\r
7151 for(; i < 16; i++)\r
7152 if(register_list & (1 << i))\r
7153 {\r
7154 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_pcrel_16(ea)));\r
7155 ea += 2;\r
7156 count++;\r
7157 }\r
7158\r
7159 USE_CYCLES(count<<CYC_MOVEM_W);\r
7160}\r
7161\r
7162\r
7163M68KMAKE_OP(movem, 16, er, pcix)\r
7164{\r
7165 uint i = 0;\r
7166 uint register_list = OPER_I_16();\r
7167 uint ea = EA_PCIX_16();\r
7168 uint count = 0;\r
7169\r
7170 for(; i < 16; i++)\r
7171 if(register_list & (1 << i))\r
7172 {\r
7173 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_pcrel_16(ea)));\r
7174 ea += 2;\r
7175 count++;\r
7176 }\r
7177\r
7178 USE_CYCLES(count<<CYC_MOVEM_W);\r
7179}\r
7180\r
7181\r
7182M68KMAKE_OP(movem, 16, er, .)\r
7183{\r
7184 uint i = 0;\r
7185 uint register_list = OPER_I_16();\r
7186 uint ea = M68KMAKE_GET_EA_AY_16;\r
7187 uint count = 0;\r
7188\r
7189 for(; i < 16; i++)\r
7190 if(register_list & (1 << i))\r
7191 {\r
7192 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));\r
7193 ea += 2;\r
7194 count++;\r
7195 }\r
7196\r
7197 USE_CYCLES(count<<CYC_MOVEM_W);\r
7198}\r
7199\r
7200\r
7201M68KMAKE_OP(movem, 32, er, pi)\r
7202{\r
7203 uint i = 0;\r
7204 uint register_list = OPER_I_16();\r
7205 uint ea = AY;\r
7206 uint count = 0;\r
7207\r
7208 for(; i < 16; i++)\r
7209 if(register_list & (1 << i))\r
7210 {\r
7211 REG_DA[i] = m68ki_read_32(ea);\r
7212 ea += 4;\r
7213 count++;\r
7214 }\r
7215 AY = ea;\r
7216\r
7217 USE_CYCLES(count<<CYC_MOVEM_L);\r
7218}\r
7219\r
7220\r
7221M68KMAKE_OP(movem, 32, er, pcdi)\r
7222{\r
7223 uint i = 0;\r
7224 uint register_list = OPER_I_16();\r
7225 uint ea = EA_PCDI_32();\r
7226 uint count = 0;\r
7227\r
7228 for(; i < 16; i++)\r
7229 if(register_list & (1 << i))\r
7230 {\r
7231 REG_DA[i] = m68ki_read_pcrel_32(ea);\r
7232 ea += 4;\r
7233 count++;\r
7234 }\r
7235\r
7236 USE_CYCLES(count<<CYC_MOVEM_L);\r
7237}\r
7238\r
7239\r
7240M68KMAKE_OP(movem, 32, er, pcix)\r
7241{\r
7242 uint i = 0;\r
7243 uint register_list = OPER_I_16();\r
7244 uint ea = EA_PCIX_32();\r
7245 uint count = 0;\r
7246\r
7247 for(; i < 16; i++)\r
7248 if(register_list & (1 << i))\r
7249 {\r
7250 REG_DA[i] = m68ki_read_pcrel_32(ea);\r
7251 ea += 4;\r
7252 count++;\r
7253 }\r
7254\r
7255 USE_CYCLES(count<<CYC_MOVEM_L);\r
7256}\r
7257\r
7258\r
7259M68KMAKE_OP(movem, 32, er, .)\r
7260{\r
7261 uint i = 0;\r
7262 uint register_list = OPER_I_16();\r
7263 uint ea = M68KMAKE_GET_EA_AY_32;\r
7264 uint count = 0;\r
7265\r
7266 for(; i < 16; i++)\r
7267 if(register_list & (1 << i))\r
7268 {\r
7269 REG_DA[i] = m68ki_read_32(ea);\r
7270 ea += 4;\r
7271 count++;\r
7272 }\r
7273\r
7274 USE_CYCLES(count<<CYC_MOVEM_L);\r
7275}\r
7276\r
7277\r
7278M68KMAKE_OP(movep, 16, re, .)\r
7279{\r
7280 uint ea = EA_AY_DI_16();\r
7281 uint src = DX;\r
7282\r
7283 m68ki_write_8(ea, MASK_OUT_ABOVE_8(src >> 8));\r
7284 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src));\r
7285}\r
7286\r
7287\r
7288M68KMAKE_OP(movep, 32, re, .)\r
7289{\r
7290 uint ea = EA_AY_DI_32();\r
7291 uint src = DX;\r
7292\r
7293 m68ki_write_8(ea, MASK_OUT_ABOVE_8(src >> 24));\r
7294 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 16));\r
7295 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 8));\r
7296 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src));\r
7297}\r
7298\r
7299\r
7300M68KMAKE_OP(movep, 16, er, .)\r
7301{\r
7302 uint ea = EA_AY_DI_16();\r
7303 uint* r_dst = &DX;\r
7304\r
7305 *r_dst = MASK_OUT_BELOW_16(*r_dst) | ((m68ki_read_8(ea) << 8) + m68ki_read_8(ea + 2));\r
7306}\r
7307\r
7308\r
7309M68KMAKE_OP(movep, 32, er, .)\r
7310{\r
7311 uint ea = EA_AY_DI_32();\r
7312\r
7313 DX = (m68ki_read_8(ea) << 24) + (m68ki_read_8(ea + 2) << 16)\r
7314 + (m68ki_read_8(ea + 4) << 8) + m68ki_read_8(ea + 6);\r
7315}\r
7316\r
7317\r
7318M68KMAKE_OP(moves, 8, ., .)\r
7319{\r
7320 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))\r
7321 {\r
7322 if(FLAG_S)\r
7323 {\r
7324 uint word2 = OPER_I_16();\r
7325 uint ea = M68KMAKE_GET_EA_AY_8;\r
7326\r
7327 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
7328 if(BIT_B(word2)) /* Register to memory */\r
7329 {\r
7330 m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15]));\r
7331 return;\r
7332 }\r
7333 if(BIT_F(word2)) /* Memory to address register */\r
7334 {\r
7335 REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC));\r
7336 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))\r
7337 USE_CYCLES(2);\r
7338 return;\r
7339 }\r
7340 /* Memory to data register */\r
7341 REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC);\r
7342 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))\r
7343 USE_CYCLES(2);\r
7344 return;\r
7345 }\r
7346 m68ki_exception_privilege_violation();\r
7347 return;\r
7348 }\r
7349 m68ki_exception_illegal();\r
7350}\r
7351\r
7352\r
7353M68KMAKE_OP(moves, 16, ., .)\r
7354{\r
7355 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))\r
7356 {\r
7357 if(FLAG_S)\r
7358 {\r
7359 uint word2 = OPER_I_16();\r
7360 uint ea = M68KMAKE_GET_EA_AY_16;\r
7361\r
7362 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
7363 if(BIT_B(word2)) /* Register to memory */\r
7364 {\r
7365 m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15]));\r
7366 return;\r
7367 }\r
7368 if(BIT_F(word2)) /* Memory to address register */\r
7369 {\r
7370 REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC));\r
7371 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))\r
7372 USE_CYCLES(2);\r
7373 return;\r
7374 }\r
7375 /* Memory to data register */\r
7376 REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC);\r
7377 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))\r
7378 USE_CYCLES(2);\r
7379 return;\r
7380 }\r
7381 m68ki_exception_privilege_violation();\r
7382 return;\r
7383 }\r
7384 m68ki_exception_illegal();\r
7385}\r
7386\r
7387\r
7388M68KMAKE_OP(moves, 32, ., .)\r
7389{\r
7390 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))\r
7391 {\r
7392 if(FLAG_S)\r
7393 {\r
7394 uint word2 = OPER_I_16();\r
7395 uint ea = M68KMAKE_GET_EA_AY_32;\r
7396\r
7397 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
7398 if(BIT_B(word2)) /* Register to memory */\r
7399 {\r
7400 m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]);\r
7401 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))\r
7402 USE_CYCLES(2);\r
7403 return;\r
7404 }\r
7405 /* Memory to register */\r
7406 REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC);\r
7407 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))\r
7408 USE_CYCLES(2);\r
7409 return;\r
7410 }\r
7411 m68ki_exception_privilege_violation();\r
7412 return;\r
7413 }\r
7414 m68ki_exception_illegal();\r
7415}\r
7416\r
7417\r
7418M68KMAKE_OP(moveq, 32, ., .)\r
7419{\r
7420 uint res = DX = MAKE_INT_8(MASK_OUT_ABOVE_8(REG_IR));\r
7421\r
7422 FLAG_N = NFLAG_32(res);\r
7423 FLAG_Z = res;\r
7424 FLAG_V = VFLAG_CLEAR;\r
7425 FLAG_C = CFLAG_CLEAR;\r
7426}\r
7427\r
7428\r
7429M68KMAKE_OP(move16, 32, ., .)\r
7430{\r
7431 UINT16 w2 = OPER_I_16();\r
7432 int ax = REG_IR & 7;\r
7433 int ay = (w2 >> 12) & 7;\r
7434\r
7435 m68ki_write_32(REG_A[ay], m68ki_read_32(REG_A[ax]));\r
7436 m68ki_write_32(REG_A[ay]+4, m68ki_read_32(REG_A[ax]+4));\r
7437 m68ki_write_32(REG_A[ay]+8, m68ki_read_32(REG_A[ax]+8));\r
7438 m68ki_write_32(REG_A[ay]+12, m68ki_read_32(REG_A[ax]+12));\r
7439\r
7440 REG_A[ax] += 16;\r
7441 REG_A[ay] += 16;\r
7442}\r
7443\r
7444\r
7445M68KMAKE_OP(muls, 16, ., d)\r
7446{\r
7447 uint* r_dst = &DX;\r
7448 uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(DY) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));\r
7449\r
7450 *r_dst = res;\r
7451\r
7452 FLAG_Z = res;\r
7453 FLAG_N = NFLAG_32(res);\r
7454 FLAG_V = VFLAG_CLEAR;\r
7455 FLAG_C = CFLAG_CLEAR;\r
7456}\r
7457\r
7458\r
7459M68KMAKE_OP(muls, 16, ., .)\r
7460{\r
7461 uint* r_dst = &DX;\r
7462 uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(M68KMAKE_GET_OPER_AY_16) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));\r
7463\r
7464 *r_dst = res;\r
7465\r
7466 FLAG_Z = res;\r
7467 FLAG_N = NFLAG_32(res);\r
7468 FLAG_V = VFLAG_CLEAR;\r
7469 FLAG_C = CFLAG_CLEAR;\r
7470}\r
7471\r
7472\r
7473M68KMAKE_OP(mulu, 16, ., d)\r
7474{\r
7475 uint* r_dst = &DX;\r
7476 uint res = MASK_OUT_ABOVE_16(DY) * MASK_OUT_ABOVE_16(*r_dst);\r
7477\r
7478 *r_dst = res;\r
7479\r
7480 FLAG_Z = res;\r
7481 FLAG_N = NFLAG_32(res);\r
7482 FLAG_V = VFLAG_CLEAR;\r
7483 FLAG_C = CFLAG_CLEAR;\r
7484}\r
7485\r
7486\r
7487M68KMAKE_OP(mulu, 16, ., .)\r
7488{\r
7489 uint* r_dst = &DX;\r
7490 uint res = M68KMAKE_GET_OPER_AY_16 * MASK_OUT_ABOVE_16(*r_dst);\r
7491\r
7492 *r_dst = res;\r
7493\r
7494 FLAG_Z = res;\r
7495 FLAG_N = NFLAG_32(res);\r
7496 FLAG_V = VFLAG_CLEAR;\r
7497 FLAG_C = CFLAG_CLEAR;\r
7498}\r
7499\r
7500\r
7501M68KMAKE_OP(mull, 32, ., d)\r
7502{\r
7503#if M68K_USE_64_BIT\r
7504\r
7505 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
7506 {\r
7507 uint word2 = OPER_I_16();\r
7508 uint64 src = DY;\r
7509 uint64 dst = REG_D[(word2 >> 12) & 7];\r
7510 uint64 res;\r
7511\r
7512 FLAG_C = CFLAG_CLEAR;\r
7513\r
7514 if(BIT_B(word2)) /* signed */\r
7515 {\r
7516 res = (sint64)((sint32)src) * (sint64)((sint32)dst);\r
7517 if(!BIT_A(word2))\r
7518 {\r
7519 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
7520 FLAG_N = NFLAG_32(res);\r
7521 FLAG_V = ((sint64)res != (sint32)res)<<7;\r
7522 REG_D[(word2 >> 12) & 7] = FLAG_Z;\r
7523 return;\r
7524 }\r
7525 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);\r
7526 FLAG_N = NFLAG_64(res);\r
7527 FLAG_V = VFLAG_CLEAR;\r
7528 REG_D[word2 & 7] = (res >> 32);\r
7529 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);\r
7530 return;\r
7531 }\r
7532\r
7533 res = src * dst;\r
7534 if(!BIT_A(word2))\r
7535 {\r
7536 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
7537 FLAG_N = NFLAG_32(res);\r
7538 FLAG_V = (res > 0xffffffff)<<7;\r
7539 REG_D[(word2 >> 12) & 7] = FLAG_Z;\r
7540 return;\r
7541 }\r
7542 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);\r
7543 FLAG_N = NFLAG_64(res);\r
7544 FLAG_V = VFLAG_CLEAR;\r
7545 REG_D[word2 & 7] = (res >> 32);\r
7546 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);\r
7547 return;\r
7548 }\r
7549 m68ki_exception_illegal();\r
7550\r
7551#else\r
7552\r
7553 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
7554 {\r
7555 uint word2 = OPER_I_16();\r
7556 uint src = DY;\r
7557 uint dst = REG_D[(word2 >> 12) & 7];\r
7558 uint neg = GET_MSB_32(src ^ dst);\r
7559 uint src1;\r
7560 uint src2;\r
7561 uint dst1;\r
7562 uint dst2;\r
7563 uint r1;\r
7564 uint r2;\r
7565 uint r3;\r
7566 uint r4;\r
7567 uint lo;\r
7568 uint hi;\r
7569\r
7570 FLAG_C = CFLAG_CLEAR;\r
7571\r
7572 if(BIT_B(word2)) /* signed */\r
7573 {\r
7574 if(GET_MSB_32(src))\r
7575 src = (uint)MASK_OUT_ABOVE_32(-(sint)src);\r
7576 if(GET_MSB_32(dst))\r
7577 dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);\r
7578 }\r
7579\r
7580 src1 = MASK_OUT_ABOVE_16(src);\r
7581 src2 = src>>16;\r
7582 dst1 = MASK_OUT_ABOVE_16(dst);\r
7583 dst2 = dst>>16;\r
7584\r
7585\r
7586 r1 = src1 * dst1;\r
7587 r2 = src1 * dst2;\r
7588 r3 = src2 * dst1;\r
7589 r4 = src2 * dst2;\r
7590\r
7591 lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);\r
7592 hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);\r
7593\r
7594 if(BIT_B(word2) && neg)\r
7595 {\r
7596 hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));\r
7597 lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);\r
7598 }\r
7599\r
7600 if(BIT_A(word2))\r
7601 {\r
7602 REG_D[word2 & 7] = hi;\r
7603 REG_D[(word2 >> 12) & 7] = lo;\r
7604 FLAG_N = NFLAG_32(hi);\r
7605 FLAG_Z = hi | lo;\r
7606 FLAG_V = VFLAG_CLEAR;\r
7607 return;\r
7608 }\r
7609\r
7610 REG_D[(word2 >> 12) & 7] = lo;\r
7611 FLAG_N = NFLAG_32(lo);\r
7612 FLAG_Z = lo;\r
7613 if(BIT_B(word2))\r
7614 FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;\r
7615 else\r
7616 FLAG_V = (hi != 0) << 7;\r
7617 return;\r
7618 }\r
7619 m68ki_exception_illegal();\r
7620\r
7621#endif\r
7622}\r
7623\r
7624\r
7625M68KMAKE_OP(mull, 32, ., .)\r
7626{\r
7627#if M68K_USE_64_BIT\r
7628\r
7629 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
7630 {\r
7631 uint word2 = OPER_I_16();\r
7632 uint64 src = M68KMAKE_GET_OPER_AY_32;\r
7633 uint64 dst = REG_D[(word2 >> 12) & 7];\r
7634 uint64 res;\r
7635\r
7636 FLAG_C = CFLAG_CLEAR;\r
7637\r
7638 if(BIT_B(word2)) /* signed */\r
7639 {\r
7640 res = (sint64)((sint32)src) * (sint64)((sint32)dst);\r
7641 if(!BIT_A(word2))\r
7642 {\r
7643 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
7644 FLAG_N = NFLAG_32(res);\r
7645 FLAG_V = ((sint64)res != (sint32)res)<<7;\r
7646 REG_D[(word2 >> 12) & 7] = FLAG_Z;\r
7647 return;\r
7648 }\r
7649 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);\r
7650 FLAG_N = NFLAG_64(res);\r
7651 FLAG_V = VFLAG_CLEAR;\r
7652 REG_D[word2 & 7] = (res >> 32);\r
7653 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);\r
7654 return;\r
7655 }\r
7656\r
7657 res = src * dst;\r
7658 if(!BIT_A(word2))\r
7659 {\r
7660 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
7661 FLAG_N = NFLAG_32(res);\r
7662 FLAG_V = (res > 0xffffffff)<<7;\r
7663 REG_D[(word2 >> 12) & 7] = FLAG_Z;\r
7664 return;\r
7665 }\r
7666 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);\r
7667 FLAG_N = NFLAG_64(res);\r
7668 FLAG_V = VFLAG_CLEAR;\r
7669 REG_D[word2 & 7] = (res >> 32);\r
7670 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);\r
7671 return;\r
7672 }\r
7673 m68ki_exception_illegal();\r
7674\r
7675#else\r
7676\r
7677 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
7678 {\r
7679 uint word2 = OPER_I_16();\r
7680 uint src = M68KMAKE_GET_OPER_AY_32;\r
7681 uint dst = REG_D[(word2 >> 12) & 7];\r
7682 uint neg = GET_MSB_32(src ^ dst);\r
7683 uint src1;\r
7684 uint src2;\r
7685 uint dst1;\r
7686 uint dst2;\r
7687 uint r1;\r
7688 uint r2;\r
7689 uint r3;\r
7690 uint r4;\r
7691 uint lo;\r
7692 uint hi;\r
7693\r
7694 FLAG_C = CFLAG_CLEAR;\r
7695\r
7696 if(BIT_B(word2)) /* signed */\r
7697 {\r
7698 if(GET_MSB_32(src))\r
7699 src = (uint)MASK_OUT_ABOVE_32(-(sint)src);\r
7700 if(GET_MSB_32(dst))\r
7701 dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);\r
7702 }\r
7703\r
7704 src1 = MASK_OUT_ABOVE_16(src);\r
7705 src2 = src>>16;\r
7706 dst1 = MASK_OUT_ABOVE_16(dst);\r
7707 dst2 = dst>>16;\r
7708\r
7709\r
7710 r1 = src1 * dst1;\r
7711 r2 = src1 * dst2;\r
7712 r3 = src2 * dst1;\r
7713 r4 = src2 * dst2;\r
7714\r
7715 lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);\r
7716 hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);\r
7717\r
7718 if(BIT_B(word2) && neg)\r
7719 {\r
7720 hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));\r
7721 lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);\r
7722 }\r
7723\r
7724 if(BIT_A(word2))\r
7725 {\r
7726 REG_D[word2 & 7] = hi;\r
7727 REG_D[(word2 >> 12) & 7] = lo;\r
7728 FLAG_N = NFLAG_32(hi);\r
7729 FLAG_Z = hi | lo;\r
7730 FLAG_V = VFLAG_CLEAR;\r
7731 return;\r
7732 }\r
7733\r
7734 REG_D[(word2 >> 12) & 7] = lo;\r
7735 FLAG_N = NFLAG_32(lo);\r
7736 FLAG_Z = lo;\r
7737 if(BIT_B(word2))\r
7738 FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;\r
7739 else\r
7740 FLAG_V = (hi != 0) << 7;\r
7741 return;\r
7742 }\r
7743 m68ki_exception_illegal();\r
7744\r
7745#endif\r
7746}\r
7747\r
7748\r
7749M68KMAKE_OP(nbcd, 8, ., d)\r
7750{\r
7751 uint* r_dst = &DY;\r
7752 uint dst = *r_dst;\r
7753 uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1());\r
7754\r
7755 if(res != 0x9a)\r
7756 {\r
7757 FLAG_V = ~res; /* Undefined V behavior */\r
7758\r
7759 if((res & 0x0f) == 0xa)\r
7760 res = (res & 0xf0) + 0x10;\r
7761\r
7762 res = MASK_OUT_ABOVE_8(res);\r
7763\r
7764 FLAG_V &= res; /* Undefined V behavior part II */\r
7765\r
7766 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
7767\r
7768 FLAG_Z |= res;\r
7769 FLAG_C = CFLAG_SET;\r
7770 FLAG_X = XFLAG_SET;\r
7771 }\r
7772 else\r
7773 {\r
7774 FLAG_V = VFLAG_CLEAR;\r
7775 FLAG_C = CFLAG_CLEAR;\r
7776 FLAG_X = XFLAG_CLEAR;\r
7777 }\r
7778 FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
7779}\r
7780\r
7781\r
7782M68KMAKE_OP(nbcd, 8, ., .)\r
7783{\r
7784 uint ea = M68KMAKE_GET_EA_AY_8;\r
7785 uint dst = m68ki_read_8(ea);\r
7786 uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1());\r
7787\r
7788 if(res != 0x9a)\r
7789 {\r
7790 FLAG_V = ~res; /* Undefined V behavior */\r
7791\r
7792 if((res & 0x0f) == 0xa)\r
7793 res = (res & 0xf0) + 0x10;\r
7794\r
7795 res = MASK_OUT_ABOVE_8(res);\r
7796\r
7797 FLAG_V &= res; /* Undefined V behavior part II */\r
7798\r
7799 m68ki_write_8(ea, MASK_OUT_ABOVE_8(res));\r
7800\r
7801 FLAG_Z |= res;\r
7802 FLAG_C = CFLAG_SET;\r
7803 FLAG_X = XFLAG_SET;\r
7804 }\r
7805 else\r
7806 {\r
7807 FLAG_V = VFLAG_CLEAR;\r
7808 FLAG_C = CFLAG_CLEAR;\r
7809 FLAG_X = XFLAG_CLEAR;\r
7810 }\r
7811 FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
7812}\r
7813\r
7814\r
7815M68KMAKE_OP(neg, 8, ., d)\r
7816{\r
7817 uint* r_dst = &DY;\r
7818 uint res = 0 - MASK_OUT_ABOVE_8(*r_dst);\r
7819\r
7820 FLAG_N = NFLAG_8(res);\r
7821 FLAG_C = FLAG_X = CFLAG_8(res);\r
7822 FLAG_V = *r_dst & res;\r
7823 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
7824\r
7825 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;\r
7826}\r
7827\r
7828\r
7829M68KMAKE_OP(neg, 8, ., .)\r
7830{\r
7831 uint ea = M68KMAKE_GET_EA_AY_8;\r
7832 uint src = m68ki_read_8(ea);\r
7833 uint res = 0 - src;\r
7834\r
7835 FLAG_N = NFLAG_8(res);\r
7836 FLAG_C = FLAG_X = CFLAG_8(res);\r
7837 FLAG_V = src & res;\r
7838 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
7839\r
7840 m68ki_write_8(ea, FLAG_Z);\r
7841}\r
7842\r
7843\r
7844M68KMAKE_OP(neg, 16, ., d)\r
7845{\r
7846 uint* r_dst = &DY;\r
7847 uint res = 0 - MASK_OUT_ABOVE_16(*r_dst);\r
7848\r
7849 FLAG_N = NFLAG_16(res);\r
7850 FLAG_C = FLAG_X = CFLAG_16(res);\r
7851 FLAG_V = (*r_dst & res)>>8;\r
7852 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
7853\r
7854 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
7855}\r
7856\r
7857\r
7858M68KMAKE_OP(neg, 16, ., .)\r
7859{\r
7860 uint ea = M68KMAKE_GET_EA_AY_16;\r
7861 uint src = m68ki_read_16(ea);\r
7862 uint res = 0 - src;\r
7863\r
7864 FLAG_N = NFLAG_16(res);\r
7865 FLAG_C = FLAG_X = CFLAG_16(res);\r
7866 FLAG_V = (src & res)>>8;\r
7867 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
7868\r
7869 m68ki_write_16(ea, FLAG_Z);\r
7870}\r
7871\r
7872\r
7873M68KMAKE_OP(neg, 32, ., d)\r
7874{\r
7875 uint* r_dst = &DY;\r
7876 uint res = 0 - *r_dst;\r
7877\r
7878 FLAG_N = NFLAG_32(res);\r
7879 FLAG_C = FLAG_X = CFLAG_SUB_32(*r_dst, 0, res);\r
7880 FLAG_V = (*r_dst & res)>>24;\r
7881 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
7882\r
7883 *r_dst = FLAG_Z;\r
7884}\r
7885\r
7886\r
7887M68KMAKE_OP(neg, 32, ., .)\r
7888{\r
7889 uint ea = M68KMAKE_GET_EA_AY_32;\r
7890 uint src = m68ki_read_32(ea);\r
7891 uint res = 0 - src;\r
7892\r
7893 FLAG_N = NFLAG_32(res);\r
7894 FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res);\r
7895 FLAG_V = (src & res)>>24;\r
7896 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
7897\r
7898 m68ki_write_32(ea, FLAG_Z);\r
7899}\r
7900\r
7901\r
7902M68KMAKE_OP(negx, 8, ., d)\r
7903{\r
7904 uint* r_dst = &DY;\r
7905 uint res = 0 - MASK_OUT_ABOVE_8(*r_dst) - XFLAG_AS_1();\r
7906\r
7907 FLAG_N = NFLAG_8(res);\r
7908 FLAG_X = FLAG_C = CFLAG_8(res);\r
7909 FLAG_V = *r_dst & res;\r
7910\r
7911 res = MASK_OUT_ABOVE_8(res);\r
7912 FLAG_Z |= res;\r
7913\r
7914 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
7915}\r
7916\r
7917\r
7918M68KMAKE_OP(negx, 8, ., .)\r
7919{\r
7920 uint ea = M68KMAKE_GET_EA_AY_8;\r
7921 uint src = m68ki_read_8(ea);\r
7922 uint res = 0 - src - XFLAG_AS_1();\r
7923\r
7924 FLAG_N = NFLAG_8(res);\r
7925 FLAG_X = FLAG_C = CFLAG_8(res);\r
7926 FLAG_V = src & res;\r
7927\r
7928 res = MASK_OUT_ABOVE_8(res);\r
7929 FLAG_Z |= res;\r
7930\r
7931 m68ki_write_8(ea, res);\r
7932}\r
7933\r
7934\r
7935M68KMAKE_OP(negx, 16, ., d)\r
7936{\r
7937 uint* r_dst = &DY;\r
7938 uint res = 0 - MASK_OUT_ABOVE_16(*r_dst) - XFLAG_AS_1();\r
7939\r
7940 FLAG_N = NFLAG_16(res);\r
7941 FLAG_X = FLAG_C = CFLAG_16(res);\r
7942 FLAG_V = (*r_dst & res)>>8;\r
7943\r
7944 res = MASK_OUT_ABOVE_16(res);\r
7945 FLAG_Z |= res;\r
7946\r
7947 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
7948}\r
7949\r
7950\r
7951M68KMAKE_OP(negx, 16, ., .)\r
7952{\r
7953 uint ea = M68KMAKE_GET_EA_AY_16;\r
7954 uint src = m68ki_read_16(ea);\r
7955 uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1();\r
7956\r
7957 FLAG_N = NFLAG_16(res);\r
7958 FLAG_X = FLAG_C = CFLAG_16(res);\r
7959 FLAG_V = (src & res)>>8;\r
7960\r
7961 res = MASK_OUT_ABOVE_16(res);\r
7962 FLAG_Z |= res;\r
7963\r
7964 m68ki_write_16(ea, res);\r
7965}\r
7966\r
7967\r
7968M68KMAKE_OP(negx, 32, ., d)\r
7969{\r
7970 uint* r_dst = &DY;\r
7971 uint res = 0 - MASK_OUT_ABOVE_32(*r_dst) - XFLAG_AS_1();\r
7972\r
7973 FLAG_N = NFLAG_32(res);\r
7974 FLAG_X = FLAG_C = CFLAG_SUB_32(*r_dst, 0, res);\r
7975 FLAG_V = (*r_dst & res)>>24;\r
7976\r
7977 res = MASK_OUT_ABOVE_32(res);\r
7978 FLAG_Z |= res;\r
7979\r
7980 *r_dst = res;\r
7981}\r
7982\r
7983\r
7984M68KMAKE_OP(negx, 32, ., .)\r
7985{\r
7986 uint ea = M68KMAKE_GET_EA_AY_32;\r
7987 uint src = m68ki_read_32(ea);\r
7988 uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1();\r
7989\r
7990 FLAG_N = NFLAG_32(res);\r
7991 FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res);\r
7992 FLAG_V = (src & res)>>24;\r
7993\r
7994 res = MASK_OUT_ABOVE_32(res);\r
7995 FLAG_Z |= res;\r
7996\r
7997 m68ki_write_32(ea, res);\r
7998}\r
7999\r
8000\r
8001M68KMAKE_OP(nop, 0, ., .)\r
8002{\r
8003 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
8004}\r
8005\r
8006\r
8007M68KMAKE_OP(not, 8, ., d)\r
8008{\r
8009 uint* r_dst = &DY;\r
8010 uint res = MASK_OUT_ABOVE_8(~*r_dst);\r
8011\r
8012 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
8013\r
8014 FLAG_N = NFLAG_8(res);\r
8015 FLAG_Z = res;\r
8016 FLAG_C = CFLAG_CLEAR;\r
8017 FLAG_V = VFLAG_CLEAR;\r
8018}\r
8019\r
8020\r
8021M68KMAKE_OP(not, 8, ., .)\r
8022{\r
8023 uint ea = M68KMAKE_GET_EA_AY_8;\r
8024 uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));\r
8025\r
8026 m68ki_write_8(ea, res);\r
8027\r
8028 FLAG_N = NFLAG_8(res);\r
8029 FLAG_Z = res;\r
8030 FLAG_C = CFLAG_CLEAR;\r
8031 FLAG_V = VFLAG_CLEAR;\r
8032}\r
8033\r
8034\r
8035M68KMAKE_OP(not, 16, ., d)\r
8036{\r
8037 uint* r_dst = &DY;\r
8038 uint res = MASK_OUT_ABOVE_16(~*r_dst);\r
8039\r
8040 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
8041\r
8042 FLAG_N = NFLAG_16(res);\r
8043 FLAG_Z = res;\r
8044 FLAG_C = CFLAG_CLEAR;\r
8045 FLAG_V = VFLAG_CLEAR;\r
8046}\r
8047\r
8048\r
8049M68KMAKE_OP(not, 16, ., .)\r
8050{\r
8051 uint ea = M68KMAKE_GET_EA_AY_16;\r
8052 uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea));\r
8053\r
8054 m68ki_write_16(ea, res);\r
8055\r
8056 FLAG_N = NFLAG_16(res);\r
8057 FLAG_Z = res;\r
8058 FLAG_C = CFLAG_CLEAR;\r
8059 FLAG_V = VFLAG_CLEAR;\r
8060}\r
8061\r
8062\r
8063M68KMAKE_OP(not, 32, ., d)\r
8064{\r
8065 uint* r_dst = &DY;\r
8066 uint res = *r_dst = MASK_OUT_ABOVE_32(~*r_dst);\r
8067\r
8068 FLAG_N = NFLAG_32(res);\r
8069 FLAG_Z = res;\r
8070 FLAG_C = CFLAG_CLEAR;\r
8071 FLAG_V = VFLAG_CLEAR;\r
8072}\r
8073\r
8074\r
8075M68KMAKE_OP(not, 32, ., .)\r
8076{\r
8077 uint ea = M68KMAKE_GET_EA_AY_32;\r
8078 uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea));\r
8079\r
8080 m68ki_write_32(ea, res);\r
8081\r
8082 FLAG_N = NFLAG_32(res);\r
8083 FLAG_Z = res;\r
8084 FLAG_C = CFLAG_CLEAR;\r
8085 FLAG_V = VFLAG_CLEAR;\r
8086}\r
8087\r
8088\r
8089M68KMAKE_OP(or, 8, er, d)\r
8090{\r
8091 uint res = MASK_OUT_ABOVE_8((DX |= MASK_OUT_ABOVE_8(DY)));\r
8092\r
8093 FLAG_N = NFLAG_8(res);\r
8094 FLAG_Z = res;\r
8095 FLAG_C = CFLAG_CLEAR;\r
8096 FLAG_V = VFLAG_CLEAR;\r
8097}\r
8098\r
8099\r
8100M68KMAKE_OP(or, 8, er, .)\r
8101{\r
8102 uint res = MASK_OUT_ABOVE_8((DX |= M68KMAKE_GET_OPER_AY_8));\r
8103\r
8104 FLAG_N = NFLAG_8(res);\r
8105 FLAG_Z = res;\r
8106 FLAG_C = CFLAG_CLEAR;\r
8107 FLAG_V = VFLAG_CLEAR;\r
8108}\r
8109\r
8110\r
8111M68KMAKE_OP(or, 16, er, d)\r
8112{\r
8113 uint res = MASK_OUT_ABOVE_16((DX |= MASK_OUT_ABOVE_16(DY)));\r
8114\r
8115 FLAG_N = NFLAG_16(res);\r
8116 FLAG_Z = res;\r
8117 FLAG_C = CFLAG_CLEAR;\r
8118 FLAG_V = VFLAG_CLEAR;\r
8119}\r
8120\r
8121\r
8122M68KMAKE_OP(or, 16, er, .)\r
8123{\r
8124 uint res = MASK_OUT_ABOVE_16((DX |= M68KMAKE_GET_OPER_AY_16));\r
8125\r
8126 FLAG_N = NFLAG_16(res);\r
8127 FLAG_Z = res;\r
8128 FLAG_C = CFLAG_CLEAR;\r
8129 FLAG_V = VFLAG_CLEAR;\r
8130}\r
8131\r
8132\r
8133M68KMAKE_OP(or, 32, er, d)\r
8134{\r
8135 uint res = DX |= DY;\r
8136\r
8137 FLAG_N = NFLAG_32(res);\r
8138 FLAG_Z = res;\r
8139 FLAG_C = CFLAG_CLEAR;\r
8140 FLAG_V = VFLAG_CLEAR;\r
8141}\r
8142\r
8143\r
8144M68KMAKE_OP(or, 32, er, .)\r
8145{\r
8146 uint res = DX |= M68KMAKE_GET_OPER_AY_32;\r
8147\r
8148 FLAG_N = NFLAG_32(res);\r
8149 FLAG_Z = res;\r
8150 FLAG_C = CFLAG_CLEAR;\r
8151 FLAG_V = VFLAG_CLEAR;\r
8152}\r
8153\r
8154\r
8155M68KMAKE_OP(or, 8, re, .)\r
8156{\r
8157 uint ea = M68KMAKE_GET_EA_AY_8;\r
8158 uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));\r
8159\r
8160 m68ki_write_8(ea, res);\r
8161\r
8162 FLAG_N = NFLAG_8(res);\r
8163 FLAG_Z = res;\r
8164 FLAG_C = CFLAG_CLEAR;\r
8165 FLAG_V = VFLAG_CLEAR;\r
8166}\r
8167\r
8168\r
8169M68KMAKE_OP(or, 16, re, .)\r
8170{\r
8171 uint ea = M68KMAKE_GET_EA_AY_16;\r
8172 uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea));\r
8173\r
8174 m68ki_write_16(ea, res);\r
8175\r
8176 FLAG_N = NFLAG_16(res);\r
8177 FLAG_Z = res;\r
8178 FLAG_C = CFLAG_CLEAR;\r
8179 FLAG_V = VFLAG_CLEAR;\r
8180}\r
8181\r
8182\r
8183M68KMAKE_OP(or, 32, re, .)\r
8184{\r
8185 uint ea = M68KMAKE_GET_EA_AY_32;\r
8186 uint res = DX | m68ki_read_32(ea);\r
8187\r
8188 m68ki_write_32(ea, res);\r
8189\r
8190 FLAG_N = NFLAG_32(res);\r
8191 FLAG_Z = res;\r
8192 FLAG_C = CFLAG_CLEAR;\r
8193 FLAG_V = VFLAG_CLEAR;\r
8194}\r
8195\r
8196\r
8197M68KMAKE_OP(ori, 8, ., d)\r
8198{\r
8199 uint res = MASK_OUT_ABOVE_8((DY |= OPER_I_8()));\r
8200\r
8201 FLAG_N = NFLAG_8(res);\r
8202 FLAG_Z = res;\r
8203 FLAG_C = CFLAG_CLEAR;\r
8204 FLAG_V = VFLAG_CLEAR;\r
8205}\r
8206\r
8207\r
8208M68KMAKE_OP(ori, 8, ., .)\r
8209{\r
8210 uint src = OPER_I_8();\r
8211 uint ea = M68KMAKE_GET_EA_AY_8;\r
8212 uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));\r
8213\r
8214 m68ki_write_8(ea, res);\r
8215\r
8216 FLAG_N = NFLAG_8(res);\r
8217 FLAG_Z = res;\r
8218 FLAG_C = CFLAG_CLEAR;\r
8219 FLAG_V = VFLAG_CLEAR;\r
8220}\r
8221\r
8222\r
8223M68KMAKE_OP(ori, 16, ., d)\r
8224{\r
8225 uint res = MASK_OUT_ABOVE_16(DY |= OPER_I_16());\r
8226\r
8227 FLAG_N = NFLAG_16(res);\r
8228 FLAG_Z = res;\r
8229 FLAG_C = CFLAG_CLEAR;\r
8230 FLAG_V = VFLAG_CLEAR;\r
8231}\r
8232\r
8233\r
8234M68KMAKE_OP(ori, 16, ., .)\r
8235{\r
8236 uint src = OPER_I_16();\r
8237 uint ea = M68KMAKE_GET_EA_AY_16;\r
8238 uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea));\r
8239\r
8240 m68ki_write_16(ea, res);\r
8241\r
8242 FLAG_N = NFLAG_16(res);\r
8243 FLAG_Z = res;\r
8244 FLAG_C = CFLAG_CLEAR;\r
8245 FLAG_V = VFLAG_CLEAR;\r
8246}\r
8247\r
8248\r
8249M68KMAKE_OP(ori, 32, ., d)\r
8250{\r
8251 uint res = DY |= OPER_I_32();\r
8252\r
8253 FLAG_N = NFLAG_32(res);\r
8254 FLAG_Z = res;\r
8255 FLAG_C = CFLAG_CLEAR;\r
8256 FLAG_V = VFLAG_CLEAR;\r
8257}\r
8258\r
8259\r
8260M68KMAKE_OP(ori, 32, ., .)\r
8261{\r
8262 uint src = OPER_I_32();\r
8263 uint ea = M68KMAKE_GET_EA_AY_32;\r
8264 uint res = src | m68ki_read_32(ea);\r
8265\r
8266 m68ki_write_32(ea, res);\r
8267\r
8268 FLAG_N = NFLAG_32(res);\r
8269 FLAG_Z = res;\r
8270 FLAG_C = CFLAG_CLEAR;\r
8271 FLAG_V = VFLAG_CLEAR;\r
8272}\r
8273\r
8274\r
8275M68KMAKE_OP(ori, 16, toc, .)\r
8276{\r
8277 m68ki_set_ccr(m68ki_get_ccr() | OPER_I_16());\r
8278}\r
8279\r
8280\r
8281M68KMAKE_OP(ori, 16, tos, .)\r
8282{\r
8283 if(FLAG_S)\r
8284 {\r
8285 uint src = OPER_I_16();\r
8286 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
8287 m68ki_set_sr(m68ki_get_sr() | src);\r
8288 return;\r
8289 }\r
8290 m68ki_exception_privilege_violation();\r
8291}\r
8292\r
8293\r
8294M68KMAKE_OP(pack, 16, rr, .)\r
8295{\r
8296 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
8297 {\r
8298 /* Note: DX and DY are reversed in Motorola's docs */\r
8299 uint src = DY + OPER_I_16();\r
8300 uint* r_dst = &DX;\r
8301\r
8302 *r_dst = MASK_OUT_BELOW_8(*r_dst) | ((src >> 4) & 0x00f0) | (src & 0x000f);\r
8303 return;\r
8304 }\r
8305 m68ki_exception_illegal();\r
8306}\r
8307\r
8308\r
8309M68KMAKE_OP(pack, 16, mm, ax7)\r
8310{\r
8311 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
8312 {\r
8313 /* Note: AX and AY are reversed in Motorola's docs */\r
8314 uint ea_src = EA_AY_PD_8();\r
8315 uint src = m68ki_read_8(ea_src);\r
8316 ea_src = EA_AY_PD_8();\r
8317 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();\r
8318\r
8319 m68ki_write_8(EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));\r
8320 return;\r
8321 }\r
8322 m68ki_exception_illegal();\r
8323}\r
8324\r
8325\r
8326M68KMAKE_OP(pack, 16, mm, ay7)\r
8327{\r
8328 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
8329 {\r
8330 /* Note: AX and AY are reversed in Motorola's docs */\r
8331 uint ea_src = EA_A7_PD_8();\r
8332 uint src = m68ki_read_8(ea_src);\r
8333 ea_src = EA_A7_PD_8();\r
8334 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();\r
8335\r
8336 m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));\r
8337 return;\r
8338 }\r
8339 m68ki_exception_illegal();\r
8340}\r
8341\r
8342\r
8343M68KMAKE_OP(pack, 16, mm, axy7)\r
8344{\r
8345 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
8346 {\r
8347 uint ea_src = EA_A7_PD_8();\r
8348 uint src = m68ki_read_8(ea_src);\r
8349 ea_src = EA_A7_PD_8();\r
8350 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();\r
8351\r
8352 m68ki_write_8(EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));\r
8353 return;\r
8354 }\r
8355 m68ki_exception_illegal();\r
8356}\r
8357\r
8358\r
8359M68KMAKE_OP(pack, 16, mm, .)\r
8360{\r
8361 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
8362 {\r
8363 /* Note: AX and AY are reversed in Motorola's docs */\r
8364 uint ea_src = EA_AY_PD_8();\r
8365 uint src = m68ki_read_8(ea_src);\r
8366 ea_src = EA_AY_PD_8();\r
8367 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();\r
8368\r
8369 m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));\r
8370 return;\r
8371 }\r
8372 m68ki_exception_illegal();\r
8373}\r
8374\r
8375\r
8376M68KMAKE_OP(pea, 32, ., .)\r
8377{\r
8378 uint ea = M68KMAKE_GET_EA_AY_32;\r
8379\r
8380 m68ki_push_32(ea);\r
8381}\r
8382\r
8383\r
8384M68KMAKE_OP(pflush, 32, ., .)\r
8385{\r
8386 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
8387 {\r
8388 // Nothing to do, unless address translation cache is emulated\r
8389 return;\r
8390 }\r
8391 m68ki_exception_illegal();\r
8392}\r
8393\r
8394\r
8395M68KMAKE_OP(reset, 0, ., .)\r
8396{\r
8397 if(FLAG_S)\r
8398 {\r
8399 m68ki_output_reset(); /* auto-disable (see m68kcpu.h) */\r
8400 USE_CYCLES(CYC_RESET);\r
8401 return;\r
8402 }\r
8403 m68ki_exception_privilege_violation();\r
8404}\r
8405\r
8406\r
8407M68KMAKE_OP(ror, 8, s, .)\r
8408{\r
8409 uint* r_dst = &DY;\r
8410 uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
8411 uint shift = orig_shift & 7;\r
8412 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
8413 uint res = ROR_8(src, shift);\r
8414\r
8415 if(orig_shift != 0)\r
8416 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8417\r
8418 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
8419\r
8420 FLAG_N = NFLAG_8(res);\r
8421 FLAG_Z = res;\r
8422 FLAG_C = src << (9-orig_shift);\r
8423 FLAG_V = VFLAG_CLEAR;\r
8424}\r
8425\r
8426\r
8427M68KMAKE_OP(ror, 16, s, .)\r
8428{\r
8429 uint* r_dst = &DY;\r
8430 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
8431 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
8432 uint res = ROR_16(src, shift);\r
8433\r
8434 if(shift != 0)\r
8435 USE_CYCLES(shift<<CYC_SHIFT);\r
8436\r
8437 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
8438\r
8439 FLAG_N = NFLAG_16(res);\r
8440 FLAG_Z = res;\r
8441 FLAG_C = src << (9-shift);\r
8442 FLAG_V = VFLAG_CLEAR;\r
8443}\r
8444\r
8445\r
8446M68KMAKE_OP(ror, 32, s, .)\r
8447{\r
8448 uint* r_dst = &DY;\r
8449 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
8450 uint64 src = *r_dst;\r
8451 uint res = ROR_32(src, shift);\r
8452\r
8453 if(shift != 0)\r
8454 USE_CYCLES(shift<<CYC_SHIFT);\r
8455\r
8456 *r_dst = res;\r
8457\r
8458 FLAG_N = NFLAG_32(res);\r
8459 FLAG_Z = res;\r
8460 FLAG_C = src << (9-shift);\r
8461 FLAG_V = VFLAG_CLEAR;\r
8462}\r
8463\r
8464\r
8465M68KMAKE_OP(ror, 8, r, .)\r
8466{\r
8467 uint* r_dst = &DY;\r
8468 uint orig_shift = DX & 0x3f;\r
8469 uint shift = orig_shift & 7;\r
8470 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
8471 uint res = ROR_8(src, shift);\r
8472\r
8473 if(orig_shift != 0)\r
8474 {\r
8475 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8476\r
8477 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
8478 FLAG_C = src << (8-((shift-1)&7));\r
8479 FLAG_N = NFLAG_8(res);\r
8480 FLAG_Z = res;\r
8481 FLAG_V = VFLAG_CLEAR;\r
8482 return;\r
8483 }\r
8484\r
8485 FLAG_C = CFLAG_CLEAR;\r
8486 FLAG_N = NFLAG_8(src);\r
8487 FLAG_Z = src;\r
8488 FLAG_V = VFLAG_CLEAR;\r
8489}\r
8490\r
8491\r
8492M68KMAKE_OP(ror, 16, r, .)\r
8493{\r
8494 uint* r_dst = &DY;\r
8495 uint orig_shift = DX & 0x3f;\r
8496 uint shift = orig_shift & 15;\r
8497 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
8498 uint res = ROR_16(src, shift);\r
8499\r
8500 if(orig_shift != 0)\r
8501 {\r
8502 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8503\r
8504 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
8505 FLAG_C = (src >> ((shift - 1) & 15)) << 8;\r
8506 FLAG_N = NFLAG_16(res);\r
8507 FLAG_Z = res;\r
8508 FLAG_V = VFLAG_CLEAR;\r
8509 return;\r
8510 }\r
8511\r
8512 FLAG_C = CFLAG_CLEAR;\r
8513 FLAG_N = NFLAG_16(src);\r
8514 FLAG_Z = src;\r
8515 FLAG_V = VFLAG_CLEAR;\r
8516}\r
8517\r
8518\r
8519M68KMAKE_OP(ror, 32, r, .)\r
8520{\r
8521 uint* r_dst = &DY;\r
8522 uint orig_shift = DX & 0x3f;\r
8523 uint shift = orig_shift & 31;\r
8524 uint64 src = *r_dst;\r
8525 uint res = ROR_32(src, shift);\r
8526\r
8527 if(orig_shift != 0)\r
8528 {\r
8529 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8530\r
8531 *r_dst = res;\r
8532 FLAG_C = (src >> ((shift - 1) & 31)) << 8;\r
8533 FLAG_N = NFLAG_32(res);\r
8534 FLAG_Z = res;\r
8535 FLAG_V = VFLAG_CLEAR;\r
8536 return;\r
8537 }\r
8538\r
8539 FLAG_C = CFLAG_CLEAR;\r
8540 FLAG_N = NFLAG_32(src);\r
8541 FLAG_Z = src;\r
8542 FLAG_V = VFLAG_CLEAR;\r
8543}\r
8544\r
8545\r
8546M68KMAKE_OP(ror, 16, ., .)\r
8547{\r
8548 uint ea = M68KMAKE_GET_EA_AY_16;\r
8549 uint src = m68ki_read_16(ea);\r
8550 uint res = ROR_16(src, 1);\r
8551\r
8552 m68ki_write_16(ea, res);\r
8553\r
8554 FLAG_N = NFLAG_16(res);\r
8555 FLAG_Z = res;\r
8556 FLAG_C = src << 8;\r
8557 FLAG_V = VFLAG_CLEAR;\r
8558}\r
8559\r
8560\r
8561M68KMAKE_OP(rol, 8, s, .)\r
8562{\r
8563 uint* r_dst = &DY;\r
8564 uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
8565 uint shift = orig_shift & 7;\r
8566 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
8567 uint res = ROL_8(src, shift);\r
8568\r
8569 if(orig_shift != 0)\r
8570 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8571\r
8572 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
8573\r
8574 FLAG_N = NFLAG_8(res);\r
8575 FLAG_Z = res;\r
8576 FLAG_C = src << orig_shift;\r
8577 FLAG_V = VFLAG_CLEAR;\r
8578}\r
8579\r
8580\r
8581M68KMAKE_OP(rol, 16, s, .)\r
8582{\r
8583 uint* r_dst = &DY;\r
8584 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
8585 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
8586 uint res = ROL_16(src, shift);\r
8587\r
8588 if(shift != 0)\r
8589 USE_CYCLES(shift<<CYC_SHIFT);\r
8590\r
8591 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
8592\r
8593 FLAG_N = NFLAG_16(res);\r
8594 FLAG_Z = res;\r
8595 FLAG_C = src >> (8-shift);\r
8596 FLAG_V = VFLAG_CLEAR;\r
8597}\r
8598\r
8599\r
8600M68KMAKE_OP(rol, 32, s, .)\r
8601{\r
8602 uint* r_dst = &DY;\r
8603 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
8604 uint64 src = *r_dst;\r
8605 uint res = ROL_32(src, shift);\r
8606\r
8607 if(shift != 0)\r
8608 USE_CYCLES(shift<<CYC_SHIFT);\r
8609\r
8610 *r_dst = res;\r
8611\r
8612 FLAG_N = NFLAG_32(res);\r
8613 FLAG_Z = res;\r
8614 FLAG_C = src >> (24-shift);\r
8615 FLAG_V = VFLAG_CLEAR;\r
8616}\r
8617\r
8618\r
8619M68KMAKE_OP(rol, 8, r, .)\r
8620{\r
8621 uint* r_dst = &DY;\r
8622 uint orig_shift = DX & 0x3f;\r
8623 uint shift = orig_shift & 7;\r
8624 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
8625 uint res = ROL_8(src, shift);\r
8626\r
8627 if(orig_shift != 0)\r
8628 {\r
8629 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8630\r
8631 if(shift != 0)\r
8632 {\r
8633 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
8634 FLAG_C = src << shift;\r
8635 FLAG_N = NFLAG_8(res);\r
8636 FLAG_Z = res;\r
8637 FLAG_V = VFLAG_CLEAR;\r
8638 return;\r
8639 }\r
8640 FLAG_C = (src & 1)<<8;\r
8641 FLAG_N = NFLAG_8(src);\r
8642 FLAG_Z = src;\r
8643 FLAG_V = VFLAG_CLEAR;\r
8644 return;\r
8645 }\r
8646\r
8647 FLAG_C = CFLAG_CLEAR;\r
8648 FLAG_N = NFLAG_8(src);\r
8649 FLAG_Z = src;\r
8650 FLAG_V = VFLAG_CLEAR;\r
8651}\r
8652\r
8653\r
8654M68KMAKE_OP(rol, 16, r, .)\r
8655{\r
8656 uint* r_dst = &DY;\r
8657 uint orig_shift = DX & 0x3f;\r
8658 uint shift = orig_shift & 15;\r
8659 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
8660 uint res = MASK_OUT_ABOVE_16(ROL_16(src, shift));\r
8661\r
8662 if(orig_shift != 0)\r
8663 {\r
8664 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8665\r
8666 if(shift != 0)\r
8667 {\r
8668 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
8669 FLAG_C = (src << shift) >> 8;\r
8670 FLAG_N = NFLAG_16(res);\r
8671 FLAG_Z = res;\r
8672 FLAG_V = VFLAG_CLEAR;\r
8673 return;\r
8674 }\r
8675 FLAG_C = (src & 1)<<8;\r
8676 FLAG_N = NFLAG_16(src);\r
8677 FLAG_Z = src;\r
8678 FLAG_V = VFLAG_CLEAR;\r
8679 return;\r
8680 }\r
8681\r
8682 FLAG_C = CFLAG_CLEAR;\r
8683 FLAG_N = NFLAG_16(src);\r
8684 FLAG_Z = src;\r
8685 FLAG_V = VFLAG_CLEAR;\r
8686}\r
8687\r
8688\r
8689M68KMAKE_OP(rol, 32, r, .)\r
8690{\r
8691 uint* r_dst = &DY;\r
8692 uint orig_shift = DX & 0x3f;\r
8693 uint shift = orig_shift & 31;\r
8694 uint64 src = *r_dst;\r
8695 uint res = ROL_32(src, shift);\r
8696\r
8697 if(orig_shift != 0)\r
8698 {\r
8699 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8700\r
8701 *r_dst = res;\r
8702\r
8703 FLAG_C = (src >> (32 - shift)) << 8;\r
8704 FLAG_N = NFLAG_32(res);\r
8705 FLAG_Z = res;\r
8706 FLAG_V = VFLAG_CLEAR;\r
8707 return;\r
8708 }\r
8709\r
8710 FLAG_C = CFLAG_CLEAR;\r
8711 FLAG_N = NFLAG_32(src);\r
8712 FLAG_Z = src;\r
8713 FLAG_V = VFLAG_CLEAR;\r
8714}\r
8715\r
8716\r
8717M68KMAKE_OP(rol, 16, ., .)\r
8718{\r
8719 uint ea = M68KMAKE_GET_EA_AY_16;\r
8720 uint src = m68ki_read_16(ea);\r
8721 uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1));\r
8722\r
8723 m68ki_write_16(ea, res);\r
8724\r
8725 FLAG_N = NFLAG_16(res);\r
8726 FLAG_Z = res;\r
8727 FLAG_C = src >> 7;\r
8728 FLAG_V = VFLAG_CLEAR;\r
8729}\r
8730\r
8731\r
8732M68KMAKE_OP(roxr, 8, s, .)\r
8733{\r
8734 uint* r_dst = &DY;\r
8735 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
8736 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
8737 uint res = ROR_9(src | (XFLAG_AS_1() << 8), shift);\r
8738\r
8739 if(shift != 0)\r
8740 USE_CYCLES(shift<<CYC_SHIFT);\r
8741\r
8742 FLAG_C = FLAG_X = res;\r
8743 res = MASK_OUT_ABOVE_8(res);\r
8744\r
8745 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
8746\r
8747 FLAG_N = NFLAG_8(res);\r
8748 FLAG_Z = res;\r
8749 FLAG_V = VFLAG_CLEAR;\r
8750}\r
8751\r
8752\r
8753M68KMAKE_OP(roxr, 16, s, .)\r
8754{\r
8755 uint* r_dst = &DY;\r
8756 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
8757 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
8758 uint res = ROR_17(src | (XFLAG_AS_1() << 16), shift);\r
8759\r
8760 if(shift != 0)\r
8761 USE_CYCLES(shift<<CYC_SHIFT);\r
8762\r
8763 FLAG_C = FLAG_X = res >> 8;\r
8764 res = MASK_OUT_ABOVE_16(res);\r
8765\r
8766 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
8767\r
8768 FLAG_N = NFLAG_16(res);\r
8769 FLAG_Z = res;\r
8770 FLAG_V = VFLAG_CLEAR;\r
8771}\r
8772\r
8773\r
8774M68KMAKE_OP(roxr, 32, s, .)\r
8775{\r
8776#if M68K_USE_64_BIT\r
8777\r
8778 uint* r_dst = &DY;\r
8779 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
8780 uint64 src = *r_dst;\r
8781 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);\r
8782\r
8783 if(shift != 0)\r
8784 USE_CYCLES(shift<<CYC_SHIFT);\r
8785\r
8786 res = ROR_33_64(res, shift);\r
8787\r
8788 FLAG_C = FLAG_X = res >> 24;\r
8789 res = MASK_OUT_ABOVE_32(res);\r
8790\r
8791 *r_dst = res;\r
8792\r
8793 FLAG_N = NFLAG_32(res);\r
8794 FLAG_Z = res;\r
8795 FLAG_V = VFLAG_CLEAR;\r
8796\r
8797#else\r
8798\r
8799 uint* r_dst = &DY;\r
8800 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
8801 uint src = *r_dst;\r
8802 uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift)));\r
8803 uint new_x_flag = src & (1 << (shift - 1));\r
8804\r
8805 if(shift != 0)\r
8806 USE_CYCLES(shift<<CYC_SHIFT);\r
8807\r
8808 *r_dst = res;\r
8809\r
8810 FLAG_C = FLAG_X = (new_x_flag != 0)<<8;\r
8811 FLAG_N = NFLAG_32(res);\r
8812 FLAG_Z = res;\r
8813 FLAG_V = VFLAG_CLEAR;\r
8814\r
8815#endif\r
8816}\r
8817\r
8818\r
8819M68KMAKE_OP(roxr, 8, r, .)\r
8820{\r
8821 uint* r_dst = &DY;\r
8822 uint orig_shift = DX & 0x3f;\r
8823\r
8824 if(orig_shift != 0)\r
8825 {\r
8826 uint shift = orig_shift % 9;\r
8827 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
8828 uint res = ROR_9(src | (XFLAG_AS_1() << 8), shift);\r
8829\r
8830 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8831\r
8832 FLAG_C = FLAG_X = res;\r
8833 res = MASK_OUT_ABOVE_8(res);\r
8834\r
8835 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
8836 FLAG_N = NFLAG_8(res);\r
8837 FLAG_Z = res;\r
8838 FLAG_V = VFLAG_CLEAR;\r
8839 return;\r
8840 }\r
8841\r
8842 FLAG_C = FLAG_X;\r
8843 FLAG_N = NFLAG_8(*r_dst);\r
8844 FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);\r
8845 FLAG_V = VFLAG_CLEAR;\r
8846}\r
8847\r
8848\r
8849M68KMAKE_OP(roxr, 16, r, .)\r
8850{\r
8851 uint* r_dst = &DY;\r
8852 uint orig_shift = DX & 0x3f;\r
8853\r
8854 if(orig_shift != 0)\r
8855 {\r
8856 uint shift = orig_shift % 17;\r
8857 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
8858 uint res = ROR_17(src | (XFLAG_AS_1() << 16), shift);\r
8859\r
8860 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8861\r
8862 FLAG_C = FLAG_X = res >> 8;\r
8863 res = MASK_OUT_ABOVE_16(res);\r
8864\r
8865 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
8866 FLAG_N = NFLAG_16(res);\r
8867 FLAG_Z = res;\r
8868 FLAG_V = VFLAG_CLEAR;\r
8869 return;\r
8870 }\r
8871\r
8872 FLAG_C = FLAG_X;\r
8873 FLAG_N = NFLAG_16(*r_dst);\r
8874 FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);\r
8875 FLAG_V = VFLAG_CLEAR;\r
8876}\r
8877\r
8878\r
8879M68KMAKE_OP(roxr, 32, r, .)\r
8880{\r
8881#if M68K_USE_64_BIT\r
8882\r
8883 uint* r_dst = &DY;\r
8884 uint orig_shift = DX & 0x3f;\r
8885\r
8886 if(orig_shift != 0)\r
8887 {\r
8888 uint shift = orig_shift % 33;\r
8889 uint64 src = *r_dst;\r
8890 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);\r
8891\r
8892 res = ROR_33_64(res, shift);\r
8893\r
8894 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8895\r
8896 FLAG_C = FLAG_X = res >> 24;\r
8897 res = MASK_OUT_ABOVE_32(res);\r
8898\r
8899 *r_dst = res;\r
8900 FLAG_N = NFLAG_32(res);\r
8901 FLAG_Z = res;\r
8902 FLAG_V = VFLAG_CLEAR;\r
8903 return;\r
8904 }\r
8905\r
8906 FLAG_C = FLAG_X;\r
8907 FLAG_N = NFLAG_32(*r_dst);\r
8908 FLAG_Z = *r_dst;\r
8909 FLAG_V = VFLAG_CLEAR;\r
8910\r
8911#else\r
8912\r
8913 uint* r_dst = &DY;\r
8914 uint orig_shift = DX & 0x3f;\r
8915 uint shift = orig_shift % 33;\r
8916 uint src = *r_dst;\r
8917 uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift)));\r
8918 uint new_x_flag = src & (1 << (shift - 1));\r
8919\r
8920 if(orig_shift != 0)\r
8921 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8922\r
8923 if(shift != 0)\r
8924 {\r
8925 *r_dst = res;\r
8926 FLAG_X = (new_x_flag != 0)<<8;\r
8927 }\r
8928 else\r
8929 res = src;\r
8930 FLAG_C = FLAG_X;\r
8931 FLAG_N = NFLAG_32(res);\r
8932 FLAG_Z = res;\r
8933 FLAG_V = VFLAG_CLEAR;\r
8934\r
8935#endif\r
8936}\r
8937\r
8938\r
8939M68KMAKE_OP(roxr, 16, ., .)\r
8940{\r
8941 uint ea = M68KMAKE_GET_EA_AY_16;\r
8942 uint src = m68ki_read_16(ea);\r
8943 uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1);\r
8944\r
8945 FLAG_C = FLAG_X = res >> 8;\r
8946 res = MASK_OUT_ABOVE_16(res);\r
8947\r
8948 m68ki_write_16(ea, res);\r
8949\r
8950 FLAG_N = NFLAG_16(res);\r
8951 FLAG_Z = res;\r
8952 FLAG_V = VFLAG_CLEAR;\r
8953}\r
8954\r
8955\r
8956M68KMAKE_OP(roxl, 8, s, .)\r
8957{\r
8958 uint* r_dst = &DY;\r
8959 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
8960 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
8961 uint res = ROL_9(src | (XFLAG_AS_1() << 8), shift);\r
8962\r
8963 if(shift != 0)\r
8964 USE_CYCLES(shift<<CYC_SHIFT);\r
8965\r
8966 FLAG_C = FLAG_X = res;\r
8967 res = MASK_OUT_ABOVE_8(res);\r
8968\r
8969 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
8970\r
8971 FLAG_N = NFLAG_8(res);\r
8972 FLAG_Z = res;\r
8973 FLAG_V = VFLAG_CLEAR;\r
8974}\r
8975\r
8976\r
8977M68KMAKE_OP(roxl, 16, s, .)\r
8978{\r
8979 uint* r_dst = &DY;\r
8980 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
8981 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
8982 uint res = ROL_17(src | (XFLAG_AS_1() << 16), shift);\r
8983\r
8984 if(shift != 0)\r
8985 USE_CYCLES(shift<<CYC_SHIFT);\r
8986\r
8987 FLAG_C = FLAG_X = res >> 8;\r
8988 res = MASK_OUT_ABOVE_16(res);\r
8989\r
8990 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
8991\r
8992 FLAG_N = NFLAG_16(res);\r
8993 FLAG_Z = res;\r
8994 FLAG_V = VFLAG_CLEAR;\r
8995}\r
8996\r
8997\r
8998M68KMAKE_OP(roxl, 32, s, .)\r
8999{\r
9000#if M68K_USE_64_BIT\r
9001\r
9002 uint* r_dst = &DY;\r
9003 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
9004 uint64 src = *r_dst;\r
9005 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);\r
9006\r
9007 if(shift != 0)\r
9008 USE_CYCLES(shift<<CYC_SHIFT);\r
9009\r
9010 res = ROL_33_64(res, shift);\r
9011\r
9012 FLAG_C = FLAG_X = res >> 24;\r
9013 res = MASK_OUT_ABOVE_32(res);\r
9014\r
9015 *r_dst = res;\r
9016\r
9017 FLAG_N = NFLAG_32(res);\r
9018 FLAG_Z = res;\r
9019 FLAG_V = VFLAG_CLEAR;\r
9020\r
9021#else\r
9022\r
9023 uint* r_dst = &DY;\r
9024 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
9025 uint src = *r_dst;\r
9026 uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1)));\r
9027 uint new_x_flag = src & (1 << (32 - shift));\r
9028\r
9029 if(shift != 0)\r
9030 USE_CYCLES(shift<<CYC_SHIFT);\r
9031\r
9032 *r_dst = res;\r
9033\r
9034 FLAG_C = FLAG_X = (new_x_flag != 0)<<8;\r
9035 FLAG_N = NFLAG_32(res);\r
9036 FLAG_Z = res;\r
9037 FLAG_V = VFLAG_CLEAR;\r
9038\r
9039#endif\r
9040}\r
9041\r
9042\r
9043M68KMAKE_OP(roxl, 8, r, .)\r
9044{\r
9045 uint* r_dst = &DY;\r
9046 uint orig_shift = DX & 0x3f;\r
9047\r
9048\r
9049 if(orig_shift != 0)\r
9050 {\r
9051 uint shift = orig_shift % 9;\r
9052 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
9053 uint res = ROL_9(src | (XFLAG_AS_1() << 8), shift);\r
9054\r
9055 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
9056\r
9057 FLAG_C = FLAG_X = res;\r
9058 res = MASK_OUT_ABOVE_8(res);\r
9059\r
9060 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
9061 FLAG_N = NFLAG_8(res);\r
9062 FLAG_Z = res;\r
9063 FLAG_V = VFLAG_CLEAR;\r
9064 return;\r
9065 }\r
9066\r
9067 FLAG_C = FLAG_X;\r
9068 FLAG_N = NFLAG_8(*r_dst);\r
9069 FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);\r
9070 FLAG_V = VFLAG_CLEAR;\r
9071}\r
9072\r
9073\r
9074M68KMAKE_OP(roxl, 16, r, .)\r
9075{\r
9076 uint* r_dst = &DY;\r
9077 uint orig_shift = DX & 0x3f;\r
9078\r
9079 if(orig_shift != 0)\r
9080 {\r
9081 uint shift = orig_shift % 17;\r
9082 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
9083 uint res = ROL_17(src | (XFLAG_AS_1() << 16), shift);\r
9084\r
9085 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
9086\r
9087 FLAG_C = FLAG_X = res >> 8;\r
9088 res = MASK_OUT_ABOVE_16(res);\r
9089\r
9090 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
9091 FLAG_N = NFLAG_16(res);\r
9092 FLAG_Z = res;\r
9093 FLAG_V = VFLAG_CLEAR;\r
9094 return;\r
9095 }\r
9096\r
9097 FLAG_C = FLAG_X;\r
9098 FLAG_N = NFLAG_16(*r_dst);\r
9099 FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);\r
9100 FLAG_V = VFLAG_CLEAR;\r
9101}\r
9102\r
9103\r
9104M68KMAKE_OP(roxl, 32, r, .)\r
9105{\r
9106#if M68K_USE_64_BIT\r
9107\r
9108 uint* r_dst = &DY;\r
9109 uint orig_shift = DX & 0x3f;\r
9110\r
9111 if(orig_shift != 0)\r
9112 {\r
9113 uint shift = orig_shift % 33;\r
9114 uint64 src = *r_dst;\r
9115 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);\r
9116\r
9117 res = ROL_33_64(res, shift);\r
9118\r
9119 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
9120\r
9121 FLAG_C = FLAG_X = res >> 24;\r
9122 res = MASK_OUT_ABOVE_32(res);\r
9123\r
9124 *r_dst = res;\r
9125 FLAG_N = NFLAG_32(res);\r
9126 FLAG_Z = res;\r
9127 FLAG_V = VFLAG_CLEAR;\r
9128 return;\r
9129 }\r
9130\r
9131 FLAG_C = FLAG_X;\r
9132 FLAG_N = NFLAG_32(*r_dst);\r
9133 FLAG_Z = *r_dst;\r
9134 FLAG_V = VFLAG_CLEAR;\r
9135\r
9136#else\r
9137\r
9138 uint* r_dst = &DY;\r
9139 uint orig_shift = DX & 0x3f;\r
9140 uint shift = orig_shift % 33;\r
9141 uint src = *r_dst;\r
9142 uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1)));\r
9143 uint new_x_flag = src & (1 << (32 - shift));\r
9144\r
9145 if(orig_shift != 0)\r
9146 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
9147\r
9148 if(shift != 0)\r
9149 {\r
9150 *r_dst = res;\r
9151 FLAG_X = (new_x_flag != 0)<<8;\r
9152 }\r
9153 else\r
9154 res = src;\r
9155 FLAG_C = FLAG_X;\r
9156 FLAG_N = NFLAG_32(res);\r
9157 FLAG_Z = res;\r
9158 FLAG_V = VFLAG_CLEAR;\r
9159\r
9160#endif\r
9161}\r
9162\r
9163\r
9164M68KMAKE_OP(roxl, 16, ., .)\r
9165{\r
9166 uint ea = M68KMAKE_GET_EA_AY_16;\r
9167 uint src = m68ki_read_16(ea);\r
9168 uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1);\r
9169\r
9170 FLAG_C = FLAG_X = res >> 8;\r
9171 res = MASK_OUT_ABOVE_16(res);\r
9172\r
9173 m68ki_write_16(ea, res);\r
9174\r
9175 FLAG_N = NFLAG_16(res);\r
9176 FLAG_Z = res;\r
9177 FLAG_V = VFLAG_CLEAR;\r
9178}\r
9179\r
9180\r
9181M68KMAKE_OP(rtd, 32, ., .)\r
9182{\r
9183 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))\r
9184 {\r
9185 uint new_pc = m68ki_pull_32();\r
9186\r
9187 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
9188 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));\r
9189 m68ki_jump(new_pc);\r
9190 return;\r
9191 }\r
9192 m68ki_exception_illegal();\r
9193}\r
9194\r
9195\r
9196M68KMAKE_OP(rte, 32, ., .)\r
9197{\r
9198 if(FLAG_S)\r
9199 {\r
9200 uint new_sr;\r
9201 uint new_pc;\r
9202 uint format_word;\r
9203\r
9204 m68ki_rte_callback(); /* auto-disable (see m68kcpu.h) */\r
9205 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
9206\r
9207 if(CPU_TYPE_IS_000(CPU_TYPE))\r
9208 {\r
9209 new_sr = m68ki_pull_16();\r
9210 new_pc = m68ki_pull_32();\r
9211 m68ki_jump(new_pc);\r
9212 m68ki_set_sr(new_sr);\r
9213\r
9214 CPU_INSTR_MODE = INSTRUCTION_YES;\r
9215 CPU_RUN_MODE = RUN_MODE_NORMAL;\r
9216\r
9217 return;\r
9218 }\r
9219\r
9220 if(CPU_TYPE_IS_010(CPU_TYPE))\r
9221 {\r
9222 format_word = m68ki_read_16(REG_A[7]+6) >> 12;\r
9223 if(format_word == 0)\r
9224 {\r
9225 new_sr = m68ki_pull_16();\r
9226 new_pc = m68ki_pull_32();\r
9227 m68ki_fake_pull_16(); /* format word */\r
9228 m68ki_jump(new_pc);\r
9229 m68ki_set_sr(new_sr);\r
9230 CPU_INSTR_MODE = INSTRUCTION_YES;\r
9231 CPU_RUN_MODE = RUN_MODE_NORMAL;\r
9232 return;\r
9233 }\r
9234 CPU_INSTR_MODE = INSTRUCTION_YES;\r
9235 CPU_RUN_MODE = RUN_MODE_NORMAL;\r
9236 /* Not handling bus fault (9) */\r
9237 m68ki_exception_format_error();\r
9238 return;\r
9239 }\r
9240\r
9241 /* Otherwise it's 020 */\r
9242rte_loop:\r
9243 format_word = m68ki_read_16(REG_A[7]+6) >> 12;\r
9244 switch(format_word)\r
9245 {\r
9246 case 0: /* Normal */\r
9247 new_sr = m68ki_pull_16();\r
9248 new_pc = m68ki_pull_32();\r
9249 m68ki_fake_pull_16(); /* format word */\r
9250 m68ki_jump(new_pc);\r
9251 m68ki_set_sr(new_sr);\r
9252 CPU_INSTR_MODE = INSTRUCTION_YES;\r
9253 CPU_RUN_MODE = RUN_MODE_NORMAL;\r
9254 return;\r
9255 case 1: /* Throwaway */\r
9256 new_sr = m68ki_pull_16();\r
9257 m68ki_fake_pull_32(); /* program counter */\r
9258 m68ki_fake_pull_16(); /* format word */\r
9259 m68ki_set_sr_noint(new_sr);\r
9260 goto rte_loop;\r
9261 case 2: /* Trap */\r
9262 new_sr = m68ki_pull_16();\r
9263 new_pc = m68ki_pull_32();\r
9264 m68ki_fake_pull_16(); /* format word */\r
9265 m68ki_fake_pull_32(); /* address */\r
9266 m68ki_jump(new_pc);\r
9267 m68ki_set_sr(new_sr);\r
9268 CPU_INSTR_MODE = INSTRUCTION_YES;\r
9269 CPU_RUN_MODE = RUN_MODE_NORMAL;\r
9270 return;\r
9271 }\r
9272 /* Not handling long or short bus fault */\r
9273 CPU_INSTR_MODE = INSTRUCTION_YES;\r
9274 CPU_RUN_MODE = RUN_MODE_NORMAL;\r
9275 m68ki_exception_format_error();\r
9276 return;\r
9277 }\r
9278 m68ki_exception_privilege_violation();\r
9279}\r
9280\r
9281\r
9282M68KMAKE_OP(rtm, 32, ., .)\r
9283{\r
9284 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))\r
9285 {\r
9286 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
9287 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",\r
9288 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,\r
9289 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));\r
9290 return;\r
9291 }\r
9292 m68ki_exception_illegal();\r
9293}\r
9294\r
9295\r
9296M68KMAKE_OP(rtr, 32, ., .)\r
9297{\r
9298 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
9299 m68ki_set_ccr(m68ki_pull_16());\r
9300 m68ki_jump(m68ki_pull_32());\r
9301}\r
9302\r
9303\r
9304M68KMAKE_OP(rts, 32, ., .)\r
9305{\r
9306 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
9307 m68ki_jump(m68ki_pull_32());\r
9308}\r
9309\r
9310\r
9311M68KMAKE_OP(sbcd, 8, rr, .)\r
9312{\r
9313 uint* r_dst = &DX;\r
9314 uint src = DY;\r
9315 uint dst = *r_dst;\r
9316 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();\r
9317\r
9318// FLAG_V = ~res; /* Undefined V behavior */\r
9319 FLAG_V = VFLAG_CLEAR; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to assume cleared. */\r
9320\r
9321 if(res > 9)\r
9322 res -= 6;\r
9323 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);\r
9324 if(res > 0x99)\r
9325 {\r
9326 res += 0xa0;\r
9327 FLAG_X = FLAG_C = CFLAG_SET;\r
9328 FLAG_N = NFLAG_SET; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to follow carry. */\r
9329 }\r
9330 else\r
9331 FLAG_N = FLAG_X = FLAG_C = 0;\r
9332\r
9333 res = MASK_OUT_ABOVE_8(res);\r
9334\r
9335// FLAG_V &= res; /* Undefined V behavior part II */\r
9336// FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
9337 FLAG_Z |= res;\r
9338\r
9339 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
9340}\r
9341\r
9342\r
9343M68KMAKE_OP(sbcd, 8, mm, ax7)\r
9344{\r
9345 uint src = OPER_AY_PD_8();\r
9346 uint ea = EA_A7_PD_8();\r
9347 uint dst = m68ki_read_8(ea);\r
9348 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();\r
9349\r
9350// FLAG_V = ~res; /* Undefined V behavior */\r
9351 FLAG_V = VFLAG_CLEAR; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to return zero. */\r
9352\r
9353 if(res > 9)\r
9354 res -= 6;\r
9355 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);\r
9356 if(res > 0x99)\r
9357 {\r
9358 res += 0xa0;\r
9359 FLAG_X = FLAG_C = CFLAG_SET;\r
9360 FLAG_N = NFLAG_SET; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to follow carry. */\r
9361 }\r
9362 else\r
9363 FLAG_N = FLAG_X = FLAG_C = 0;\r
9364\r
9365 res = MASK_OUT_ABOVE_8(res);\r
9366\r
9367// FLAG_V &= res; /* Undefined V behavior part II */\r
9368// FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
9369 FLAG_Z |= res;\r
9370\r
9371 m68ki_write_8(ea, res);\r
9372}\r
9373\r
9374\r
9375M68KMAKE_OP(sbcd, 8, mm, ay7)\r
9376{\r
9377 uint src = OPER_A7_PD_8();\r
9378 uint ea = EA_AX_PD_8();\r
9379 uint dst = m68ki_read_8(ea);\r
9380 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();\r
9381\r
9382// FLAG_V = ~res; /* Undefined V behavior */\r
9383 FLAG_V = VFLAG_CLEAR; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to return zero. */\r
9384\r
9385 if(res > 9)\r
9386 res -= 6;\r
9387 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);\r
9388 if(res > 0x99)\r
9389 {\r
9390 res += 0xa0;\r
9391 FLAG_X = FLAG_C = CFLAG_SET;\r
9392 FLAG_N = NFLAG_SET; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to follow carry. */\r
9393 }\r
9394 else\r
9395 FLAG_N = FLAG_X = FLAG_C = 0;\r
9396\r
9397 res = MASK_OUT_ABOVE_8(res);\r
9398\r
9399// FLAG_V &= res; /* Undefined V behavior part II */\r
9400// FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
9401 FLAG_Z |= res;\r
9402\r
9403 m68ki_write_8(ea, res);\r
9404}\r
9405\r
9406\r
9407M68KMAKE_OP(sbcd, 8, mm, axy7)\r
9408{\r
9409 uint src = OPER_A7_PD_8();\r
9410 uint ea = EA_A7_PD_8();\r
9411 uint dst = m68ki_read_8(ea);\r
9412 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();\r
9413\r
9414// FLAG_V = ~res; /* Undefined V behavior */\r
9415 FLAG_V = VFLAG_CLEAR; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to return zero. */\r
9416\r
9417 if(res > 9)\r
9418 res -= 6;\r
9419 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);\r
9420 if(res > 0x99)\r
9421 {\r
9422 res += 0xa0;\r
9423 FLAG_X = FLAG_C = CFLAG_SET;\r
9424 FLAG_N = NFLAG_SET; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to follow carry. */\r
9425 }\r
9426 else\r
9427 FLAG_N = FLAG_X = FLAG_C = 0;\r
9428\r
9429 res = MASK_OUT_ABOVE_8(res);\r
9430\r
9431// FLAG_V &= res; /* Undefined V behavior part II */\r
9432// FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
9433 FLAG_Z |= res;\r
9434\r
9435 m68ki_write_8(ea, res);\r
9436}\r
9437\r
9438\r
9439M68KMAKE_OP(sbcd, 8, mm, .)\r
9440{\r
9441 uint src = OPER_AY_PD_8();\r
9442 uint ea = EA_AX_PD_8();\r
9443 uint dst = m68ki_read_8(ea);\r
9444 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();\r
9445\r
9446// FLAG_V = ~res; /* Undefined V behavior */\r
9447 FLAG_V = VFLAG_CLEAR; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to return zero. */\r
9448\r
9449 if(res > 9)\r
9450 res -= 6;\r
9451 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);\r
9452 if(res > 0x99)\r
9453 {\r
9454 res += 0xa0;\r
9455 FLAG_X = FLAG_C = CFLAG_SET;\r
9456 FLAG_N = NFLAG_SET; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to follow carry. */\r
9457 }\r
9458 else\r
9459 FLAG_N = FLAG_X = FLAG_C = 0;\r
9460\r
9461 res = MASK_OUT_ABOVE_8(res);\r
9462\r
9463// FLAG_V &= res; /* Undefined V behavior part II */\r
9464// FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
9465 FLAG_Z |= res;\r
9466\r
9467 m68ki_write_8(ea, res);\r
9468}\r
9469\r
9470\r
9471M68KMAKE_OP(st, 8, ., d)\r
9472{\r
9473 DY |= 0xff;\r
9474}\r
9475\r
9476\r
9477M68KMAKE_OP(st, 8, ., .)\r
9478{\r
9479 m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0xff);\r
9480}\r
9481\r
9482\r
9483M68KMAKE_OP(sf, 8, ., d)\r
9484{\r
9485 DY &= 0xffffff00;\r
9486}\r
9487\r
9488\r
9489M68KMAKE_OP(sf, 8, ., .)\r
9490{\r
9491 m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0);\r
9492}\r
9493\r
9494\r
9495M68KMAKE_OP(scc, 8, ., d)\r
9496{\r
9497 if(M68KMAKE_CC)\r
9498 {\r
9499 DY |= 0xff;\r
9500 USE_CYCLES(CYC_SCC_R_TRUE);\r
9501 return;\r
9502 }\r
9503 DY &= 0xffffff00;\r
9504}\r
9505\r
9506\r
9507M68KMAKE_OP(scc, 8, ., .)\r
9508{\r
9509 m68ki_write_8(M68KMAKE_GET_EA_AY_8, M68KMAKE_CC ? 0xff : 0);\r
9510}\r
9511\r
9512\r
9513M68KMAKE_OP(stop, 0, ., .)\r
9514{\r
9515 if(FLAG_S)\r
9516 {\r
9517 uint new_sr = OPER_I_16();\r
9518 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
9519 CPU_STOPPED |= STOP_LEVEL_STOP;\r
9520 m68ki_set_sr(new_sr);\r
9521 m68ki_remaining_cycles = 0;\r
9522 return;\r
9523 }\r
9524 m68ki_exception_privilege_violation();\r
9525}\r
9526\r
9527\r
9528M68KMAKE_OP(sub, 8, er, d)\r
9529{\r
9530 uint* r_dst = &DX;\r
9531 uint src = MASK_OUT_ABOVE_8(DY);\r
9532 uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
9533 uint res = dst - src;\r
9534\r
9535 FLAG_N = NFLAG_8(res);\r
9536 FLAG_X = FLAG_C = CFLAG_8(res);\r
9537 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
9538 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
9539\r
9540 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;\r
9541}\r
9542\r
9543\r
9544M68KMAKE_OP(sub, 8, er, .)\r
9545{\r
9546 uint* r_dst = &DX;\r
9547 uint src = M68KMAKE_GET_OPER_AY_8;\r
9548 uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
9549 uint res = dst - src;\r
9550\r
9551 FLAG_N = NFLAG_8(res);\r
9552 FLAG_X = FLAG_C = CFLAG_8(res);\r
9553 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
9554 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
9555\r
9556 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;\r
9557}\r
9558\r
9559\r
9560M68KMAKE_OP(sub, 16, er, d)\r
9561{\r
9562 uint* r_dst = &DX;\r
9563 uint src = MASK_OUT_ABOVE_16(DY);\r
9564 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
9565 uint res = dst - src;\r
9566\r
9567 FLAG_N = NFLAG_16(res);\r
9568 FLAG_X = FLAG_C = CFLAG_16(res);\r
9569 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
9570 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
9571\r
9572 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
9573}\r
9574\r
9575\r
9576M68KMAKE_OP(sub, 16, er, a)\r
9577{\r
9578 uint* r_dst = &DX;\r
9579 uint src = MASK_OUT_ABOVE_16(AY);\r
9580 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
9581 uint res = dst - src;\r
9582\r
9583 FLAG_N = NFLAG_16(res);\r
9584 FLAG_X = FLAG_C = CFLAG_16(res);\r
9585 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
9586 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
9587\r
9588 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
9589}\r
9590\r
9591\r
9592M68KMAKE_OP(sub, 16, er, .)\r
9593{\r
9594 uint* r_dst = &DX;\r
9595 uint src = M68KMAKE_GET_OPER_AY_16;\r
9596 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
9597 uint res = dst - src;\r
9598\r
9599 FLAG_N = NFLAG_16(res);\r
9600 FLAG_X = FLAG_C = CFLAG_16(res);\r
9601 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
9602 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
9603\r
9604 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
9605}\r
9606\r
9607\r
9608M68KMAKE_OP(sub, 32, er, d)\r
9609{\r
9610 uint* r_dst = &DX;\r
9611 uint src = DY;\r
9612 uint dst = *r_dst;\r
9613 uint res = dst - src;\r
9614\r
9615 FLAG_N = NFLAG_32(res);\r
9616 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
9617 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
9618 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
9619\r
9620 *r_dst = FLAG_Z;\r
9621}\r
9622\r
9623\r
9624M68KMAKE_OP(sub, 32, er, a)\r
9625{\r
9626 uint* r_dst = &DX;\r
9627 uint src = AY;\r
9628 uint dst = *r_dst;\r
9629 uint res = dst - src;\r
9630\r
9631 FLAG_N = NFLAG_32(res);\r
9632 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
9633 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
9634 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
9635\r
9636 *r_dst = FLAG_Z;\r
9637}\r
9638\r
9639\r
9640M68KMAKE_OP(sub, 32, er, .)\r
9641{\r
9642 uint* r_dst = &DX;\r
9643 uint src = M68KMAKE_GET_OPER_AY_32;\r
9644 uint dst = *r_dst;\r
9645 uint res = dst - src;\r
9646\r
9647 FLAG_N = NFLAG_32(res);\r
9648 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
9649 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
9650 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
9651\r
9652 *r_dst = FLAG_Z;\r
9653}\r
9654\r
9655\r
9656M68KMAKE_OP(sub, 8, re, .)\r
9657{\r
9658 uint ea = M68KMAKE_GET_EA_AY_8;\r
9659 uint src = MASK_OUT_ABOVE_8(DX);\r
9660 uint dst = m68ki_read_8(ea);\r
9661 uint res = dst - src;\r
9662\r
9663 FLAG_N = NFLAG_8(res);\r
9664 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
9665 FLAG_X = FLAG_C = CFLAG_8(res);\r
9666 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
9667\r
9668 m68ki_write_8(ea, FLAG_Z);\r
9669}\r
9670\r
9671\r
9672M68KMAKE_OP(sub, 16, re, .)\r
9673{\r
9674 uint ea = M68KMAKE_GET_EA_AY_16;\r
9675 uint src = MASK_OUT_ABOVE_16(DX);\r
9676 uint dst = m68ki_read_16(ea);\r
9677 uint res = dst - src;\r
9678\r
9679 FLAG_N = NFLAG_16(res);\r
9680 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
9681 FLAG_X = FLAG_C = CFLAG_16(res);\r
9682 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
9683\r
9684 m68ki_write_16(ea, FLAG_Z);\r
9685}\r
9686\r
9687\r
9688M68KMAKE_OP(sub, 32, re, .)\r
9689{\r
9690 uint ea = M68KMAKE_GET_EA_AY_32;\r
9691 uint src = DX;\r
9692 uint dst = m68ki_read_32(ea);\r
9693 uint res = dst - src;\r
9694\r
9695 FLAG_N = NFLAG_32(res);\r
9696 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
9697 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
9698 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
9699\r
9700 m68ki_write_32(ea, FLAG_Z);\r
9701}\r
9702\r
9703\r
9704M68KMAKE_OP(suba, 16, ., d)\r
9705{\r
9706 uint* r_dst = &AX;\r
9707\r
9708 *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(DY));\r
9709}\r
9710\r
9711\r
9712M68KMAKE_OP(suba, 16, ., a)\r
9713{\r
9714 uint* r_dst = &AX;\r
9715\r
9716 *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(AY));\r
9717}\r
9718\r
9719\r
9720M68KMAKE_OP(suba, 16, ., .)\r
9721{\r
9722 uint* r_dst = &AX;\r
9723\r
9724 *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(M68KMAKE_GET_OPER_AY_16));\r
9725}\r
9726\r
9727\r
9728M68KMAKE_OP(suba, 32, ., d)\r
9729{\r
9730 uint* r_dst = &AX;\r
9731\r
9732 *r_dst = MASK_OUT_ABOVE_32(*r_dst - DY);\r
9733}\r
9734\r
9735\r
9736M68KMAKE_OP(suba, 32, ., a)\r
9737{\r
9738 uint* r_dst = &AX;\r
9739\r
9740 *r_dst = MASK_OUT_ABOVE_32(*r_dst - AY);\r
9741}\r
9742\r
9743\r
9744M68KMAKE_OP(suba, 32, ., .)\r
9745{\r
9746 uint* r_dst = &AX;\r
9747\r
9748 *r_dst = MASK_OUT_ABOVE_32(*r_dst - M68KMAKE_GET_OPER_AY_32);\r
9749}\r
9750\r
9751\r
9752M68KMAKE_OP(subi, 8, ., d)\r
9753{\r
9754 uint* r_dst = &DY;\r
9755 uint src = OPER_I_8();\r
9756 uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
9757 uint res = dst - src;\r
9758\r
9759 FLAG_N = NFLAG_8(res);\r
9760 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
9761 FLAG_X = FLAG_C = CFLAG_8(res);\r
9762 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
9763\r
9764 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;\r
9765}\r
9766\r
9767\r
9768M68KMAKE_OP(subi, 8, ., .)\r
9769{\r
9770 uint src = OPER_I_8();\r
9771 uint ea = M68KMAKE_GET_EA_AY_8;\r
9772 uint dst = m68ki_read_8(ea);\r
9773 uint res = dst - src;\r
9774\r
9775 FLAG_N = NFLAG_8(res);\r
9776 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
9777 FLAG_X = FLAG_C = CFLAG_8(res);\r
9778 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
9779\r
9780 m68ki_write_8(ea, FLAG_Z);\r
9781}\r
9782\r
9783\r
9784M68KMAKE_OP(subi, 16, ., d)\r
9785{\r
9786 uint* r_dst = &DY;\r
9787 uint src = OPER_I_16();\r
9788 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
9789 uint res = dst - src;\r
9790\r
9791 FLAG_N = NFLAG_16(res);\r
9792 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
9793 FLAG_X = FLAG_C = CFLAG_16(res);\r
9794 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
9795\r
9796 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
9797}\r
9798\r
9799\r
9800M68KMAKE_OP(subi, 16, ., .)\r
9801{\r
9802 uint src = OPER_I_16();\r
9803 uint ea = M68KMAKE_GET_EA_AY_16;\r
9804 uint dst = m68ki_read_16(ea);\r
9805 uint res = dst - src;\r
9806\r
9807 FLAG_N = NFLAG_16(res);\r
9808 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
9809 FLAG_X = FLAG_C = CFLAG_16(res);\r
9810 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
9811\r
9812 m68ki_write_16(ea, FLAG_Z);\r
9813}\r
9814\r
9815\r
9816M68KMAKE_OP(subi, 32, ., d)\r
9817{\r
9818 uint* r_dst = &DY;\r
9819 uint src = OPER_I_32();\r
9820 uint dst = *r_dst;\r
9821 uint res = dst - src;\r
9822\r
9823 FLAG_N = NFLAG_32(res);\r
9824 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
9825 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
9826 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
9827\r
9828 *r_dst = FLAG_Z;\r
9829}\r
9830\r
9831\r
9832M68KMAKE_OP(subi, 32, ., .)\r
9833{\r
9834 uint src = OPER_I_32();\r
9835 uint ea = M68KMAKE_GET_EA_AY_32;\r
9836 uint dst = m68ki_read_32(ea);\r
9837 uint res = dst - src;\r
9838\r
9839 FLAG_N = NFLAG_32(res);\r
9840 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
9841 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
9842 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
9843\r
9844 m68ki_write_32(ea, FLAG_Z);\r
9845}\r
9846\r
9847\r
9848M68KMAKE_OP(subq, 8, ., d)\r
9849{\r
9850 uint* r_dst = &DY;\r
9851 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
9852 uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
9853 uint res = dst - src;\r
9854\r
9855 FLAG_N = NFLAG_8(res);\r
9856 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
9857 FLAG_X = FLAG_C = CFLAG_8(res);\r
9858 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
9859\r
9860 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;\r
9861}\r
9862\r
9863\r
9864M68KMAKE_OP(subq, 8, ., .)\r
9865{\r
9866 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
9867 uint ea = M68KMAKE_GET_EA_AY_8;\r
9868 uint dst = m68ki_read_8(ea);\r
9869 uint res = dst - src;\r
9870\r
9871 FLAG_N = NFLAG_8(res);\r
9872 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
9873 FLAG_X = FLAG_C = CFLAG_8(res);\r
9874 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
9875\r
9876 m68ki_write_8(ea, FLAG_Z);\r
9877}\r
9878\r
9879\r
9880M68KMAKE_OP(subq, 16, ., d)\r
9881{\r
9882 uint* r_dst = &DY;\r
9883 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
9884 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
9885 uint res = dst - src;\r
9886\r
9887 FLAG_N = NFLAG_16(res);\r
9888 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
9889 FLAG_X = FLAG_C = CFLAG_16(res);\r
9890 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
9891\r
9892 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
9893}\r
9894\r
9895\r
9896M68KMAKE_OP(subq, 16, ., a)\r
9897{\r
9898 uint* r_dst = &AY;\r
9899\r
9900 *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1));\r
9901}\r
9902\r
9903\r
9904M68KMAKE_OP(subq, 16, ., .)\r
9905{\r
9906 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
9907 uint ea = M68KMAKE_GET_EA_AY_16;\r
9908 uint dst = m68ki_read_16(ea);\r
9909 uint res = dst - src;\r
9910\r
9911 FLAG_N = NFLAG_16(res);\r
9912 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
9913 FLAG_X = FLAG_C = CFLAG_16(res);\r
9914 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
9915\r
9916 m68ki_write_16(ea, FLAG_Z);\r
9917}\r
9918\r
9919\r
9920M68KMAKE_OP(subq, 32, ., d)\r
9921{\r
9922 uint* r_dst = &DY;\r
9923 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
9924 uint dst = *r_dst;\r
9925 uint res = dst - src;\r
9926\r
9927 FLAG_N = NFLAG_32(res);\r
9928 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
9929 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
9930 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
9931\r
9932 *r_dst = FLAG_Z;\r
9933}\r
9934\r
9935\r
9936M68KMAKE_OP(subq, 32, ., a)\r
9937{\r
9938 uint* r_dst = &AY;\r
9939\r
9940 *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1));\r
9941}\r
9942\r
9943\r
9944M68KMAKE_OP(subq, 32, ., .)\r
9945{\r
9946 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
9947 uint ea = M68KMAKE_GET_EA_AY_32;\r
9948 uint dst = m68ki_read_32(ea);\r
9949 uint res = dst - src;\r
9950\r
9951 FLAG_N = NFLAG_32(res);\r
9952 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
9953 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
9954 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
9955\r
9956 m68ki_write_32(ea, FLAG_Z);\r
9957}\r
9958\r
9959\r
9960M68KMAKE_OP(subx, 8, rr, .)\r
9961{\r
9962 uint* r_dst = &DX;\r
9963 uint src = MASK_OUT_ABOVE_8(DY);\r
9964 uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
9965 uint res = dst - src - XFLAG_AS_1();\r
9966\r
9967 FLAG_N = NFLAG_8(res);\r
9968 FLAG_X = FLAG_C = CFLAG_8(res);\r
9969 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
9970\r
9971 res = MASK_OUT_ABOVE_8(res);\r
9972 FLAG_Z |= res;\r
9973\r
9974 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
9975}\r
9976\r
9977\r
9978M68KMAKE_OP(subx, 16, rr, .)\r
9979{\r
9980 uint* r_dst = &DX;\r
9981 uint src = MASK_OUT_ABOVE_16(DY);\r
9982 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
9983 uint res = dst - src - XFLAG_AS_1();\r
9984\r
9985 FLAG_N = NFLAG_16(res);\r
9986 FLAG_X = FLAG_C = CFLAG_16(res);\r
9987 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
9988\r
9989 res = MASK_OUT_ABOVE_16(res);\r
9990 FLAG_Z |= res;\r
9991\r
9992 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
9993}\r
9994\r
9995\r
9996M68KMAKE_OP(subx, 32, rr, .)\r
9997{\r
9998 uint* r_dst = &DX;\r
9999 uint src = DY;\r
10000 uint dst = *r_dst;\r
10001 uint res = dst - src - XFLAG_AS_1();\r
10002\r
10003 FLAG_N = NFLAG_32(res);\r
10004 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
10005 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
10006\r
10007 res = MASK_OUT_ABOVE_32(res);\r
10008 FLAG_Z |= res;\r
10009\r
10010 *r_dst = res;\r
10011}\r
10012\r
10013\r
10014M68KMAKE_OP(subx, 8, mm, ax7)\r
10015{\r
10016 uint src = OPER_AY_PD_8();\r
10017 uint ea = EA_A7_PD_8();\r
10018 uint dst = m68ki_read_8(ea);\r
10019 uint res = dst - src - XFLAG_AS_1();\r
10020\r
10021 FLAG_N = NFLAG_8(res);\r
10022 FLAG_X = FLAG_C = CFLAG_8(res);\r
10023 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
10024\r
10025 res = MASK_OUT_ABOVE_8(res);\r
10026 FLAG_Z |= res;\r
10027\r
10028 m68ki_write_8(ea, res);\r
10029}\r
10030\r
10031\r
10032M68KMAKE_OP(subx, 8, mm, ay7)\r
10033{\r
10034 uint src = OPER_A7_PD_8();\r
10035 uint ea = EA_AX_PD_8();\r
10036 uint dst = m68ki_read_8(ea);\r
10037 uint res = dst - src - XFLAG_AS_1();\r
10038\r
10039 FLAG_N = NFLAG_8(res);\r
10040 FLAG_X = FLAG_C = CFLAG_8(res);\r
10041 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
10042\r
10043 res = MASK_OUT_ABOVE_8(res);\r
10044 FLAG_Z |= res;\r
10045\r
10046 m68ki_write_8(ea, res);\r
10047}\r
10048\r
10049\r
10050M68KMAKE_OP(subx, 8, mm, axy7)\r
10051{\r
10052 uint src = OPER_A7_PD_8();\r
10053 uint ea = EA_A7_PD_8();\r
10054 uint dst = m68ki_read_8(ea);\r
10055 uint res = dst - src - XFLAG_AS_1();\r
10056\r
10057 FLAG_N = NFLAG_8(res);\r
10058 FLAG_X = FLAG_C = CFLAG_8(res);\r
10059 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
10060\r
10061 res = MASK_OUT_ABOVE_8(res);\r
10062 FLAG_Z |= res;\r
10063\r
10064 m68ki_write_8(ea, res);\r
10065}\r
10066\r
10067\r
10068M68KMAKE_OP(subx, 8, mm, .)\r
10069{\r
10070 uint src = OPER_AY_PD_8();\r
10071 uint ea = EA_AX_PD_8();\r
10072 uint dst = m68ki_read_8(ea);\r
10073 uint res = dst - src - XFLAG_AS_1();\r
10074\r
10075 FLAG_N = NFLAG_8(res);\r
10076 FLAG_X = FLAG_C = CFLAG_8(res);\r
10077 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
10078\r
10079 res = MASK_OUT_ABOVE_8(res);\r
10080 FLAG_Z |= res;\r
10081\r
10082 m68ki_write_8(ea, res);\r
10083}\r
10084\r
10085\r
10086M68KMAKE_OP(subx, 16, mm, .)\r
10087{\r
10088 uint src = OPER_AY_PD_16();\r
10089 uint ea = EA_AX_PD_16();\r
10090 uint dst = m68ki_read_16(ea);\r
10091 uint res = dst - src - XFLAG_AS_1();\r
10092\r
10093 FLAG_N = NFLAG_16(res);\r
10094 FLAG_X = FLAG_C = CFLAG_16(res);\r
10095 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
10096\r
10097 res = MASK_OUT_ABOVE_16(res);\r
10098 FLAG_Z |= res;\r
10099\r
10100 m68ki_write_16(ea, res);\r
10101}\r
10102\r
10103\r
10104M68KMAKE_OP(subx, 32, mm, .)\r
10105{\r
10106 uint src = OPER_AY_PD_32();\r
10107 uint ea = EA_AX_PD_32();\r
10108 uint dst = m68ki_read_32(ea);\r
10109 uint res = dst - src - XFLAG_AS_1();\r
10110\r
10111 FLAG_N = NFLAG_32(res);\r
10112 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
10113 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
10114\r
10115 res = MASK_OUT_ABOVE_32(res);\r
10116 FLAG_Z |= res;\r
10117\r
10118 m68ki_write_32(ea, res);\r
10119}\r
10120\r
10121\r
10122M68KMAKE_OP(swap, 32, ., .)\r
10123{\r
10124 uint* r_dst = &DY;\r
10125\r
10126 FLAG_Z = MASK_OUT_ABOVE_32(*r_dst<<16);\r
10127 *r_dst = (*r_dst>>16) | FLAG_Z;\r
10128\r
10129 FLAG_Z = *r_dst;\r
10130 FLAG_N = NFLAG_32(*r_dst);\r
10131 FLAG_C = CFLAG_CLEAR;\r
10132 FLAG_V = VFLAG_CLEAR;\r
10133}\r
10134\r
10135\r
10136M68KMAKE_OP(tas, 8, ., d)\r
10137{\r
10138 uint* r_dst = &DY;\r
10139\r
10140 FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);\r
10141 FLAG_N = NFLAG_8(*r_dst);\r
10142 FLAG_V = VFLAG_CLEAR;\r
10143 FLAG_C = CFLAG_CLEAR;\r
10144 *r_dst |= 0x80;\r
10145}\r
10146\r
10147\r
10148M68KMAKE_OP(tas, 8, ., .)\r
10149{\r
10150 uint ea = M68KMAKE_GET_EA_AY_8;\r
10151 uint dst = m68ki_read_8(ea);\r
10152\r
10153 FLAG_Z = dst;\r
10154 FLAG_N = NFLAG_8(dst);\r
10155 FLAG_V = VFLAG_CLEAR;\r
10156 FLAG_C = CFLAG_CLEAR;\r
10157// m68ki_write_8(ea, dst | 0x80); // notaz: genesis, but only to mem\r
10158}\r
10159\r
10160\r
10161M68KMAKE_OP(trap, 0, ., .)\r
10162{\r
10163 /* Trap#n stacks exception frame type 0 */\r
10164 m68ki_exception_trapN(EXCEPTION_TRAP_BASE + (REG_IR & 0xf)); /* HJB 990403 */\r
10165}\r
10166\r
10167\r
10168M68KMAKE_OP(trapt, 0, ., .)\r
10169{\r
10170 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10171 {\r
10172 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */\r
10173 return;\r
10174 }\r
10175 m68ki_exception_illegal();\r
10176}\r
10177\r
10178\r
10179M68KMAKE_OP(trapt, 16, ., .)\r
10180{\r
10181 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10182 {\r
10183 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */\r
10184 return;\r
10185 }\r
10186 m68ki_exception_illegal();\r
10187}\r
10188\r
10189\r
10190M68KMAKE_OP(trapt, 32, ., .)\r
10191{\r
10192 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10193 {\r
10194 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */\r
10195 return;\r
10196 }\r
10197 m68ki_exception_illegal();\r
10198}\r
10199\r
10200\r
10201M68KMAKE_OP(trapf, 0, ., .)\r
10202{\r
10203 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10204 {\r
10205 return;\r
10206 }\r
10207 m68ki_exception_illegal();\r
10208}\r
10209\r
10210\r
10211M68KMAKE_OP(trapf, 16, ., .)\r
10212{\r
10213 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10214 {\r
10215 REG_PC += 2;\r
10216 return;\r
10217 }\r
10218 m68ki_exception_illegal();\r
10219}\r
10220\r
10221\r
10222M68KMAKE_OP(trapf, 32, ., .)\r
10223{\r
10224 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10225 {\r
10226 REG_PC += 4;\r
10227 return;\r
10228 }\r
10229 m68ki_exception_illegal();\r
10230}\r
10231\r
10232\r
10233M68KMAKE_OP(trapcc, 0, ., .)\r
10234{\r
10235 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10236 {\r
10237 if(M68KMAKE_CC)\r
10238 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */\r
10239 return;\r
10240 }\r
10241 m68ki_exception_illegal();\r
10242}\r
10243\r
10244\r
10245M68KMAKE_OP(trapcc, 16, ., .)\r
10246{\r
10247 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10248 {\r
10249 if(M68KMAKE_CC)\r
10250 {\r
10251 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */\r
10252 return;\r
10253 }\r
10254 REG_PC += 2;\r
10255 return;\r
10256 }\r
10257 m68ki_exception_illegal();\r
10258}\r
10259\r
10260\r
10261M68KMAKE_OP(trapcc, 32, ., .)\r
10262{\r
10263 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10264 {\r
10265 if(M68KMAKE_CC)\r
10266 {\r
10267 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */\r
10268 return;\r
10269 }\r
10270 REG_PC += 4;\r
10271 return;\r
10272 }\r
10273 m68ki_exception_illegal();\r
10274}\r
10275\r
10276\r
10277M68KMAKE_OP(trapv, 0, ., .)\r
10278{\r
10279 if(COND_VC())\r
10280 {\r
10281 return;\r
10282 }\r
10283 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */\r
10284}\r
10285\r
10286\r
10287M68KMAKE_OP(tst, 8, ., d)\r
10288{\r
10289 uint res = MASK_OUT_ABOVE_8(DY);\r
10290\r
10291 FLAG_N = NFLAG_8(res);\r
10292 FLAG_Z = res;\r
10293 FLAG_V = VFLAG_CLEAR;\r
10294 FLAG_C = CFLAG_CLEAR;\r
10295}\r
10296\r
10297\r
10298M68KMAKE_OP(tst, 8, ., .)\r
10299{\r
10300 uint res = M68KMAKE_GET_OPER_AY_8;\r
10301\r
10302 FLAG_N = NFLAG_8(res);\r
10303 FLAG_Z = res;\r
10304 FLAG_V = VFLAG_CLEAR;\r
10305 FLAG_C = CFLAG_CLEAR;\r
10306}\r
10307\r
10308\r
10309M68KMAKE_OP(tst, 8, ., pcdi)\r
10310{\r
10311 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10312 {\r
10313 uint res = OPER_PCDI_8();\r
10314\r
10315 FLAG_N = NFLAG_8(res);\r
10316 FLAG_Z = res;\r
10317 FLAG_V = VFLAG_CLEAR;\r
10318 FLAG_C = CFLAG_CLEAR;\r
10319 return;\r
10320 }\r
10321 m68ki_exception_illegal();\r
10322}\r
10323\r
10324\r
10325M68KMAKE_OP(tst, 8, ., pcix)\r
10326{\r
10327 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10328 {\r
10329 uint res = OPER_PCIX_8();\r
10330\r
10331 FLAG_N = NFLAG_8(res);\r
10332 FLAG_Z = res;\r
10333 FLAG_V = VFLAG_CLEAR;\r
10334 FLAG_C = CFLAG_CLEAR;\r
10335 return;\r
10336 }\r
10337 m68ki_exception_illegal();\r
10338}\r
10339\r
10340\r
10341M68KMAKE_OP(tst, 8, ., i)\r
10342{\r
10343 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10344 {\r
10345 uint res = OPER_I_8();\r
10346\r
10347 FLAG_N = NFLAG_8(res);\r
10348 FLAG_Z = res;\r
10349 FLAG_V = VFLAG_CLEAR;\r
10350 FLAG_C = CFLAG_CLEAR;\r
10351 return;\r
10352 }\r
10353 m68ki_exception_illegal();\r
10354}\r
10355\r
10356\r
10357M68KMAKE_OP(tst, 16, ., d)\r
10358{\r
10359 uint res = MASK_OUT_ABOVE_16(DY);\r
10360\r
10361 FLAG_N = NFLAG_16(res);\r
10362 FLAG_Z = res;\r
10363 FLAG_V = VFLAG_CLEAR;\r
10364 FLAG_C = CFLAG_CLEAR;\r
10365}\r
10366\r
10367\r
10368M68KMAKE_OP(tst, 16, ., a)\r
10369{\r
10370 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10371 {\r
10372 uint res = MAKE_INT_16(AY);\r
10373\r
10374 FLAG_N = NFLAG_16(res);\r
10375 FLAG_Z = res;\r
10376 FLAG_V = VFLAG_CLEAR;\r
10377 FLAG_C = CFLAG_CLEAR;\r
10378 return;\r
10379 }\r
10380 m68ki_exception_illegal();\r
10381}\r
10382\r
10383\r
10384M68KMAKE_OP(tst, 16, ., .)\r
10385{\r
10386 uint res = M68KMAKE_GET_OPER_AY_16;\r
10387\r
10388 FLAG_N = NFLAG_16(res);\r
10389 FLAG_Z = res;\r
10390 FLAG_V = VFLAG_CLEAR;\r
10391 FLAG_C = CFLAG_CLEAR;\r
10392}\r
10393\r
10394\r
10395M68KMAKE_OP(tst, 16, ., pcdi)\r
10396{\r
10397 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10398 {\r
10399 uint res = OPER_PCDI_16();\r
10400\r
10401 FLAG_N = NFLAG_16(res);\r
10402 FLAG_Z = res;\r
10403 FLAG_V = VFLAG_CLEAR;\r
10404 FLAG_C = CFLAG_CLEAR;\r
10405 return;\r
10406 }\r
10407 m68ki_exception_illegal();\r
10408}\r
10409\r
10410\r
10411M68KMAKE_OP(tst, 16, ., pcix)\r
10412{\r
10413 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10414 {\r
10415 uint res = OPER_PCIX_16();\r
10416\r
10417 FLAG_N = NFLAG_16(res);\r
10418 FLAG_Z = res;\r
10419 FLAG_V = VFLAG_CLEAR;\r
10420 FLAG_C = CFLAG_CLEAR;\r
10421 return;\r
10422 }\r
10423 m68ki_exception_illegal();\r
10424}\r
10425\r
10426\r
10427M68KMAKE_OP(tst, 16, ., i)\r
10428{\r
10429 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10430 {\r
10431 uint res = OPER_I_16();\r
10432\r
10433 FLAG_N = NFLAG_16(res);\r
10434 FLAG_Z = res;\r
10435 FLAG_V = VFLAG_CLEAR;\r
10436 FLAG_C = CFLAG_CLEAR;\r
10437 return;\r
10438 }\r
10439 m68ki_exception_illegal();\r
10440}\r
10441\r
10442\r
10443M68KMAKE_OP(tst, 32, ., d)\r
10444{\r
10445 uint res = DY;\r
10446\r
10447 FLAG_N = NFLAG_32(res);\r
10448 FLAG_Z = res;\r
10449 FLAG_V = VFLAG_CLEAR;\r
10450 FLAG_C = CFLAG_CLEAR;\r
10451}\r
10452\r
10453\r
10454M68KMAKE_OP(tst, 32, ., a)\r
10455{\r
10456 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10457 {\r
10458 uint res = AY;\r
10459\r
10460 FLAG_N = NFLAG_32(res);\r
10461 FLAG_Z = res;\r
10462 FLAG_V = VFLAG_CLEAR;\r
10463 FLAG_C = CFLAG_CLEAR;\r
10464 return;\r
10465 }\r
10466 m68ki_exception_illegal();\r
10467}\r
10468\r
10469\r
10470M68KMAKE_OP(tst, 32, ., .)\r
10471{\r
10472 uint res = M68KMAKE_GET_OPER_AY_32;\r
10473\r
10474 FLAG_N = NFLAG_32(res);\r
10475 FLAG_Z = res;\r
10476 FLAG_V = VFLAG_CLEAR;\r
10477 FLAG_C = CFLAG_CLEAR;\r
10478}\r
10479\r
10480\r
10481M68KMAKE_OP(tst, 32, ., pcdi)\r
10482{\r
10483 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10484 {\r
10485 uint res = OPER_PCDI_32();\r
10486\r
10487 FLAG_N = NFLAG_32(res);\r
10488 FLAG_Z = res;\r
10489 FLAG_V = VFLAG_CLEAR;\r
10490 FLAG_C = CFLAG_CLEAR;\r
10491 return;\r
10492 }\r
10493 m68ki_exception_illegal();\r
10494}\r
10495\r
10496\r
10497M68KMAKE_OP(tst, 32, ., pcix)\r
10498{\r
10499 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10500 {\r
10501 uint res = OPER_PCIX_32();\r
10502\r
10503 FLAG_N = NFLAG_32(res);\r
10504 FLAG_Z = res;\r
10505 FLAG_V = VFLAG_CLEAR;\r
10506 FLAG_C = CFLAG_CLEAR;\r
10507 return;\r
10508 }\r
10509 m68ki_exception_illegal();\r
10510}\r
10511\r
10512\r
10513M68KMAKE_OP(tst, 32, ., i)\r
10514{\r
10515 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10516 {\r
10517 uint res = OPER_I_32();\r
10518\r
10519 FLAG_N = NFLAG_32(res);\r
10520 FLAG_Z = res;\r
10521 FLAG_V = VFLAG_CLEAR;\r
10522 FLAG_C = CFLAG_CLEAR;\r
10523 return;\r
10524 }\r
10525 m68ki_exception_illegal();\r
10526}\r
10527\r
10528\r
10529M68KMAKE_OP(unlk, 32, ., a7)\r
10530{\r
10531 REG_A[7] = m68ki_read_32(REG_A[7]);\r
10532}\r
10533\r
10534\r
10535M68KMAKE_OP(unlk, 32, ., .)\r
10536{\r
10537 uint* r_dst = &AY;\r
10538\r
10539 REG_A[7] = *r_dst;\r
10540 *r_dst = m68ki_pull_32();\r
10541}\r
10542\r
10543\r
10544M68KMAKE_OP(unpk, 16, rr, .)\r
10545{\r
10546 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10547 {\r
10548 /* Note: DX and DY are reversed in Motorola's docs */\r
10549 uint src = DY;\r
10550 uint* r_dst = &DX;\r
10551\r
10552 *r_dst = MASK_OUT_BELOW_16(*r_dst) | (((((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16()) & 0xffff);\r
10553 return;\r
10554 }\r
10555 m68ki_exception_illegal();\r
10556}\r
10557\r
10558\r
10559M68KMAKE_OP(unpk, 16, mm, ax7)\r
10560{\r
10561 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10562 {\r
10563 /* Note: AX and AY are reversed in Motorola's docs */\r
10564 uint src = OPER_AY_PD_8();\r
10565 uint ea_dst;\r
10566\r
10567 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();\r
10568 ea_dst = EA_A7_PD_8();\r
10569 m68ki_write_8(ea_dst, (src >> 8) & 0xff);\r
10570 ea_dst = EA_A7_PD_8();\r
10571 m68ki_write_8(ea_dst, src & 0xff);\r
10572 return;\r
10573 }\r
10574 m68ki_exception_illegal();\r
10575}\r
10576\r
10577\r
10578M68KMAKE_OP(unpk, 16, mm, ay7)\r
10579{\r
10580 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10581 {\r
10582 /* Note: AX and AY are reversed in Motorola's docs */\r
10583 uint src = OPER_A7_PD_8();\r
10584 uint ea_dst;\r
10585\r
10586 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();\r
10587 ea_dst = EA_AX_PD_8();\r
10588 m68ki_write_8(ea_dst, (src >> 8) & 0xff);\r
10589 ea_dst = EA_AX_PD_8();\r
10590 m68ki_write_8(ea_dst, src & 0xff);\r
10591 return;\r
10592 }\r
10593 m68ki_exception_illegal();\r
10594}\r
10595\r
10596\r
10597M68KMAKE_OP(unpk, 16, mm, axy7)\r
10598{\r
10599 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10600 {\r
10601 uint src = OPER_A7_PD_8();\r
10602 uint ea_dst;\r
10603\r
10604 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();\r
10605 ea_dst = EA_A7_PD_8();\r
10606 m68ki_write_8(ea_dst, (src >> 8) & 0xff);\r
10607 ea_dst = EA_A7_PD_8();\r
10608 m68ki_write_8(ea_dst, src & 0xff);\r
10609 return;\r
10610 }\r
10611 m68ki_exception_illegal();\r
10612}\r
10613\r
10614\r
10615M68KMAKE_OP(unpk, 16, mm, .)\r
10616{\r
10617 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10618 {\r
10619 /* Note: AX and AY are reversed in Motorola's docs */\r
10620 uint src = OPER_AY_PD_8();\r
10621 uint ea_dst;\r
10622\r
10623 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();\r
10624 ea_dst = EA_AX_PD_8();\r
10625 m68ki_write_8(ea_dst, (src >> 8) & 0xff);\r
10626 ea_dst = EA_AX_PD_8();\r
10627 m68ki_write_8(ea_dst, src & 0xff);\r
10628 return;\r
10629 }\r
10630 m68ki_exception_illegal();\r
10631}\r
10632\r
10633\r
10634\r
10635XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\r
10636M68KMAKE_END\r
fast MegaDrive/MegaCD/32X emulator