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0.0088 release
[picodrive.git] / cpu / musashi / m68k_in.c
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cc68a136 1/*\r
2must fix:\r
3 callm\r
4 chk\r
5*/\r
6/* ======================================================================== */\r
7/* ========================= LICENSING & COPYRIGHT ======================== */\r
8/* ======================================================================== */\r
9/*\r
10 * MUSASHI\r
c6a4c892 11 * Version 3.31\r
cc68a136 12 *\r
13 * A portable Motorola M680x0 processor emulation engine.\r
c6a4c892 14 * Copyright 1998-2007 Karl Stenerud. All rights reserved.\r
cc68a136 15 *\r
16 * This code may be freely used for non-commercial purposes as long as this\r
17 * copyright notice remains unaltered in the source code and any binary files\r
18 * containing this code in compiled form.\r
19 *\r
20 * All other lisencing terms must be negotiated with the author\r
21 * (Karl Stenerud).\r
22 *\r
23 * The latest version of this code can be obtained at:\r
24 * http://kstenerud.cjb.net\r
25 */\r
26\r
27/* Special thanks to Bart Trzynadlowski for his insight into the\r
28 * undocumented features of this chip:\r
29 *\r
30 * http://dynarec.com/~bart/files/68knotes.txt\r
31 */\r
32\r
33\r
34/* Input file for m68kmake\r
35 * -----------------------\r
36 *\r
37 * All sections begin with 80 X's in a row followed by an end-of-line\r
38 * sequence.\r
39 * After this, m68kmake will expect to find one of the following section\r
40 * identifiers:\r
41 * M68KMAKE_PROTOTYPE_HEADER - header for opcode handler prototypes\r
42 * M68KMAKE_PROTOTYPE_FOOTER - footer for opcode handler prototypes\r
43 * M68KMAKE_TABLE_HEADER - header for opcode handler jumptable\r
44 * M68KMAKE_TABLE_FOOTER - footer for opcode handler jumptable\r
45 * M68KMAKE_TABLE_BODY - the table itself\r
46 * M68KMAKE_OPCODE_HANDLER_HEADER - header for opcode handler implementation\r
47 * M68KMAKE_OPCODE_HANDLER_FOOTER - footer for opcode handler implementation\r
48 * M68KMAKE_OPCODE_HANDLER_BODY - body section for opcode handler implementation\r
49 *\r
50 * NOTE: M68KMAKE_OPCODE_HANDLER_BODY must be last in the file and\r
51 * M68KMAKE_TABLE_BODY must be second last in the file.\r
52 *\r
53 * The M68KMAKE_OPHANDLER_BODY section contains the opcode handler\r
54 * primitives themselves. Each opcode handler begins with:\r
55 * M68KMAKE_OP(A, B, C, D)\r
56 *\r
57 * where A is the opcode handler name, B is the size of the operation,\r
58 * C denotes any special processing mode, and D denotes a specific\r
59 * addressing mode.\r
60 * For C and D where nothing is specified, use "."\r
61 *\r
62 * Example:\r
63 * M68KMAKE_OP(abcd, 8, rr, .) abcd, size 8, register to register, default EA\r
64 * M68KMAKE_OP(abcd, 8, mm, ax7) abcd, size 8, memory to memory, register X is A7\r
65 * M68KMAKE_OP(tst, 16, ., pcix) tst, size 16, PCIX addressing\r
66 *\r
67 * All opcode handler primitives end with a closing curly brace "}" at column 1\r
68 *\r
69 * NOTE: Do not place a M68KMAKE_OP() directive inside the opcode handler,\r
70 * and do not put a closing curly brace at column 1 unless it is\r
71 * marking the end of the handler!\r
72 *\r
73 * Inside the handler, m68kmake will recognize M68KMAKE_GET_OPER_xx_xx,\r
74 * M68KMAKE_GET_EA_xx_xx, and M68KMAKE_CC directives, and create multiple\r
75 * opcode handlers to handle variations in the opcode handler.\r
76 * Note: M68KMAKE_CC will only be interpreted in condition code opcodes.\r
77 * As well, M68KMAKE_GET_EA_xx_xx and M68KMAKE_GET_OPER_xx_xx will only\r
78 * be interpreted on instructions where the corresponding table entry\r
79 * specifies multiple effective addressing modes.\r
80 * Example:\r
81 * clr 32 . . 0100001010...... A+-DXWL... U U U 12 6 4\r
82 *\r
83 * This table entry says that the clr.l opcde has 7 variations (A+-DXWL).\r
84 * It is run in user or supervisor mode for all CPUs, and uses 12 cycles for\r
85 * 68000, 6 cycles for 68010, and 4 cycles for 68020.\r
86 */\r
87\r
88XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\r
89M68KMAKE_PROTOTYPE_HEADER\r
90\r
91#ifndef M68KOPS__HEADER\r
92#define M68KOPS__HEADER\r
93\r
94/* ======================================================================== */\r
95/* ============================ OPCODE HANDLERS =========================== */\r
96/* ======================================================================== */\r
97\r
98\r
99\r
100XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\r
101M68KMAKE_PROTOTYPE_FOOTER\r
102\r
103\r
104/* Build the opcode handler table */\r
105void m68ki_build_opcode_table(void);\r
106\r
107extern void (*m68ki_instruction_jump_table[0x10000])(void); /* opcode handler jump table */\r
108extern unsigned char m68ki_cycles[][0x10000];\r
109\r
110\r
111/* ======================================================================== */\r
112/* ============================== END OF FILE ============================= */\r
113/* ======================================================================== */\r
114\r
115#endif /* M68KOPS__HEADER */\r
116\r
117\r
118\r
119XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\r
120M68KMAKE_TABLE_HEADER\r
121\r
122/* ======================================================================== */\r
123/* ========================= OPCODE TABLE BUILDER ========================= */\r
124/* ======================================================================== */\r
125\r
126#include "m68kops.h"\r
127\r
128#define NUM_CPU_TYPES 4\r
129\r
130void (*m68ki_instruction_jump_table[0x10000])(void); /* opcode handler jump table */\r
131unsigned char m68ki_cycles[NUM_CPU_TYPES][0x10000]; /* Cycles used by CPU type */\r
132\r
133/* This is used to generate the opcode handler jump table */\r
134typedef struct\r
135{\r
136 void (*opcode_handler)(void); /* handler function */\r
137 unsigned int mask; /* mask on opcode */\r
138 unsigned int match; /* what to match after masking */\r
139 unsigned char cycles[NUM_CPU_TYPES]; /* cycles each cpu type takes */\r
140} opcode_handler_struct;\r
141\r
142\r
143/* Opcode handler table */\r
144static opcode_handler_struct m68k_opcode_handler_table[] =\r
145{\r
146/* function mask match 000 010 020 040 */\r
147\r
148\r
149\r
150XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\r
151M68KMAKE_TABLE_FOOTER\r
152\r
153 {0, 0, 0, {0, 0, 0, 0}}\r
154};\r
155\r
156\r
157/* Build the opcode handler jump table */\r
158void m68ki_build_opcode_table(void)\r
159{\r
160 opcode_handler_struct *ostruct;\r
161 int instr;\r
162 int i;\r
163 int j;\r
164 int k;\r
165\r
166 for(i = 0; i < 0x10000; i++)\r
167 {\r
168 /* default to illegal */\r
169 m68ki_instruction_jump_table[i] = m68k_op_illegal;\r
170 for(k=0;k<NUM_CPU_TYPES;k++)\r
171 m68ki_cycles[k][i] = 0;\r
172 }\r
173\r
174 ostruct = m68k_opcode_handler_table;\r
175 while(ostruct->mask != 0xff00)\r
176 {\r
177 for(i = 0;i < 0x10000;i++)\r
178 {\r
179 if((i & ostruct->mask) == ostruct->match)\r
180 {\r
181 m68ki_instruction_jump_table[i] = ostruct->opcode_handler;\r
182 for(k=0;k<NUM_CPU_TYPES;k++)\r
183 m68ki_cycles[k][i] = ostruct->cycles[k];\r
184 }\r
185 }\r
186 ostruct++;\r
187 }\r
188 while(ostruct->mask == 0xff00)\r
189 {\r
190 for(i = 0;i <= 0xff;i++)\r
191 {\r
192 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;\r
193 for(k=0;k<NUM_CPU_TYPES;k++)\r
194 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];\r
195 }\r
196 ostruct++;\r
197 }\r
198 while(ostruct->mask == 0xf1f8)\r
199 {\r
200 for(i = 0;i < 8;i++)\r
201 {\r
202 for(j = 0;j < 8;j++)\r
203 {\r
204 instr = ostruct->match | (i << 9) | j;\r
205 m68ki_instruction_jump_table[instr] = ostruct->opcode_handler;\r
206 for(k=0;k<NUM_CPU_TYPES;k++)\r
207 m68ki_cycles[k][instr] = ostruct->cycles[k];\r
208 }\r
209 }\r
210 ostruct++;\r
211 }\r
212 while(ostruct->mask == 0xfff0)\r
213 {\r
214 for(i = 0;i <= 0x0f;i++)\r
215 {\r
216 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;\r
217 for(k=0;k<NUM_CPU_TYPES;k++)\r
218 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];\r
219 }\r
220 ostruct++;\r
221 }\r
222 while(ostruct->mask == 0xf1ff)\r
223 {\r
224 for(i = 0;i <= 0x07;i++)\r
225 {\r
226 m68ki_instruction_jump_table[ostruct->match | (i << 9)] = ostruct->opcode_handler;\r
227 for(k=0;k<NUM_CPU_TYPES;k++)\r
228 m68ki_cycles[k][ostruct->match | (i << 9)] = ostruct->cycles[k];\r
229 }\r
230 ostruct++;\r
231 }\r
232 while(ostruct->mask == 0xfff8)\r
233 {\r
234 for(i = 0;i <= 0x07;i++)\r
235 {\r
236 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;\r
237 for(k=0;k<NUM_CPU_TYPES;k++)\r
238 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];\r
239 }\r
240 ostruct++;\r
241 }\r
242 while(ostruct->mask == 0xffff)\r
243 {\r
244 m68ki_instruction_jump_table[ostruct->match] = ostruct->opcode_handler;\r
245 for(k=0;k<NUM_CPU_TYPES;k++)\r
246 m68ki_cycles[k][ostruct->match] = ostruct->cycles[k];\r
247 ostruct++;\r
248 }\r
249}\r
250\r
251\r
252/* ======================================================================== */\r
253/* ============================== END OF FILE ============================= */\r
254/* ======================================================================== */\r
255\r
256\r
257\r
258XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\r
259M68KMAKE_OPCODE_HANDLER_HEADER\r
260\r
261#include "m68kcpu.h"\r
c6a4c892 262extern void m68040_fpu_op0(void);\r
263extern void m68040_fpu_op1(void);\r
cc68a136 264\r
265/* ======================================================================== */\r
266/* ========================= INSTRUCTION HANDLERS ========================= */\r
267/* ======================================================================== */\r
268\r
269\r
270\r
271XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\r
272M68KMAKE_OPCODE_HANDLER_FOOTER\r
273\r
274/* ======================================================================== */\r
275/* ============================== END OF FILE ============================= */\r
276/* ======================================================================== */\r
277\r
278\r
279\r
280XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\r
281M68KMAKE_TABLE_BODY\r
282\r
283The following table is arranged as follows:\r
284\r
285name: Opcode mnemonic\r
286\r
287size: Operation size\r
288\r
289spec proc: Special processing mode:\r
290 .: normal\r
291 s: static operand\r
292 r: register operand\r
293 rr: register to register\r
294 mm: memory to memory\r
295 er: effective address to register\r
296 re: register to effective address\r
297 dd: data register to data register\r
298 da: data register to address register\r
299 aa: address register to address register\r
300 cr: control register to register\r
301 rc: register to control register\r
302 toc: to condition code register\r
303 tos: to status register\r
304 tou: to user stack pointer\r
305 frc: from condition code register\r
306 frs: from status register\r
307 fru: from user stack pointer\r
308 * for move.x, the special processing mode is a specific\r
309 destination effective addressing mode.\r
310\r
311spec ea: Specific effective addressing mode:\r
312 .: normal\r
313 i: immediate\r
314 d: data register\r
315 a: address register\r
316 ai: address register indirect\r
317 pi: address register indirect with postincrement\r
318 pd: address register indirect with predecrement\r
319 di: address register indirect with displacement\r
320 ix: address register indirect with index\r
321 aw: absolute word address\r
322 al: absolute long address\r
323 pcdi: program counter relative with displacement\r
324 pcix: program counter relative with index\r
325 a7: register specified in instruction is A7\r
326 ax7: register field X of instruction is A7\r
327 ay7: register field Y of instruction is A7\r
328 axy7: register fields X and Y of instruction are A7\r
329\r
330bit pattern: Pattern to recognize this opcode. "." means don't care.\r
331\r
332allowed ea: List of allowed addressing modes:\r
333 .: not present\r
334 A: address register indirect\r
335 +: ARI (address register indirect) with postincrement\r
336 -: ARI with predecrement\r
337 D: ARI with displacement\r
338 X: ARI with index\r
339 W: absolute word address\r
340 L: absolute long address\r
341 d: program counter indirect with displacement\r
342 x: program counter indirect with index\r
343 I: immediate\r
344mode: CPU operating mode for each cpu type. U = user or supervisor,\r
345 S = supervisor only, "." = opcode not present.\r
346\r
347cpu cycles: Base number of cycles required to execute this opcode on the\r
348 specified CPU type.\r
349 Use "." if CPU does not have this opcode.\r
350\r
351\r
352\r
353 spec spec allowed ea mode cpu cycles\r
354name size proc ea bit pattern A+-DXWLdxI 0 1 2 4 000 010 020 040 comments\r
355====== ==== ==== ==== ================ ========== = = = = === === === === =============\r
356M68KMAKE_TABLE_START\r
3571010 0 . . 1010............ .......... U U U U 4 4 4 4\r
3581111 0 . . 1111............ .......... U U U U 4 4 4 4\r
c6a4c892 359040fpu0 32 . . 11110010........ .......... . . . U . . . 0\r
360040fpu1 32 . . 11110011........ .......... . . . U . . . 0\r
cc68a136 361abcd 8 rr . 1100...100000... .......... U U U U 6 6 4 4\r
362abcd 8 mm ax7 1100111100001... .......... U U U U 18 18 16 16\r
363abcd 8 mm ay7 1100...100001111 .......... U U U U 18 18 16 16\r
364abcd 8 mm axy7 1100111100001111 .......... U U U U 18 18 16 16\r
365abcd 8 mm . 1100...100001... .......... U U U U 18 18 16 16\r
366add 8 er d 1101...000000... .......... U U U U 4 4 2 2\r
367add 8 er . 1101...000...... A+-DXWLdxI U U U U 4 4 2 2\r
368add 16 er d 1101...001000... .......... U U U U 4 4 2 2\r
369add 16 er a 1101...001001... .......... U U U U 4 4 2 2\r
370add 16 er . 1101...001...... A+-DXWLdxI U U U U 4 4 2 2\r
371add 32 er d 1101...010000... .......... U U U U 6 6 2 2\r
372add 32 er a 1101...010001... .......... U U U U 6 6 2 2\r
373add 32 er . 1101...010...... A+-DXWLdxI U U U U 6 6 2 2\r
374add 8 re . 1101...100...... A+-DXWL... U U U U 8 8 4 4\r
375add 16 re . 1101...101...... A+-DXWL... U U U U 8 8 4 4\r
376add 32 re . 1101...110...... A+-DXWL... U U U U 12 12 4 4\r
377adda 16 . d 1101...011000... .......... U U U U 8 8 2 2\r
378adda 16 . a 1101...011001... .......... U U U U 8 8 2 2\r
379adda 16 . . 1101...011...... A+-DXWLdxI U U U U 8 8 2 2\r
380adda 32 . d 1101...111000... .......... U U U U 6 6 2 2\r
381adda 32 . a 1101...111001... .......... U U U U 6 6 2 2\r
382adda 32 . . 1101...111...... A+-DXWLdxI U U U U 6 6 2 2\r
383addi 8 . d 0000011000000... .......... U U U U 8 8 2 2\r
384addi 8 . . 0000011000...... A+-DXWL... U U U U 12 12 4 4\r
385addi 16 . d 0000011001000... .......... U U U U 8 8 2 2\r
386addi 16 . . 0000011001...... A+-DXWL... U U U U 12 12 4 4\r
387addi 32 . d 0000011010000... .......... U U U U 16 14 2 2\r
388addi 32 . . 0000011010...... A+-DXWL... U U U U 20 20 4 4\r
389addq 8 . d 0101...000000... .......... U U U U 4 4 2 2\r
390addq 8 . . 0101...000...... A+-DXWL... U U U U 8 8 4 4\r
391addq 16 . d 0101...001000... .......... U U U U 4 4 2 2\r
392addq 16 . a 0101...001001... .......... U U U U 4 4 2 2\r
393addq 16 . . 0101...001...... A+-DXWL... U U U U 8 8 4 4\r
394addq 32 . d 0101...010000... .......... U U U U 8 8 2 2\r
395addq 32 . a 0101...010001... .......... U U U U 8 8 2 2\r
396addq 32 . . 0101...010...... A+-DXWL... U U U U 12 12 4 4\r
397addx 8 rr . 1101...100000... .......... U U U U 4 4 2 2\r
398addx 16 rr . 1101...101000... .......... U U U U 4 4 2 2\r
399addx 32 rr . 1101...110000... .......... U U U U 8 6 2 2\r
400addx 8 mm ax7 1101111100001... .......... U U U U 18 18 12 12\r
401addx 8 mm ay7 1101...100001111 .......... U U U U 18 18 12 12\r
402addx 8 mm axy7 1101111100001111 .......... U U U U 18 18 12 12\r
403addx 8 mm . 1101...100001... .......... U U U U 18 18 12 12\r
404addx 16 mm . 1101...101001... .......... U U U U 18 18 12 12\r
405addx 32 mm . 1101...110001... .......... U U U U 30 30 12 12\r
406and 8 er d 1100...000000... .......... U U U U 4 4 2 2\r
407and 8 er . 1100...000...... A+-DXWLdxI U U U U 4 4 2 2\r
408and 16 er d 1100...001000... .......... U U U U 4 4 2 2\r
409and 16 er . 1100...001...... A+-DXWLdxI U U U U 4 4 2 2\r
410and 32 er d 1100...010000... .......... U U U U 6 6 2 2\r
411and 32 er . 1100...010...... A+-DXWLdxI U U U U 6 6 2 2\r
412and 8 re . 1100...100...... A+-DXWL... U U U U 8 8 4 4\r
413and 16 re . 1100...101...... A+-DXWL... U U U U 8 8 4 4\r
414and 32 re . 1100...110...... A+-DXWL... U U U U 12 12 4 4\r
415andi 16 toc . 0000001000111100 .......... U U U U 20 16 12 12\r
416andi 16 tos . 0000001001111100 .......... S S S S 20 16 12 12\r
417andi 8 . d 0000001000000... .......... U U U U 8 8 2 2\r
418andi 8 . . 0000001000...... A+-DXWL... U U U U 12 12 4 4\r
419andi 16 . d 0000001001000... .......... U U U U 8 8 2 2\r
420andi 16 . . 0000001001...... A+-DXWL... U U U U 12 12 4 4\r
421andi 32 . d 0000001010000... .......... U U U U 14 14 2 2\r
422andi 32 . . 0000001010...... A+-DXWL... U U U U 20 20 4 4\r
423asr 8 s . 1110...000000... .......... U U U U 6 6 6 6\r
424asr 16 s . 1110...001000... .......... U U U U 6 6 6 6\r
425asr 32 s . 1110...010000... .......... U U U U 8 8 6 6\r
426asr 8 r . 1110...000100... .......... U U U U 6 6 6 6\r
427asr 16 r . 1110...001100... .......... U U U U 6 6 6 6\r
428asr 32 r . 1110...010100... .......... U U U U 8 8 6 6\r
429asr 16 . . 1110000011...... A+-DXWL... U U U U 8 8 5 5\r
430asl 8 s . 1110...100000... .......... U U U U 6 6 8 8\r
431asl 16 s . 1110...101000... .......... U U U U 6 6 8 8\r
432asl 32 s . 1110...110000... .......... U U U U 8 8 8 8\r
433asl 8 r . 1110...100100... .......... U U U U 6 6 8 8\r
434asl 16 r . 1110...101100... .......... U U U U 6 6 8 8\r
435asl 32 r . 1110...110100... .......... U U U U 8 8 8 8\r
436asl 16 . . 1110000111...... A+-DXWL... U U U U 8 8 6 6\r
437bcc 8 . . 0110............ .......... U U U U 10 10 6 6\r
438bcc 16 . . 0110....00000000 .......... U U U U 10 10 6 6\r
439bcc 32 . . 0110....11111111 .......... U U U U 10 10 6 6\r
440bchg 8 r . 0000...101...... A+-DXWL... U U U U 8 8 4 4\r
441bchg 32 r d 0000...101000... .......... U U U U 8 8 4 4\r
442bchg 8 s . 0000100001...... A+-DXWL... U U U U 12 12 4 4\r
443bchg 32 s d 0000100001000... .......... U U U U 12 12 4 4\r
444bclr 8 r . 0000...110...... A+-DXWL... U U U U 8 10 4 4\r
445bclr 32 r d 0000...110000... .......... U U U U 10 10 4 4\r
446bclr 8 s . 0000100010...... A+-DXWL... U U U U 12 12 4 4\r
447bclr 32 s d 0000100010000... .......... U U U U 14 14 4 4\r
448bfchg 32 . d 1110101011000... .......... . . U U . . 12 12 timing not quite correct\r
449bfchg 32 . . 1110101011...... A..DXWL... . . U U . . 20 20\r
450bfclr 32 . d 1110110011000... .......... . . U U . . 12 12\r
451bfclr 32 . . 1110110011...... A..DXWL... . . U U . . 20 20\r
452bfexts 32 . d 1110101111000... .......... . . U U . . 8 8\r
453bfexts 32 . . 1110101111...... A..DXWLdx. . . U U . . 15 15\r
454bfextu 32 . d 1110100111000... .......... . . U U . . 8 8\r
455bfextu 32 . . 1110100111...... A..DXWLdx. . . U U . . 15 15\r
456bfffo 32 . d 1110110111000... .......... . . U U . . 18 18\r
457bfffo 32 . . 1110110111...... A..DXWLdx. . . U U . . 28 28\r
458bfins 32 . d 1110111111000... .......... . . U U . . 10 10\r
459bfins 32 . . 1110111111...... A..DXWL... . . U U . . 17 17\r
460bfset 32 . d 1110111011000... .......... . . U U . . 12 12\r
461bfset 32 . . 1110111011...... A..DXWL... . . U U . . 20 20\r
462bftst 32 . d 1110100011000... .......... . . U U . . 6 6\r
463bftst 32 . . 1110100011...... A..DXWLdx. . . U U . . 13 13\r
464bkpt 0 . . 0100100001001... .......... . U U U . 10 10 10\r
465bra 8 . . 01100000........ .......... U U U U 10 10 10 10\r
466bra 16 . . 0110000000000000 .......... U U U U 10 10 10 10\r
467bra 32 . . 0110000011111111 .......... U U U U 10 10 10 10\r
468bset 32 r d 0000...111000... .......... U U U U 8 8 4 4\r
469bset 8 r . 0000...111...... A+-DXWL... U U U U 8 8 4 4\r
470bset 8 s . 0000100011...... A+-DXWL... U U U U 12 12 4 4\r
471bset 32 s d 0000100011000... .......... U U U U 12 12 4 4\r
472bsr 8 . . 01100001........ .......... U U U U 18 18 7 7\r
473bsr 16 . . 0110000100000000 .......... U U U U 18 18 7 7\r
474bsr 32 . . 0110000111111111 .......... U U U U 18 18 7 7\r
475btst 8 r . 0000...100...... A+-DXWLdxI U U U U 4 4 4 4\r
476btst 32 r d 0000...100000... .......... U U U U 6 6 4 4\r
477btst 8 s . 0000100000...... A+-DXWLdx. U U U U 8 8 4 4\r
478btst 32 s d 0000100000000... .......... U U U U 10 10 4 4\r
479callm 32 . . 0000011011...... A..DXWLdx. . . U U . . 60 60 not properly emulated\r
480cas 8 . . 0000101011...... A+-DXWL... . . U U . . 12 12\r
481cas 16 . . 0000110011...... A+-DXWL... . . U U . . 12 12\r
482cas 32 . . 0000111011...... A+-DXWL... . . U U . . 12 12\r
483cas2 16 . . 0000110011111100 .......... . . U U . . 12 12\r
484cas2 32 . . 0000111011111100 .......... . . U U . . 12 12\r
485chk 16 . d 0100...110000... .......... U U U U 10 8 8 8\r
486chk 16 . . 0100...110...... A+-DXWLdxI U U U U 10 8 8 8\r
487chk 32 . d 0100...100000... .......... . . U U . . 8 8\r
488chk 32 . . 0100...100...... A+-DXWLdxI . . U U . . 8 8\r
489chk2cmp2 8 . pcdi 0000000011111010 .......... . . U U . . 23 23\r
490chk2cmp2 8 . pcix 0000000011111011 .......... . . U U . . 23 23\r
491chk2cmp2 8 . . 0000000011...... A..DXWL... . . U U . . 18 18\r
492chk2cmp2 16 . pcdi 0000001011111010 .......... . . U U . . 23 23\r
493chk2cmp2 16 . pcix 0000001011111011 .......... . . U U . . 23 23\r
494chk2cmp2 16 . . 0000001011...... A..DXWL... . . U U . . 18 18\r
495chk2cmp2 32 . pcdi 0000010011111010 .......... . . U U . . 23 23\r
496chk2cmp2 32 . pcix 0000010011111011 .......... . . U U . . 23 23\r
497chk2cmp2 32 . . 0000010011...... A..DXWL... . . U U . . 18 18\r
498clr 8 . d 0100001000000... .......... U U U U 4 4 2 2\r
499clr 8 . . 0100001000...... A+-DXWL... U U U U 6 4 4 4 notaz hack: changed 000 cycles 8 -> 6 like in starscream for Fatal Rewind\r
500clr 16 . d 0100001001000... .......... U U U U 4 4 2 2\r
c6a4c892 501clr 16 . . 0100001001...... A+-DXWL... U U U U 6 4 4 4 notaz hack: ditto\r
cc68a136 502clr 32 . d 0100001010000... .......... U U U U 6 6 2 2\r
503clr 32 . . 0100001010...... A+-DXWL... U U U U 12 6 4 4\r
504cmp 8 . d 1011...000000... .......... U U U U 4 4 2 2\r
505cmp 8 . . 1011...000...... A+-DXWLdxI U U U U 4 4 2 2\r
506cmp 16 . d 1011...001000... .......... U U U U 4 4 2 2\r
507cmp 16 . a 1011...001001... .......... U U U U 4 4 2 2\r
508cmp 16 . . 1011...001...... A+-DXWLdxI U U U U 4 4 2 2\r
509cmp 32 . d 1011...010000... .......... U U U U 6 6 2 2\r
510cmp 32 . a 1011...010001... .......... U U U U 6 6 2 2\r
511cmp 32 . . 1011...010...... A+-DXWLdxI U U U U 6 6 2 2\r
512cmpa 16 . d 1011...011000... .......... U U U U 6 6 4 4\r
513cmpa 16 . a 1011...011001... .......... U U U U 6 6 4 4\r
514cmpa 16 . . 1011...011...... A+-DXWLdxI U U U U 6 6 4 4\r
515cmpa 32 . d 1011...111000... .......... U U U U 6 6 4 4\r
516cmpa 32 . a 1011...111001... .......... U U U U 6 6 4 4\r
517cmpa 32 . . 1011...111...... A+-DXWLdxI U U U U 6 6 4 4\r
518cmpi 8 . d 0000110000000... .......... U U U U 8 8 2 2\r
519cmpi 8 . . 0000110000...... A+-DXWL... U U U U 8 8 2 2\r
520cmpi 8 . pcdi 0000110000111010 .......... . . U U . . 7 7\r
521cmpi 8 . pcix 0000110000111011 .......... . . U U . . 9 9\r
522cmpi 16 . d 0000110001000... .......... U U U U 8 8 2 2\r
523cmpi 16 . . 0000110001...... A+-DXWL... U U U U 8 8 2 2\r
524cmpi 16 . pcdi 0000110001111010 .......... . . U U . . 7 7\r
525cmpi 16 . pcix 0000110001111011 .......... . . U U . . 9 9\r
526cmpi 32 . d 0000110010000... .......... U U U U 14 12 2 2\r
527cmpi 32 . . 0000110010...... A+-DXWL... U U U U 12 12 2 2\r
528cmpi 32 . pcdi 0000110010111010 .......... . . U U . . 7 7\r
529cmpi 32 . pcix 0000110010111011 .......... . . U U . . 9 9\r
530cmpm 8 . ax7 1011111100001... .......... U U U U 12 12 9 9\r
531cmpm 8 . ay7 1011...100001111 .......... U U U U 12 12 9 9\r
532cmpm 8 . axy7 1011111100001111 .......... U U U U 12 12 9 9\r
533cmpm 8 . . 1011...100001... .......... U U U U 12 12 9 9\r
534cmpm 16 . . 1011...101001... .......... U U U U 12 12 9 9\r
535cmpm 32 . . 1011...110001... .......... U U U U 20 20 9 9\r
536cpbcc 32 . . 1111...01....... .......... . . U . . . 4 . unemulated\r
537cpdbcc 32 . . 1111...001001... .......... . . U . . . 4 . unemulated\r
538cpgen 32 . . 1111...000...... .......... . . U . . . 4 . unemulated\r
539cpscc 32 . . 1111...001...... .......... . . U . . . 4 . unemulated\r
540cptrapcc 32 . . 1111...001111... .......... . . U . . . 4 . unemulated\r
541dbt 16 . . 0101000011001... .......... U U U U 12 12 6 6\r
542dbf 16 . . 0101000111001... .......... U U U U 12 12 6 6\r
543dbcc 16 . . 0101....11001... .......... U U U U 12 12 6 6\r
544divs 16 . d 1000...111000... .......... U U U U 158 122 56 56\r
545divs 16 . . 1000...111...... A+-DXWLdxI U U U U 158 122 56 56\r
546divu 16 . d 1000...011000... .......... U U U U 140 108 44 44\r
547divu 16 . . 1000...011...... A+-DXWLdxI U U U U 140 108 44 44\r
548divl 32 . d 0100110001000... .......... . . U U . . 84 84\r
549divl 32 . . 0100110001...... A+-DXWLdxI . . U U . . 84 84\r
550eor 8 . d 1011...100000... .......... U U U U 4 4 2 2\r
551eor 8 . . 1011...100...... A+-DXWL... U U U U 8 8 4 4\r
552eor 16 . d 1011...101000... .......... U U U U 4 4 2 2\r
553eor 16 . . 1011...101...... A+-DXWL... U U U U 8 8 4 4\r
554eor 32 . d 1011...110000... .......... U U U U 8 6 2 2\r
555eor 32 . . 1011...110...... A+-DXWL... U U U U 12 12 4 4\r
556eori 16 toc . 0000101000111100 .......... U U U U 20 16 12 12\r
557eori 16 tos . 0000101001111100 .......... S S S S 20 16 12 12\r
558eori 8 . d 0000101000000... .......... U U U U 8 8 2 2\r
559eori 8 . . 0000101000...... A+-DXWL... U U U U 12 12 4 4\r
560eori 16 . d 0000101001000... .......... U U U U 8 8 2 2\r
561eori 16 . . 0000101001...... A+-DXWL... U U U U 12 12 4 4\r
562eori 32 . d 0000101010000... .......... U U U U 16 14 2 2\r
563eori 32 . . 0000101010...... A+-DXWL... U U U U 20 20 4 4\r
564exg 32 dd . 1100...101000... .......... U U U U 6 6 2 2\r
565exg 32 aa . 1100...101001... .......... U U U U 6 6 2 2\r
566exg 32 da . 1100...110001... .......... U U U U 6 6 2 2\r
567ext 16 . . 0100100010000... .......... U U U U 4 4 4 4\r
568ext 32 . . 0100100011000... .......... U U U U 4 4 4 4\r
569extb 32 . . 0100100111000... .......... . . U U . . 4 4\r
570illegal 0 . . 0100101011111100 .......... U U U U 4 4 4 4\r
571jmp 32 . . 0100111011...... A..DXWLdx. U U U U 4 4 0 0\r
572jsr 32 . . 0100111010...... A..DXWLdx. U U U U 12 12 0 0\r
573lea 32 . . 0100...111...... A..DXWLdx. U U U U 0 0 2 2\r
574link 16 . a7 0100111001010111 .......... U U U U 16 16 5 5\r
575link 16 . . 0100111001010... .......... U U U U 16 16 5 5\r
576link 32 . a7 0100100000001111 .......... . . U U . . 6 6\r
577link 32 . . 0100100000001... .......... . . U U . . 6 6\r
578lsr 8 s . 1110...000001... .......... U U U U 6 6 4 4\r
579lsr 16 s . 1110...001001... .......... U U U U 6 6 4 4\r
580lsr 32 s . 1110...010001... .......... U U U U 8 8 4 4\r
581lsr 8 r . 1110...000101... .......... U U U U 6 6 6 6\r
582lsr 16 r . 1110...001101... .......... U U U U 6 6 6 6\r
583lsr 32 r . 1110...010101... .......... U U U U 8 8 6 6\r
584lsr 16 . . 1110001011...... A+-DXWL... U U U U 8 8 5 5\r
585lsl 8 s . 1110...100001... .......... U U U U 6 6 4 4\r
586lsl 16 s . 1110...101001... .......... U U U U 6 6 4 4\r
587lsl 32 s . 1110...110001... .......... U U U U 8 8 4 4\r
588lsl 8 r . 1110...100101... .......... U U U U 6 6 6 6\r
589lsl 16 r . 1110...101101... .......... U U U U 6 6 6 6\r
590lsl 32 r . 1110...110101... .......... U U U U 8 8 6 6\r
591lsl 16 . . 1110001111...... A+-DXWL... U U U U 8 8 5 5\r
592move 8 d d 0001...000000... .......... U U U U 4 4 2 2\r
593move 8 d . 0001...000...... A+-DXWLdxI U U U U 4 4 2 2\r
594move 8 ai d 0001...010000... .......... U U U U 8 8 4 4\r
595move 8 ai . 0001...010...... A+-DXWLdxI U U U U 8 8 4 4\r
596move 8 pi d 0001...011000... .......... U U U U 8 8 4 4\r
597move 8 pi . 0001...011...... A+-DXWLdxI U U U U 8 8 4 4\r
598move 8 pi7 d 0001111011000... .......... U U U U 8 8 4 4\r
599move 8 pi7 . 0001111011...... A+-DXWLdxI U U U U 8 8 4 4\r
600move 8 pd d 0001...100000... .......... U U U U 8 8 5 5\r
601move 8 pd . 0001...100...... A+-DXWLdxI U U U U 8 8 5 5\r
602move 8 pd7 d 0001111100000... .......... U U U U 8 8 5 5\r
603move 8 pd7 . 0001111100...... A+-DXWLdxI U U U U 8 8 5 5\r
604move 8 di d 0001...101000... .......... U U U U 12 12 5 5\r
605move 8 di . 0001...101...... A+-DXWLdxI U U U U 12 12 5 5\r
606move 8 ix d 0001...110000... .......... U U U U 14 14 7 7\r
607move 8 ix . 0001...110...... A+-DXWLdxI U U U U 14 14 7 7\r
608move 8 aw d 0001000111000... .......... U U U U 12 12 4 4\r
609move 8 aw . 0001000111...... A+-DXWLdxI U U U U 12 12 4 4\r
610move 8 al d 0001001111000... .......... U U U U 16 16 6 6\r
611move 8 al . 0001001111...... A+-DXWLdxI U U U U 16 16 6 6\r
612move 16 d d 0011...000000... .......... U U U U 4 4 2 2\r
613move 16 d a 0011...000001... .......... U U U U 4 4 2 2\r
614move 16 d . 0011...000...... A+-DXWLdxI U U U U 4 4 2 2\r
615move 16 ai d 0011...010000... .......... U U U U 8 8 4 4\r
616move 16 ai a 0011...010001... .......... U U U U 8 8 4 4\r
617move 16 ai . 0011...010...... A+-DXWLdxI U U U U 8 8 4 4\r
618move 16 pi d 0011...011000... .......... U U U U 8 8 4 4\r
619move 16 pi a 0011...011001... .......... U U U U 8 8 4 4\r
620move 16 pi . 0011...011...... A+-DXWLdxI U U U U 8 8 4 4\r
621move 16 pd d 0011...100000... .......... U U U U 8 8 5 5\r
622move 16 pd a 0011...100001... .......... U U U U 8 8 5 5\r
623move 16 pd . 0011...100...... A+-DXWLdxI U U U U 8 8 5 5\r
624move 16 di d 0011...101000... .......... U U U U 12 12 5 5\r
625move 16 di a 0011...101001... .......... U U U U 12 12 5 5\r
626move 16 di . 0011...101...... A+-DXWLdxI U U U U 12 12 5 5\r
627move 16 ix d 0011...110000... .......... U U U U 14 14 7 7\r
628move 16 ix a 0011...110001... .......... U U U U 14 14 7 7\r
629move 16 ix . 0011...110...... A+-DXWLdxI U U U U 14 14 7 7\r
630move 16 aw d 0011000111000... .......... U U U U 12 12 4 4\r
631move 16 aw a 0011000111001... .......... U U U U 12 12 4 4\r
632move 16 aw . 0011000111...... A+-DXWLdxI U U U U 12 12 4 4\r
633move 16 al d 0011001111000... .......... U U U U 16 16 6 6\r
634move 16 al a 0011001111001... .......... U U U U 16 16 6 6\r
635move 16 al . 0011001111...... A+-DXWLdxI U U U U 16 16 6 6\r
636move 32 d d 0010...000000... .......... U U U U 4 4 2 2\r
637move 32 d a 0010...000001... .......... U U U U 4 4 2 2\r
638move 32 d . 0010...000...... A+-DXWLdxI U U U U 4 4 2 2\r
639move 32 ai d 0010...010000... .......... U U U U 12 12 4 4\r
640move 32 ai a 0010...010001... .......... U U U U 12 12 4 4\r
641move 32 ai . 0010...010...... A+-DXWLdxI U U U U 12 12 4 4\r
642move 32 pi d 0010...011000... .......... U U U U 12 12 4 4\r
643move 32 pi a 0010...011001... .......... U U U U 12 12 4 4\r
644move 32 pi . 0010...011...... A+-DXWLdxI U U U U 12 12 4 4\r
645move 32 pd d 0010...100000... .......... U U U U 12 14 5 5\r
646move 32 pd a 0010...100001... .......... U U U U 12 14 5 5\r
647move 32 pd . 0010...100...... A+-DXWLdxI U U U U 12 14 5 5\r
648move 32 di d 0010...101000... .......... U U U U 16 16 5 5\r
649move 32 di a 0010...101001... .......... U U U U 16 16 5 5\r
650move 32 di . 0010...101...... A+-DXWLdxI U U U U 16 16 5 5\r
651move 32 ix d 0010...110000... .......... U U U U 18 18 7 7\r
652move 32 ix a 0010...110001... .......... U U U U 18 18 7 7\r
653move 32 ix . 0010...110...... A+-DXWLdxI U U U U 18 18 7 7\r
654move 32 aw d 0010000111000... .......... U U U U 16 16 4 4\r
655move 32 aw a 0010000111001... .......... U U U U 16 16 4 4\r
656move 32 aw . 0010000111...... A+-DXWLdxI U U U U 16 16 4 4\r
657move 32 al d 0010001111000... .......... U U U U 20 20 6 6\r
658move 32 al a 0010001111001... .......... U U U U 20 20 6 6\r
659move 32 al . 0010001111...... A+-DXWLdxI U U U U 20 20 6 6\r
660movea 16 . d 0011...001000... .......... U U U U 4 4 2 2\r
661movea 16 . a 0011...001001... .......... U U U U 4 4 2 2\r
662movea 16 . . 0011...001...... A+-DXWLdxI U U U U 4 4 2 2\r
663movea 32 . d 0010...001000... .......... U U U U 4 4 2 2\r
664movea 32 . a 0010...001001... .......... U U U U 4 4 2 2\r
665movea 32 . . 0010...001...... A+-DXWLdxI U U U U 4 4 2 2\r
666move 16 frc d 0100001011000... .......... . U U U . 4 4 4\r
667move 16 frc . 0100001011...... A+-DXWL... . U U U . 8 4 4\r
668move 16 toc d 0100010011000... .......... U U U U 12 12 4 4\r
669move 16 toc . 0100010011...... A+-DXWLdxI U U U U 12 12 4 4\r
670move 16 frs d 0100000011000... .......... U S S S 6 4 8 8 U only for 000\r
671move 16 frs . 0100000011...... A+-DXWL... U S S S 8 8 8 8 U only for 000\r
672move 16 tos d 0100011011000... .......... S S S S 12 12 8 8\r
673move 16 tos . 0100011011...... A+-DXWLdxI S S S S 12 12 8 8\r
674move 32 fru . 0100111001101... .......... S S S S 4 6 2 2\r
675move 32 tou . 0100111001100... .......... S S S S 4 6 2 2\r
676movec 32 cr . 0100111001111010 .......... . S S S . 12 6 6\r
677movec 32 rc . 0100111001111011 .......... . S S S . 10 12 12\r
678movem 16 re pd 0100100010100... .......... U U U U 8 8 4 4\r
679movem 16 re . 0100100010...... A..DXWL... U U U U 8 8 4 4\r
680movem 32 re pd 0100100011100... .......... U U U U 8 8 4 4\r
681movem 32 re . 0100100011...... A..DXWL... U U U U 8 8 4 4\r
682movem 16 er pi 0100110010011... .......... U U U U 12 12 8 8\r
683movem 16 er pcdi 0100110010111010 .......... U U U U 16 16 9 9\r
684movem 16 er pcix 0100110010111011 .......... U U U U 18 18 11 11\r
685movem 16 er . 0100110010...... A..DXWL... U U U U 12 12 8 8\r
686movem 32 er pi 0100110011011... .......... U U U U 12 12 8 8\r
687movem 32 er pcdi 0100110011111010 .......... U U U U 16 16 9 9\r
688movem 32 er pcix 0100110011111011 .......... U U U U 18 18 11 11\r
689movem 32 er . 0100110011...... A..DXWL... U U U U 12 12 8 8\r
690movep 16 er . 0000...100001... .......... U U U U 16 16 12 12\r
691movep 32 er . 0000...101001... .......... U U U U 24 24 18 18\r
692movep 16 re . 0000...110001... .......... U U U U 16 16 11 11\r
693movep 32 re . 0000...111001... .......... U U U U 24 24 17 17\r
694moveq 32 . . 0111...0........ .......... U U U U 4 4 2 2\r
695moves 8 . . 0000111000...... A+-DXWL... . S S S . 14 5 5\r
696moves 16 . . 0000111001...... A+-DXWL... . S S S . 14 5 5\r
697moves 32 . . 0000111010...... A+-DXWL... . S S S . 16 5 5\r
698move16 32 . . 1111011000100... .......... . . . U . . . 4 TODO: correct timing\r
699muls 16 . d 1100...111000... .......... U U U U 54 32 27 27\r
700muls 16 . . 1100...111...... A+-DXWLdxI U U U U 54 32 27 27\r
701mulu 16 . d 1100...011000... .......... U U U U 54 30 27 27\r
702mulu 16 . . 1100...011...... A+-DXWLdxI U U U U 54 30 27 27\r
703mull 32 . d 0100110000000... .......... . . U U . . 43 43\r
704mull 32 . . 0100110000...... A+-DXWLdxI . . U U . . 43 43\r
705nbcd 8 . d 0100100000000... .......... U U U U 6 6 6 6\r
706nbcd 8 . . 0100100000...... A+-DXWL... U U U U 8 8 6 6\r
707neg 8 . d 0100010000000... .......... U U U U 4 4 2 2\r
708neg 8 . . 0100010000...... A+-DXWL... U U U U 8 8 4 4\r
709neg 16 . d 0100010001000... .......... U U U U 4 4 2 2\r
710neg 16 . . 0100010001...... A+-DXWL... U U U U 8 8 4 4\r
711neg 32 . d 0100010010000... .......... U U U U 6 6 2 2\r
712neg 32 . . 0100010010...... A+-DXWL... U U U U 12 12 4 4\r
713negx 8 . d 0100000000000... .......... U U U U 4 4 2 2\r
714negx 8 . . 0100000000...... A+-DXWL... U U U U 8 8 4 4\r
715negx 16 . d 0100000001000... .......... U U U U 4 4 2 2\r
716negx 16 . . 0100000001...... A+-DXWL... U U U U 8 8 4 4\r
717negx 32 . d 0100000010000... .......... U U U U 6 6 2 2\r
718negx 32 . . 0100000010...... A+-DXWL... U U U U 12 12 4 4\r
719nop 0 . . 0100111001110001 .......... U U U U 4 4 2 2\r
720not 8 . d 0100011000000... .......... U U U U 4 4 2 2\r
721not 8 . . 0100011000...... A+-DXWL... U U U U 8 8 4 4\r
722not 16 . d 0100011001000... .......... U U U U 4 4 2 2\r
723not 16 . . 0100011001...... A+-DXWL... U U U U 8 8 4 4\r
724not 32 . d 0100011010000... .......... U U U U 6 6 2 2\r
725not 32 . . 0100011010...... A+-DXWL... U U U U 12 12 4 4\r
726or 8 er d 1000...000000... .......... U U U U 4 4 2 2\r
727or 8 er . 1000...000...... A+-DXWLdxI U U U U 4 4 2 2\r
728or 16 er d 1000...001000... .......... U U U U 4 4 2 2\r
729or 16 er . 1000...001...... A+-DXWLdxI U U U U 4 4 2 2\r
730or 32 er d 1000...010000... .......... U U U U 6 6 2 2\r
731or 32 er . 1000...010...... A+-DXWLdxI U U U U 6 6 2 2\r
732or 8 re . 1000...100...... A+-DXWL... U U U U 8 8 4 4\r
733or 16 re . 1000...101...... A+-DXWL... U U U U 8 8 4 4\r
734or 32 re . 1000...110...... A+-DXWL... U U U U 12 12 4 4\r
735ori 16 toc . 0000000000111100 .......... U U U U 20 16 12 12\r
736ori 16 tos . 0000000001111100 .......... S S S S 20 16 12 12\r
737ori 8 . d 0000000000000... .......... U U U U 8 8 2 2\r
738ori 8 . . 0000000000...... A+-DXWL... U U U U 12 12 4 4\r
739ori 16 . d 0000000001000... .......... U U U U 8 8 2 2\r
740ori 16 . . 0000000001...... A+-DXWL... U U U U 12 12 4 4\r
741ori 32 . d 0000000010000... .......... U U U U 16 14 2 2\r
742ori 32 . . 0000000010...... A+-DXWL... U U U U 20 20 4 4\r
743pack 16 rr . 1000...101000... .......... . . U U . . 6 6\r
744pack 16 mm ax7 1000111101001... .......... . . U U . . 13 13\r
745pack 16 mm ay7 1000...101001111 .......... . . U U . . 13 13\r
746pack 16 mm axy7 1000111101001111 .......... . . U U . . 13 13\r
747pack 16 mm . 1000...101001... .......... . . U U . . 13 13\r
748pea 32 . . 0100100001...... A..DXWLdx. U U U U 6 6 5 5\r
749pflush 32 . . 1111010100011000 .......... . . . S . . . 4 TODO: correct timing\r
750reset 0 . . 0100111001110000 .......... S S S S 0 0 0 0\r
751ror 8 s . 1110...000011... .......... U U U U 6 6 8 8\r
752ror 16 s . 1110...001011... .......... U U U U 6 6 8 8\r
753ror 32 s . 1110...010011... .......... U U U U 8 8 8 8\r
754ror 8 r . 1110...000111... .......... U U U U 6 6 8 8\r
755ror 16 r . 1110...001111... .......... U U U U 6 6 8 8\r
756ror 32 r . 1110...010111... .......... U U U U 8 8 8 8\r
757ror 16 . . 1110011011...... A+-DXWL... U U U U 8 8 7 7\r
758rol 8 s . 1110...100011... .......... U U U U 6 6 8 8\r
759rol 16 s . 1110...101011... .......... U U U U 6 6 8 8\r
760rol 32 s . 1110...110011... .......... U U U U 8 8 8 8\r
761rol 8 r . 1110...100111... .......... U U U U 6 6 8 8\r
762rol 16 r . 1110...101111... .......... U U U U 6 6 8 8\r
763rol 32 r . 1110...110111... .......... U U U U 8 8 8 8\r
764rol 16 . . 1110011111...... A+-DXWL... U U U U 8 8 7 7\r
765roxr 8 s . 1110...000010... .......... U U U U 6 6 12 12\r
766roxr 16 s . 1110...001010... .......... U U U U 6 6 12 12\r
767roxr 32 s . 1110...010010... .......... U U U U 8 8 12 12\r
768roxr 8 r . 1110...000110... .......... U U U U 6 6 12 12\r
769roxr 16 r . 1110...001110... .......... U U U U 6 6 12 12\r
770roxr 32 r . 1110...010110... .......... U U U U 8 8 12 12\r
771roxr 16 . . 1110010011...... A+-DXWL... U U U U 8 8 5 5\r
772roxl 8 s . 1110...100010... .......... U U U U 6 6 12 12\r
773roxl 16 s . 1110...101010... .......... U U U U 6 6 12 12\r
774roxl 32 s . 1110...110010... .......... U U U U 8 8 12 12\r
775roxl 8 r . 1110...100110... .......... U U U U 6 6 12 12\r
776roxl 16 r . 1110...101110... .......... U U U U 6 6 12 12\r
777roxl 32 r . 1110...110110... .......... U U U U 8 8 12 12\r
778roxl 16 . . 1110010111...... A+-DXWL... U U U U 8 8 5 5\r
779rtd 32 . . 0100111001110100 .......... . U U U . 16 10 10\r
780rte 32 . . 0100111001110011 .......... S S S S 20 24 20 20 bus fault not emulated\r
781rtm 32 . . 000001101100.... .......... . . U U . . 19 19 not properly emulated\r
782rtr 32 . . 0100111001110111 .......... U U U U 20 20 14 14\r
783rts 32 . . 0100111001110101 .......... U U U U 16 16 10 10\r
784sbcd 8 rr . 1000...100000... .......... U U U U 6 6 4 4\r
785sbcd 8 mm ax7 1000111100001... .......... U U U U 18 18 16 16\r
786sbcd 8 mm ay7 1000...100001111 .......... U U U U 18 18 16 16\r
787sbcd 8 mm axy7 1000111100001111 .......... U U U U 18 18 16 16\r
788sbcd 8 mm . 1000...100001... .......... U U U U 18 18 16 16\r
789st 8 . d 0101000011000... .......... U U U U 6 4 4 4\r
790st 8 . . 0101000011...... A+-DXWL... U U U U 8 8 6 6\r
791sf 8 . d 0101000111000... .......... U U U U 4 4 4 4\r
792sf 8 . . 0101000111...... A+-DXWL... U U U U 8 8 6 6\r
793scc 8 . d 0101....11000... .......... U U U U 4 4 4 4\r
794scc 8 . . 0101....11...... A+-DXWL... U U U U 8 8 6 6\r
795stop 0 . . 0100111001110010 .......... S S S S 4 4 8 8\r
796sub 8 er d 1001...000000... .......... U U U U 4 4 2 2\r
797sub 8 er . 1001...000...... A+-DXWLdxI U U U U 4 4 2 2\r
798sub 16 er d 1001...001000... .......... U U U U 4 4 2 2\r
799sub 16 er a 1001...001001... .......... U U U U 4 4 2 2\r
800sub 16 er . 1001...001...... A+-DXWLdxI U U U U 4 4 2 2\r
801sub 32 er d 1001...010000... .......... U U U U 6 6 2 2\r
802sub 32 er a 1001...010001... .......... U U U U 6 6 2 2\r
803sub 32 er . 1001...010...... A+-DXWLdxI U U U U 6 6 2 2\r
804sub 8 re . 1001...100...... A+-DXWL... U U U U 8 8 4 4\r
805sub 16 re . 1001...101...... A+-DXWL... U U U U 8 8 4 4\r
806sub 32 re . 1001...110...... A+-DXWL... U U U U 12 12 4 4\r
807suba 16 . d 1001...011000... .......... U U U U 8 8 2 2\r
808suba 16 . a 1001...011001... .......... U U U U 8 8 2 2\r
809suba 16 . . 1001...011...... A+-DXWLdxI U U U U 8 8 2 2\r
810suba 32 . d 1001...111000... .......... U U U U 6 6 2 2\r
811suba 32 . a 1001...111001... .......... U U U U 6 6 2 2\r
812suba 32 . . 1001...111...... A+-DXWLdxI U U U U 6 6 2 2\r
813subi 8 . d 0000010000000... .......... U U U U 8 8 2 2\r
814subi 8 . . 0000010000...... A+-DXWL... U U U U 12 12 4 4\r
815subi 16 . d 0000010001000... .......... U U U U 8 8 2 2\r
816subi 16 . . 0000010001...... A+-DXWL... U U U U 12 12 4 4\r
817subi 32 . d 0000010010000... .......... U U U U 16 14 2 2\r
818subi 32 . . 0000010010...... A+-DXWL... U U U U 20 20 4 4\r
819subq 8 . d 0101...100000... .......... U U U U 4 4 2 2\r
820subq 8 . . 0101...100...... A+-DXWL... U U U U 8 8 4 4\r
821subq 16 . d 0101...101000... .......... U U U U 4 4 2 2\r
822subq 16 . a 0101...101001... .......... U U U U 8 4 2 2\r
823subq 16 . . 0101...101...... A+-DXWL... U U U U 8 8 4 4\r
824subq 32 . d 0101...110000... .......... U U U U 8 8 2 2\r
825subq 32 . a 0101...110001... .......... U U U U 8 8 2 2\r
826subq 32 . . 0101...110...... A+-DXWL... U U U U 12 12 4 4\r
827subx 8 rr . 1001...100000... .......... U U U U 4 4 2 2\r
828subx 16 rr . 1001...101000... .......... U U U U 4 4 2 2\r
829subx 32 rr . 1001...110000... .......... U U U U 8 6 2 2\r
830subx 8 mm ax7 1001111100001... .......... U U U U 18 18 12 12\r
831subx 8 mm ay7 1001...100001111 .......... U U U U 18 18 12 12\r
832subx 8 mm axy7 1001111100001111 .......... U U U U 18 18 12 12\r
833subx 8 mm . 1001...100001... .......... U U U U 18 18 12 12\r
834subx 16 mm . 1001...101001... .......... U U U U 18 18 12 12\r
835subx 32 mm . 1001...110001... .......... U U U U 30 30 12 12\r
836swap 32 . . 0100100001000... .......... U U U U 4 4 4 4\r
837tas 8 . d 0100101011000... .......... U U U U 4 4 4 4\r
838tas 8 . . 0100101011...... A+-DXWL... U U U U 14 14 12 12\r
839trap 0 . . 010011100100.... .......... U U U U 4 4 4 4\r
840trapt 0 . . 0101000011111100 .......... . . U U . . 4 4\r
841trapt 16 . . 0101000011111010 .......... . . U U . . 6 6\r
842trapt 32 . . 0101000011111011 .......... . . U U . . 8 8\r
843trapf 0 . . 0101000111111100 .......... . . U U . . 4 4\r
844trapf 16 . . 0101000111111010 .......... . . U U . . 6 6\r
845trapf 32 . . 0101000111111011 .......... . . U U . . 8 8\r
846trapcc 0 . . 0101....11111100 .......... . . U U . . 4 4\r
847trapcc 16 . . 0101....11111010 .......... . . U U . . 6 6\r
848trapcc 32 . . 0101....11111011 .......... . . U U . . 8 8\r
849trapv 0 . . 0100111001110110 .......... U U U U 4 4 4 4\r
850tst 8 . d 0100101000000... .......... U U U U 4 4 2 2\r
851tst 8 . . 0100101000...... A+-DXWL... U U U U 4 4 2 2\r
852tst 8 . pcdi 0100101000111010 .......... . . U U . . 7 7\r
853tst 8 . pcix 0100101000111011 .......... . . U U . . 9 9\r
854tst 8 . i 0100101000111100 .......... . . U U . . 6 6\r
855tst 16 . d 0100101001000... .......... U U U U 4 4 2 2\r
856tst 16 . a 0100101001001... .......... . . U U . . 2 2\r
857tst 16 . . 0100101001...... A+-DXWL... U U U U 4 4 2 2\r
858tst 16 . pcdi 0100101001111010 .......... . . U U . . 7 7\r
859tst 16 . pcix 0100101001111011 .......... . . U U . . 9 9\r
860tst 16 . i 0100101001111100 .......... . . U U . . 6 6\r
861tst 32 . d 0100101010000... .......... U U U U 4 4 2 2\r
862tst 32 . a 0100101010001... .......... . . U U . . 2 2\r
863tst 32 . . 0100101010...... A+-DXWL... U U U U 4 4 2 2\r
864tst 32 . pcdi 0100101010111010 .......... . . U U . . 7 7\r
865tst 32 . pcix 0100101010111011 .......... . . U U . . 9 9\r
866tst 32 . i 0100101010111100 .......... . . U U . . 6 6\r
867unlk 32 . a7 0100111001011111 .......... U U U U 12 12 6 6\r
868unlk 32 . . 0100111001011... .......... U U U U 12 12 6 6\r
869unpk 16 rr . 1000...110000... .......... . . U U . . 8 8\r
870unpk 16 mm ax7 1000111110001... .......... . . U U . . 13 13\r
871unpk 16 mm ay7 1000...110001111 .......... . . U U . . 13 13\r
872unpk 16 mm axy7 1000111110001111 .......... . . U U . . 13 13\r
873unpk 16 mm . 1000...110001... .......... . . U U . . 13 13\r
874\r
875\r
876\r
877XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\r
878M68KMAKE_OPCODE_HANDLER_BODY\r
879\r
880M68KMAKE_OP(1010, 0, ., .)\r
881{\r
882 m68ki_exception_1010();\r
883}\r
884\r
885\r
886M68KMAKE_OP(1111, 0, ., .)\r
887{\r
888 m68ki_exception_1111();\r
889}\r
890\r
891\r
c6a4c892 892M68KMAKE_OP(040fpu0, 32, ., .)\r
893{\r
894 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
895 {\r
896 m68040_fpu_op0();\r
897 return;\r
898 }\r
899 m68ki_exception_1111();\r
900}\r
901\r
902\r
903M68KMAKE_OP(040fpu1, 32, ., .)\r
904{\r
905 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
906 {\r
907 m68040_fpu_op1();\r
908 return;\r
909 }\r
910 m68ki_exception_1111();\r
911}\r
912\r
913\r
914\r
cc68a136 915M68KMAKE_OP(abcd, 8, rr, .)\r
916{\r
917 uint* r_dst = &DX;\r
918 uint src = DY;\r
919 uint dst = *r_dst;\r
920 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();\r
921\r
922 FLAG_V = ~res; /* Undefined V behavior */\r
923\r
924 if(res > 9)\r
925 res += 6;\r
926 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);\r
927 FLAG_X = FLAG_C = (res > 0x99) << 8;\r
928 if(FLAG_C)\r
929 res -= 0xa0;\r
930\r
931 FLAG_V &= res; /* Undefined V behavior part II */\r
932 FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
933\r
934 res = MASK_OUT_ABOVE_8(res);\r
935 FLAG_Z |= res;\r
936\r
937 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
938}\r
939\r
940\r
941M68KMAKE_OP(abcd, 8, mm, ax7)\r
942{\r
943 uint src = OPER_AY_PD_8();\r
944 uint ea = EA_A7_PD_8();\r
945 uint dst = m68ki_read_8(ea);\r
946 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();\r
947\r
948 FLAG_V = ~res; /* Undefined V behavior */\r
949\r
950 if(res > 9)\r
951 res += 6;\r
952 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);\r
953 FLAG_X = FLAG_C = (res > 0x99) << 8;\r
954 if(FLAG_C)\r
955 res -= 0xa0;\r
956\r
957 FLAG_V &= res; /* Undefined V behavior part II */\r
958 FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
959\r
960 res = MASK_OUT_ABOVE_8(res);\r
961 FLAG_Z |= res;\r
962\r
963 m68ki_write_8(ea, res);\r
964}\r
965\r
966\r
967M68KMAKE_OP(abcd, 8, mm, ay7)\r
968{\r
969 uint src = OPER_A7_PD_8();\r
970 uint ea = EA_AX_PD_8();\r
971 uint dst = m68ki_read_8(ea);\r
972 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();\r
973\r
974 FLAG_V = ~res; /* Undefined V behavior */\r
975\r
976 if(res > 9)\r
977 res += 6;\r
978 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);\r
979 FLAG_X = FLAG_C = (res > 0x99) << 8;\r
980 if(FLAG_C)\r
981 res -= 0xa0;\r
982\r
983 FLAG_V &= res; /* Undefined V behavior part II */\r
984 FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
985\r
986 res = MASK_OUT_ABOVE_8(res);\r
987 FLAG_Z |= res;\r
988\r
989 m68ki_write_8(ea, res);\r
990}\r
991\r
992\r
993M68KMAKE_OP(abcd, 8, mm, axy7)\r
994{\r
995 uint src = OPER_A7_PD_8();\r
996 uint ea = EA_A7_PD_8();\r
997 uint dst = m68ki_read_8(ea);\r
998 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();\r
999\r
1000 FLAG_V = ~res; /* Undefined V behavior */\r
1001\r
1002 if(res > 9)\r
1003 res += 6;\r
1004 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);\r
1005 FLAG_X = FLAG_C = (res > 0x99) << 8;\r
1006 if(FLAG_C)\r
1007 res -= 0xa0;\r
1008\r
1009 FLAG_V &= res; /* Undefined V behavior part II */\r
1010 FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
1011\r
1012 res = MASK_OUT_ABOVE_8(res);\r
1013 FLAG_Z |= res;\r
1014\r
1015 m68ki_write_8(ea, res);\r
1016}\r
1017\r
1018\r
1019M68KMAKE_OP(abcd, 8, mm, .)\r
1020{\r
1021 uint src = OPER_AY_PD_8();\r
1022 uint ea = EA_AX_PD_8();\r
1023 uint dst = m68ki_read_8(ea);\r
1024 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();\r
1025\r
1026 FLAG_V = ~res; /* Undefined V behavior */\r
1027\r
1028 if(res > 9)\r
1029 res += 6;\r
1030 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);\r
1031 FLAG_X = FLAG_C = (res > 0x99) << 8;\r
1032 if(FLAG_C)\r
1033 res -= 0xa0;\r
1034\r
1035 FLAG_V &= res; /* Undefined V behavior part II */\r
1036 FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
1037\r
1038 res = MASK_OUT_ABOVE_8(res);\r
1039 FLAG_Z |= res;\r
1040\r
1041 m68ki_write_8(ea, res);\r
1042}\r
1043\r
1044\r
1045M68KMAKE_OP(add, 8, er, d)\r
1046{\r
1047 uint* r_dst = &DX;\r
1048 uint src = MASK_OUT_ABOVE_8(DY);\r
1049 uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
1050 uint res = src + dst;\r
1051\r
1052 FLAG_N = NFLAG_8(res);\r
1053 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1054 FLAG_X = FLAG_C = CFLAG_8(res);\r
1055 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
1056\r
1057 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;\r
1058}\r
1059\r
1060\r
1061M68KMAKE_OP(add, 8, er, .)\r
1062{\r
1063 uint* r_dst = &DX;\r
1064 uint src = M68KMAKE_GET_OPER_AY_8;\r
1065 uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
1066 uint res = src + dst;\r
1067\r
1068 FLAG_N = NFLAG_8(res);\r
1069 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1070 FLAG_X = FLAG_C = CFLAG_8(res);\r
1071 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
1072\r
1073 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;\r
1074}\r
1075\r
1076\r
1077M68KMAKE_OP(add, 16, er, d)\r
1078{\r
1079 uint* r_dst = &DX;\r
1080 uint src = MASK_OUT_ABOVE_16(DY);\r
1081 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
1082 uint res = src + dst;\r
1083\r
1084 FLAG_N = NFLAG_16(res);\r
1085 FLAG_V = VFLAG_ADD_16(src, dst, res);\r
1086 FLAG_X = FLAG_C = CFLAG_16(res);\r
1087 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
1088\r
1089 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
1090}\r
1091\r
1092\r
1093M68KMAKE_OP(add, 16, er, a)\r
1094{\r
1095 uint* r_dst = &DX;\r
1096 uint src = MASK_OUT_ABOVE_16(AY);\r
1097 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
1098 uint res = src + dst;\r
1099\r
1100 FLAG_N = NFLAG_16(res);\r
1101 FLAG_V = VFLAG_ADD_16(src, dst, res);\r
1102 FLAG_X = FLAG_C = CFLAG_16(res);\r
1103 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
1104\r
1105 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
1106}\r
1107\r
1108\r
1109M68KMAKE_OP(add, 16, er, .)\r
1110{\r
1111 uint* r_dst = &DX;\r
1112 uint src = M68KMAKE_GET_OPER_AY_16;\r
1113 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
1114 uint res = src + dst;\r
1115\r
1116 FLAG_N = NFLAG_16(res);\r
1117 FLAG_V = VFLAG_ADD_16(src, dst, res);\r
1118 FLAG_X = FLAG_C = CFLAG_16(res);\r
1119 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
1120\r
1121 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
1122}\r
1123\r
1124\r
1125M68KMAKE_OP(add, 32, er, d)\r
1126{\r
1127 uint* r_dst = &DX;\r
1128 uint src = DY;\r
1129 uint dst = *r_dst;\r
1130 uint res = src + dst;\r
1131\r
1132 FLAG_N = NFLAG_32(res);\r
1133 FLAG_V = VFLAG_ADD_32(src, dst, res);\r
1134 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
1135 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
1136\r
1137 *r_dst = FLAG_Z;\r
1138}\r
1139\r
1140\r
1141M68KMAKE_OP(add, 32, er, a)\r
1142{\r
1143 uint* r_dst = &DX;\r
1144 uint src = AY;\r
1145 uint dst = *r_dst;\r
1146 uint res = src + dst;\r
1147\r
1148 FLAG_N = NFLAG_32(res);\r
1149 FLAG_V = VFLAG_ADD_32(src, dst, res);\r
1150 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
1151 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
1152\r
1153 *r_dst = FLAG_Z;\r
1154}\r
1155\r
1156\r
1157M68KMAKE_OP(add, 32, er, .)\r
1158{\r
1159 uint* r_dst = &DX;\r
1160 uint src = M68KMAKE_GET_OPER_AY_32;\r
1161 uint dst = *r_dst;\r
1162 uint res = src + dst;\r
1163\r
1164 FLAG_N = NFLAG_32(res);\r
1165 FLAG_V = VFLAG_ADD_32(src, dst, res);\r
1166 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
1167 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
1168\r
1169 *r_dst = FLAG_Z;\r
1170}\r
1171\r
1172\r
1173M68KMAKE_OP(add, 8, re, .)\r
1174{\r
1175 uint ea = M68KMAKE_GET_EA_AY_8;\r
1176 uint src = MASK_OUT_ABOVE_8(DX);\r
1177 uint dst = m68ki_read_8(ea);\r
1178 uint res = src + dst;\r
1179\r
1180 FLAG_N = NFLAG_8(res);\r
1181 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1182 FLAG_X = FLAG_C = CFLAG_8(res);\r
1183 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
1184\r
1185 m68ki_write_8(ea, FLAG_Z);\r
1186}\r
1187\r
1188\r
1189M68KMAKE_OP(add, 16, re, .)\r
1190{\r
1191 uint ea = M68KMAKE_GET_EA_AY_16;\r
1192 uint src = MASK_OUT_ABOVE_16(DX);\r
1193 uint dst = m68ki_read_16(ea);\r
1194 uint res = src + dst;\r
1195\r
1196 FLAG_N = NFLAG_16(res);\r
1197 FLAG_V = VFLAG_ADD_16(src, dst, res);\r
1198 FLAG_X = FLAG_C = CFLAG_16(res);\r
1199 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
1200\r
1201 m68ki_write_16(ea, FLAG_Z);\r
1202}\r
1203\r
1204\r
1205M68KMAKE_OP(add, 32, re, .)\r
1206{\r
1207 uint ea = M68KMAKE_GET_EA_AY_32;\r
1208 uint src = DX;\r
1209 uint dst = m68ki_read_32(ea);\r
1210 uint res = src + dst;\r
1211\r
1212 FLAG_N = NFLAG_32(res);\r
1213 FLAG_V = VFLAG_ADD_32(src, dst, res);\r
1214 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
1215 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
1216\r
1217 m68ki_write_32(ea, FLAG_Z);\r
1218}\r
1219\r
1220\r
1221M68KMAKE_OP(adda, 16, ., d)\r
1222{\r
1223 uint* r_dst = &AX;\r
1224\r
1225 *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(DY));\r
1226}\r
1227\r
1228\r
1229M68KMAKE_OP(adda, 16, ., a)\r
1230{\r
1231 uint* r_dst = &AX;\r
1232\r
1233 *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(AY));\r
1234}\r
1235\r
1236\r
1237M68KMAKE_OP(adda, 16, ., .)\r
1238{\r
1239 uint* r_dst = &AX;\r
c6a4c892 1240 uint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);\r
cc68a136 1241\r
c6a4c892 1242 *r_dst = MASK_OUT_ABOVE_32(*r_dst + src);\r
cc68a136 1243}\r
1244\r
1245\r
1246M68KMAKE_OP(adda, 32, ., d)\r
1247{\r
1248 uint* r_dst = &AX;\r
1249\r
1250 *r_dst = MASK_OUT_ABOVE_32(*r_dst + DY);\r
1251}\r
1252\r
1253\r
1254M68KMAKE_OP(adda, 32, ., a)\r
1255{\r
1256 uint* r_dst = &AX;\r
1257\r
1258 *r_dst = MASK_OUT_ABOVE_32(*r_dst + AY);\r
1259}\r
1260\r
1261\r
1262M68KMAKE_OP(adda, 32, ., .)\r
1263{\r
1264 uint* r_dst = &AX;\r
1265\r
1266 *r_dst = MASK_OUT_ABOVE_32(*r_dst + M68KMAKE_GET_OPER_AY_32);\r
1267}\r
1268\r
1269\r
1270M68KMAKE_OP(addi, 8, ., d)\r
1271{\r
1272 uint* r_dst = &DY;\r
1273 uint src = OPER_I_8();\r
1274 uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
1275 uint res = src + dst;\r
1276\r
1277 FLAG_N = NFLAG_8(res);\r
1278 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1279 FLAG_X = FLAG_C = CFLAG_8(res);\r
1280 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
1281\r
1282 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;\r
1283}\r
1284\r
1285\r
1286M68KMAKE_OP(addi, 8, ., .)\r
1287{\r
1288 uint src = OPER_I_8();\r
1289 uint ea = M68KMAKE_GET_EA_AY_8;\r
1290 uint dst = m68ki_read_8(ea);\r
1291 uint res = src + dst;\r
1292\r
1293 FLAG_N = NFLAG_8(res);\r
1294 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1295 FLAG_X = FLAG_C = CFLAG_8(res);\r
1296 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
1297\r
1298 m68ki_write_8(ea, FLAG_Z);\r
1299}\r
1300\r
1301\r
1302M68KMAKE_OP(addi, 16, ., d)\r
1303{\r
1304 uint* r_dst = &DY;\r
1305 uint src = OPER_I_16();\r
1306 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
1307 uint res = src + dst;\r
1308\r
1309 FLAG_N = NFLAG_16(res);\r
1310 FLAG_V = VFLAG_ADD_16(src, dst, res);\r
1311 FLAG_X = FLAG_C = CFLAG_16(res);\r
1312 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
1313\r
1314 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
1315}\r
1316\r
1317\r
1318M68KMAKE_OP(addi, 16, ., .)\r
1319{\r
1320 uint src = OPER_I_16();\r
1321 uint ea = M68KMAKE_GET_EA_AY_16;\r
1322 uint dst = m68ki_read_16(ea);\r
1323 uint res = src + dst;\r
1324\r
1325 FLAG_N = NFLAG_16(res);\r
1326 FLAG_V = VFLAG_ADD_16(src, dst, res);\r
1327 FLAG_X = FLAG_C = CFLAG_16(res);\r
1328 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
1329\r
1330 m68ki_write_16(ea, FLAG_Z);\r
1331}\r
1332\r
1333\r
1334M68KMAKE_OP(addi, 32, ., d)\r
1335{\r
1336 uint* r_dst = &DY;\r
1337 uint src = OPER_I_32();\r
1338 uint dst = *r_dst;\r
1339 uint res = src + dst;\r
1340\r
1341 FLAG_N = NFLAG_32(res);\r
1342 FLAG_V = VFLAG_ADD_32(src, dst, res);\r
1343 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
1344 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
1345\r
1346 *r_dst = FLAG_Z;\r
1347}\r
1348\r
1349\r
1350M68KMAKE_OP(addi, 32, ., .)\r
1351{\r
1352 uint src = OPER_I_32();\r
1353 uint ea = M68KMAKE_GET_EA_AY_32;\r
1354 uint dst = m68ki_read_32(ea);\r
1355 uint res = src + dst;\r
1356\r
1357 FLAG_N = NFLAG_32(res);\r
1358 FLAG_V = VFLAG_ADD_32(src, dst, res);\r
1359 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
1360 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
1361\r
1362 m68ki_write_32(ea, FLAG_Z);\r
1363}\r
1364\r
1365\r
1366M68KMAKE_OP(addq, 8, ., d)\r
1367{\r
1368 uint* r_dst = &DY;\r
1369 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
1370 uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
1371 uint res = src + dst;\r
1372\r
1373 FLAG_N = NFLAG_8(res);\r
1374 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1375 FLAG_X = FLAG_C = CFLAG_8(res);\r
1376 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
1377\r
1378 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;\r
1379}\r
1380\r
1381\r
1382M68KMAKE_OP(addq, 8, ., .)\r
1383{\r
1384 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
1385 uint ea = M68KMAKE_GET_EA_AY_8;\r
1386 uint dst = m68ki_read_8(ea);\r
1387 uint res = src + dst;\r
1388\r
1389 FLAG_N = NFLAG_8(res);\r
1390 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1391 FLAG_X = FLAG_C = CFLAG_8(res);\r
1392 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
1393\r
1394 m68ki_write_8(ea, FLAG_Z);\r
1395}\r
1396\r
1397\r
1398M68KMAKE_OP(addq, 16, ., d)\r
1399{\r
1400 uint* r_dst = &DY;\r
1401 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
1402 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
1403 uint res = src + dst;\r
1404\r
1405 FLAG_N = NFLAG_16(res);\r
1406 FLAG_V = VFLAG_ADD_16(src, dst, res);\r
1407 FLAG_X = FLAG_C = CFLAG_16(res);\r
1408 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
1409\r
1410 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
1411}\r
1412\r
1413\r
1414M68KMAKE_OP(addq, 16, ., a)\r
1415{\r
1416 uint* r_dst = &AY;\r
1417\r
1418 *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1);\r
1419}\r
1420\r
1421\r
1422M68KMAKE_OP(addq, 16, ., .)\r
1423{\r
1424 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
1425 uint ea = M68KMAKE_GET_EA_AY_16;\r
1426 uint dst = m68ki_read_16(ea);\r
1427 uint res = src + dst;\r
1428\r
1429 FLAG_N = NFLAG_16(res);\r
1430 FLAG_V = VFLAG_ADD_16(src, dst, res);\r
1431 FLAG_X = FLAG_C = CFLAG_16(res);\r
1432 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
1433\r
1434 m68ki_write_16(ea, FLAG_Z);\r
1435}\r
1436\r
1437\r
1438M68KMAKE_OP(addq, 32, ., d)\r
1439{\r
1440 uint* r_dst = &DY;\r
1441 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
1442 uint dst = *r_dst;\r
1443 uint res = src + dst;\r
1444\r
1445 FLAG_N = NFLAG_32(res);\r
1446 FLAG_V = VFLAG_ADD_32(src, dst, res);\r
1447 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
1448 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
1449\r
1450 *r_dst = FLAG_Z;\r
1451}\r
1452\r
1453\r
1454M68KMAKE_OP(addq, 32, ., a)\r
1455{\r
1456 uint* r_dst = &AY;\r
1457\r
1458 *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1);\r
1459}\r
1460\r
1461\r
1462M68KMAKE_OP(addq, 32, ., .)\r
1463{\r
1464 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
1465 uint ea = M68KMAKE_GET_EA_AY_32;\r
1466 uint dst = m68ki_read_32(ea);\r
1467 uint res = src + dst;\r
1468\r
1469\r
1470 FLAG_N = NFLAG_32(res);\r
1471 FLAG_V = VFLAG_ADD_32(src, dst, res);\r
1472 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
1473 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
1474\r
1475 m68ki_write_32(ea, FLAG_Z);\r
1476}\r
1477\r
1478\r
1479M68KMAKE_OP(addx, 8, rr, .)\r
1480{\r
1481 uint* r_dst = &DX;\r
1482 uint src = MASK_OUT_ABOVE_8(DY);\r
1483 uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
1484 uint res = src + dst + XFLAG_AS_1();\r
1485\r
1486 FLAG_N = NFLAG_8(res);\r
1487 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1488 FLAG_X = FLAG_C = CFLAG_8(res);\r
1489\r
1490 res = MASK_OUT_ABOVE_8(res);\r
1491 FLAG_Z |= res;\r
1492\r
1493 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
1494}\r
1495\r
1496\r
1497M68KMAKE_OP(addx, 16, rr, .)\r
1498{\r
1499 uint* r_dst = &DX;\r
1500 uint src = MASK_OUT_ABOVE_16(DY);\r
1501 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
1502 uint res = src + dst + XFLAG_AS_1();\r
1503\r
1504 FLAG_N = NFLAG_16(res);\r
1505 FLAG_V = VFLAG_ADD_16(src, dst, res);\r
1506 FLAG_X = FLAG_C = CFLAG_16(res);\r
1507\r
1508 res = MASK_OUT_ABOVE_16(res);\r
1509 FLAG_Z |= res;\r
1510\r
1511 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
1512}\r
1513\r
1514\r
1515M68KMAKE_OP(addx, 32, rr, .)\r
1516{\r
1517 uint* r_dst = &DX;\r
1518 uint src = DY;\r
1519 uint dst = *r_dst;\r
1520 uint res = src + dst + XFLAG_AS_1();\r
1521\r
1522 FLAG_N = NFLAG_32(res);\r
1523 FLAG_V = VFLAG_ADD_32(src, dst, res);\r
1524 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
1525\r
1526 res = MASK_OUT_ABOVE_32(res);\r
1527 FLAG_Z |= res;\r
1528\r
1529 *r_dst = res;\r
1530}\r
1531\r
1532\r
1533M68KMAKE_OP(addx, 8, mm, ax7)\r
1534{\r
1535 uint src = OPER_AY_PD_8();\r
1536 uint ea = EA_A7_PD_8();\r
1537 uint dst = m68ki_read_8(ea);\r
1538 uint res = src + dst + XFLAG_AS_1();\r
1539\r
1540 FLAG_N = NFLAG_8(res);\r
1541 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1542 FLAG_X = FLAG_C = CFLAG_8(res);\r
1543\r
1544 res = MASK_OUT_ABOVE_8(res);\r
1545 FLAG_Z |= res;\r
1546\r
1547 m68ki_write_8(ea, res);\r
1548}\r
1549\r
1550\r
1551M68KMAKE_OP(addx, 8, mm, ay7)\r
1552{\r
1553 uint src = OPER_A7_PD_8();\r
1554 uint ea = EA_AX_PD_8();\r
1555 uint dst = m68ki_read_8(ea);\r
1556 uint res = src + dst + XFLAG_AS_1();\r
1557\r
1558 FLAG_N = NFLAG_8(res);\r
1559 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1560 FLAG_X = FLAG_C = CFLAG_8(res);\r
1561\r
1562 res = MASK_OUT_ABOVE_8(res);\r
1563 FLAG_Z |= res;\r
1564\r
1565 m68ki_write_8(ea, res);\r
1566}\r
1567\r
1568\r
1569M68KMAKE_OP(addx, 8, mm, axy7)\r
1570{\r
1571 uint src = OPER_A7_PD_8();\r
1572 uint ea = EA_A7_PD_8();\r
1573 uint dst = m68ki_read_8(ea);\r
1574 uint res = src + dst + XFLAG_AS_1();\r
1575\r
1576 FLAG_N = NFLAG_8(res);\r
1577 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1578 FLAG_X = FLAG_C = CFLAG_8(res);\r
1579\r
1580 res = MASK_OUT_ABOVE_8(res);\r
1581 FLAG_Z |= res;\r
1582\r
1583 m68ki_write_8(ea, res);\r
1584}\r
1585\r
1586\r
1587M68KMAKE_OP(addx, 8, mm, .)\r
1588{\r
1589 uint src = OPER_AY_PD_8();\r
1590 uint ea = EA_AX_PD_8();\r
1591 uint dst = m68ki_read_8(ea);\r
1592 uint res = src + dst + XFLAG_AS_1();\r
1593\r
1594 FLAG_N = NFLAG_8(res);\r
1595 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1596 FLAG_X = FLAG_C = CFLAG_8(res);\r
1597\r
1598 res = MASK_OUT_ABOVE_8(res);\r
1599 FLAG_Z |= res;\r
1600\r
1601 m68ki_write_8(ea, res);\r
1602}\r
1603\r
1604\r
1605M68KMAKE_OP(addx, 16, mm, .)\r
1606{\r
1607 uint src = OPER_AY_PD_16();\r
1608 uint ea = EA_AX_PD_16();\r
1609 uint dst = m68ki_read_16(ea);\r
1610 uint res = src + dst + XFLAG_AS_1();\r
1611\r
1612 FLAG_N = NFLAG_16(res);\r
1613 FLAG_V = VFLAG_ADD_16(src, dst, res);\r
1614 FLAG_X = FLAG_C = CFLAG_16(res);\r
1615\r
1616 res = MASK_OUT_ABOVE_16(res);\r
1617 FLAG_Z |= res;\r
1618\r
1619 m68ki_write_16(ea, res);\r
1620}\r
1621\r
1622\r
1623M68KMAKE_OP(addx, 32, mm, .)\r
1624{\r
1625 uint src = OPER_AY_PD_32();\r
1626 uint ea = EA_AX_PD_32();\r
1627 uint dst = m68ki_read_32(ea);\r
1628 uint res = src + dst + XFLAG_AS_1();\r
1629\r
1630 FLAG_N = NFLAG_32(res);\r
1631 FLAG_V = VFLAG_ADD_32(src, dst, res);\r
1632 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
1633\r
1634 res = MASK_OUT_ABOVE_32(res);\r
1635 FLAG_Z |= res;\r
1636\r
1637 m68ki_write_32(ea, res);\r
1638}\r
1639\r
1640\r
1641M68KMAKE_OP(and, 8, er, d)\r
1642{\r
1643 FLAG_Z = MASK_OUT_ABOVE_8(DX &= (DY | 0xffffff00));\r
1644\r
1645 FLAG_N = NFLAG_8(FLAG_Z);\r
1646 FLAG_C = CFLAG_CLEAR;\r
1647 FLAG_V = VFLAG_CLEAR;\r
1648}\r
1649\r
1650\r
1651M68KMAKE_OP(and, 8, er, .)\r
1652{\r
1653 FLAG_Z = MASK_OUT_ABOVE_8(DX &= (M68KMAKE_GET_OPER_AY_8 | 0xffffff00));\r
1654\r
1655 FLAG_N = NFLAG_8(FLAG_Z);\r
1656 FLAG_C = CFLAG_CLEAR;\r
1657 FLAG_V = VFLAG_CLEAR;\r
1658}\r
1659\r
1660\r
1661M68KMAKE_OP(and, 16, er, d)\r
1662{\r
1663 FLAG_Z = MASK_OUT_ABOVE_16(DX &= (DY | 0xffff0000));\r
1664\r
1665 FLAG_N = NFLAG_16(FLAG_Z);\r
1666 FLAG_C = CFLAG_CLEAR;\r
1667 FLAG_V = VFLAG_CLEAR;\r
1668}\r
1669\r
1670\r
1671M68KMAKE_OP(and, 16, er, .)\r
1672{\r
1673 FLAG_Z = MASK_OUT_ABOVE_16(DX &= (M68KMAKE_GET_OPER_AY_16 | 0xffff0000));\r
1674\r
1675 FLAG_N = NFLAG_16(FLAG_Z);\r
1676 FLAG_C = CFLAG_CLEAR;\r
1677 FLAG_V = VFLAG_CLEAR;\r
1678}\r
1679\r
1680\r
1681M68KMAKE_OP(and, 32, er, d)\r
1682{\r
1683 FLAG_Z = DX &= DY;\r
1684\r
1685 FLAG_N = NFLAG_32(FLAG_Z);\r
1686 FLAG_C = CFLAG_CLEAR;\r
1687 FLAG_V = VFLAG_CLEAR;\r
1688}\r
1689\r
1690\r
1691M68KMAKE_OP(and, 32, er, .)\r
1692{\r
1693 FLAG_Z = DX &= M68KMAKE_GET_OPER_AY_32;\r
1694\r
1695 FLAG_N = NFLAG_32(FLAG_Z);\r
1696 FLAG_C = CFLAG_CLEAR;\r
1697 FLAG_V = VFLAG_CLEAR;\r
1698}\r
1699\r
1700\r
1701M68KMAKE_OP(and, 8, re, .)\r
1702{\r
1703 uint ea = M68KMAKE_GET_EA_AY_8;\r
1704 uint res = DX & m68ki_read_8(ea);\r
1705\r
1706 FLAG_N = NFLAG_8(res);\r
1707 FLAG_C = CFLAG_CLEAR;\r
1708 FLAG_V = VFLAG_CLEAR;\r
1709 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
1710\r
1711 m68ki_write_8(ea, FLAG_Z);\r
1712}\r
1713\r
1714\r
1715M68KMAKE_OP(and, 16, re, .)\r
1716{\r
1717 uint ea = M68KMAKE_GET_EA_AY_16;\r
1718 uint res = DX & m68ki_read_16(ea);\r
1719\r
1720 FLAG_N = NFLAG_16(res);\r
1721 FLAG_C = CFLAG_CLEAR;\r
1722 FLAG_V = VFLAG_CLEAR;\r
1723 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
1724\r
1725 m68ki_write_16(ea, FLAG_Z);\r
1726}\r
1727\r
1728\r
1729M68KMAKE_OP(and, 32, re, .)\r
1730{\r
1731 uint ea = M68KMAKE_GET_EA_AY_32;\r
1732 uint res = DX & m68ki_read_32(ea);\r
1733\r
1734 FLAG_N = NFLAG_32(res);\r
1735 FLAG_Z = res;\r
1736 FLAG_C = CFLAG_CLEAR;\r
1737 FLAG_V = VFLAG_CLEAR;\r
1738\r
1739 m68ki_write_32(ea, res);\r
1740}\r
1741\r
1742\r
1743M68KMAKE_OP(andi, 8, ., d)\r
1744{\r
1745 FLAG_Z = MASK_OUT_ABOVE_8(DY &= (OPER_I_8() | 0xffffff00));\r
1746\r
1747 FLAG_N = NFLAG_8(FLAG_Z);\r
1748 FLAG_C = CFLAG_CLEAR;\r
1749 FLAG_V = VFLAG_CLEAR;\r
1750}\r
1751\r
1752\r
1753M68KMAKE_OP(andi, 8, ., .)\r
1754{\r
1755 uint src = OPER_I_8();\r
1756 uint ea = M68KMAKE_GET_EA_AY_8;\r
1757 uint res = src & m68ki_read_8(ea);\r
1758\r
1759 FLAG_N = NFLAG_8(res);\r
1760 FLAG_Z = res;\r
1761 FLAG_C = CFLAG_CLEAR;\r
1762 FLAG_V = VFLAG_CLEAR;\r
1763\r
1764 m68ki_write_8(ea, res);\r
1765}\r
1766\r
1767\r
1768M68KMAKE_OP(andi, 16, ., d)\r
1769{\r
1770 FLAG_Z = MASK_OUT_ABOVE_16(DY &= (OPER_I_16() | 0xffff0000));\r
1771\r
1772 FLAG_N = NFLAG_16(FLAG_Z);\r
1773 FLAG_C = CFLAG_CLEAR;\r
1774 FLAG_V = VFLAG_CLEAR;\r
1775}\r
1776\r
1777\r
1778M68KMAKE_OP(andi, 16, ., .)\r
1779{\r
1780 uint src = OPER_I_16();\r
1781 uint ea = M68KMAKE_GET_EA_AY_16;\r
1782 uint res = src & m68ki_read_16(ea);\r
1783\r
1784 FLAG_N = NFLAG_16(res);\r
1785 FLAG_Z = res;\r
1786 FLAG_C = CFLAG_CLEAR;\r
1787 FLAG_V = VFLAG_CLEAR;\r
1788\r
1789 m68ki_write_16(ea, res);\r
1790}\r
1791\r
1792\r
1793M68KMAKE_OP(andi, 32, ., d)\r
1794{\r
1795 FLAG_Z = DY &= (OPER_I_32());\r
1796\r
1797 FLAG_N = NFLAG_32(FLAG_Z);\r
1798 FLAG_C = CFLAG_CLEAR;\r
1799 FLAG_V = VFLAG_CLEAR;\r
1800}\r
1801\r
1802\r
1803M68KMAKE_OP(andi, 32, ., .)\r
1804{\r
1805 uint src = OPER_I_32();\r
1806 uint ea = M68KMAKE_GET_EA_AY_32;\r
1807 uint res = src & m68ki_read_32(ea);\r
1808\r
1809 FLAG_N = NFLAG_32(res);\r
1810 FLAG_Z = res;\r
1811 FLAG_C = CFLAG_CLEAR;\r
1812 FLAG_V = VFLAG_CLEAR;\r
1813\r
1814 m68ki_write_32(ea, res);\r
1815}\r
1816\r
1817\r
1818M68KMAKE_OP(andi, 16, toc, .)\r
1819{\r
1820 m68ki_set_ccr(m68ki_get_ccr() & OPER_I_16());\r
1821}\r
1822\r
1823\r
1824M68KMAKE_OP(andi, 16, tos, .)\r
1825{\r
1826 if(FLAG_S)\r
1827 {\r
1828 uint src = OPER_I_16();\r
1829 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
1830 m68ki_set_sr(m68ki_get_sr() & src);\r
1831 return;\r
1832 }\r
1833 m68ki_exception_privilege_violation();\r
1834}\r
1835\r
1836\r
1837M68KMAKE_OP(asr, 8, s, .)\r
1838{\r
1839 uint* r_dst = &DY;\r
1840 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
1841 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
1842 uint res = src >> shift;\r
1843\r
1844 if(shift != 0)\r
1845 USE_CYCLES(shift<<CYC_SHIFT);\r
1846\r
1847 if(GET_MSB_8(src))\r
1848 res |= m68ki_shift_8_table[shift];\r
1849\r
1850 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
1851\r
1852 FLAG_N = NFLAG_8(res);\r
1853 FLAG_Z = res;\r
1854 FLAG_V = VFLAG_CLEAR;\r
1855 FLAG_X = FLAG_C = src << (9-shift);\r
1856}\r
1857\r
1858\r
1859M68KMAKE_OP(asr, 16, s, .)\r
1860{\r
1861 uint* r_dst = &DY;\r
1862 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
1863 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
1864 uint res = src >> shift;\r
1865\r
1866 if(shift != 0)\r
1867 USE_CYCLES(shift<<CYC_SHIFT);\r
1868\r
1869 if(GET_MSB_16(src))\r
1870 res |= m68ki_shift_16_table[shift];\r
1871\r
1872 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
1873\r
1874 FLAG_N = NFLAG_16(res);\r
1875 FLAG_Z = res;\r
1876 FLAG_V = VFLAG_CLEAR;\r
1877 FLAG_X = FLAG_C = src << (9-shift);\r
1878}\r
1879\r
1880\r
1881M68KMAKE_OP(asr, 32, s, .)\r
1882{\r
1883 uint* r_dst = &DY;\r
1884 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
1885 uint src = *r_dst;\r
1886 uint res = src >> shift;\r
1887\r
1888 if(shift != 0)\r
1889 USE_CYCLES(shift<<CYC_SHIFT);\r
1890\r
1891 if(GET_MSB_32(src))\r
1892 res |= m68ki_shift_32_table[shift];\r
1893\r
1894 *r_dst = res;\r
1895\r
1896 FLAG_N = NFLAG_32(res);\r
1897 FLAG_Z = res;\r
1898 FLAG_V = VFLAG_CLEAR;\r
1899 FLAG_X = FLAG_C = src << (9-shift);\r
1900}\r
1901\r
1902\r
1903M68KMAKE_OP(asr, 8, r, .)\r
1904{\r
1905 uint* r_dst = &DY;\r
1906 uint shift = DX & 0x3f;\r
1907 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
1908 uint res = src >> shift;\r
1909\r
1910 if(shift != 0)\r
1911 {\r
1912 USE_CYCLES(shift<<CYC_SHIFT);\r
1913\r
1914 if(shift < 8)\r
1915 {\r
1916 if(GET_MSB_8(src))\r
1917 res |= m68ki_shift_8_table[shift];\r
1918\r
1919 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
1920\r
1921 FLAG_X = FLAG_C = src << (9-shift);\r
1922 FLAG_N = NFLAG_8(res);\r
1923 FLAG_Z = res;\r
1924 FLAG_V = VFLAG_CLEAR;\r
1925 return;\r
1926 }\r
1927\r
1928 if(GET_MSB_8(src))\r
1929 {\r
1930 *r_dst |= 0xff;\r
1931 FLAG_C = CFLAG_SET;\r
1932 FLAG_X = XFLAG_SET;\r
1933 FLAG_N = NFLAG_SET;\r
1934 FLAG_Z = ZFLAG_CLEAR;\r
1935 FLAG_V = VFLAG_CLEAR;\r
1936 return;\r
1937 }\r
1938\r
1939 *r_dst &= 0xffffff00;\r
1940 FLAG_C = CFLAG_CLEAR;\r
1941 FLAG_X = XFLAG_CLEAR;\r
1942 FLAG_N = NFLAG_CLEAR;\r
1943 FLAG_Z = ZFLAG_SET;\r
1944 FLAG_V = VFLAG_CLEAR;\r
1945 return;\r
1946 }\r
1947\r
1948 FLAG_C = CFLAG_CLEAR;\r
1949 FLAG_N = NFLAG_8(src);\r
1950 FLAG_Z = src;\r
1951 FLAG_V = VFLAG_CLEAR;\r
1952}\r
1953\r
1954\r
1955M68KMAKE_OP(asr, 16, r, .)\r
1956{\r
1957 uint* r_dst = &DY;\r
1958 uint shift = DX & 0x3f;\r
1959 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
1960 uint res = src >> shift;\r
1961\r
1962 if(shift != 0)\r
1963 {\r
1964 USE_CYCLES(shift<<CYC_SHIFT);\r
1965\r
1966 if(shift < 16)\r
1967 {\r
1968 if(GET_MSB_16(src))\r
1969 res |= m68ki_shift_16_table[shift];\r
1970\r
1971 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
1972\r
1973 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;\r
1974 FLAG_N = NFLAG_16(res);\r
1975 FLAG_Z = res;\r
1976 FLAG_V = VFLAG_CLEAR;\r
1977 return;\r
1978 }\r
1979\r
1980 if(GET_MSB_16(src))\r
1981 {\r
1982 *r_dst |= 0xffff;\r
1983 FLAG_C = CFLAG_SET;\r
1984 FLAG_X = XFLAG_SET;\r
1985 FLAG_N = NFLAG_SET;\r
1986 FLAG_Z = ZFLAG_CLEAR;\r
1987 FLAG_V = VFLAG_CLEAR;\r
1988 return;\r
1989 }\r
1990\r
1991 *r_dst &= 0xffff0000;\r
1992 FLAG_C = CFLAG_CLEAR;\r
1993 FLAG_X = XFLAG_CLEAR;\r
1994 FLAG_N = NFLAG_CLEAR;\r
1995 FLAG_Z = ZFLAG_SET;\r
1996 FLAG_V = VFLAG_CLEAR;\r
1997 return;\r
1998 }\r
1999\r
2000 FLAG_C = CFLAG_CLEAR;\r
2001 FLAG_N = NFLAG_16(src);\r
2002 FLAG_Z = src;\r
2003 FLAG_V = VFLAG_CLEAR;\r
2004}\r
2005\r
2006\r
2007M68KMAKE_OP(asr, 32, r, .)\r
2008{\r
2009 uint* r_dst = &DY;\r
2010 uint shift = DX & 0x3f;\r
2011 uint src = *r_dst;\r
2012 uint res = src >> shift;\r
2013\r
2014 if(shift != 0)\r
2015 {\r
2016 USE_CYCLES(shift<<CYC_SHIFT);\r
2017\r
2018 if(shift < 32)\r
2019 {\r
2020 if(GET_MSB_32(src))\r
2021 res |= m68ki_shift_32_table[shift];\r
2022\r
2023 *r_dst = res;\r
2024\r
2025 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;\r
2026 FLAG_N = NFLAG_32(res);\r
2027 FLAG_Z = res;\r
2028 FLAG_V = VFLAG_CLEAR;\r
2029 return;\r
2030 }\r
2031\r
2032 if(GET_MSB_32(src))\r
2033 {\r
2034 *r_dst = 0xffffffff;\r
2035 FLAG_C = CFLAG_SET;\r
2036 FLAG_X = XFLAG_SET;\r
2037 FLAG_N = NFLAG_SET;\r
2038 FLAG_Z = ZFLAG_CLEAR;\r
2039 FLAG_V = VFLAG_CLEAR;\r
2040 return;\r
2041 }\r
2042\r
2043 *r_dst = 0;\r
2044 FLAG_C = CFLAG_CLEAR;\r
2045 FLAG_X = XFLAG_CLEAR;\r
2046 FLAG_N = NFLAG_CLEAR;\r
2047 FLAG_Z = ZFLAG_SET;\r
2048 FLAG_V = VFLAG_CLEAR;\r
2049 return;\r
2050 }\r
2051\r
2052 FLAG_C = CFLAG_CLEAR;\r
2053 FLAG_N = NFLAG_32(src);\r
2054 FLAG_Z = src;\r
2055 FLAG_V = VFLAG_CLEAR;\r
2056}\r
2057\r
2058\r
2059M68KMAKE_OP(asr, 16, ., .)\r
2060{\r
2061 uint ea = M68KMAKE_GET_EA_AY_16;\r
2062 uint src = m68ki_read_16(ea);\r
2063 uint res = src >> 1;\r
2064\r
2065 if(GET_MSB_16(src))\r
2066 res |= 0x8000;\r
2067\r
2068 m68ki_write_16(ea, res);\r
2069\r
2070 FLAG_N = NFLAG_16(res);\r
2071 FLAG_Z = res;\r
2072 FLAG_V = VFLAG_CLEAR;\r
2073 FLAG_C = FLAG_X = src << 8;\r
2074}\r
2075\r
2076\r
2077M68KMAKE_OP(asl, 8, s, .)\r
2078{\r
2079 uint* r_dst = &DY;\r
2080 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
2081 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
2082 uint res = MASK_OUT_ABOVE_8(src << shift);\r
2083\r
2084 if(shift != 0)\r
2085 USE_CYCLES(shift<<CYC_SHIFT);\r
2086\r
2087 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
2088\r
2089 FLAG_X = FLAG_C = src << shift;\r
2090 FLAG_N = NFLAG_8(res);\r
2091 FLAG_Z = res;\r
2092 src &= m68ki_shift_8_table[shift + 1];\r
2093 FLAG_V = (!(src == 0 || (src == m68ki_shift_8_table[shift + 1] && shift < 8)))<<7;\r
2094}\r
2095\r
2096\r
2097M68KMAKE_OP(asl, 16, s, .)\r
2098{\r
2099 uint* r_dst = &DY;\r
2100 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
2101 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
2102 uint res = MASK_OUT_ABOVE_16(src << shift);\r
2103\r
2104 if(shift != 0)\r
2105 USE_CYCLES(shift<<CYC_SHIFT);\r
2106\r
2107 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
2108\r
2109 FLAG_N = NFLAG_16(res);\r
2110 FLAG_Z = res;\r
2111 FLAG_X = FLAG_C = src >> (8-shift);\r
2112 src &= m68ki_shift_16_table[shift + 1];\r
2113 FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7;\r
2114}\r
2115\r
2116\r
2117M68KMAKE_OP(asl, 32, s, .)\r
2118{\r
2119 uint* r_dst = &DY;\r
2120 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
2121 uint src = *r_dst;\r
2122 uint res = MASK_OUT_ABOVE_32(src << shift);\r
2123\r
2124 if(shift != 0)\r
2125 USE_CYCLES(shift<<CYC_SHIFT);\r
2126\r
2127 *r_dst = res;\r
2128\r
2129 FLAG_N = NFLAG_32(res);\r
2130 FLAG_Z = res;\r
2131 FLAG_X = FLAG_C = src >> (24-shift);\r
2132 src &= m68ki_shift_32_table[shift + 1];\r
2133 FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7;\r
2134}\r
2135\r
2136\r
2137M68KMAKE_OP(asl, 8, r, .)\r
2138{\r
2139 uint* r_dst = &DY;\r
2140 uint shift = DX & 0x3f;\r
2141 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
2142 uint res = MASK_OUT_ABOVE_8(src << shift);\r
2143\r
2144 if(shift != 0)\r
2145 {\r
2146 USE_CYCLES(shift<<CYC_SHIFT);\r
2147\r
2148 if(shift < 8)\r
2149 {\r
2150 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
2151 FLAG_X = FLAG_C = src << shift;\r
2152 FLAG_N = NFLAG_8(res);\r
2153 FLAG_Z = res;\r
2154 src &= m68ki_shift_8_table[shift + 1];\r
2155 FLAG_V = (!(src == 0 || src == m68ki_shift_8_table[shift + 1]))<<7;\r
2156 return;\r
2157 }\r
2158\r
2159 *r_dst &= 0xffffff00;\r
2160 FLAG_X = FLAG_C = ((shift == 8 ? src & 1 : 0))<<8;\r
2161 FLAG_N = NFLAG_CLEAR;\r
2162 FLAG_Z = ZFLAG_SET;\r
2163 FLAG_V = (!(src == 0))<<7;\r
2164 return;\r
2165 }\r
2166\r
2167 FLAG_C = CFLAG_CLEAR;\r
2168 FLAG_N = NFLAG_8(src);\r
2169 FLAG_Z = src;\r
2170 FLAG_V = VFLAG_CLEAR;\r
2171}\r
2172\r
2173\r
2174M68KMAKE_OP(asl, 16, r, .)\r
2175{\r
2176 uint* r_dst = &DY;\r
2177 uint shift = DX & 0x3f;\r
2178 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
2179 uint res = MASK_OUT_ABOVE_16(src << shift);\r
2180\r
2181 if(shift != 0)\r
2182 {\r
2183 USE_CYCLES(shift<<CYC_SHIFT);\r
2184\r
2185 if(shift < 16)\r
2186 {\r
2187 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
2188 FLAG_X = FLAG_C = (src << shift) >> 8;\r
2189 FLAG_N = NFLAG_16(res);\r
2190 FLAG_Z = res;\r
2191 src &= m68ki_shift_16_table[shift + 1];\r
2192 FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7;\r
2193 return;\r
2194 }\r
2195\r
2196 *r_dst &= 0xffff0000;\r
2197 FLAG_X = FLAG_C = ((shift == 16 ? src & 1 : 0))<<8;\r
2198 FLAG_N = NFLAG_CLEAR;\r
2199 FLAG_Z = ZFLAG_SET;\r
2200 FLAG_V = (!(src == 0))<<7;\r
2201 return;\r
2202 }\r
2203\r
2204 FLAG_C = CFLAG_CLEAR;\r
2205 FLAG_N = NFLAG_16(src);\r
2206 FLAG_Z = src;\r
2207 FLAG_V = VFLAG_CLEAR;\r
2208}\r
2209\r
2210\r
2211M68KMAKE_OP(asl, 32, r, .)\r
2212{\r
2213 uint* r_dst = &DY;\r
2214 uint shift = DX & 0x3f;\r
2215 uint src = *r_dst;\r
2216 uint res = MASK_OUT_ABOVE_32(src << shift);\r
2217\r
2218 if(shift != 0)\r
2219 {\r
2220 USE_CYCLES(shift<<CYC_SHIFT);\r
2221\r
2222 if(shift < 32)\r
2223 {\r
2224 *r_dst = res;\r
2225 FLAG_X = FLAG_C = (src >> (32 - shift)) << 8;\r
2226 FLAG_N = NFLAG_32(res);\r
2227 FLAG_Z = res;\r
2228 src &= m68ki_shift_32_table[shift + 1];\r
2229 FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7;\r
2230 return;\r
2231 }\r
2232\r
2233 *r_dst = 0;\r
2234 FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8;\r
2235 FLAG_N = NFLAG_CLEAR;\r
2236 FLAG_Z = ZFLAG_SET;\r
2237 FLAG_V = (!(src == 0))<<7;\r
2238 return;\r
2239 }\r
2240\r
2241 FLAG_C = CFLAG_CLEAR;\r
2242 FLAG_N = NFLAG_32(src);\r
2243 FLAG_Z = src;\r
2244 FLAG_V = VFLAG_CLEAR;\r
2245}\r
2246\r
2247\r
2248M68KMAKE_OP(asl, 16, ., .)\r
2249{\r
2250 uint ea = M68KMAKE_GET_EA_AY_16;\r
2251 uint src = m68ki_read_16(ea);\r
2252 uint res = MASK_OUT_ABOVE_16(src << 1);\r
2253\r
2254 m68ki_write_16(ea, res);\r
2255\r
2256 FLAG_N = NFLAG_16(res);\r
2257 FLAG_Z = res;\r
2258 FLAG_X = FLAG_C = src >> 7;\r
2259 src &= 0xc000;\r
2260 FLAG_V = (!(src == 0 || src == 0xc000))<<7;\r
2261}\r
2262\r
2263\r
2264M68KMAKE_OP(bcc, 8, ., .)\r
2265{\r
2266 if(M68KMAKE_CC)\r
2267 {\r
2268 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
2269 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));\r
2270 return;\r
2271 }\r
2272 USE_CYCLES(CYC_BCC_NOTAKE_B);\r
2273}\r
2274\r
2275\r
2276M68KMAKE_OP(bcc, 16, ., .)\r
2277{\r
2278 if(M68KMAKE_CC)\r
2279 {\r
2280 uint offset = OPER_I_16();\r
2281 REG_PC -= 2;\r
2282 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
2283 m68ki_branch_16(offset);\r
2284 return;\r
2285 }\r
2286 REG_PC += 2;\r
2287 USE_CYCLES(CYC_BCC_NOTAKE_W);\r
2288}\r
2289\r
2290\r
2291M68KMAKE_OP(bcc, 32, ., .)\r
2292{\r
2293 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2294 {\r
2295 if(M68KMAKE_CC)\r
2296 {\r
2297 uint offset = OPER_I_32();\r
2298 REG_PC -= 4;\r
2299 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
2300 m68ki_branch_32(offset);\r
2301 return;\r
2302 }\r
2303 REG_PC += 4;\r
2304 return;\r
2305 }\r
2306 else\r
2307 {\r
2308 if(M68KMAKE_CC)\r
2309 {\r
2310 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
2311 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));\r
2312 return;\r
2313 }\r
2314 USE_CYCLES(CYC_BCC_NOTAKE_B);\r
2315 }\r
2316}\r
2317\r
2318\r
2319M68KMAKE_OP(bchg, 32, r, d)\r
2320{\r
2321 uint* r_dst = &DY;\r
2322 uint mask = 1 << (DX & 0x1f);\r
2323\r
2324 FLAG_Z = *r_dst & mask;\r
2325 *r_dst ^= mask;\r
2326}\r
2327\r
2328\r
2329M68KMAKE_OP(bchg, 8, r, .)\r
2330{\r
2331 uint ea = M68KMAKE_GET_EA_AY_8;\r
2332 uint src = m68ki_read_8(ea);\r
2333 uint mask = 1 << (DX & 7);\r
2334\r
2335 FLAG_Z = src & mask;\r
2336 m68ki_write_8(ea, src ^ mask);\r
2337}\r
2338\r
2339\r
2340M68KMAKE_OP(bchg, 32, s, d)\r
2341{\r
2342 uint* r_dst = &DY;\r
2343 uint mask = 1 << (OPER_I_8() & 0x1f);\r
2344\r
2345 FLAG_Z = *r_dst & mask;\r
2346 *r_dst ^= mask;\r
2347}\r
2348\r
2349\r
2350M68KMAKE_OP(bchg, 8, s, .)\r
2351{\r
2352 uint mask = 1 << (OPER_I_8() & 7);\r
2353 uint ea = M68KMAKE_GET_EA_AY_8;\r
2354 uint src = m68ki_read_8(ea);\r
2355\r
2356 FLAG_Z = src & mask;\r
2357 m68ki_write_8(ea, src ^ mask);\r
2358}\r
2359\r
2360\r
2361M68KMAKE_OP(bclr, 32, r, d)\r
2362{\r
2363 uint* r_dst = &DY;\r
2364 uint mask = 1 << (DX & 0x1f);\r
2365\r
2366 FLAG_Z = *r_dst & mask;\r
2367 *r_dst &= ~mask;\r
2368}\r
2369\r
2370\r
2371M68KMAKE_OP(bclr, 8, r, .)\r
2372{\r
2373 uint ea = M68KMAKE_GET_EA_AY_8;\r
2374 uint src = m68ki_read_8(ea);\r
2375 uint mask = 1 << (DX & 7);\r
2376\r
2377 FLAG_Z = src & mask;\r
2378 m68ki_write_8(ea, src & ~mask);\r
2379}\r
2380\r
2381\r
2382M68KMAKE_OP(bclr, 32, s, d)\r
2383{\r
2384 uint* r_dst = &DY;\r
2385 uint mask = 1 << (OPER_I_8() & 0x1f);\r
2386\r
2387 FLAG_Z = *r_dst & mask;\r
2388 *r_dst &= ~mask;\r
2389}\r
2390\r
2391\r
2392M68KMAKE_OP(bclr, 8, s, .)\r
2393{\r
2394 uint mask = 1 << (OPER_I_8() & 7);\r
2395 uint ea = M68KMAKE_GET_EA_AY_8;\r
2396 uint src = m68ki_read_8(ea);\r
2397\r
2398 FLAG_Z = src & mask;\r
2399 m68ki_write_8(ea, src & ~mask);\r
2400}\r
2401\r
2402\r
2403M68KMAKE_OP(bfchg, 32, ., d)\r
2404{\r
2405 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2406 {\r
2407 uint word2 = OPER_I_16();\r
2408 uint offset = (word2>>6)&31;\r
2409 uint width = word2;\r
2410 uint* data = &DY;\r
2411 uint64 mask;\r
2412\r
2413\r
2414 if(BIT_B(word2))\r
2415 offset = REG_D[offset&7];\r
2416 if(BIT_5(word2))\r
2417 width = REG_D[width&7];\r
2418\r
2419 offset &= 31;\r
2420 width = ((width-1) & 31) + 1;\r
2421\r
2422 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
2423 mask = ROR_32(mask, offset);\r
2424\r
2425 FLAG_N = NFLAG_32(*data<<offset);\r
2426 FLAG_Z = *data & mask;\r
2427 FLAG_V = VFLAG_CLEAR;\r
2428 FLAG_C = CFLAG_CLEAR;\r
2429\r
2430 *data ^= mask;\r
2431\r
2432 return;\r
2433 }\r
2434 m68ki_exception_illegal();\r
2435}\r
2436\r
2437\r
2438M68KMAKE_OP(bfchg, 32, ., .)\r
2439{\r
2440 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2441 {\r
2442 uint word2 = OPER_I_16();\r
2443 sint offset = (word2>>6)&31;\r
2444 uint width = word2;\r
2445 uint mask_base;\r
2446 uint data_long;\r
2447 uint mask_long;\r
2448 uint data_byte = 0;\r
2449 uint mask_byte = 0;\r
2450 uint ea = M68KMAKE_GET_EA_AY_8;\r
2451\r
2452\r
2453 if(BIT_B(word2))\r
2454 offset = MAKE_INT_32(REG_D[offset&7]);\r
2455 if(BIT_5(word2))\r
2456 width = REG_D[width&7];\r
2457\r
2458 /* Offset is signed so we have to use ugly math =( */\r
2459 ea += offset / 8;\r
2460 offset %= 8;\r
2461 if(offset < 0)\r
2462 {\r
2463 offset += 8;\r
2464 ea--;\r
2465 }\r
2466 width = ((width-1) & 31) + 1;\r
2467\r
2468 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
2469 mask_long = mask_base >> offset;\r
2470\r
2471 data_long = m68ki_read_32(ea);\r
2472 FLAG_N = NFLAG_32(data_long << offset);\r
2473 FLAG_Z = data_long & mask_long;\r
2474 FLAG_V = VFLAG_CLEAR;\r
2475 FLAG_C = CFLAG_CLEAR;\r
2476\r
2477 m68ki_write_32(ea, data_long ^ mask_long);\r
2478\r
2479 if((width + offset) > 32)\r
2480 {\r
2481 mask_byte = MASK_OUT_ABOVE_8(mask_base);\r
2482 data_byte = m68ki_read_8(ea+4);\r
2483 FLAG_Z |= (data_byte & mask_byte);\r
2484 m68ki_write_8(ea+4, data_byte ^ mask_byte);\r
2485 }\r
2486 return;\r
2487 }\r
2488 m68ki_exception_illegal();\r
2489}\r
2490\r
2491\r
2492M68KMAKE_OP(bfclr, 32, ., d)\r
2493{\r
2494 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2495 {\r
2496 uint word2 = OPER_I_16();\r
2497 uint offset = (word2>>6)&31;\r
2498 uint width = word2;\r
2499 uint* data = &DY;\r
2500 uint64 mask;\r
2501\r
2502\r
2503 if(BIT_B(word2))\r
2504 offset = REG_D[offset&7];\r
2505 if(BIT_5(word2))\r
2506 width = REG_D[width&7];\r
2507\r
2508\r
2509 offset &= 31;\r
2510 width = ((width-1) & 31) + 1;\r
2511\r
2512\r
2513 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
2514 mask = ROR_32(mask, offset);\r
2515\r
2516 FLAG_N = NFLAG_32(*data<<offset);\r
2517 FLAG_Z = *data & mask;\r
2518 FLAG_V = VFLAG_CLEAR;\r
2519 FLAG_C = CFLAG_CLEAR;\r
2520\r
2521 *data &= ~mask;\r
2522\r
2523 return;\r
2524 }\r
2525 m68ki_exception_illegal();\r
2526}\r
2527\r
2528\r
2529M68KMAKE_OP(bfclr, 32, ., .)\r
2530{\r
2531 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2532 {\r
2533 uint word2 = OPER_I_16();\r
2534 sint offset = (word2>>6)&31;\r
2535 uint width = word2;\r
2536 uint mask_base;\r
2537 uint data_long;\r
2538 uint mask_long;\r
2539 uint data_byte = 0;\r
2540 uint mask_byte = 0;\r
2541 uint ea = M68KMAKE_GET_EA_AY_8;\r
2542\r
2543\r
2544 if(BIT_B(word2))\r
2545 offset = MAKE_INT_32(REG_D[offset&7]);\r
2546 if(BIT_5(word2))\r
2547 width = REG_D[width&7];\r
2548\r
2549 /* Offset is signed so we have to use ugly math =( */\r
2550 ea += offset / 8;\r
2551 offset %= 8;\r
2552 if(offset < 0)\r
2553 {\r
2554 offset += 8;\r
2555 ea--;\r
2556 }\r
2557 width = ((width-1) & 31) + 1;\r
2558\r
2559 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
2560 mask_long = mask_base >> offset;\r
2561\r
2562 data_long = m68ki_read_32(ea);\r
2563 FLAG_N = NFLAG_32(data_long << offset);\r
2564 FLAG_Z = data_long & mask_long;\r
2565 FLAG_V = VFLAG_CLEAR;\r
2566 FLAG_C = CFLAG_CLEAR;\r
2567\r
2568 m68ki_write_32(ea, data_long & ~mask_long);\r
2569\r
2570 if((width + offset) > 32)\r
2571 {\r
2572 mask_byte = MASK_OUT_ABOVE_8(mask_base);\r
2573 data_byte = m68ki_read_8(ea+4);\r
2574 FLAG_Z |= (data_byte & mask_byte);\r
2575 m68ki_write_8(ea+4, data_byte & ~mask_byte);\r
2576 }\r
2577 return;\r
2578 }\r
2579 m68ki_exception_illegal();\r
2580}\r
2581\r
2582\r
2583M68KMAKE_OP(bfexts, 32, ., d)\r
2584{\r
2585 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2586 {\r
2587 uint word2 = OPER_I_16();\r
2588 uint offset = (word2>>6)&31;\r
2589 uint width = word2;\r
2590 uint64 data = DY;\r
2591\r
2592\r
2593 if(BIT_B(word2))\r
2594 offset = REG_D[offset&7];\r
2595 if(BIT_5(word2))\r
2596 width = REG_D[width&7];\r
2597\r
2598 offset &= 31;\r
2599 width = ((width-1) & 31) + 1;\r
2600\r
2601 data = ROL_32(data, offset);\r
2602 FLAG_N = NFLAG_32(data);\r
2603 data = MAKE_INT_32(data) >> (32 - width);\r
2604\r
2605 FLAG_Z = data;\r
2606 FLAG_V = VFLAG_CLEAR;\r
2607 FLAG_C = CFLAG_CLEAR;\r
2608\r
2609 REG_D[(word2>>12)&7] = data;\r
2610\r
2611 return;\r
2612 }\r
2613 m68ki_exception_illegal();\r
2614}\r
2615\r
2616\r
2617M68KMAKE_OP(bfexts, 32, ., .)\r
2618{\r
2619 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2620 {\r
2621 uint word2 = OPER_I_16();\r
2622 sint offset = (word2>>6)&31;\r
2623 uint width = word2;\r
2624 uint data;\r
2625 uint ea = M68KMAKE_GET_EA_AY_8;\r
2626\r
2627\r
2628 if(BIT_B(word2))\r
2629 offset = MAKE_INT_32(REG_D[offset&7]);\r
2630 if(BIT_5(word2))\r
2631 width = REG_D[width&7];\r
2632\r
2633 /* Offset is signed so we have to use ugly math =( */\r
2634 ea += offset / 8;\r
2635 offset %= 8;\r
2636 if(offset < 0)\r
2637 {\r
2638 offset += 8;\r
2639 ea--;\r
2640 }\r
2641 width = ((width-1) & 31) + 1;\r
2642\r
2643 data = m68ki_read_32(ea);\r
2644\r
2645 data = MASK_OUT_ABOVE_32(data<<offset);\r
2646\r
2647 if((offset+width) > 32)\r
2648 data |= (m68ki_read_8(ea+4) << offset) >> 8;\r
2649\r
2650 FLAG_N = NFLAG_32(data);\r
2651 data = MAKE_INT_32(data) >> (32 - width);\r
2652\r
2653 FLAG_Z = data;\r
2654 FLAG_V = VFLAG_CLEAR;\r
2655 FLAG_C = CFLAG_CLEAR;\r
2656\r
2657 REG_D[(word2 >> 12) & 7] = data;\r
2658\r
2659 return;\r
2660 }\r
2661 m68ki_exception_illegal();\r
2662}\r
2663\r
2664\r
2665M68KMAKE_OP(bfextu, 32, ., d)\r
2666{\r
2667 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2668 {\r
2669 uint word2 = OPER_I_16();\r
2670 uint offset = (word2>>6)&31;\r
2671 uint width = word2;\r
2672 uint64 data = DY;\r
2673\r
2674\r
2675 if(BIT_B(word2))\r
2676 offset = REG_D[offset&7];\r
2677 if(BIT_5(word2))\r
2678 width = REG_D[width&7];\r
2679\r
2680 offset &= 31;\r
2681 width = ((width-1) & 31) + 1;\r
2682\r
2683 data = ROL_32(data, offset);\r
2684 FLAG_N = NFLAG_32(data);\r
2685 data >>= 32 - width;\r
2686\r
2687 FLAG_Z = data;\r
2688 FLAG_V = VFLAG_CLEAR;\r
2689 FLAG_C = CFLAG_CLEAR;\r
2690\r
2691 REG_D[(word2>>12)&7] = data;\r
2692\r
2693 return;\r
2694 }\r
2695 m68ki_exception_illegal();\r
2696}\r
2697\r
2698\r
2699M68KMAKE_OP(bfextu, 32, ., .)\r
2700{\r
2701 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2702 {\r
2703 uint word2 = OPER_I_16();\r
2704 sint offset = (word2>>6)&31;\r
2705 uint width = word2;\r
2706 uint data;\r
2707 uint ea = M68KMAKE_GET_EA_AY_8;\r
2708\r
2709\r
2710 if(BIT_B(word2))\r
2711 offset = MAKE_INT_32(REG_D[offset&7]);\r
2712 if(BIT_5(word2))\r
2713 width = REG_D[width&7];\r
2714\r
2715 /* Offset is signed so we have to use ugly math =( */\r
2716 ea += offset / 8;\r
2717 offset %= 8;\r
2718 if(offset < 0)\r
2719 {\r
2720 offset += 8;\r
2721 ea--;\r
2722 }\r
2723 width = ((width-1) & 31) + 1;\r
2724\r
2725 data = m68ki_read_32(ea);\r
2726 data = MASK_OUT_ABOVE_32(data<<offset);\r
2727\r
2728 if((offset+width) > 32)\r
2729 data |= (m68ki_read_8(ea+4) << offset) >> 8;\r
2730\r
2731 FLAG_N = NFLAG_32(data);\r
2732 data >>= (32 - width);\r
2733\r
2734 FLAG_Z = data;\r
2735 FLAG_V = VFLAG_CLEAR;\r
2736 FLAG_C = CFLAG_CLEAR;\r
2737\r
2738 REG_D[(word2 >> 12) & 7] = data;\r
2739\r
2740 return;\r
2741 }\r
2742 m68ki_exception_illegal();\r
2743}\r
2744\r
2745\r
2746M68KMAKE_OP(bfffo, 32, ., d)\r
2747{\r
2748 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2749 {\r
2750 uint word2 = OPER_I_16();\r
2751 uint offset = (word2>>6)&31;\r
2752 uint width = word2;\r
2753 uint64 data = DY;\r
2754 uint bit;\r
2755\r
2756\r
2757 if(BIT_B(word2))\r
2758 offset = REG_D[offset&7];\r
2759 if(BIT_5(word2))\r
2760 width = REG_D[width&7];\r
2761\r
2762 offset &= 31;\r
2763 width = ((width-1) & 31) + 1;\r
2764\r
2765 data = ROL_32(data, offset);\r
2766 FLAG_N = NFLAG_32(data);\r
2767 data >>= 32 - width;\r
2768\r
2769 FLAG_Z = data;\r
2770 FLAG_V = VFLAG_CLEAR;\r
2771 FLAG_C = CFLAG_CLEAR;\r
2772\r
2773 for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)\r
2774 offset++;\r
2775\r
2776 REG_D[(word2>>12)&7] = offset;\r
2777\r
2778 return;\r
2779 }\r
2780 m68ki_exception_illegal();\r
2781}\r
2782\r
2783\r
2784M68KMAKE_OP(bfffo, 32, ., .)\r
2785{\r
2786 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2787 {\r
2788 uint word2 = OPER_I_16();\r
2789 sint offset = (word2>>6)&31;\r
2790 sint local_offset;\r
2791 uint width = word2;\r
2792 uint data;\r
2793 uint bit;\r
2794 uint ea = M68KMAKE_GET_EA_AY_8;\r
2795\r
2796\r
2797 if(BIT_B(word2))\r
2798 offset = MAKE_INT_32(REG_D[offset&7]);\r
2799 if(BIT_5(word2))\r
2800 width = REG_D[width&7];\r
2801\r
2802 /* Offset is signed so we have to use ugly math =( */\r
2803 ea += offset / 8;\r
2804 local_offset = offset % 8;\r
2805 if(local_offset < 0)\r
2806 {\r
2807 local_offset += 8;\r
2808 ea--;\r
2809 }\r
2810 width = ((width-1) & 31) + 1;\r
2811\r
2812 data = m68ki_read_32(ea);\r
2813 data = MASK_OUT_ABOVE_32(data<<local_offset);\r
2814\r
2815 if((local_offset+width) > 32)\r
2816 data |= (m68ki_read_8(ea+4) << local_offset) >> 8;\r
2817\r
2818 FLAG_N = NFLAG_32(data);\r
2819 data >>= (32 - width);\r
2820\r
2821 FLAG_Z = data;\r
2822 FLAG_V = VFLAG_CLEAR;\r
2823 FLAG_C = CFLAG_CLEAR;\r
2824\r
2825 for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)\r
2826 offset++;\r
2827\r
2828 REG_D[(word2>>12)&7] = offset;\r
2829\r
2830 return;\r
2831 }\r
2832 m68ki_exception_illegal();\r
2833}\r
2834\r
2835\r
2836M68KMAKE_OP(bfins, 32, ., d)\r
2837{\r
2838 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2839 {\r
2840 uint word2 = OPER_I_16();\r
2841 uint offset = (word2>>6)&31;\r
2842 uint width = word2;\r
2843 uint* data = &DY;\r
2844 uint64 mask;\r
2845 uint64 insert = REG_D[(word2>>12)&7];\r
2846\r
2847\r
2848 if(BIT_B(word2))\r
2849 offset = REG_D[offset&7];\r
2850 if(BIT_5(word2))\r
2851 width = REG_D[width&7];\r
2852\r
2853\r
2854 offset &= 31;\r
2855 width = ((width-1) & 31) + 1;\r
2856\r
2857\r
2858 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
2859 mask = ROR_32(mask, offset);\r
2860\r
2861 insert = MASK_OUT_ABOVE_32(insert << (32 - width));\r
2862 FLAG_N = NFLAG_32(insert);\r
2863 FLAG_Z = insert;\r
2864 insert = ROR_32(insert, offset);\r
2865\r
2866 FLAG_V = VFLAG_CLEAR;\r
2867 FLAG_C = CFLAG_CLEAR;\r
2868\r
2869 *data &= ~mask;\r
2870 *data |= insert;\r
2871\r
2872 return;\r
2873 }\r
2874 m68ki_exception_illegal();\r
2875}\r
2876\r
2877\r
2878M68KMAKE_OP(bfins, 32, ., .)\r
2879{\r
2880 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2881 {\r
2882 uint word2 = OPER_I_16();\r
2883 sint offset = (word2>>6)&31;\r
2884 uint width = word2;\r
2885 uint insert_base = REG_D[(word2>>12)&7];\r
2886 uint insert_long;\r
2887 uint insert_byte;\r
2888 uint mask_base;\r
2889 uint data_long;\r
2890 uint mask_long;\r
2891 uint data_byte = 0;\r
2892 uint mask_byte = 0;\r
2893 uint ea = M68KMAKE_GET_EA_AY_8;\r
2894\r
2895\r
2896 if(BIT_B(word2))\r
2897 offset = MAKE_INT_32(REG_D[offset&7]);\r
2898 if(BIT_5(word2))\r
2899 width = REG_D[width&7];\r
2900\r
2901 /* Offset is signed so we have to use ugly math =( */\r
2902 ea += offset / 8;\r
2903 offset %= 8;\r
2904 if(offset < 0)\r
2905 {\r
2906 offset += 8;\r
2907 ea--;\r
2908 }\r
2909 width = ((width-1) & 31) + 1;\r
2910\r
2911 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
2912 mask_long = mask_base >> offset;\r
2913\r
2914 insert_base = MASK_OUT_ABOVE_32(insert_base << (32 - width));\r
2915 FLAG_N = NFLAG_32(insert_base);\r
2916 FLAG_Z = insert_base;\r
2917 insert_long = insert_base >> offset;\r
2918\r
2919 data_long = m68ki_read_32(ea);\r
2920 FLAG_V = VFLAG_CLEAR;\r
2921 FLAG_C = CFLAG_CLEAR;\r
2922\r
2923 m68ki_write_32(ea, (data_long & ~mask_long) | insert_long);\r
2924\r
2925 if((width + offset) > 32)\r
2926 {\r
2927 mask_byte = MASK_OUT_ABOVE_8(mask_base);\r
2928 insert_byte = MASK_OUT_ABOVE_8(insert_base);\r
2929 data_byte = m68ki_read_8(ea+4);\r
2930 FLAG_Z |= (data_byte & mask_byte);\r
2931 m68ki_write_8(ea+4, (data_byte & ~mask_byte) | insert_byte);\r
2932 }\r
2933 return;\r
2934 }\r
2935 m68ki_exception_illegal();\r
2936}\r
2937\r
2938\r
2939M68KMAKE_OP(bfset, 32, ., d)\r
2940{\r
2941 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2942 {\r
2943 uint word2 = OPER_I_16();\r
2944 uint offset = (word2>>6)&31;\r
2945 uint width = word2;\r
2946 uint* data = &DY;\r
2947 uint64 mask;\r
2948\r
2949\r
2950 if(BIT_B(word2))\r
2951 offset = REG_D[offset&7];\r
2952 if(BIT_5(word2))\r
2953 width = REG_D[width&7];\r
2954\r
2955\r
2956 offset &= 31;\r
2957 width = ((width-1) & 31) + 1;\r
2958\r
2959\r
2960 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
2961 mask = ROR_32(mask, offset);\r
2962\r
2963 FLAG_N = NFLAG_32(*data<<offset);\r
2964 FLAG_Z = *data & mask;\r
2965 FLAG_V = VFLAG_CLEAR;\r
2966 FLAG_C = CFLAG_CLEAR;\r
2967\r
2968 *data |= mask;\r
2969\r
2970 return;\r
2971 }\r
2972 m68ki_exception_illegal();\r
2973}\r
2974\r
2975\r
2976M68KMAKE_OP(bfset, 32, ., .)\r
2977{\r
2978 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2979 {\r
2980 uint word2 = OPER_I_16();\r
2981 sint offset = (word2>>6)&31;\r
2982 uint width = word2;\r
2983 uint mask_base;\r
2984 uint data_long;\r
2985 uint mask_long;\r
2986 uint data_byte = 0;\r
2987 uint mask_byte = 0;\r
2988 uint ea = M68KMAKE_GET_EA_AY_8;\r
2989\r
2990\r
2991 if(BIT_B(word2))\r
2992 offset = MAKE_INT_32(REG_D[offset&7]);\r
2993 if(BIT_5(word2))\r
2994 width = REG_D[width&7];\r
2995\r
2996 /* Offset is signed so we have to use ugly math =( */\r
2997 ea += offset / 8;\r
2998 offset %= 8;\r
2999 if(offset < 0)\r
3000 {\r
3001 offset += 8;\r
3002 ea--;\r
3003 }\r
3004 width = ((width-1) & 31) + 1;\r
3005\r
3006\r
3007 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
3008 mask_long = mask_base >> offset;\r
3009\r
3010 data_long = m68ki_read_32(ea);\r
3011 FLAG_N = NFLAG_32(data_long << offset);\r
3012 FLAG_Z = data_long & mask_long;\r
3013 FLAG_V = VFLAG_CLEAR;\r
3014 FLAG_C = CFLAG_CLEAR;\r
3015\r
3016 m68ki_write_32(ea, data_long | mask_long);\r
3017\r
3018 if((width + offset) > 32)\r
3019 {\r
3020 mask_byte = MASK_OUT_ABOVE_8(mask_base);\r
3021 data_byte = m68ki_read_8(ea+4);\r
3022 FLAG_Z |= (data_byte & mask_byte);\r
3023 m68ki_write_8(ea+4, data_byte | mask_byte);\r
3024 }\r
3025 return;\r
3026 }\r
3027 m68ki_exception_illegal();\r
3028}\r
3029\r
3030\r
3031M68KMAKE_OP(bftst, 32, ., d)\r
3032{\r
3033 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3034 {\r
3035 uint word2 = OPER_I_16();\r
3036 uint offset = (word2>>6)&31;\r
3037 uint width = word2;\r
3038 uint* data = &DY;\r
3039 uint64 mask;\r
3040\r
3041\r
3042 if(BIT_B(word2))\r
3043 offset = REG_D[offset&7];\r
3044 if(BIT_5(word2))\r
3045 width = REG_D[width&7];\r
3046\r
3047\r
3048 offset &= 31;\r
3049 width = ((width-1) & 31) + 1;\r
3050\r
3051\r
3052 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
3053 mask = ROR_32(mask, offset);\r
3054\r
3055 FLAG_N = NFLAG_32(*data<<offset);\r
3056 FLAG_Z = *data & mask;\r
3057 FLAG_V = VFLAG_CLEAR;\r
3058 FLAG_C = CFLAG_CLEAR;\r
3059\r
3060 return;\r
3061 }\r
3062 m68ki_exception_illegal();\r
3063}\r
3064\r
3065\r
3066M68KMAKE_OP(bftst, 32, ., .)\r
3067{\r
3068 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3069 {\r
3070 uint word2 = OPER_I_16();\r
3071 sint offset = (word2>>6)&31;\r
3072 uint width = word2;\r
3073 uint mask_base;\r
3074 uint data_long;\r
3075 uint mask_long;\r
3076 uint data_byte = 0;\r
3077 uint mask_byte = 0;\r
3078 uint ea = M68KMAKE_GET_EA_AY_8;\r
3079\r
3080 if(BIT_B(word2))\r
3081 offset = MAKE_INT_32(REG_D[offset&7]);\r
3082 if(BIT_5(word2))\r
3083 width = REG_D[width&7];\r
3084\r
3085 /* Offset is signed so we have to use ugly math =( */\r
3086 ea += offset / 8;\r
3087 offset %= 8;\r
3088 if(offset < 0)\r
3089 {\r
3090 offset += 8;\r
3091 ea--;\r
3092 }\r
3093 width = ((width-1) & 31) + 1;\r
3094\r
3095\r
3096 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
3097 mask_long = mask_base >> offset;\r
3098\r
3099 data_long = m68ki_read_32(ea);\r
3100 FLAG_N = ((data_long & (0x80000000 >> offset))<<offset)>>24;\r
3101 FLAG_Z = data_long & mask_long;\r
3102 FLAG_V = VFLAG_CLEAR;\r
3103 FLAG_C = CFLAG_CLEAR;\r
3104\r
3105 if((width + offset) > 32)\r
3106 {\r
3107 mask_byte = MASK_OUT_ABOVE_8(mask_base);\r
3108 data_byte = m68ki_read_8(ea+4);\r
3109 FLAG_Z |= (data_byte & mask_byte);\r
3110 }\r
3111 return;\r
3112 }\r
3113 m68ki_exception_illegal();\r
3114}\r
3115\r
3116\r
3117M68KMAKE_OP(bkpt, 0, ., .)\r
3118{\r
3119 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))\r
3120 {\r
3121 m68ki_bkpt_ack(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE) ? REG_IR & 7 : 0); /* auto-disable (see m68kcpu.h) */\r
3122 }\r
3123 m68ki_exception_illegal();\r
3124}\r
3125\r
3126\r
3127M68KMAKE_OP(bra, 8, ., .)\r
3128{\r
3129 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3130 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));\r
c6a4c892 3131 if(REG_PC == REG_PPC)\r
3132 USE_ALL_CYCLES();\r
cc68a136 3133}\r
3134\r
3135\r
3136M68KMAKE_OP(bra, 16, ., .)\r
3137{\r
3138 uint offset = OPER_I_16();\r
3139 REG_PC -= 2;\r
3140 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3141 m68ki_branch_16(offset);\r
c6a4c892 3142 if(REG_PC == REG_PPC)\r
3143 USE_ALL_CYCLES();\r
cc68a136 3144}\r
3145\r
3146\r
3147M68KMAKE_OP(bra, 32, ., .)\r
3148{\r
3149 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3150 {\r
3151 uint offset = OPER_I_32();\r
3152 REG_PC -= 4;\r
3153 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3154 m68ki_branch_32(offset);\r
3155 if(REG_PC == REG_PPC)\r
3156 USE_ALL_CYCLES();\r
3157 return;\r
3158 }\r
3159 else\r
3160 {\r
3161 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3162 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));\r
c6a4c892 3163 if(REG_PC == REG_PPC)\r
3164 USE_ALL_CYCLES();\r
cc68a136 3165 }\r
3166}\r
3167\r
3168\r
3169M68KMAKE_OP(bset, 32, r, d)\r
3170{\r
3171 uint* r_dst = &DY;\r
3172 uint mask = 1 << (DX & 0x1f);\r
3173\r
3174 FLAG_Z = *r_dst & mask;\r
3175 *r_dst |= mask;\r
3176}\r
3177\r
3178\r
3179M68KMAKE_OP(bset, 8, r, .)\r
3180{\r
3181 uint ea = M68KMAKE_GET_EA_AY_8;\r
3182 uint src = m68ki_read_8(ea);\r
3183 uint mask = 1 << (DX & 7);\r
3184\r
3185 FLAG_Z = src & mask;\r
3186 m68ki_write_8(ea, src | mask);\r
3187}\r
3188\r
3189\r
3190M68KMAKE_OP(bset, 32, s, d)\r
3191{\r
3192 uint* r_dst = &DY;\r
3193 uint mask = 1 << (OPER_I_8() & 0x1f);\r
3194\r
3195 FLAG_Z = *r_dst & mask;\r
3196 *r_dst |= mask;\r
3197}\r
3198\r
3199\r
3200M68KMAKE_OP(bset, 8, s, .)\r
3201{\r
3202 uint mask = 1 << (OPER_I_8() & 7);\r
3203 uint ea = M68KMAKE_GET_EA_AY_8;\r
3204 uint src = m68ki_read_8(ea);\r
3205\r
3206 FLAG_Z = src & mask;\r
3207 m68ki_write_8(ea, src | mask);\r
3208}\r
3209\r
3210\r
3211M68KMAKE_OP(bsr, 8, ., .)\r
3212{\r
3213 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3214 m68ki_push_32(REG_PC);\r
3215 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));\r
3216}\r
3217\r
3218\r
3219M68KMAKE_OP(bsr, 16, ., .)\r
3220{\r
3221 uint offset = OPER_I_16();\r
3222 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3223 m68ki_push_32(REG_PC);\r
3224 REG_PC -= 2;\r
3225 m68ki_branch_16(offset);\r
3226}\r
3227\r
3228\r
3229M68KMAKE_OP(bsr, 32, ., .)\r
3230{\r
3231 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3232 {\r
3233 uint offset = OPER_I_32();\r
3234 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3235 m68ki_push_32(REG_PC);\r
3236 REG_PC -= 4;\r
3237 m68ki_branch_32(offset);\r
3238 return;\r
3239 }\r
3240 else\r
3241 {\r
3242 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3243 m68ki_push_32(REG_PC);\r
3244 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));\r
3245 }\r
3246}\r
3247\r
3248\r
3249M68KMAKE_OP(btst, 32, r, d)\r
3250{\r
3251 FLAG_Z = DY & (1 << (DX & 0x1f));\r
3252}\r
3253\r
3254\r
3255M68KMAKE_OP(btst, 8, r, .)\r
3256{\r
3257 FLAG_Z = M68KMAKE_GET_OPER_AY_8 & (1 << (DX & 7));\r
3258}\r
3259\r
3260\r
3261M68KMAKE_OP(btst, 32, s, d)\r
3262{\r
3263 FLAG_Z = DY & (1 << (OPER_I_8() & 0x1f));\r
3264}\r
3265\r
3266\r
3267M68KMAKE_OP(btst, 8, s, .)\r
3268{\r
3269 uint bit = OPER_I_8() & 7;\r
3270\r
3271 FLAG_Z = M68KMAKE_GET_OPER_AY_8 & (1 << bit);\r
3272}\r
3273\r
3274\r
3275M68KMAKE_OP(callm, 32, ., .)\r
3276{\r
3277 /* note: watch out for pcrelative modes */\r
3278 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))\r
3279 {\r
3280 uint ea = M68KMAKE_GET_EA_AY_32;\r
3281\r
3282 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3283 REG_PC += 2;\r
3284(void)ea; /* just to avoid an 'unused variable' warning */\r
3285 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",\r
3286 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,\r
3287 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));\r
3288 return;\r
3289 }\r
3290 m68ki_exception_illegal();\r
3291}\r
3292\r
3293\r
3294M68KMAKE_OP(cas, 8, ., .)\r
3295{\r
3296 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3297 {\r
3298 uint word2 = OPER_I_16();\r
3299 uint ea = M68KMAKE_GET_EA_AY_8;\r
3300 uint dest = m68ki_read_8(ea);\r
3301 uint* compare = &REG_D[word2 & 7];\r
3302 uint res = dest - MASK_OUT_ABOVE_8(*compare);\r
3303\r
3304 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3305 FLAG_N = NFLAG_8(res);\r
3306 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
3307 FLAG_V = VFLAG_SUB_8(*compare, dest, res);\r
3308 FLAG_C = CFLAG_8(res);\r
3309\r
3310 if(COND_NE())\r
3311 *compare = MASK_OUT_BELOW_8(*compare) | dest;\r
3312 else\r
3313 {\r
3314 USE_CYCLES(3);\r
3315 m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7]));\r
3316 }\r
3317 return;\r
3318 }\r
3319 m68ki_exception_illegal();\r
3320}\r
3321\r
3322\r
3323M68KMAKE_OP(cas, 16, ., .)\r
3324{\r
3325 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3326 {\r
3327 uint word2 = OPER_I_16();\r
3328 uint ea = M68KMAKE_GET_EA_AY_16;\r
3329 uint dest = m68ki_read_16(ea);\r
3330 uint* compare = &REG_D[word2 & 7];\r
3331 uint res = dest - MASK_OUT_ABOVE_16(*compare);\r
3332\r
3333 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3334 FLAG_N = NFLAG_16(res);\r
3335 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
3336 FLAG_V = VFLAG_SUB_16(*compare, dest, res);\r
3337 FLAG_C = CFLAG_16(res);\r
3338\r
3339 if(COND_NE())\r
3340 *compare = MASK_OUT_BELOW_16(*compare) | dest;\r
3341 else\r
3342 {\r
3343 USE_CYCLES(3);\r
3344 m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7]));\r
3345 }\r
3346 return;\r
3347 }\r
3348 m68ki_exception_illegal();\r
3349}\r
3350\r
3351\r
3352M68KMAKE_OP(cas, 32, ., .)\r
3353{\r
3354 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3355 {\r
3356 uint word2 = OPER_I_16();\r
3357 uint ea = M68KMAKE_GET_EA_AY_32;\r
3358 uint dest = m68ki_read_32(ea);\r
3359 uint* compare = &REG_D[word2 & 7];\r
3360 uint res = dest - *compare;\r
3361\r
3362 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3363 FLAG_N = NFLAG_32(res);\r
3364 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
3365 FLAG_V = VFLAG_SUB_32(*compare, dest, res);\r
3366 FLAG_C = CFLAG_SUB_32(*compare, dest, res);\r
3367\r
3368 if(COND_NE())\r
3369 *compare = dest;\r
3370 else\r
3371 {\r
3372 USE_CYCLES(3);\r
3373 m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]);\r
3374 }\r
3375 return;\r
3376 }\r
3377 m68ki_exception_illegal();\r
3378}\r
3379\r
3380\r
3381M68KMAKE_OP(cas2, 16, ., .)\r
3382{\r
3383 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3384 {\r
3385 uint word2 = OPER_I_32();\r
3386 uint* compare1 = &REG_D[(word2 >> 16) & 7];\r
3387 uint ea1 = REG_DA[(word2 >> 28) & 15];\r
3388 uint dest1 = m68ki_read_16(ea1);\r
3389 uint res1 = dest1 - MASK_OUT_ABOVE_16(*compare1);\r
3390 uint* compare2 = &REG_D[word2 & 7];\r
3391 uint ea2 = REG_DA[(word2 >> 12) & 15];\r
3392 uint dest2 = m68ki_read_16(ea2);\r
3393 uint res2;\r
3394\r
3395 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3396 FLAG_N = NFLAG_16(res1);\r
3397 FLAG_Z = MASK_OUT_ABOVE_16(res1);\r
3398 FLAG_V = VFLAG_SUB_16(*compare1, dest1, res1);\r
3399 FLAG_C = CFLAG_16(res1);\r
3400\r
3401 if(COND_EQ())\r
3402 {\r
3403 res2 = dest2 - MASK_OUT_ABOVE_16(*compare2);\r
3404\r
3405 FLAG_N = NFLAG_16(res2);\r
3406 FLAG_Z = MASK_OUT_ABOVE_16(res2);\r
3407 FLAG_V = VFLAG_SUB_16(*compare2, dest2, res2);\r
3408 FLAG_C = CFLAG_16(res2);\r
3409\r
3410 if(COND_EQ())\r
3411 {\r
3412 USE_CYCLES(3);\r
3413 m68ki_write_16(ea1, REG_D[(word2 >> 22) & 7]);\r
3414 m68ki_write_16(ea2, REG_D[(word2 >> 6) & 7]);\r
3415 return;\r
3416 }\r
3417 }\r
3418 *compare1 = BIT_1F(word2) ? MAKE_INT_16(dest1) : MASK_OUT_BELOW_16(*compare1) | dest1;\r
3419 *compare2 = BIT_F(word2) ? MAKE_INT_16(dest2) : MASK_OUT_BELOW_16(*compare2) | dest2;\r
3420 return;\r
3421 }\r
3422 m68ki_exception_illegal();\r
3423}\r
3424\r
3425\r
3426M68KMAKE_OP(cas2, 32, ., .)\r
3427{\r
3428 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3429 {\r
3430 uint word2 = OPER_I_32();\r
3431 uint* compare1 = &REG_D[(word2 >> 16) & 7];\r
3432 uint ea1 = REG_DA[(word2 >> 28) & 15];\r
3433 uint dest1 = m68ki_read_32(ea1);\r
3434 uint res1 = dest1 - *compare1;\r
3435 uint* compare2 = &REG_D[word2 & 7];\r
3436 uint ea2 = REG_DA[(word2 >> 12) & 15];\r
3437 uint dest2 = m68ki_read_32(ea2);\r
3438 uint res2;\r
3439\r
3440 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3441 FLAG_N = NFLAG_32(res1);\r
3442 FLAG_Z = MASK_OUT_ABOVE_32(res1);\r
3443 FLAG_V = VFLAG_SUB_32(*compare1, dest1, res1);\r
3444 FLAG_C = CFLAG_SUB_32(*compare1, dest1, res1);\r
3445\r
3446 if(COND_EQ())\r
3447 {\r
3448 res2 = dest2 - *compare2;\r
3449\r
3450 FLAG_N = NFLAG_32(res2);\r
3451 FLAG_Z = MASK_OUT_ABOVE_32(res2);\r
3452 FLAG_V = VFLAG_SUB_32(*compare2, dest2, res2);\r
3453 FLAG_C = CFLAG_SUB_32(*compare2, dest2, res2);\r
3454\r
3455 if(COND_EQ())\r
3456 {\r
3457 USE_CYCLES(3);\r
3458 m68ki_write_32(ea1, REG_D[(word2 >> 22) & 7]);\r
3459 m68ki_write_32(ea2, REG_D[(word2 >> 6) & 7]);\r
3460 return;\r
3461 }\r
3462 }\r
3463 *compare1 = dest1;\r
3464 *compare2 = dest2;\r
3465 return;\r
3466 }\r
3467 m68ki_exception_illegal();\r
3468}\r
3469\r
3470\r
3471M68KMAKE_OP(chk, 16, ., d)\r
3472{\r
3473 sint src = MAKE_INT_16(DX);\r
3474 sint bound = MAKE_INT_16(DY);\r
3475\r
3476 FLAG_Z = ZFLAG_16(src); /* Undocumented */\r
3477 FLAG_V = VFLAG_CLEAR; /* Undocumented */\r
3478 FLAG_C = CFLAG_CLEAR; /* Undocumented */\r
3479\r
3480 if(src >= 0 && src <= bound)\r
3481 {\r
3482 return;\r
3483 }\r
3484 FLAG_N = (src < 0)<<7;\r
3485 m68ki_exception_trap(EXCEPTION_CHK);\r
3486}\r
3487\r
3488\r
3489M68KMAKE_OP(chk, 16, ., .)\r
3490{\r
3491 sint src = MAKE_INT_16(DX);\r
3492 sint bound = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);\r
3493\r
3494 FLAG_Z = ZFLAG_16(src); /* Undocumented */\r
3495 FLAG_V = VFLAG_CLEAR; /* Undocumented */\r
3496 FLAG_C = CFLAG_CLEAR; /* Undocumented */\r
3497\r
3498 if(src >= 0 && src <= bound)\r
3499 {\r
3500 return;\r
3501 }\r
3502 FLAG_N = (src < 0)<<7;\r
3503 m68ki_exception_trap(EXCEPTION_CHK);\r
3504}\r
3505\r
3506\r
3507M68KMAKE_OP(chk, 32, ., d)\r
3508{\r
3509 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3510 {\r
3511 sint src = MAKE_INT_32(DX);\r
3512 sint bound = MAKE_INT_32(DY);\r
3513\r
3514 FLAG_Z = ZFLAG_32(src); /* Undocumented */\r
3515 FLAG_V = VFLAG_CLEAR; /* Undocumented */\r
3516 FLAG_C = CFLAG_CLEAR; /* Undocumented */\r
3517\r
3518 if(src >= 0 && src <= bound)\r
3519 {\r
3520 return;\r
3521 }\r
3522 FLAG_N = (src < 0)<<7;\r
3523 m68ki_exception_trap(EXCEPTION_CHK);\r
3524 return;\r
3525 }\r
3526 m68ki_exception_illegal();\r
3527}\r
3528\r
3529\r
3530M68KMAKE_OP(chk, 32, ., .)\r
3531{\r
3532 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3533 {\r
3534 sint src = MAKE_INT_32(DX);\r
3535 sint bound = MAKE_INT_32(M68KMAKE_GET_OPER_AY_32);\r
3536\r
3537 FLAG_Z = ZFLAG_32(src); /* Undocumented */\r
3538 FLAG_V = VFLAG_CLEAR; /* Undocumented */\r
3539 FLAG_C = CFLAG_CLEAR; /* Undocumented */\r
3540\r
3541 if(src >= 0 && src <= bound)\r
3542 {\r
3543 return;\r
3544 }\r
3545 FLAG_N = (src < 0)<<7;\r
3546 m68ki_exception_trap(EXCEPTION_CHK);\r
3547 return;\r
3548 }\r
3549 m68ki_exception_illegal();\r
3550}\r
3551\r
3552\r
3553M68KMAKE_OP(chk2cmp2, 8, ., pcdi)\r
3554{\r
3555 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3556 {\r
3557 uint word2 = OPER_I_16();\r
3558 uint compare = REG_DA[(word2 >> 12) & 15]&0xff;\r
3559 uint ea = EA_PCDI_8();\r
3560 uint lower_bound = m68ki_read_pcrel_8(ea);\r
3561 uint upper_bound = m68ki_read_pcrel_8(ea + 1);\r
3562\r
3563 if(!BIT_F(word2))\r
3564 FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound);\r
3565 else\r
3566 FLAG_C = compare - lower_bound;\r
3567 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));\r
3568 if(COND_CS())\r
3569 {\r
3570 if(BIT_B(word2))\r
3571 m68ki_exception_trap(EXCEPTION_CHK);\r
3572 return;\r
3573 }\r
3574\r
3575 FLAG_C = upper_bound - compare;\r
3576 if(COND_CS() && BIT_B(word2))\r
3577 m68ki_exception_trap(EXCEPTION_CHK);\r
3578 return;\r
3579 }\r
3580 m68ki_exception_illegal();\r
3581}\r
3582\r
3583\r
3584M68KMAKE_OP(chk2cmp2, 8, ., pcix)\r
3585{\r
3586 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3587 {\r
3588 uint word2 = OPER_I_16();\r
3589 uint compare = REG_DA[(word2 >> 12) & 15]&0xff;\r
3590 uint ea = EA_PCIX_8();\r
3591 uint lower_bound = m68ki_read_pcrel_8(ea);\r
3592 uint upper_bound = m68ki_read_pcrel_8(ea + 1);\r
3593\r
3594 if(!BIT_F(word2))\r
3595 FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound);\r
3596 else\r
3597 FLAG_C = compare - lower_bound;\r
3598 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));\r
3599 if(COND_CS())\r
3600 {\r
3601 if(BIT_B(word2))\r
3602 m68ki_exception_trap(EXCEPTION_CHK);\r
3603 return;\r
3604 }\r
3605\r
3606 FLAG_C = upper_bound - compare;\r
3607 if(COND_CS() && BIT_B(word2))\r
3608 m68ki_exception_trap(EXCEPTION_CHK);\r
3609 return;\r
3610 }\r
3611 m68ki_exception_illegal();\r
3612}\r
3613\r
3614\r
3615M68KMAKE_OP(chk2cmp2, 8, ., .)\r
3616{\r
3617 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3618 {\r
3619 uint word2 = OPER_I_16();\r
3620 uint compare = REG_DA[(word2 >> 12) & 15]&0xff;\r
3621 uint ea = M68KMAKE_GET_EA_AY_8;\r
3622 uint lower_bound = m68ki_read_8(ea);\r
3623 uint upper_bound = m68ki_read_8(ea + 1);\r
3624\r
3625 if(!BIT_F(word2))\r
3626 FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound);\r
3627 else\r
3628 FLAG_C = compare - lower_bound;\r
3629 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));\r
3630 if(COND_CS())\r
3631 {\r
3632 if(BIT_B(word2))\r
3633 m68ki_exception_trap(EXCEPTION_CHK);\r
3634 return;\r
3635 }\r
3636\r
3637 FLAG_C = upper_bound - compare;\r
3638 if(COND_CS() && BIT_B(word2))\r
3639 m68ki_exception_trap(EXCEPTION_CHK);\r
3640 return;\r
3641 }\r
3642 m68ki_exception_illegal();\r
3643}\r
3644\r
3645\r
3646M68KMAKE_OP(chk2cmp2, 16, ., pcdi)\r
3647{\r
3648 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3649 {\r
3650 uint word2 = OPER_I_16();\r
3651 uint compare = REG_DA[(word2 >> 12) & 15]&0xffff;\r
3652 uint ea = EA_PCDI_16();\r
3653 uint lower_bound = m68ki_read_pcrel_16(ea);\r
3654 uint upper_bound = m68ki_read_pcrel_16(ea + 2);\r
3655\r
3656 if(!BIT_F(word2))\r
3657 FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound);\r
3658 else\r
3659 FLAG_C = compare - lower_bound;\r
3660 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));\r
3661 FLAG_C = CFLAG_16(FLAG_C);\r
3662 if(COND_CS())\r
3663 {\r
3664 if(BIT_B(word2))\r
3665 m68ki_exception_trap(EXCEPTION_CHK);\r
3666 return;\r
3667 }\r
3668\r
3669 if(!BIT_F(word2))\r
3670 FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare);\r
3671 else\r
3672 FLAG_C = upper_bound - compare;\r
3673 FLAG_C = CFLAG_16(FLAG_C);\r
3674 if(COND_CS() && BIT_B(word2))\r
3675 m68ki_exception_trap(EXCEPTION_CHK);\r
3676 return;\r
3677 }\r
3678 m68ki_exception_illegal();\r
3679}\r
3680\r
3681\r
3682M68KMAKE_OP(chk2cmp2, 16, ., pcix)\r
3683{\r
3684 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3685 {\r
3686 uint word2 = OPER_I_16();\r
3687 uint compare = REG_DA[(word2 >> 12) & 15]&0xffff;\r
3688 uint ea = EA_PCIX_16();\r
3689 uint lower_bound = m68ki_read_pcrel_16(ea);\r
3690 uint upper_bound = m68ki_read_pcrel_16(ea + 2);\r
3691\r
3692 if(!BIT_F(word2))\r
3693 FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound);\r
3694 else\r
3695 FLAG_C = compare - lower_bound;\r
3696 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));\r
3697 FLAG_C = CFLAG_16(FLAG_C);\r
3698 if(COND_CS())\r
3699 {\r
3700 if(BIT_B(word2))\r
3701 m68ki_exception_trap(EXCEPTION_CHK);\r
3702 return;\r
3703 }\r
3704\r
3705 if(!BIT_F(word2))\r
3706 FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare);\r
3707 else\r
3708 FLAG_C = upper_bound - compare;\r
3709 FLAG_C = CFLAG_16(FLAG_C);\r
3710 if(COND_CS() && BIT_B(word2))\r
3711 m68ki_exception_trap(EXCEPTION_CHK);\r
3712 return;\r
3713 }\r
3714 m68ki_exception_illegal();\r
3715}\r
3716\r
3717\r
3718M68KMAKE_OP(chk2cmp2, 16, ., .)\r
3719{\r
3720 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3721 {\r
3722 uint word2 = OPER_I_16();\r
3723 uint compare = REG_DA[(word2 >> 12) & 15]&0xffff;\r
3724 uint ea = M68KMAKE_GET_EA_AY_16;\r
3725 uint lower_bound = m68ki_read_16(ea);\r
3726 uint upper_bound = m68ki_read_16(ea + 2);\r
3727\r
3728 if(!BIT_F(word2))\r
3729 FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound);\r
3730 else\r
3731 FLAG_C = compare - lower_bound;\r
3732\r
3733 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));\r
3734 FLAG_C = CFLAG_16(FLAG_C);\r
3735 if(COND_CS())\r
3736 {\r
3737 if(BIT_B(word2))\r
3738 m68ki_exception_trap(EXCEPTION_CHK);\r
3739 return;\r
3740 }\r
3741 if(!BIT_F(word2))\r
3742 FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare);\r
3743 else\r
3744 FLAG_C = upper_bound - compare;\r
3745\r
3746 FLAG_C = CFLAG_16(FLAG_C);\r
3747 if(COND_CS() && BIT_B(word2))\r
3748 m68ki_exception_trap(EXCEPTION_CHK);\r
3749 return;\r
3750 }\r
3751 m68ki_exception_illegal();\r
3752}\r
3753\r
3754\r
3755M68KMAKE_OP(chk2cmp2, 32, ., pcdi)\r
3756{\r
3757 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3758 {\r
3759 uint word2 = OPER_I_16();\r
3760 uint compare = REG_DA[(word2 >> 12) & 15];\r
3761 uint ea = EA_PCDI_32();\r
3762 uint lower_bound = m68ki_read_pcrel_32(ea);\r
3763 uint upper_bound = m68ki_read_pcrel_32(ea + 4);\r
3764\r
3765 FLAG_C = compare - lower_bound;\r
3766 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));\r
3767 FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);\r
3768 if(COND_CS())\r
3769 {\r
3770 if(BIT_B(word2))\r
3771 m68ki_exception_trap(EXCEPTION_CHK);\r
3772 return;\r
3773 }\r
3774\r
3775 FLAG_C = upper_bound - compare;\r
3776 FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);\r
3777 if(COND_CS() && BIT_B(word2))\r
3778 m68ki_exception_trap(EXCEPTION_CHK);\r
3779 return;\r
3780 }\r
3781 m68ki_exception_illegal();\r
3782}\r
3783\r
3784\r
3785M68KMAKE_OP(chk2cmp2, 32, ., pcix)\r
3786{\r
3787 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3788 {\r
3789 uint word2 = OPER_I_16();\r
3790 uint compare = REG_DA[(word2 >> 12) & 15];\r
3791 uint ea = EA_PCIX_32();\r
3792 uint lower_bound = m68ki_read_pcrel_32(ea);\r
3793 uint upper_bound = m68ki_read_pcrel_32(ea + 4);\r
3794\r
3795 FLAG_C = compare - lower_bound;\r
3796 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));\r
3797 FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);\r
3798 if(COND_CS())\r
3799 {\r
3800 if(BIT_B(word2))\r
3801 m68ki_exception_trap(EXCEPTION_CHK);\r
3802 return;\r
3803 }\r
3804\r
3805 FLAG_C = upper_bound - compare;\r
3806 FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);\r
3807 if(COND_CS() && BIT_B(word2))\r
3808 m68ki_exception_trap(EXCEPTION_CHK);\r
3809 return;\r
3810 }\r
3811 m68ki_exception_illegal();\r
3812}\r
3813\r
3814\r
3815M68KMAKE_OP(chk2cmp2, 32, ., .)\r
3816{\r
3817 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3818 {\r
3819 uint word2 = OPER_I_16();\r
3820 uint compare = REG_DA[(word2 >> 12) & 15];\r
3821 uint ea = M68KMAKE_GET_EA_AY_32;\r
3822 uint lower_bound = m68ki_read_32(ea);\r
3823 uint upper_bound = m68ki_read_32(ea + 4);\r
3824\r
3825 FLAG_C = compare - lower_bound;\r
3826 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));\r
3827 FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);\r
3828 if(COND_CS())\r
3829 {\r
3830 if(BIT_B(word2))\r
3831 m68ki_exception_trap(EXCEPTION_CHK);\r
3832 return;\r
3833 }\r
3834\r
3835 FLAG_C = upper_bound - compare;\r
3836 FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);\r
3837 if(COND_CS() && BIT_B(word2))\r
3838 m68ki_exception_trap(EXCEPTION_CHK);\r
3839 return;\r
3840 }\r
3841 m68ki_exception_illegal();\r
3842}\r
3843\r
3844\r
3845M68KMAKE_OP(clr, 8, ., d)\r
3846{\r
3847 DY &= 0xffffff00;\r
3848\r
3849 FLAG_N = NFLAG_CLEAR;\r
3850 FLAG_V = VFLAG_CLEAR;\r
3851 FLAG_C = CFLAG_CLEAR;\r
3852 FLAG_Z = ZFLAG_SET;\r
3853}\r
3854\r
3855\r
3856M68KMAKE_OP(clr, 8, ., .)\r
3857{\r
3858 m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0);\r
3859\r
3860 FLAG_N = NFLAG_CLEAR;\r
3861 FLAG_V = VFLAG_CLEAR;\r
3862 FLAG_C = CFLAG_CLEAR;\r
3863 FLAG_Z = ZFLAG_SET;\r
3864}\r
3865\r
3866\r
3867M68KMAKE_OP(clr, 16, ., d)\r
3868{\r
3869 DY &= 0xffff0000;\r
3870\r
3871 FLAG_N = NFLAG_CLEAR;\r
3872 FLAG_V = VFLAG_CLEAR;\r
3873 FLAG_C = CFLAG_CLEAR;\r
3874 FLAG_Z = ZFLAG_SET;\r
3875}\r
3876\r
3877\r
3878M68KMAKE_OP(clr, 16, ., .)\r
3879{\r
3880 m68ki_write_16(M68KMAKE_GET_EA_AY_16, 0);\r
3881\r
3882 FLAG_N = NFLAG_CLEAR;\r
3883 FLAG_V = VFLAG_CLEAR;\r
3884 FLAG_C = CFLAG_CLEAR;\r
3885 FLAG_Z = ZFLAG_SET;\r
3886}\r
3887\r
3888\r
3889M68KMAKE_OP(clr, 32, ., d)\r
3890{\r
3891 DY = 0;\r
3892\r
3893 FLAG_N = NFLAG_CLEAR;\r
3894 FLAG_V = VFLAG_CLEAR;\r
3895 FLAG_C = CFLAG_CLEAR;\r
3896 FLAG_Z = ZFLAG_SET;\r
3897}\r
3898\r
3899\r
3900M68KMAKE_OP(clr, 32, ., .)\r
3901{\r
3902 m68ki_write_32(M68KMAKE_GET_EA_AY_32, 0);\r
3903\r
3904 FLAG_N = NFLAG_CLEAR;\r
3905 FLAG_V = VFLAG_CLEAR;\r
3906 FLAG_C = CFLAG_CLEAR;\r
3907 FLAG_Z = ZFLAG_SET;\r
3908}\r
3909\r
3910\r
3911M68KMAKE_OP(cmp, 8, ., d)\r
3912{\r
3913 uint src = MASK_OUT_ABOVE_8(DY);\r
3914 uint dst = MASK_OUT_ABOVE_8(DX);\r
3915 uint res = dst - src;\r
3916\r
3917 FLAG_N = NFLAG_8(res);\r
3918 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
3919 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
3920 FLAG_C = CFLAG_8(res);\r
3921}\r
3922\r
3923\r
3924M68KMAKE_OP(cmp, 8, ., .)\r
3925{\r
3926 uint src = M68KMAKE_GET_OPER_AY_8;\r
3927 uint dst = MASK_OUT_ABOVE_8(DX);\r
3928 uint res = dst - src;\r
3929\r
3930 FLAG_N = NFLAG_8(res);\r
3931 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
3932 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
3933 FLAG_C = CFLAG_8(res);\r
3934}\r
3935\r
3936\r
3937M68KMAKE_OP(cmp, 16, ., d)\r
3938{\r
3939 uint src = MASK_OUT_ABOVE_16(DY);\r
3940 uint dst = MASK_OUT_ABOVE_16(DX);\r
3941 uint res = dst - src;\r
3942\r
3943 FLAG_N = NFLAG_16(res);\r
3944 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
3945 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
3946 FLAG_C = CFLAG_16(res);\r
3947}\r
3948\r
3949\r
3950M68KMAKE_OP(cmp, 16, ., a)\r
3951{\r
3952 uint src = MASK_OUT_ABOVE_16(AY);\r
3953 uint dst = MASK_OUT_ABOVE_16(DX);\r
3954 uint res = dst - src;\r
3955\r
3956 FLAG_N = NFLAG_16(res);\r
3957 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
3958 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
3959 FLAG_C = CFLAG_16(res);\r
3960}\r
3961\r
3962\r
3963M68KMAKE_OP(cmp, 16, ., .)\r
3964{\r
3965 uint src = M68KMAKE_GET_OPER_AY_16;\r
3966 uint dst = MASK_OUT_ABOVE_16(DX);\r
3967 uint res = dst - src;\r
3968\r
3969 FLAG_N = NFLAG_16(res);\r
3970 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
3971 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
3972 FLAG_C = CFLAG_16(res);\r
3973}\r
3974\r
3975\r
3976M68KMAKE_OP(cmp, 32, ., d)\r
3977{\r
3978 uint src = DY;\r
3979 uint dst = DX;\r
3980 uint res = dst - src;\r
3981\r
3982 FLAG_N = NFLAG_32(res);\r
3983 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
3984 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
3985 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
3986}\r
3987\r
3988\r
3989M68KMAKE_OP(cmp, 32, ., a)\r
3990{\r
3991 uint src = AY;\r
3992 uint dst = DX;\r
3993 uint res = dst - src;\r
3994\r
3995 FLAG_N = NFLAG_32(res);\r
3996 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
3997 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
3998 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
3999}\r
4000\r
4001\r
4002M68KMAKE_OP(cmp, 32, ., .)\r
4003{\r
4004 uint src = M68KMAKE_GET_OPER_AY_32;\r
4005 uint dst = DX;\r
4006 uint res = dst - src;\r
4007\r
4008 FLAG_N = NFLAG_32(res);\r
4009 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4010 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4011 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4012}\r
4013\r
4014\r
4015M68KMAKE_OP(cmpa, 16, ., d)\r
4016{\r
4017 uint src = MAKE_INT_16(DY);\r
4018 uint dst = AX;\r
4019 uint res = dst - src;\r
4020\r
4021 FLAG_N = NFLAG_32(res);\r
4022 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4023 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4024 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4025}\r
4026\r
4027\r
4028M68KMAKE_OP(cmpa, 16, ., a)\r
4029{\r
4030 uint src = MAKE_INT_16(AY);\r
4031 uint dst = AX;\r
4032 uint res = dst - src;\r
4033\r
4034 FLAG_N = NFLAG_32(res);\r
4035 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4036 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4037 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4038}\r
4039\r
4040\r
4041M68KMAKE_OP(cmpa, 16, ., .)\r
4042{\r
4043 uint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);\r
4044 uint dst = AX;\r
4045 uint res = dst - src;\r
4046\r
4047 FLAG_N = NFLAG_32(res);\r
4048 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4049 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4050 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4051}\r
4052\r
4053\r
4054M68KMAKE_OP(cmpa, 32, ., d)\r
4055{\r
4056 uint src = DY;\r
4057 uint dst = AX;\r
4058 uint res = dst - src;\r
4059\r
4060 FLAG_N = NFLAG_32(res);\r
4061 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4062 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4063 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4064}\r
4065\r
4066\r
4067M68KMAKE_OP(cmpa, 32, ., a)\r
4068{\r
4069 uint src = AY;\r
4070 uint dst = AX;\r
4071 uint res = dst - src;\r
4072\r
4073 FLAG_N = NFLAG_32(res);\r
4074 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4075 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4076 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4077}\r
4078\r
4079\r
4080M68KMAKE_OP(cmpa, 32, ., .)\r
4081{\r
4082 uint src = M68KMAKE_GET_OPER_AY_32;\r
4083 uint dst = AX;\r
4084 uint res = dst - src;\r
4085\r
4086 FLAG_N = NFLAG_32(res);\r
4087 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4088 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4089 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4090}\r
4091\r
4092\r
4093M68KMAKE_OP(cmpi, 8, ., d)\r
4094{\r
4095 uint src = OPER_I_8();\r
4096 uint dst = MASK_OUT_ABOVE_8(DY);\r
4097 uint res = dst - src;\r
4098\r
4099 FLAG_N = NFLAG_8(res);\r
4100 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
4101 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
4102 FLAG_C = CFLAG_8(res);\r
4103}\r
4104\r
4105\r
4106M68KMAKE_OP(cmpi, 8, ., .)\r
4107{\r
4108 uint src = OPER_I_8();\r
4109 uint dst = M68KMAKE_GET_OPER_AY_8;\r
4110 uint res = dst - src;\r
4111\r
4112 FLAG_N = NFLAG_8(res);\r
4113 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
4114 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
4115 FLAG_C = CFLAG_8(res);\r
4116}\r
4117\r
4118\r
4119M68KMAKE_OP(cmpi, 8, ., pcdi)\r
4120{\r
4121 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4122 {\r
4123 uint src = OPER_I_8();\r
4124 uint dst = OPER_PCDI_8();\r
4125 uint res = dst - src;\r
4126\r
4127 FLAG_N = NFLAG_8(res);\r
4128 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
4129 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
4130 FLAG_C = CFLAG_8(res);\r
4131 return;\r
4132 }\r
4133 m68ki_exception_illegal();\r
4134}\r
4135\r
4136\r
4137M68KMAKE_OP(cmpi, 8, ., pcix)\r
4138{\r
4139 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4140 {\r
4141 uint src = OPER_I_8();\r
4142 uint dst = OPER_PCIX_8();\r
4143 uint res = dst - src;\r
4144\r
4145 FLAG_N = NFLAG_8(res);\r
4146 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
4147 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
4148 FLAG_C = CFLAG_8(res);\r
4149 return;\r
4150 }\r
4151 m68ki_exception_illegal();\r
4152}\r
4153\r
4154\r
4155M68KMAKE_OP(cmpi, 16, ., d)\r
4156{\r
4157 uint src = OPER_I_16();\r
4158 uint dst = MASK_OUT_ABOVE_16(DY);\r
4159 uint res = dst - src;\r
4160\r
4161 FLAG_N = NFLAG_16(res);\r
4162 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
4163 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
4164 FLAG_C = CFLAG_16(res);\r
4165}\r
4166\r
4167\r
4168M68KMAKE_OP(cmpi, 16, ., .)\r
4169{\r
4170 uint src = OPER_I_16();\r
4171 uint dst = M68KMAKE_GET_OPER_AY_16;\r
4172 uint res = dst - src;\r
4173\r
4174 FLAG_N = NFLAG_16(res);\r
4175 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
4176 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
4177 FLAG_C = CFLAG_16(res);\r
4178}\r
4179\r
4180\r
4181M68KMAKE_OP(cmpi, 16, ., pcdi)\r
4182{\r
4183 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4184 {\r
4185 uint src = OPER_I_16();\r
4186 uint dst = OPER_PCDI_16();\r
4187 uint res = dst - src;\r
4188\r
4189 FLAG_N = NFLAG_16(res);\r
4190 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
4191 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
4192 FLAG_C = CFLAG_16(res);\r
4193 return;\r
4194 }\r
4195 m68ki_exception_illegal();\r
4196}\r
4197\r
4198\r
4199M68KMAKE_OP(cmpi, 16, ., pcix)\r
4200{\r
4201 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4202 {\r
4203 uint src = OPER_I_16();\r
4204 uint dst = OPER_PCIX_16();\r
4205 uint res = dst - src;\r
4206\r
4207 FLAG_N = NFLAG_16(res);\r
4208 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
4209 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
4210 FLAG_C = CFLAG_16(res);\r
4211 return;\r
4212 }\r
4213 m68ki_exception_illegal();\r
4214}\r
4215\r
4216\r
4217M68KMAKE_OP(cmpi, 32, ., d)\r
4218{\r
4219 uint src = OPER_I_32();\r
4220 uint dst = DY;\r
4221 uint res = dst - src;\r
4222\r
4223 m68ki_cmpild_callback(src, REG_IR & 7); /* auto-disable (see m68kcpu.h) */\r
4224\r
4225 FLAG_N = NFLAG_32(res);\r
4226 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4227 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4228 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4229}\r
4230\r
4231\r
4232M68KMAKE_OP(cmpi, 32, ., .)\r
4233{\r
4234 uint src = OPER_I_32();\r
4235 uint dst = M68KMAKE_GET_OPER_AY_32;\r
4236 uint res = dst - src;\r
4237\r
4238 FLAG_N = NFLAG_32(res);\r
4239 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4240 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4241 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4242}\r
4243\r
4244\r
4245M68KMAKE_OP(cmpi, 32, ., pcdi)\r
4246{\r
4247 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4248 {\r
4249 uint src = OPER_I_32();\r
4250 uint dst = OPER_PCDI_32();\r
4251 uint res = dst - src;\r
4252\r
4253 FLAG_N = NFLAG_32(res);\r
4254 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4255 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4256 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4257 return;\r
4258 }\r
4259 m68ki_exception_illegal();\r
4260}\r
4261\r
4262\r
4263M68KMAKE_OP(cmpi, 32, ., pcix)\r
4264{\r
4265 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4266 {\r
4267 uint src = OPER_I_32();\r
4268 uint dst = OPER_PCIX_32();\r
4269 uint res = dst - src;\r
4270\r
4271 FLAG_N = NFLAG_32(res);\r
4272 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4273 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4274 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4275 return;\r
4276 }\r
4277 m68ki_exception_illegal();\r
4278}\r
4279\r
4280\r
4281M68KMAKE_OP(cmpm, 8, ., ax7)\r
4282{\r
4283 uint src = OPER_AY_PI_8();\r
4284 uint dst = OPER_A7_PI_8();\r
4285 uint res = dst - src;\r
4286\r
4287 FLAG_N = NFLAG_8(res);\r
4288 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
4289 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
4290 FLAG_C = CFLAG_8(res);\r
4291}\r
4292\r
4293\r
4294M68KMAKE_OP(cmpm, 8, ., ay7)\r
4295{\r
4296 uint src = OPER_A7_PI_8();\r
4297 uint dst = OPER_AX_PI_8();\r
4298 uint res = dst - src;\r
4299\r
4300 FLAG_N = NFLAG_8(res);\r
4301 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
4302 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
4303 FLAG_C = CFLAG_8(res);\r
4304}\r
4305\r
4306\r
4307M68KMAKE_OP(cmpm, 8, ., axy7)\r
4308{\r
4309 uint src = OPER_A7_PI_8();\r
4310 uint dst = OPER_A7_PI_8();\r
4311 uint res = dst - src;\r
4312\r
4313 FLAG_N = NFLAG_8(res);\r
4314 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
4315 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
4316 FLAG_C = CFLAG_8(res);\r
4317}\r
4318\r
4319\r
4320M68KMAKE_OP(cmpm, 8, ., .)\r
4321{\r
4322 uint src = OPER_AY_PI_8();\r
4323 uint dst = OPER_AX_PI_8();\r
4324 uint res = dst - src;\r
4325\r
4326 FLAG_N = NFLAG_8(res);\r
4327 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
4328 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
4329 FLAG_C = CFLAG_8(res);\r
4330}\r
4331\r
4332\r
4333M68KMAKE_OP(cmpm, 16, ., .)\r
4334{\r
4335 uint src = OPER_AY_PI_16();\r
4336 uint dst = OPER_AX_PI_16();\r
4337 uint res = dst - src;\r
4338\r
4339 FLAG_N = NFLAG_16(res);\r
4340 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
4341 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
4342 FLAG_C = CFLAG_16(res);\r
4343}\r
4344\r
4345\r
4346M68KMAKE_OP(cmpm, 32, ., .)\r
4347{\r
4348 uint src = OPER_AY_PI_32();\r
4349 uint dst = OPER_AX_PI_32();\r
4350 uint res = dst - src;\r
4351\r
4352 FLAG_N = NFLAG_32(res);\r
4353 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4354 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4355 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4356}\r
4357\r
4358\r
4359M68KMAKE_OP(cpbcc, 32, ., .)\r
4360{\r
4361 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4362 {\r
4363 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",\r
4364 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,\r
4365 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));\r
4366 return;\r
4367 }\r
4368 m68ki_exception_1111();\r
4369}\r
4370\r
4371\r
4372M68KMAKE_OP(cpdbcc, 32, ., .)\r
4373{\r
4374 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4375 {\r
4376 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",\r
4377 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,\r
4378 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));\r
4379 return;\r
4380 }\r
4381 m68ki_exception_1111();\r
4382}\r
4383\r
4384\r
4385M68KMAKE_OP(cpgen, 32, ., .)\r
4386{\r
4387 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4388 {\r
4389 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",\r
4390 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,\r
4391 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));\r
4392 return;\r
4393 }\r
4394 m68ki_exception_1111();\r
4395}\r
4396\r
4397\r
4398M68KMAKE_OP(cpscc, 32, ., .)\r
4399{\r
4400 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4401 {\r
4402 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",\r
4403 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,\r
4404 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));\r
4405 return;\r
4406 }\r
4407 m68ki_exception_1111();\r
4408}\r
4409\r
4410\r
4411M68KMAKE_OP(cptrapcc, 32, ., .)\r
4412{\r
4413 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4414 {\r
4415 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",\r
4416 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,\r
4417 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));\r
4418 return;\r
4419 }\r
4420 m68ki_exception_1111();\r
4421}\r
4422\r
4423\r
4424M68KMAKE_OP(dbt, 16, ., .)\r
4425{\r
4426 REG_PC += 2;\r
4427}\r
4428\r
4429\r
4430M68KMAKE_OP(dbf, 16, ., .)\r
4431{\r
4432 uint* r_dst = &DY;\r
4433 uint res = MASK_OUT_ABOVE_16(*r_dst - 1);\r
4434\r
4435 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
4436 if(res != 0xffff)\r
4437 {\r
4438 uint offset = OPER_I_16();\r
4439 REG_PC -= 2;\r
4440 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
4441 m68ki_branch_16(offset);\r
4442 USE_CYCLES(CYC_DBCC_F_NOEXP);\r
4443 return;\r
4444 }\r
4445 REG_PC += 2;\r
4446 USE_CYCLES(CYC_DBCC_F_EXP);\r
4447}\r
4448\r
4449\r
4450M68KMAKE_OP(dbcc, 16, ., .)\r
4451{\r
4452 if(M68KMAKE_NOT_CC)\r
4453 {\r
4454 uint* r_dst = &DY;\r
4455 uint res = MASK_OUT_ABOVE_16(*r_dst - 1);\r
4456\r
4457 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
4458 if(res != 0xffff)\r
4459 {\r
4460 uint offset = OPER_I_16();\r
4461 REG_PC -= 2;\r
4462 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
4463 m68ki_branch_16(offset);\r
4464 USE_CYCLES(CYC_DBCC_F_NOEXP);\r
4465 return;\r
4466 }\r
4467 REG_PC += 2;\r
4468 USE_CYCLES(CYC_DBCC_F_EXP);\r
4469 return;\r
4470 }\r
4471 REG_PC += 2;\r
4472}\r
4473\r
4474\r
4475M68KMAKE_OP(divs, 16, ., d)\r
4476{\r
4477 uint* r_dst = &DX;\r
4478 sint src = MAKE_INT_16(DY);\r
4479 sint quotient;\r
4480 sint remainder;\r
4481\r
4482 if(src != 0)\r
4483 {\r
4484 if((uint32)*r_dst == 0x80000000 && src == -1)\r
4485 {\r
4486 FLAG_Z = 0;\r
4487 FLAG_N = NFLAG_CLEAR;\r
4488 FLAG_V = VFLAG_CLEAR;\r
4489 FLAG_C = CFLAG_CLEAR;\r
4490 *r_dst = 0;\r
4491 return;\r
4492 }\r
4493\r
4494 quotient = MAKE_INT_32(*r_dst) / src;\r
4495 remainder = MAKE_INT_32(*r_dst) % src;\r
4496\r
4497 if(quotient == MAKE_INT_16(quotient))\r
4498 {\r
4499 FLAG_Z = quotient;\r
4500 FLAG_N = NFLAG_16(quotient);\r
4501 FLAG_V = VFLAG_CLEAR;\r
4502 FLAG_C = CFLAG_CLEAR;\r
4503 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));\r
4504 return;\r
4505 }\r
4506 FLAG_V = VFLAG_SET;\r
4507 return;\r
4508 }\r
4509 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);\r
4510}\r
4511\r
4512\r
4513M68KMAKE_OP(divs, 16, ., .)\r
4514{\r
4515 uint* r_dst = &DX;\r
4516 sint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);\r
4517 sint quotient;\r
4518 sint remainder;\r
4519\r
4520 if(src != 0)\r
4521 {\r
4522 if((uint32)*r_dst == 0x80000000 && src == -1)\r
4523 {\r
4524 FLAG_Z = 0;\r
4525 FLAG_N = NFLAG_CLEAR;\r
4526 FLAG_V = VFLAG_CLEAR;\r
4527 FLAG_C = CFLAG_CLEAR;\r
4528 *r_dst = 0;\r
4529 return;\r
4530 }\r
4531\r
4532 quotient = MAKE_INT_32(*r_dst) / src;\r
4533 remainder = MAKE_INT_32(*r_dst) % src;\r
4534\r
4535 if(quotient == MAKE_INT_16(quotient))\r
4536 {\r
4537 FLAG_Z = quotient;\r
4538 FLAG_N = NFLAG_16(quotient);\r
4539 FLAG_V = VFLAG_CLEAR;\r
4540 FLAG_C = CFLAG_CLEAR;\r
4541 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));\r
4542 return;\r
4543 }\r
4544 FLAG_V = VFLAG_SET;\r
4545 return;\r
4546 }\r
4547 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);\r
4548}\r
4549\r
4550\r
4551M68KMAKE_OP(divu, 16, ., d)\r
4552{\r
4553 uint* r_dst = &DX;\r
4554 uint src = MASK_OUT_ABOVE_16(DY);\r
4555\r
4556 if(src != 0)\r
4557 {\r
4558 uint quotient = *r_dst / src;\r
4559 uint remainder = *r_dst % src;\r
4560\r
4561 if(quotient < 0x10000)\r
4562 {\r
4563 FLAG_Z = quotient;\r
4564 FLAG_N = NFLAG_16(quotient);\r
4565 FLAG_V = VFLAG_CLEAR;\r
4566 FLAG_C = CFLAG_CLEAR;\r
4567 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));\r
4568 return;\r
4569 }\r
4570 FLAG_V = VFLAG_SET;\r
4571 return;\r
4572 }\r
4573 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);\r
4574}\r
4575\r
4576\r
4577M68KMAKE_OP(divu, 16, ., .)\r
4578{\r
4579 uint* r_dst = &DX;\r
4580 uint src = M68KMAKE_GET_OPER_AY_16;\r
4581\r
4582 if(src != 0)\r
4583 {\r
4584 uint quotient = *r_dst / src;\r
4585 uint remainder = *r_dst % src;\r
4586\r
4587 if(quotient < 0x10000)\r
4588 {\r
4589 FLAG_Z = quotient;\r
4590 FLAG_N = NFLAG_16(quotient);\r
4591 FLAG_V = VFLAG_CLEAR;\r
4592 FLAG_C = CFLAG_CLEAR;\r
4593 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));\r
4594 return;\r
4595 }\r
4596 FLAG_V = VFLAG_SET;\r
4597 return;\r
4598 }\r
4599 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);\r
4600}\r
4601\r
4602\r
4603M68KMAKE_OP(divl, 32, ., d)\r
4604{\r
4605#if M68K_USE_64_BIT\r
4606\r
4607 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4608 {\r
4609 uint word2 = OPER_I_16();\r
4610 uint64 divisor = DY;\r
4611 uint64 dividend = 0;\r
4612 uint64 quotient = 0;\r
4613 uint64 remainder = 0;\r
4614\r
4615 if(divisor != 0)\r
4616 {\r
4617 if(BIT_A(word2)) /* 64 bit */\r
4618 {\r
4619 dividend = REG_D[word2 & 7];\r
4620 dividend <<= 32;\r
4621 dividend |= REG_D[(word2 >> 12) & 7];\r
4622\r
4623 if(BIT_B(word2)) /* signed */\r
4624 {\r
4625 quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor));\r
4626 remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));\r
4627 if((sint64)quotient != (sint64)((sint32)quotient))\r
4628 {\r
4629 FLAG_V = VFLAG_SET;\r
4630 return;\r
4631 }\r
4632 }\r
4633 else /* unsigned */\r
4634 {\r
4635 quotient = dividend / divisor;\r
4636 if(quotient > 0xffffffff)\r
4637 {\r
4638 FLAG_V = VFLAG_SET;\r
4639 return;\r
4640 }\r
4641 remainder = dividend % divisor;\r
4642 }\r
4643 }\r
4644 else /* 32 bit */\r
4645 {\r
4646 dividend = REG_D[(word2 >> 12) & 7];\r
4647 if(BIT_B(word2)) /* signed */\r
4648 {\r
4649 quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));\r
4650 remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));\r
4651 }\r
4652 else /* unsigned */\r
4653 {\r
4654 quotient = dividend / divisor;\r
4655 remainder = dividend % divisor;\r
4656 }\r
4657 }\r
4658\r
4659 REG_D[word2 & 7] = remainder;\r
4660 REG_D[(word2 >> 12) & 7] = quotient;\r
4661\r
4662 FLAG_N = NFLAG_32(quotient);\r
4663 FLAG_Z = quotient;\r
4664 FLAG_V = VFLAG_CLEAR;\r
4665 FLAG_C = CFLAG_CLEAR;\r
4666 return;\r
4667 }\r
4668 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);\r
4669 return;\r
4670 }\r
4671 m68ki_exception_illegal();\r
4672\r
4673#else\r
4674\r
4675 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4676 {\r
4677 uint word2 = OPER_I_16();\r
4678 uint divisor = DY;\r
4679 uint dividend_hi = REG_D[word2 & 7];\r
4680 uint dividend_lo = REG_D[(word2 >> 12) & 7];\r
4681 uint quotient = 0;\r
4682 uint remainder = 0;\r
4683 uint dividend_neg = 0;\r
4684 uint divisor_neg = 0;\r
4685 sint i;\r
4686 uint overflow;\r
4687\r
4688 if(divisor != 0)\r
4689 {\r
4690 /* quad / long : long quotient, long remainder */\r
4691 if(BIT_A(word2))\r
4692 {\r
4693 if(BIT_B(word2)) /* signed */\r
4694 {\r
4695 /* special case in signed divide */\r
4696 if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)\r
4697 {\r
4698 REG_D[word2 & 7] = 0;\r
4699 REG_D[(word2 >> 12) & 7] = 0x80000000;\r
4700\r
4701 FLAG_N = NFLAG_SET;\r
4702 FLAG_Z = ZFLAG_CLEAR;\r
4703 FLAG_V = VFLAG_CLEAR;\r
4704 FLAG_C = CFLAG_CLEAR;\r
4705 return;\r
4706 }\r
4707 if(GET_MSB_32(dividend_hi))\r
4708 {\r
4709 dividend_neg = 1;\r
4710 dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));\r
4711 dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);\r
4712 }\r
4713 if(GET_MSB_32(divisor))\r
4714 {\r
4715 divisor_neg = 1;\r
4716 divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);\r
4717\r
4718 }\r
4719 }\r
4720\r
4721 /* if the upper long is greater than the divisor, we're overflowing. */\r
4722 if(dividend_hi >= divisor)\r
4723 {\r
4724 FLAG_V = VFLAG_SET;\r
4725 return;\r
4726 }\r
4727\r
4728 for(i = 31; i >= 0; i--)\r
4729 {\r
4730 quotient <<= 1;\r
4731 remainder = (remainder << 1) + ((dividend_hi >> i) & 1);\r
4732 if(remainder >= divisor)\r
4733 {\r
4734 remainder -= divisor;\r
4735 quotient++;\r
4736 }\r
4737 }\r
4738 for(i = 31; i >= 0; i--)\r
4739 {\r
4740 quotient <<= 1;\r
4741 overflow = GET_MSB_32(remainder);\r
4742 remainder = (remainder << 1) + ((dividend_lo >> i) & 1);\r
4743 if(remainder >= divisor || overflow)\r
4744 {\r
4745 remainder -= divisor;\r
4746 quotient++;\r
4747 }\r
4748 }\r
4749\r
4750 if(BIT_B(word2)) /* signed */\r
4751 {\r
4752 if(quotient > 0x7fffffff)\r
4753 {\r
4754 FLAG_V = VFLAG_SET;\r
4755 return;\r
4756 }\r
4757 if(dividend_neg)\r
4758 {\r
4759 remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);\r
4760 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);\r
4761 }\r
4762 if(divisor_neg)\r
4763 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);\r
4764 }\r
4765\r
4766 REG_D[word2 & 7] = remainder;\r
4767 REG_D[(word2 >> 12) & 7] = quotient;\r
4768\r
4769 FLAG_N = NFLAG_32(quotient);\r
4770 FLAG_Z = quotient;\r
4771 FLAG_V = VFLAG_CLEAR;\r
4772 FLAG_C = CFLAG_CLEAR;\r
4773 return;\r
4774 }\r
4775\r
4776 /* long / long: long quotient, maybe long remainder */\r
4777 if(BIT_B(word2)) /* signed */\r
4778 {\r
4779 /* Special case in divide */\r
4780 if(dividend_lo == 0x80000000 && divisor == 0xffffffff)\r
4781 {\r
4782 FLAG_N = NFLAG_SET;\r
4783 FLAG_Z = ZFLAG_CLEAR;\r
4784 FLAG_V = VFLAG_CLEAR;\r
4785 FLAG_C = CFLAG_CLEAR;\r
4786 REG_D[(word2 >> 12) & 7] = 0x80000000;\r
4787 REG_D[word2 & 7] = 0;\r
4788 return;\r
4789 }\r
4790 REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);\r
4791 quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);\r
4792 }\r
4793 else\r
4794 {\r
4795 REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);\r
4796 quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);\r
4797 }\r
4798\r
4799 FLAG_N = NFLAG_32(quotient);\r
4800 FLAG_Z = quotient;\r
4801 FLAG_V = VFLAG_CLEAR;\r
4802 FLAG_C = CFLAG_CLEAR;\r
4803 return;\r
4804 }\r
4805 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);\r
4806 return;\r
4807 }\r
4808 m68ki_exception_illegal();\r
4809\r
4810#endif\r
4811}\r
4812\r
4813\r
4814M68KMAKE_OP(divl, 32, ., .)\r
4815{\r
4816#if M68K_USE_64_BIT\r
4817\r
4818 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4819 {\r
4820 uint word2 = OPER_I_16();\r
4821 uint64 divisor = M68KMAKE_GET_OPER_AY_32;\r
4822 uint64 dividend = 0;\r
4823 uint64 quotient = 0;\r
4824 uint64 remainder = 0;\r
4825\r
4826 if(divisor != 0)\r
4827 {\r
4828 if(BIT_A(word2)) /* 64 bit */\r
4829 {\r
4830 dividend = REG_D[word2 & 7];\r
4831 dividend <<= 32;\r
4832 dividend |= REG_D[(word2 >> 12) & 7];\r
4833\r
4834 if(BIT_B(word2)) /* signed */\r
4835 {\r
4836 quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor));\r
4837 remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));\r
4838 if((sint64)quotient != (sint64)((sint32)quotient))\r
4839 {\r
4840 FLAG_V = VFLAG_SET;\r
4841 return;\r
4842 }\r
4843 }\r
4844 else /* unsigned */\r
4845 {\r
4846 quotient = dividend / divisor;\r
4847 if(quotient > 0xffffffff)\r
4848 {\r
4849 FLAG_V = VFLAG_SET;\r
4850 return;\r
4851 }\r
4852 remainder = dividend % divisor;\r
4853 }\r
4854 }\r
4855 else /* 32 bit */\r
4856 {\r
4857 dividend = REG_D[(word2 >> 12) & 7];\r
4858 if(BIT_B(word2)) /* signed */\r
4859 {\r
4860 quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));\r
4861 remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));\r
4862 }\r
4863 else /* unsigned */\r
4864 {\r
4865 quotient = dividend / divisor;\r
4866 remainder = dividend % divisor;\r
4867 }\r
4868 }\r
4869\r
4870 REG_D[word2 & 7] = remainder;\r
4871 REG_D[(word2 >> 12) & 7] = quotient;\r
4872\r
4873 FLAG_N = NFLAG_32(quotient);\r
4874 FLAG_Z = quotient;\r
4875 FLAG_V = VFLAG_CLEAR;\r
4876 FLAG_C = CFLAG_CLEAR;\r
4877 return;\r
4878 }\r
4879 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);\r
4880 return;\r
4881 }\r
4882 m68ki_exception_illegal();\r
4883\r
4884#else\r
4885\r
4886 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4887 {\r
4888 uint word2 = OPER_I_16();\r
4889 uint divisor = M68KMAKE_GET_OPER_AY_32;\r
4890 uint dividend_hi = REG_D[word2 & 7];\r
4891 uint dividend_lo = REG_D[(word2 >> 12) & 7];\r
4892 uint quotient = 0;\r
4893 uint remainder = 0;\r
4894 uint dividend_neg = 0;\r
4895 uint divisor_neg = 0;\r
4896 sint i;\r
4897 uint overflow;\r
4898\r
4899 if(divisor != 0)\r
4900 {\r
4901 /* quad / long : long quotient, long remainder */\r
4902 if(BIT_A(word2))\r
4903 {\r
4904 if(BIT_B(word2)) /* signed */\r
4905 {\r
4906 /* special case in signed divide */\r
4907 if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)\r
4908 {\r
4909 REG_D[word2 & 7] = 0;\r
4910 REG_D[(word2 >> 12) & 7] = 0x80000000;\r
4911\r
4912 FLAG_N = NFLAG_SET;\r
4913 FLAG_Z = ZFLAG_CLEAR;\r
4914 FLAG_V = VFLAG_CLEAR;\r
4915 FLAG_C = CFLAG_CLEAR;\r
4916 return;\r
4917 }\r
4918 if(GET_MSB_32(dividend_hi))\r
4919 {\r
4920 dividend_neg = 1;\r
4921 dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));\r
4922 dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);\r
4923 }\r
4924 if(GET_MSB_32(divisor))\r
4925 {\r
4926 divisor_neg = 1;\r
4927 divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);\r
4928\r
4929 }\r
4930 }\r
4931\r
4932 /* if the upper long is greater than the divisor, we're overflowing. */\r
4933 if(dividend_hi >= divisor)\r
4934 {\r
4935 FLAG_V = VFLAG_SET;\r
4936 return;\r
4937 }\r
4938\r
4939 for(i = 31; i >= 0; i--)\r
4940 {\r
4941 quotient <<= 1;\r
4942 remainder = (remainder << 1) + ((dividend_hi >> i) & 1);\r
4943 if(remainder >= divisor)\r
4944 {\r
4945 remainder -= divisor;\r
4946 quotient++;\r
4947 }\r
4948 }\r
4949 for(i = 31; i >= 0; i--)\r
4950 {\r
4951 quotient <<= 1;\r
4952 overflow = GET_MSB_32(remainder);\r
4953 remainder = (remainder << 1) + ((dividend_lo >> i) & 1);\r
4954 if(remainder >= divisor || overflow)\r
4955 {\r
4956 remainder -= divisor;\r
4957 quotient++;\r
4958 }\r
4959 }\r
4960\r
4961 if(BIT_B(word2)) /* signed */\r
4962 {\r
4963 if(quotient > 0x7fffffff)\r
4964 {\r
4965 FLAG_V = VFLAG_SET;\r
4966 return;\r
4967 }\r
4968 if(dividend_neg)\r
4969 {\r
4970 remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);\r
4971 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);\r
4972 }\r
4973 if(divisor_neg)\r
4974 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);\r
4975 }\r
4976\r
4977 REG_D[word2 & 7] = remainder;\r
4978 REG_D[(word2 >> 12) & 7] = quotient;\r
4979\r
4980 FLAG_N = NFLAG_32(quotient);\r
4981 FLAG_Z = quotient;\r
4982 FLAG_V = VFLAG_CLEAR;\r
4983 FLAG_C = CFLAG_CLEAR;\r
4984 return;\r
4985 }\r
4986\r
4987 /* long / long: long quotient, maybe long remainder */\r
4988 if(BIT_B(word2)) /* signed */\r
4989 {\r
4990 /* Special case in divide */\r
4991 if(dividend_lo == 0x80000000 && divisor == 0xffffffff)\r
4992 {\r
4993 FLAG_N = NFLAG_SET;\r
4994 FLAG_Z = ZFLAG_CLEAR;\r
4995 FLAG_V = VFLAG_CLEAR;\r
4996 FLAG_C = CFLAG_CLEAR;\r
4997 REG_D[(word2 >> 12) & 7] = 0x80000000;\r
4998 REG_D[word2 & 7] = 0;\r
4999 return;\r
5000 }\r
5001 REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);\r
5002 quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);\r
5003 }\r
5004 else\r
5005 {\r
5006 REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);\r
5007 quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);\r
5008 }\r
5009\r
5010 FLAG_N = NFLAG_32(quotient);\r
5011 FLAG_Z = quotient;\r
5012 FLAG_V = VFLAG_CLEAR;\r
5013 FLAG_C = CFLAG_CLEAR;\r
5014 return;\r
5015 }\r
5016 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);\r
5017 return;\r
5018 }\r
5019 m68ki_exception_illegal();\r
5020\r
5021#endif\r
5022}\r
5023\r
5024\r
5025M68KMAKE_OP(eor, 8, ., d)\r
5026{\r
5027 uint res = MASK_OUT_ABOVE_8(DY ^= MASK_OUT_ABOVE_8(DX));\r
5028\r
5029 FLAG_N = NFLAG_8(res);\r
5030 FLAG_Z = res;\r
5031 FLAG_C = CFLAG_CLEAR;\r
5032 FLAG_V = VFLAG_CLEAR;\r
5033}\r
5034\r
5035\r
5036M68KMAKE_OP(eor, 8, ., .)\r
5037{\r
5038 uint ea = M68KMAKE_GET_EA_AY_8;\r
5039 uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));\r
5040\r
5041 m68ki_write_8(ea, res);\r
5042\r
5043 FLAG_N = NFLAG_8(res);\r
5044 FLAG_Z = res;\r
5045 FLAG_C = CFLAG_CLEAR;\r
5046 FLAG_V = VFLAG_CLEAR;\r
5047}\r
5048\r
5049\r
5050M68KMAKE_OP(eor, 16, ., d)\r
5051{\r
5052 uint res = MASK_OUT_ABOVE_16(DY ^= MASK_OUT_ABOVE_16(DX));\r
5053\r
5054 FLAG_N = NFLAG_16(res);\r
5055 FLAG_Z = res;\r
5056 FLAG_C = CFLAG_CLEAR;\r
5057 FLAG_V = VFLAG_CLEAR;\r
5058}\r
5059\r
5060\r
5061M68KMAKE_OP(eor, 16, ., .)\r
5062{\r
5063 uint ea = M68KMAKE_GET_EA_AY_16;\r
5064 uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea));\r
5065\r
5066 m68ki_write_16(ea, res);\r
5067\r
5068 FLAG_N = NFLAG_16(res);\r
5069 FLAG_Z = res;\r
5070 FLAG_C = CFLAG_CLEAR;\r
5071 FLAG_V = VFLAG_CLEAR;\r
5072}\r
5073\r
5074\r
5075M68KMAKE_OP(eor, 32, ., d)\r
5076{\r
5077 uint res = DY ^= DX;\r
5078\r
5079 FLAG_N = NFLAG_32(res);\r
5080 FLAG_Z = res;\r
5081 FLAG_C = CFLAG_CLEAR;\r
5082 FLAG_V = VFLAG_CLEAR;\r
5083}\r
5084\r
5085\r
5086M68KMAKE_OP(eor, 32, ., .)\r
5087{\r
5088 uint ea = M68KMAKE_GET_EA_AY_32;\r
5089 uint res = DX ^ m68ki_read_32(ea);\r
5090\r
5091 m68ki_write_32(ea, res);\r
5092\r
5093 FLAG_N = NFLAG_32(res);\r
5094 FLAG_Z = res;\r
5095 FLAG_C = CFLAG_CLEAR;\r
5096 FLAG_V = VFLAG_CLEAR;\r
5097}\r
5098\r
5099\r
5100M68KMAKE_OP(eori, 8, ., d)\r
5101{\r
5102 uint res = MASK_OUT_ABOVE_8(DY ^= OPER_I_8());\r
5103\r
5104 FLAG_N = NFLAG_8(res);\r
5105 FLAG_Z = res;\r
5106 FLAG_C = CFLAG_CLEAR;\r
5107 FLAG_V = VFLAG_CLEAR;\r
5108}\r
5109\r
5110\r
5111M68KMAKE_OP(eori, 8, ., .)\r
5112{\r
5113 uint src = OPER_I_8();\r
5114 uint ea = M68KMAKE_GET_EA_AY_8;\r
5115 uint res = src ^ m68ki_read_8(ea);\r
5116\r
5117 m68ki_write_8(ea, res);\r
5118\r
5119 FLAG_N = NFLAG_8(res);\r
5120 FLAG_Z = res;\r
5121 FLAG_C = CFLAG_CLEAR;\r
5122 FLAG_V = VFLAG_CLEAR;\r
5123}\r
5124\r
5125\r
5126M68KMAKE_OP(eori, 16, ., d)\r
5127{\r
5128 uint res = MASK_OUT_ABOVE_16(DY ^= OPER_I_16());\r
5129\r
5130 FLAG_N = NFLAG_16(res);\r
5131 FLAG_Z = res;\r
5132 FLAG_C = CFLAG_CLEAR;\r
5133 FLAG_V = VFLAG_CLEAR;\r
5134}\r
5135\r
5136\r
5137M68KMAKE_OP(eori, 16, ., .)\r
5138{\r
5139 uint src = OPER_I_16();\r
5140 uint ea = M68KMAKE_GET_EA_AY_16;\r
5141 uint res = src ^ m68ki_read_16(ea);\r
5142\r
5143 m68ki_write_16(ea, res);\r
5144\r
5145 FLAG_N = NFLAG_16(res);\r
5146 FLAG_Z = res;\r
5147 FLAG_C = CFLAG_CLEAR;\r
5148 FLAG_V = VFLAG_CLEAR;\r
5149}\r
5150\r
5151\r
5152M68KMAKE_OP(eori, 32, ., d)\r
5153{\r
5154 uint res = DY ^= OPER_I_32();\r
5155\r
5156 FLAG_N = NFLAG_32(res);\r
5157 FLAG_Z = res;\r
5158 FLAG_C = CFLAG_CLEAR;\r
5159 FLAG_V = VFLAG_CLEAR;\r
5160}\r
5161\r
5162\r
5163M68KMAKE_OP(eori, 32, ., .)\r
5164{\r
5165 uint src = OPER_I_32();\r
5166 uint ea = M68KMAKE_GET_EA_AY_32;\r
5167 uint res = src ^ m68ki_read_32(ea);\r
5168\r
5169 m68ki_write_32(ea, res);\r
5170\r
5171 FLAG_N = NFLAG_32(res);\r
5172 FLAG_Z = res;\r
5173 FLAG_C = CFLAG_CLEAR;\r
5174 FLAG_V = VFLAG_CLEAR;\r
5175}\r
5176\r
5177\r
5178M68KMAKE_OP(eori, 16, toc, .)\r
5179{\r
5180 m68ki_set_ccr(m68ki_get_ccr() ^ OPER_I_16());\r
5181}\r
5182\r
5183\r
5184M68KMAKE_OP(eori, 16, tos, .)\r
5185{\r
5186 if(FLAG_S)\r
5187 {\r
5188 uint src = OPER_I_16();\r
5189 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
5190 m68ki_set_sr(m68ki_get_sr() ^ src);\r
5191 return;\r
5192 }\r
5193 m68ki_exception_privilege_violation();\r
5194}\r
5195\r
5196\r
5197M68KMAKE_OP(exg, 32, dd, .)\r
5198{\r
5199 uint* reg_a = &DX;\r
5200 uint* reg_b = &DY;\r
5201 uint tmp = *reg_a;\r
5202 *reg_a = *reg_b;\r
5203 *reg_b = tmp;\r
5204}\r
5205\r
5206\r
5207M68KMAKE_OP(exg, 32, aa, .)\r
5208{\r
5209 uint* reg_a = &AX;\r
5210 uint* reg_b = &AY;\r
5211 uint tmp = *reg_a;\r
5212 *reg_a = *reg_b;\r
5213 *reg_b = tmp;\r
5214}\r
5215\r
5216\r
5217M68KMAKE_OP(exg, 32, da, .)\r
5218{\r
5219 uint* reg_a = &DX;\r
5220 uint* reg_b = &AY;\r
5221 uint tmp = *reg_a;\r
5222 *reg_a = *reg_b;\r
5223 *reg_b = tmp;\r
5224}\r
5225\r
5226\r
5227M68KMAKE_OP(ext, 16, ., .)\r
5228{\r
5229 uint* r_dst = &DY;\r
5230\r
5231 *r_dst = MASK_OUT_BELOW_16(*r_dst) | MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xff00 : 0);\r
5232\r
5233 FLAG_N = NFLAG_16(*r_dst);\r
5234 FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);\r
5235 FLAG_V = VFLAG_CLEAR;\r
5236 FLAG_C = CFLAG_CLEAR;\r
5237}\r
5238\r
5239\r
5240M68KMAKE_OP(ext, 32, ., .)\r
5241{\r
5242 uint* r_dst = &DY;\r
5243\r
5244 *r_dst = MASK_OUT_ABOVE_16(*r_dst) | (GET_MSB_16(*r_dst) ? 0xffff0000 : 0);\r
5245\r
5246 FLAG_N = NFLAG_32(*r_dst);\r
5247 FLAG_Z = *r_dst;\r
5248 FLAG_V = VFLAG_CLEAR;\r
5249 FLAG_C = CFLAG_CLEAR;\r
5250}\r
5251\r
5252\r
5253M68KMAKE_OP(extb, 32, ., .)\r
5254{\r
5255 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
5256 {\r
5257 uint* r_dst = &DY;\r
5258\r
5259 *r_dst = MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xffffff00 : 0);\r
5260\r
5261 FLAG_N = NFLAG_32(*r_dst);\r
5262 FLAG_Z = *r_dst;\r
5263 FLAG_V = VFLAG_CLEAR;\r
5264 FLAG_C = CFLAG_CLEAR;\r
5265 return;\r
5266 }\r
5267 m68ki_exception_illegal();\r
5268}\r
5269\r
5270\r
5271M68KMAKE_OP(illegal, 0, ., .)\r
5272{\r
5273 m68ki_exception_illegal();\r
5274}\r
5275\r
5276M68KMAKE_OP(jmp, 32, ., .)\r
5277{\r
5278 m68ki_jump(M68KMAKE_GET_EA_AY_32);\r
5279 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
5280 if(REG_PC == REG_PPC)\r
5281 USE_ALL_CYCLES();\r
5282}\r
5283\r
5284\r
5285M68KMAKE_OP(jsr, 32, ., .)\r
5286{\r
5287 uint ea = M68KMAKE_GET_EA_AY_32;\r
5288 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
c6a4c892 5289 m68ki_push_32(REG_PC);\r
cc68a136 5290 m68ki_jump(ea);\r
5291}\r
5292\r
5293\r
5294M68KMAKE_OP(lea, 32, ., .)\r
5295{\r
5296 AX = M68KMAKE_GET_EA_AY_32;\r
5297}\r
5298\r
5299\r
5300M68KMAKE_OP(link, 16, ., a7)\r
5301{\r
5302 REG_A[7] -= 4;\r
5303 m68ki_write_32(REG_A[7], REG_A[7]);\r
5304 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));\r
5305}\r
5306\r
5307\r
5308M68KMAKE_OP(link, 16, ., .)\r
5309{\r
5310 uint* r_dst = &AY;\r
5311\r
5312 m68ki_push_32(*r_dst);\r
5313 *r_dst = REG_A[7];\r
5314 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));\r
5315}\r
5316\r
5317\r
5318M68KMAKE_OP(link, 32, ., a7)\r
5319{\r
5320 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
5321 {\r
5322 REG_A[7] -= 4;\r
5323 m68ki_write_32(REG_A[7], REG_A[7]);\r
5324 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32());\r
5325 return;\r
5326 }\r
5327 m68ki_exception_illegal();\r
5328}\r
5329\r
5330\r
5331M68KMAKE_OP(link, 32, ., .)\r
5332{\r
5333 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
5334 {\r
5335 uint* r_dst = &AY;\r
5336\r
5337 m68ki_push_32(*r_dst);\r
5338 *r_dst = REG_A[7];\r
5339 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32());\r
5340 return;\r
5341 }\r
5342 m68ki_exception_illegal();\r
5343}\r
5344\r
5345\r
5346M68KMAKE_OP(lsr, 8, s, .)\r
5347{\r
5348 uint* r_dst = &DY;\r
5349 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
5350 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
5351 uint res = src >> shift;\r
5352\r
5353 if(shift != 0)\r
5354 USE_CYCLES(shift<<CYC_SHIFT);\r
5355\r
5356 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
5357\r
5358 FLAG_N = NFLAG_CLEAR;\r
5359 FLAG_Z = res;\r
5360 FLAG_X = FLAG_C = src << (9-shift);\r
5361 FLAG_V = VFLAG_CLEAR;\r
5362}\r
5363\r
5364\r
5365M68KMAKE_OP(lsr, 16, s, .)\r
5366{\r
5367 uint* r_dst = &DY;\r
5368 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
5369 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
5370 uint res = src >> shift;\r
5371\r
5372 if(shift != 0)\r
5373 USE_CYCLES(shift<<CYC_SHIFT);\r
5374\r
5375 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
5376\r
5377 FLAG_N = NFLAG_CLEAR;\r
5378 FLAG_Z = res;\r
5379 FLAG_X = FLAG_C = src << (9-shift);\r
5380 FLAG_V = VFLAG_CLEAR;\r
5381}\r
5382\r
5383\r
5384M68KMAKE_OP(lsr, 32, s, .)\r
5385{\r
5386 uint* r_dst = &DY;\r
5387 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
5388 uint src = *r_dst;\r
5389 uint res = src >> shift;\r
5390\r
5391 if(shift != 0)\r
5392 USE_CYCLES(shift<<CYC_SHIFT);\r
5393\r
5394 *r_dst = res;\r
5395\r
5396 FLAG_N = NFLAG_CLEAR;\r
5397 FLAG_Z = res;\r
5398 FLAG_X = FLAG_C = src << (9-shift);\r
5399 FLAG_V = VFLAG_CLEAR;\r
5400}\r
5401\r
5402\r
5403M68KMAKE_OP(lsr, 8, r, .)\r
5404{\r
5405 uint* r_dst = &DY;\r
5406 uint shift = DX & 0x3f;\r
5407 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
5408 uint res = src >> shift;\r
5409\r
5410 if(shift != 0)\r
5411 {\r
5412 USE_CYCLES(shift<<CYC_SHIFT);\r
5413\r
5414 if(shift <= 8)\r
5415 {\r
5416 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
5417 FLAG_X = FLAG_C = src << (9-shift);\r
5418 FLAG_N = NFLAG_CLEAR;\r
5419 FLAG_Z = res;\r
5420 FLAG_V = VFLAG_CLEAR;\r
5421 return;\r
5422 }\r
5423\r
5424 *r_dst &= 0xffffff00;\r
5425 FLAG_X = XFLAG_CLEAR;\r
5426 FLAG_C = CFLAG_CLEAR;\r
5427 FLAG_N = NFLAG_CLEAR;\r
5428 FLAG_Z = ZFLAG_SET;\r
5429 FLAG_V = VFLAG_CLEAR;\r
5430 return;\r
5431 }\r
5432\r
5433 FLAG_C = CFLAG_CLEAR;\r
5434 FLAG_N = NFLAG_8(src);\r
5435 FLAG_Z = src;\r
5436 FLAG_V = VFLAG_CLEAR;\r
5437}\r
5438\r
5439\r
5440M68KMAKE_OP(lsr, 16, r, .)\r
5441{\r
5442 uint* r_dst = &DY;\r
5443 uint shift = DX & 0x3f;\r
5444 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
5445 uint res = src >> shift;\r
5446\r
5447 if(shift != 0)\r
5448 {\r
5449 USE_CYCLES(shift<<CYC_SHIFT);\r
5450\r
5451 if(shift <= 16)\r
5452 {\r
5453 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
5454 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;\r
5455 FLAG_N = NFLAG_CLEAR;\r
5456 FLAG_Z = res;\r
5457 FLAG_V = VFLAG_CLEAR;\r
5458 return;\r
5459 }\r
5460\r
5461 *r_dst &= 0xffff0000;\r
5462 FLAG_X = XFLAG_CLEAR;\r
5463 FLAG_C = CFLAG_CLEAR;\r
5464 FLAG_N = NFLAG_CLEAR;\r
5465 FLAG_Z = ZFLAG_SET;\r
5466 FLAG_V = VFLAG_CLEAR;\r
5467 return;\r
5468 }\r
5469\r
5470 FLAG_C = CFLAG_CLEAR;\r
5471 FLAG_N = NFLAG_16(src);\r
5472 FLAG_Z = src;\r
5473 FLAG_V = VFLAG_CLEAR;\r
5474}\r
5475\r
5476\r
5477M68KMAKE_OP(lsr, 32, r, .)\r
5478{\r
5479 uint* r_dst = &DY;\r
5480 uint shift = DX & 0x3f;\r
5481 uint src = *r_dst;\r
5482 uint res = src >> shift;\r
5483\r
5484 if(shift != 0)\r
5485 {\r
5486 USE_CYCLES(shift<<CYC_SHIFT);\r
5487\r
5488 if(shift < 32)\r
5489 {\r
5490 *r_dst = res;\r
5491 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;\r
5492 FLAG_N = NFLAG_CLEAR;\r
5493 FLAG_Z = res;\r
5494 FLAG_V = VFLAG_CLEAR;\r
5495 return;\r
5496 }\r
5497\r
5498 *r_dst = 0;\r
5499 FLAG_X = FLAG_C = (shift == 32 ? GET_MSB_32(src)>>23 : 0);\r
5500 FLAG_N = NFLAG_CLEAR;\r
5501 FLAG_Z = ZFLAG_SET;\r
5502 FLAG_V = VFLAG_CLEAR;\r
5503 return;\r
5504 }\r
5505\r
5506 FLAG_C = CFLAG_CLEAR;\r
5507 FLAG_N = NFLAG_32(src);\r
5508 FLAG_Z = src;\r
5509 FLAG_V = VFLAG_CLEAR;\r
5510}\r
5511\r
5512\r
5513M68KMAKE_OP(lsr, 16, ., .)\r
5514{\r
5515 uint ea = M68KMAKE_GET_EA_AY_16;\r
5516 uint src = m68ki_read_16(ea);\r
5517 uint res = src >> 1;\r
5518\r
5519 m68ki_write_16(ea, res);\r
5520\r
5521 FLAG_N = NFLAG_CLEAR;\r
5522 FLAG_Z = res;\r
5523 FLAG_C = FLAG_X = src << 8;\r
5524 FLAG_V = VFLAG_CLEAR;\r
5525}\r
5526\r
5527\r
5528M68KMAKE_OP(lsl, 8, s, .)\r
5529{\r
5530 uint* r_dst = &DY;\r
5531 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
5532 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
5533 uint res = MASK_OUT_ABOVE_8(src << shift);\r
5534\r
5535 if(shift != 0)\r
5536 USE_CYCLES(shift<<CYC_SHIFT);\r
5537\r
5538 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
5539\r
5540 FLAG_N = NFLAG_8(res);\r
5541 FLAG_Z = res;\r
5542 FLAG_X = FLAG_C = src << shift;\r
5543 FLAG_V = VFLAG_CLEAR;\r
5544}\r
5545\r
5546\r
5547M68KMAKE_OP(lsl, 16, s, .)\r
5548{\r
5549 uint* r_dst = &DY;\r
5550 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
5551 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
5552 uint res = MASK_OUT_ABOVE_16(src << shift);\r
5553\r
5554 if(shift != 0)\r
5555 USE_CYCLES(shift<<CYC_SHIFT);\r
5556\r
5557 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
5558\r
5559 FLAG_N = NFLAG_16(res);\r
5560 FLAG_Z = res;\r
5561 FLAG_X = FLAG_C = src >> (8-shift);\r
5562 FLAG_V = VFLAG_CLEAR;\r
5563}\r
5564\r
5565\r
5566M68KMAKE_OP(lsl, 32, s, .)\r
5567{\r
5568 uint* r_dst = &DY;\r
5569 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
5570 uint src = *r_dst;\r
5571 uint res = MASK_OUT_ABOVE_32(src << shift);\r
5572\r
5573 if(shift != 0)\r
5574 USE_CYCLES(shift<<CYC_SHIFT);\r
5575\r
5576 *r_dst = res;\r
5577\r
5578 FLAG_N = NFLAG_32(res);\r
5579 FLAG_Z = res;\r
5580 FLAG_X = FLAG_C = src >> (24-shift);\r
5581 FLAG_V = VFLAG_CLEAR;\r
5582}\r
5583\r
5584\r
5585M68KMAKE_OP(lsl, 8, r, .)\r
5586{\r
5587 uint* r_dst = &DY;\r
5588 uint shift = DX & 0x3f;\r
5589 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
5590 uint res = MASK_OUT_ABOVE_8(src << shift);\r
5591\r
5592 if(shift != 0)\r
5593 {\r
5594 USE_CYCLES(shift<<CYC_SHIFT);\r
5595\r
5596 if(shift <= 8)\r
5597 {\r
5598 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
5599 FLAG_X = FLAG_C = src << shift;\r
5600 FLAG_N = NFLAG_8(res);\r
5601 FLAG_Z = res;\r
5602 FLAG_V = VFLAG_CLEAR;\r
5603 return;\r
5604 }\r
5605\r
5606 *r_dst &= 0xffffff00;\r
5607 FLAG_X = XFLAG_CLEAR;\r
5608 FLAG_C = CFLAG_CLEAR;\r
5609 FLAG_N = NFLAG_CLEAR;\r
5610 FLAG_Z = ZFLAG_SET;\r
5611 FLAG_V = VFLAG_CLEAR;\r
5612 return;\r
5613 }\r
5614\r
5615 FLAG_C = CFLAG_CLEAR;\r
5616 FLAG_N = NFLAG_8(src);\r
5617 FLAG_Z = src;\r
5618 FLAG_V = VFLAG_CLEAR;\r
5619}\r
5620\r
5621\r
5622M68KMAKE_OP(lsl, 16, r, .)\r
5623{\r
5624 uint* r_dst = &DY;\r
5625 uint shift = DX & 0x3f;\r
5626 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
5627 uint res = MASK_OUT_ABOVE_16(src << shift);\r
5628\r
5629 if(shift != 0)\r
5630 {\r
5631 USE_CYCLES(shift<<CYC_SHIFT);\r
5632\r
5633 if(shift <= 16)\r
5634 {\r
5635 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
5636 FLAG_X = FLAG_C = (src << shift) >> 8;\r
5637 FLAG_N = NFLAG_16(res);\r
5638 FLAG_Z = res;\r
5639 FLAG_V = VFLAG_CLEAR;\r
5640 return;\r
5641 }\r
5642\r
5643 *r_dst &= 0xffff0000;\r
5644 FLAG_X = XFLAG_CLEAR;\r
5645 FLAG_C = CFLAG_CLEAR;\r
5646 FLAG_N = NFLAG_CLEAR;\r
5647 FLAG_Z = ZFLAG_SET;\r
5648 FLAG_V = VFLAG_CLEAR;\r
5649 return;\r
5650 }\r
5651\r
5652 FLAG_C = CFLAG_CLEAR;\r
5653 FLAG_N = NFLAG_16(src);\r
5654 FLAG_Z = src;\r
5655 FLAG_V = VFLAG_CLEAR;\r
5656}\r
5657\r
5658\r
5659M68KMAKE_OP(lsl, 32, r, .)\r
5660{\r
5661 uint* r_dst = &DY;\r
5662 uint shift = DX & 0x3f;\r
5663 uint src = *r_dst;\r
5664 uint res = MASK_OUT_ABOVE_32(src << shift);\r
5665\r
5666 if(shift != 0)\r
5667 {\r
5668 USE_CYCLES(shift<<CYC_SHIFT);\r
5669\r
5670 if(shift < 32)\r
5671 {\r
5672 *r_dst = res;\r
5673 FLAG_X = FLAG_C = (src >> (32 - shift)) << 8;\r
5674 FLAG_N = NFLAG_32(res);\r
5675 FLAG_Z = res;\r
5676 FLAG_V = VFLAG_CLEAR;\r
5677 return;\r
5678 }\r
5679\r
5680 *r_dst = 0;\r
5681 FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8;\r
5682 FLAG_N = NFLAG_CLEAR;\r
5683 FLAG_Z = ZFLAG_SET;\r
5684 FLAG_V = VFLAG_CLEAR;\r
5685 return;\r
5686 }\r
5687\r
5688 FLAG_C = CFLAG_CLEAR;\r
5689 FLAG_N = NFLAG_32(src);\r
5690 FLAG_Z = src;\r
5691 FLAG_V = VFLAG_CLEAR;\r
5692}\r
5693\r
5694\r
5695M68KMAKE_OP(lsl, 16, ., .)\r
5696{\r
5697 uint ea = M68KMAKE_GET_EA_AY_16;\r
5698 uint src = m68ki_read_16(ea);\r
5699 uint res = MASK_OUT_ABOVE_16(src << 1);\r
5700\r
5701 m68ki_write_16(ea, res);\r
5702\r
5703 FLAG_N = NFLAG_16(res);\r
5704 FLAG_Z = res;\r
5705 FLAG_X = FLAG_C = src >> 7;\r
5706 FLAG_V = VFLAG_CLEAR;\r
5707}\r
5708\r
5709\r
5710M68KMAKE_OP(move, 8, d, d)\r
5711{\r
5712 uint res = MASK_OUT_ABOVE_8(DY);\r
5713 uint* r_dst = &DX;\r
5714\r
5715 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
5716\r
5717 FLAG_N = NFLAG_8(res);\r
5718 FLAG_Z = res;\r
5719 FLAG_V = VFLAG_CLEAR;\r
5720 FLAG_C = CFLAG_CLEAR;\r
5721}\r
5722\r
5723\r
5724M68KMAKE_OP(move, 8, d, .)\r
5725{\r
5726 uint res = M68KMAKE_GET_OPER_AY_8;\r
5727 uint* r_dst = &DX;\r
5728\r
5729 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
5730\r
5731 FLAG_N = NFLAG_8(res);\r
5732 FLAG_Z = res;\r
5733 FLAG_V = VFLAG_CLEAR;\r
5734 FLAG_C = CFLAG_CLEAR;\r
5735}\r
5736\r
5737\r
5738M68KMAKE_OP(move, 8, ai, d)\r
5739{\r
5740 uint res = MASK_OUT_ABOVE_8(DY);\r
5741 uint ea = EA_AX_AI_8();\r
5742\r
5743 m68ki_write_8(ea, res);\r
5744\r
5745 FLAG_N = NFLAG_8(res);\r
5746 FLAG_Z = res;\r
5747 FLAG_V = VFLAG_CLEAR;\r
5748 FLAG_C = CFLAG_CLEAR;\r
5749}\r
5750\r
5751\r
5752M68KMAKE_OP(move, 8, ai, .)\r
5753{\r
5754 uint res = M68KMAKE_GET_OPER_AY_8;\r
5755 uint ea = EA_AX_AI_8();\r
5756\r
5757 m68ki_write_8(ea, res);\r
5758\r
5759 FLAG_N = NFLAG_8(res);\r
5760 FLAG_Z = res;\r
5761 FLAG_V = VFLAG_CLEAR;\r
5762 FLAG_C = CFLAG_CLEAR;\r
5763}\r
5764\r
5765\r
5766M68KMAKE_OP(move, 8, pi7, d)\r
5767{\r
5768 uint res = MASK_OUT_ABOVE_8(DY);\r
5769 uint ea = EA_A7_PI_8();\r
5770\r
5771 m68ki_write_8(ea, res);\r
5772\r
5773 FLAG_N = NFLAG_8(res);\r
5774 FLAG_Z = res;\r
5775 FLAG_V = VFLAG_CLEAR;\r
5776 FLAG_C = CFLAG_CLEAR;\r
5777}\r
5778\r
5779\r
5780M68KMAKE_OP(move, 8, pi, d)\r
5781{\r
5782 uint res = MASK_OUT_ABOVE_8(DY);\r
5783 uint ea = EA_AX_PI_8();\r
5784\r
5785 m68ki_write_8(ea, res);\r
5786\r
5787 FLAG_N = NFLAG_8(res);\r
5788 FLAG_Z = res;\r
5789 FLAG_V = VFLAG_CLEAR;\r
5790 FLAG_C = CFLAG_CLEAR;\r
5791}\r
5792\r
5793\r
5794M68KMAKE_OP(move, 8, pi7, .)\r
5795{\r
5796 uint res = M68KMAKE_GET_OPER_AY_8;\r
5797 uint ea = EA_A7_PI_8();\r
5798\r
5799 m68ki_write_8(ea, res);\r
5800\r
5801 FLAG_N = NFLAG_8(res);\r
5802 FLAG_Z = res;\r
5803 FLAG_V = VFLAG_CLEAR;\r
5804 FLAG_C = CFLAG_CLEAR;\r
5805}\r
5806\r
5807\r
5808M68KMAKE_OP(move, 8, pi, .)\r
5809{\r
5810 uint res = M68KMAKE_GET_OPER_AY_8;\r
5811 uint ea = EA_AX_PI_8();\r
5812\r
5813 m68ki_write_8(ea, res);\r
5814\r
5815 FLAG_N = NFLAG_8(res);\r
5816 FLAG_Z = res;\r
5817 FLAG_V = VFLAG_CLEAR;\r
5818 FLAG_C = CFLAG_CLEAR;\r
5819}\r
5820\r
5821\r
5822M68KMAKE_OP(move, 8, pd7, d)\r
5823{\r
5824 uint res = MASK_OUT_ABOVE_8(DY);\r
5825 uint ea = EA_A7_PD_8();\r
5826\r
5827 m68ki_write_8(ea, res);\r
5828\r
5829 FLAG_N = NFLAG_8(res);\r
5830 FLAG_Z = res;\r
5831 FLAG_V = VFLAG_CLEAR;\r
5832 FLAG_C = CFLAG_CLEAR;\r
5833}\r
5834\r
5835\r
5836M68KMAKE_OP(move, 8, pd, d)\r
5837{\r
5838 uint res = MASK_OUT_ABOVE_8(DY);\r
5839 uint ea = EA_AX_PD_8();\r
5840\r
5841 m68ki_write_8(ea, res);\r
5842\r
5843 FLAG_N = NFLAG_8(res);\r
5844 FLAG_Z = res;\r
5845 FLAG_V = VFLAG_CLEAR;\r
5846 FLAG_C = CFLAG_CLEAR;\r
5847}\r
5848\r
5849\r
5850M68KMAKE_OP(move, 8, pd7, .)\r
5851{\r
5852 uint res = M68KMAKE_GET_OPER_AY_8;\r
5853 uint ea = EA_A7_PD_8();\r
5854\r
5855 m68ki_write_8(ea, res);\r
5856\r
5857 FLAG_N = NFLAG_8(res);\r
5858 FLAG_Z = res;\r
5859 FLAG_V = VFLAG_CLEAR;\r
5860 FLAG_C = CFLAG_CLEAR;\r
5861}\r
5862\r
5863\r
5864M68KMAKE_OP(move, 8, pd, .)\r
5865{\r
5866 uint res = M68KMAKE_GET_OPER_AY_8;\r
5867 uint ea = EA_AX_PD_8();\r
5868\r
5869 m68ki_write_8(ea, res);\r
5870\r
5871 FLAG_N = NFLAG_8(res);\r
5872 FLAG_Z = res;\r
5873 FLAG_V = VFLAG_CLEAR;\r
5874 FLAG_C = CFLAG_CLEAR;\r
5875}\r
5876\r
5877\r
5878M68KMAKE_OP(move, 8, di, d)\r
5879{\r
5880 uint res = MASK_OUT_ABOVE_8(DY);\r
5881 uint ea = EA_AX_DI_8();\r
5882\r
5883 m68ki_write_8(ea, res);\r
5884\r
5885 FLAG_N = NFLAG_8(res);\r
5886 FLAG_Z = res;\r
5887 FLAG_V = VFLAG_CLEAR;\r
5888 FLAG_C = CFLAG_CLEAR;\r
5889}\r
5890\r
5891\r
5892M68KMAKE_OP(move, 8, di, .)\r
5893{\r
5894 uint res = M68KMAKE_GET_OPER_AY_8;\r
5895 uint ea = EA_AX_DI_8();\r
5896\r
5897 m68ki_write_8(ea, res);\r
5898\r
5899 FLAG_N = NFLAG_8(res);\r
5900 FLAG_Z = res;\r
5901 FLAG_V = VFLAG_CLEAR;\r
5902 FLAG_C = CFLAG_CLEAR;\r
5903}\r
5904\r
5905\r
5906M68KMAKE_OP(move, 8, ix, d)\r
5907{\r
5908 uint res = MASK_OUT_ABOVE_8(DY);\r
5909 uint ea = EA_AX_IX_8();\r
5910\r
5911 m68ki_write_8(ea, res);\r
5912\r
5913 FLAG_N = NFLAG_8(res);\r
5914 FLAG_Z = res;\r
5915 FLAG_V = VFLAG_CLEAR;\r
5916 FLAG_C = CFLAG_CLEAR;\r
5917}\r
5918\r
5919\r
5920M68KMAKE_OP(move, 8, ix, .)\r
5921{\r
5922 uint res = M68KMAKE_GET_OPER_AY_8;\r
5923 uint ea = EA_AX_IX_8();\r
5924\r
5925 m68ki_write_8(ea, res);\r
5926\r
5927 FLAG_N = NFLAG_8(res);\r
5928 FLAG_Z = res;\r
5929 FLAG_V = VFLAG_CLEAR;\r
5930 FLAG_C = CFLAG_CLEAR;\r
5931}\r
5932\r
5933\r
5934M68KMAKE_OP(move, 8, aw, d)\r
5935{\r
5936 uint res = MASK_OUT_ABOVE_8(DY);\r
5937 uint ea = EA_AW_8();\r
5938\r
5939 m68ki_write_8(ea, res);\r
5940\r
5941 FLAG_N = NFLAG_8(res);\r
5942 FLAG_Z = res;\r
5943 FLAG_V = VFLAG_CLEAR;\r
5944 FLAG_C = CFLAG_CLEAR;\r
5945}\r
5946\r
5947\r
5948M68KMAKE_OP(move, 8, aw, .)\r
5949{\r
5950 uint res = M68KMAKE_GET_OPER_AY_8;\r
5951 uint ea = EA_AW_8();\r
5952\r
5953 m68ki_write_8(ea, res);\r
5954\r
5955 FLAG_N = NFLAG_8(res);\r
5956 FLAG_Z = res;\r
5957 FLAG_V = VFLAG_CLEAR;\r
5958 FLAG_C = CFLAG_CLEAR;\r
5959}\r
5960\r
5961\r
5962M68KMAKE_OP(move, 8, al, d)\r
5963{\r
5964 uint res = MASK_OUT_ABOVE_8(DY);\r
5965 uint ea = EA_AL_8();\r
5966\r
5967 m68ki_write_8(ea, res);\r
5968\r
5969 FLAG_N = NFLAG_8(res);\r
5970 FLAG_Z = res;\r
5971 FLAG_V = VFLAG_CLEAR;\r
5972 FLAG_C = CFLAG_CLEAR;\r
5973}\r
5974\r
5975\r
5976M68KMAKE_OP(move, 8, al, .)\r
5977{\r
5978 uint res = M68KMAKE_GET_OPER_AY_8;\r
5979 uint ea = EA_AL_8();\r
5980\r
5981 m68ki_write_8(ea, res);\r
5982\r
5983 FLAG_N = NFLAG_8(res);\r
5984 FLAG_Z = res;\r
5985 FLAG_V = VFLAG_CLEAR;\r
5986 FLAG_C = CFLAG_CLEAR;\r
5987}\r
5988\r
5989\r
5990M68KMAKE_OP(move, 16, d, d)\r
5991{\r
5992 uint res = MASK_OUT_ABOVE_16(DY);\r
5993 uint* r_dst = &DX;\r
5994\r
5995 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
5996\r
5997 FLAG_N = NFLAG_16(res);\r
5998 FLAG_Z = res;\r
5999 FLAG_V = VFLAG_CLEAR;\r
6000 FLAG_C = CFLAG_CLEAR;\r
6001}\r
6002\r
6003\r
6004M68KMAKE_OP(move, 16, d, a)\r
6005{\r
6006 uint res = MASK_OUT_ABOVE_16(AY);\r
6007 uint* r_dst = &DX;\r
6008\r
6009 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
6010\r
6011 FLAG_N = NFLAG_16(res);\r
6012 FLAG_Z = res;\r
6013 FLAG_V = VFLAG_CLEAR;\r
6014 FLAG_C = CFLAG_CLEAR;\r
6015}\r
6016\r
6017\r
6018M68KMAKE_OP(move, 16, d, .)\r
6019{\r
6020 uint res = M68KMAKE_GET_OPER_AY_16;\r
6021 uint* r_dst = &DX;\r
6022\r
6023 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
6024\r
6025 FLAG_N = NFLAG_16(res);\r
6026 FLAG_Z = res;\r
6027 FLAG_V = VFLAG_CLEAR;\r
6028 FLAG_C = CFLAG_CLEAR;\r
6029}\r
6030\r
6031\r
6032M68KMAKE_OP(move, 16, ai, d)\r
6033{\r
6034 uint res = MASK_OUT_ABOVE_16(DY);\r
6035 uint ea = EA_AX_AI_16();\r
6036\r
6037 m68ki_write_16(ea, res);\r
6038\r
6039 FLAG_N = NFLAG_16(res);\r
6040 FLAG_Z = res;\r
6041 FLAG_V = VFLAG_CLEAR;\r
6042 FLAG_C = CFLAG_CLEAR;\r
6043}\r
6044\r
6045\r
6046M68KMAKE_OP(move, 16, ai, a)\r
6047{\r
6048 uint res = MASK_OUT_ABOVE_16(AY);\r
6049 uint ea = EA_AX_AI_16();\r
6050\r
6051 m68ki_write_16(ea, res);\r
6052\r
6053 FLAG_N = NFLAG_16(res);\r
6054 FLAG_Z = res;\r
6055 FLAG_V = VFLAG_CLEAR;\r
6056 FLAG_C = CFLAG_CLEAR;\r
6057}\r
6058\r
6059\r
6060M68KMAKE_OP(move, 16, ai, .)\r
6061{\r
6062 uint res = M68KMAKE_GET_OPER_AY_16;\r
6063 uint ea = EA_AX_AI_16();\r
6064\r
6065 m68ki_write_16(ea, res);\r
6066\r
6067 FLAG_N = NFLAG_16(res);\r
6068 FLAG_Z = res;\r
6069 FLAG_V = VFLAG_CLEAR;\r
6070 FLAG_C = CFLAG_CLEAR;\r
6071}\r
6072\r
6073\r
6074M68KMAKE_OP(move, 16, pi, d)\r
6075{\r
6076 uint res = MASK_OUT_ABOVE_16(DY);\r
6077 uint ea = EA_AX_PI_16();\r
6078\r
6079 m68ki_write_16(ea, res);\r
6080\r
6081 FLAG_N = NFLAG_16(res);\r
6082 FLAG_Z = res;\r
6083 FLAG_V = VFLAG_CLEAR;\r
6084 FLAG_C = CFLAG_CLEAR;\r
6085}\r
6086\r
6087\r
6088M68KMAKE_OP(move, 16, pi, a)\r
6089{\r
6090 uint res = MASK_OUT_ABOVE_16(AY);\r
6091 uint ea = EA_AX_PI_16();\r
6092\r
6093 m68ki_write_16(ea, res);\r
6094\r
6095 FLAG_N = NFLAG_16(res);\r
6096 FLAG_Z = res;\r
6097 FLAG_V = VFLAG_CLEAR;\r
6098 FLAG_C = CFLAG_CLEAR;\r
6099}\r
6100\r
6101\r
6102M68KMAKE_OP(move, 16, pi, .)\r
6103{\r
6104 uint res = M68KMAKE_GET_OPER_AY_16;\r
6105 uint ea = EA_AX_PI_16();\r
6106\r
6107 m68ki_write_16(ea, res);\r
6108\r
6109 FLAG_N = NFLAG_16(res);\r
6110 FLAG_Z = res;\r
6111 FLAG_V = VFLAG_CLEAR;\r
6112 FLAG_C = CFLAG_CLEAR;\r
6113}\r
6114\r
6115\r
6116M68KMAKE_OP(move, 16, pd, d)\r
6117{\r
6118 uint res = MASK_OUT_ABOVE_16(DY);\r
6119 uint ea = EA_AX_PD_16();\r
6120\r
6121 m68ki_write_16(ea, res);\r
6122\r
6123 FLAG_N = NFLAG_16(res);\r
6124 FLAG_Z = res;\r
6125 FLAG_V = VFLAG_CLEAR;\r
6126 FLAG_C = CFLAG_CLEAR;\r
6127}\r
6128\r
6129\r
6130M68KMAKE_OP(move, 16, pd, a)\r
6131{\r
6132 uint res = MASK_OUT_ABOVE_16(AY);\r
6133 uint ea = EA_AX_PD_16();\r
6134\r
6135 m68ki_write_16(ea, res);\r
6136\r
6137 FLAG_N = NFLAG_16(res);\r
6138 FLAG_Z = res;\r
6139 FLAG_V = VFLAG_CLEAR;\r
6140 FLAG_C = CFLAG_CLEAR;\r
6141}\r
6142\r
6143\r
6144M68KMAKE_OP(move, 16, pd, .)\r
6145{\r
6146 uint res = M68KMAKE_GET_OPER_AY_16;\r
6147 uint ea = EA_AX_PD_16();\r
6148\r
6149 m68ki_write_16(ea, res);\r
6150\r
6151 FLAG_N = NFLAG_16(res);\r
6152 FLAG_Z = res;\r
6153 FLAG_V = VFLAG_CLEAR;\r
6154 FLAG_C = CFLAG_CLEAR;\r
6155}\r
6156\r
6157\r
6158M68KMAKE_OP(move, 16, di, d)\r
6159{\r
6160 uint res = MASK_OUT_ABOVE_16(DY);\r
6161 uint ea = EA_AX_DI_16();\r
6162\r
6163 m68ki_write_16(ea, res);\r
6164\r
6165 FLAG_N = NFLAG_16(res);\r
6166 FLAG_Z = res;\r
6167 FLAG_V = VFLAG_CLEAR;\r
6168 FLAG_C = CFLAG_CLEAR;\r
6169}\r
6170\r
6171\r
6172M68KMAKE_OP(move, 16, di, a)\r
6173{\r
6174 uint res = MASK_OUT_ABOVE_16(AY);\r
6175 uint ea = EA_AX_DI_16();\r
6176\r
6177 m68ki_write_16(ea, res);\r
6178\r
6179 FLAG_N = NFLAG_16(res);\r
6180 FLAG_Z = res;\r
6181 FLAG_V = VFLAG_CLEAR;\r
6182 FLAG_C = CFLAG_CLEAR;\r
6183}\r
6184\r
6185\r
6186M68KMAKE_OP(move, 16, di, .)\r
6187{\r
6188 uint res = M68KMAKE_GET_OPER_AY_16;\r
6189 uint ea = EA_AX_DI_16();\r
6190\r
6191 m68ki_write_16(ea, res);\r
6192\r
6193 FLAG_N = NFLAG_16(res);\r
6194 FLAG_Z = res;\r
6195 FLAG_V = VFLAG_CLEAR;\r
6196 FLAG_C = CFLAG_CLEAR;\r
6197}\r
6198\r
6199\r
6200M68KMAKE_OP(move, 16, ix, d)\r
6201{\r
6202 uint res = MASK_OUT_ABOVE_16(DY);\r
6203 uint ea = EA_AX_IX_16();\r
6204\r
6205 m68ki_write_16(ea, res);\r
6206\r
6207 FLAG_N = NFLAG_16(res);\r
6208 FLAG_Z = res;\r
6209 FLAG_V = VFLAG_CLEAR;\r
6210 FLAG_C = CFLAG_CLEAR;\r
6211}\r
6212\r
6213\r
6214M68KMAKE_OP(move, 16, ix, a)\r
6215{\r
6216 uint res = MASK_OUT_ABOVE_16(AY);\r
6217 uint ea = EA_AX_IX_16();\r
6218\r
6219 m68ki_write_16(ea, res);\r
6220\r
6221 FLAG_N = NFLAG_16(res);\r
6222 FLAG_Z = res;\r
6223 FLAG_V = VFLAG_CLEAR;\r
6224 FLAG_C = CFLAG_CLEAR;\r
6225}\r
6226\r
6227\r
6228M68KMAKE_OP(move, 16, ix, .)\r
6229{\r
6230 uint res = M68KMAKE_GET_OPER_AY_16;\r
6231 uint ea = EA_AX_IX_16();\r
6232\r
6233 m68ki_write_16(ea, res);\r
6234\r
6235 FLAG_N = NFLAG_16(res);\r
6236 FLAG_Z = res;\r
6237 FLAG_V = VFLAG_CLEAR;\r
6238 FLAG_C = CFLAG_CLEAR;\r
6239}\r
6240\r
6241\r
6242M68KMAKE_OP(move, 16, aw, d)\r
6243{\r
6244 uint res = MASK_OUT_ABOVE_16(DY);\r
6245 uint ea = EA_AW_16();\r
6246\r
6247 m68ki_write_16(ea, res);\r
6248\r
6249 FLAG_N = NFLAG_16(res);\r
6250 FLAG_Z = res;\r
6251 FLAG_V = VFLAG_CLEAR;\r
6252 FLAG_C = CFLAG_CLEAR;\r
6253}\r
6254\r
6255\r
6256M68KMAKE_OP(move, 16, aw, a)\r
6257{\r
6258 uint res = MASK_OUT_ABOVE_16(AY);\r
6259 uint ea = EA_AW_16();\r
6260\r
6261 m68ki_write_16(ea, res);\r
6262\r
6263 FLAG_N = NFLAG_16(res);\r
6264 FLAG_Z = res;\r
6265 FLAG_V = VFLAG_CLEAR;\r
6266 FLAG_C = CFLAG_CLEAR;\r
6267}\r
6268\r
6269\r
6270M68KMAKE_OP(move, 16, aw, .)\r
6271{\r
6272 uint res = M68KMAKE_GET_OPER_AY_16;\r
6273 uint ea = EA_AW_16();\r
6274\r
6275 m68ki_write_16(ea, res);\r
6276\r
6277 FLAG_N = NFLAG_16(res);\r
6278 FLAG_Z = res;\r
6279 FLAG_V = VFLAG_CLEAR;\r
6280 FLAG_C = CFLAG_CLEAR;\r
6281}\r
6282\r
6283\r
6284M68KMAKE_OP(move, 16, al, d)\r
6285{\r
6286 uint res = MASK_OUT_ABOVE_16(DY);\r
6287 uint ea = EA_AL_16();\r
6288\r
6289 m68ki_write_16(ea, res);\r
6290\r
6291 FLAG_N = NFLAG_16(res);\r
6292 FLAG_Z = res;\r
6293 FLAG_V = VFLAG_CLEAR;\r
6294 FLAG_C = CFLAG_CLEAR;\r
6295}\r
6296\r
6297\r
6298M68KMAKE_OP(move, 16, al, a)\r
6299{\r
6300 uint res = MASK_OUT_ABOVE_16(AY);\r
6301 uint ea = EA_AL_16();\r
6302\r
6303 m68ki_write_16(ea, res);\r
6304\r
6305 FLAG_N = NFLAG_16(res);\r
6306 FLAG_Z = res;\r
6307 FLAG_V = VFLAG_CLEAR;\r
6308 FLAG_C = CFLAG_CLEAR;\r
6309}\r
6310\r
6311\r
6312M68KMAKE_OP(move, 16, al, .)\r
6313{\r
6314 uint res = M68KMAKE_GET_OPER_AY_16;\r
6315 uint ea = EA_AL_16();\r
6316\r
6317 m68ki_write_16(ea, res);\r
6318\r
6319 FLAG_N = NFLAG_16(res);\r
6320 FLAG_Z = res;\r
6321 FLAG_V = VFLAG_CLEAR;\r
6322 FLAG_C = CFLAG_CLEAR;\r
6323}\r
6324\r
6325\r
6326M68KMAKE_OP(move, 32, d, d)\r
6327{\r
6328 uint res = DY;\r
6329 uint* r_dst = &DX;\r
6330\r
6331 *r_dst = res;\r
6332\r
6333 FLAG_N = NFLAG_32(res);\r
6334 FLAG_Z = res;\r
6335 FLAG_V = VFLAG_CLEAR;\r
6336 FLAG_C = CFLAG_CLEAR;\r
6337}\r
6338\r
6339\r
6340M68KMAKE_OP(move, 32, d, a)\r
6341{\r
6342 uint res = AY;\r
6343 uint* r_dst = &DX;\r
6344\r
6345 *r_dst = res;\r
6346\r
6347 FLAG_N = NFLAG_32(res);\r
6348 FLAG_Z = res;\r
6349 FLAG_V = VFLAG_CLEAR;\r
6350 FLAG_C = CFLAG_CLEAR;\r
6351}\r
6352\r
6353\r
6354M68KMAKE_OP(move, 32, d, .)\r
6355{\r
6356 uint res = M68KMAKE_GET_OPER_AY_32;\r
6357 uint* r_dst = &DX;\r
6358\r
6359 *r_dst = res;\r
6360\r
6361 FLAG_N = NFLAG_32(res);\r
6362 FLAG_Z = res;\r
6363 FLAG_V = VFLAG_CLEAR;\r
6364 FLAG_C = CFLAG_CLEAR;\r
6365}\r
6366\r
6367\r
6368M68KMAKE_OP(move, 32, ai, d)\r
6369{\r
6370 uint res = DY;\r
6371 uint ea = EA_AX_AI_32();\r
6372\r
6373 m68ki_write_32(ea, res);\r
6374\r
6375 FLAG_N = NFLAG_32(res);\r
6376 FLAG_Z = res;\r
6377 FLAG_V = VFLAG_CLEAR;\r
6378 FLAG_C = CFLAG_CLEAR;\r
6379}\r
6380\r
6381\r
6382M68KMAKE_OP(move, 32, ai, a)\r
6383{\r
6384 uint res = AY;\r
6385 uint ea = EA_AX_AI_32();\r
6386\r
6387 m68ki_write_32(ea, res);\r
6388\r
6389 FLAG_N = NFLAG_32(res);\r
6390 FLAG_Z = res;\r
6391 FLAG_V = VFLAG_CLEAR;\r
6392 FLAG_C = CFLAG_CLEAR;\r
6393}\r
6394\r
6395\r
6396M68KMAKE_OP(move, 32, ai, .)\r
6397{\r
6398 uint res = M68KMAKE_GET_OPER_AY_32;\r
6399 uint ea = EA_AX_AI_32();\r
6400\r
6401 m68ki_write_32(ea, res);\r
6402\r
6403 FLAG_N = NFLAG_32(res);\r
6404 FLAG_Z = res;\r
6405 FLAG_V = VFLAG_CLEAR;\r
6406 FLAG_C = CFLAG_CLEAR;\r
6407}\r
6408\r
6409\r
6410M68KMAKE_OP(move, 32, pi, d)\r
6411{\r
6412 uint res = DY;\r
6413 uint ea = EA_AX_PI_32();\r
6414\r
6415 m68ki_write_32(ea, res);\r
6416\r
6417 FLAG_N = NFLAG_32(res);\r
6418 FLAG_Z = res;\r
6419 FLAG_V = VFLAG_CLEAR;\r
6420 FLAG_C = CFLAG_CLEAR;\r
6421}\r
6422\r
6423\r
6424M68KMAKE_OP(move, 32, pi, a)\r
6425{\r
6426 uint res = AY;\r
6427 uint ea = EA_AX_PI_32();\r
6428\r
6429 m68ki_write_32(ea, res);\r
6430\r
6431 FLAG_N = NFLAG_32(res);\r
6432 FLAG_Z = res;\r
6433 FLAG_V = VFLAG_CLEAR;\r
6434 FLAG_C = CFLAG_CLEAR;\r
6435}\r
6436\r
6437\r
6438M68KMAKE_OP(move, 32, pi, .)\r
6439{\r
6440 uint res = M68KMAKE_GET_OPER_AY_32;\r
6441 uint ea = EA_AX_PI_32();\r
6442\r
6443 m68ki_write_32(ea, res);\r
6444\r
6445 FLAG_N = NFLAG_32(res);\r
6446 FLAG_Z = res;\r
6447 FLAG_V = VFLAG_CLEAR;\r
6448 FLAG_C = CFLAG_CLEAR;\r
6449}\r
6450\r
6451\r
6452M68KMAKE_OP(move, 32, pd, d)\r
6453{\r
6454 uint res = DY;\r
6455 uint ea = EA_AX_PD_32();\r
6456\r
c6a4c892 6457 m68ki_write_16(ea+2, res & 0xFFFF );\r
6458 m68ki_write_16(ea, (res >> 16) & 0xFFFF );\r
cc68a136 6459\r
6460 FLAG_N = NFLAG_32(res);\r
6461 FLAG_Z = res;\r
6462 FLAG_V = VFLAG_CLEAR;\r
6463 FLAG_C = CFLAG_CLEAR;\r
6464}\r
6465\r
6466\r
6467M68KMAKE_OP(move, 32, pd, a)\r
6468{\r
6469 uint res = AY;\r
6470 uint ea = EA_AX_PD_32();\r
6471\r
c6a4c892 6472 m68ki_write_16(ea+2, res & 0xFFFF );\r
6473 m68ki_write_16(ea, (res >> 16) & 0xFFFF );\r
cc68a136 6474\r
6475 FLAG_N = NFLAG_32(res);\r
6476 FLAG_Z = res;\r
6477 FLAG_V = VFLAG_CLEAR;\r
6478 FLAG_C = CFLAG_CLEAR;\r
6479}\r
6480\r
6481\r
6482M68KMAKE_OP(move, 32, pd, .)\r
6483{\r
6484 uint res = M68KMAKE_GET_OPER_AY_32;\r
6485 uint ea = EA_AX_PD_32();\r
6486\r
c6a4c892 6487 m68ki_write_16(ea+2, res & 0xFFFF );\r
6488 m68ki_write_16(ea, (res >> 16) & 0xFFFF );\r
cc68a136 6489\r
6490 FLAG_N = NFLAG_32(res);\r
6491 FLAG_Z = res;\r
6492 FLAG_V = VFLAG_CLEAR;\r
6493 FLAG_C = CFLAG_CLEAR;\r
6494}\r
6495\r
6496\r
6497M68KMAKE_OP(move, 32, di, d)\r
6498{\r
6499 uint res = DY;\r
6500 uint ea = EA_AX_DI_32();\r
6501\r
6502 m68ki_write_32(ea, res);\r
6503\r
6504 FLAG_N = NFLAG_32(res);\r
6505 FLAG_Z = res;\r
6506 FLAG_V = VFLAG_CLEAR;\r
6507 FLAG_C = CFLAG_CLEAR;\r
6508}\r
6509\r
6510\r
6511M68KMAKE_OP(move, 32, di, a)\r
6512{\r
6513 uint res = AY;\r
6514 uint ea = EA_AX_DI_32();\r
6515\r
6516 m68ki_write_32(ea, res);\r
6517\r
6518 FLAG_N = NFLAG_32(res);\r
6519 FLAG_Z = res;\r
6520 FLAG_V = VFLAG_CLEAR;\r
6521 FLAG_C = CFLAG_CLEAR;\r
6522}\r
6523\r
6524\r
6525M68KMAKE_OP(move, 32, di, .)\r
6526{\r
6527 uint res = M68KMAKE_GET_OPER_AY_32;\r
6528 uint ea = EA_AX_DI_32();\r
6529\r
6530 m68ki_write_32(ea, res);\r
6531\r
6532 FLAG_N = NFLAG_32(res);\r
6533 FLAG_Z = res;\r
6534 FLAG_V = VFLAG_CLEAR;\r
6535 FLAG_C = CFLAG_CLEAR;\r
6536}\r
6537\r
6538\r
6539M68KMAKE_OP(move, 32, ix, d)\r
6540{\r
6541 uint res = DY;\r
6542 uint ea = EA_AX_IX_32();\r
6543\r
6544 m68ki_write_32(ea, res);\r
6545\r
6546 FLAG_N = NFLAG_32(res);\r
6547 FLAG_Z = res;\r
6548 FLAG_V = VFLAG_CLEAR;\r
6549 FLAG_C = CFLAG_CLEAR;\r
6550}\r
6551\r
6552\r
6553M68KMAKE_OP(move, 32, ix, a)\r
6554{\r
6555 uint res = AY;\r
6556 uint ea = EA_AX_IX_32();\r
6557\r
6558 m68ki_write_32(ea, res);\r
6559\r
6560 FLAG_N = NFLAG_32(res);\r
6561 FLAG_Z = res;\r
6562 FLAG_V = VFLAG_CLEAR;\r
6563 FLAG_C = CFLAG_CLEAR;\r
6564}\r
6565\r
6566\r
6567M68KMAKE_OP(move, 32, ix, .)\r
6568{\r
6569 uint res = M68KMAKE_GET_OPER_AY_32;\r
6570 uint ea = EA_AX_IX_32();\r
6571\r
6572 m68ki_write_32(ea, res);\r
6573\r
6574 FLAG_N = NFLAG_32(res);\r
6575 FLAG_Z = res;\r
6576 FLAG_V = VFLAG_CLEAR;\r
6577 FLAG_C = CFLAG_CLEAR;\r
6578}\r
6579\r
6580\r
6581M68KMAKE_OP(move, 32, aw, d)\r
6582{\r
6583 uint res = DY;\r
6584 uint ea = EA_AW_32();\r
6585\r
6586 m68ki_write_32(ea, res);\r
6587\r
6588 FLAG_N = NFLAG_32(res);\r
6589 FLAG_Z = res;\r
6590 FLAG_V = VFLAG_CLEAR;\r
6591 FLAG_C = CFLAG_CLEAR;\r
6592}\r
6593\r
6594\r
6595M68KMAKE_OP(move, 32, aw, a)\r
6596{\r
6597 uint res = AY;\r
6598 uint ea = EA_AW_32();\r
6599\r
6600 m68ki_write_32(ea, res);\r
6601\r
6602 FLAG_N = NFLAG_32(res);\r
6603 FLAG_Z = res;\r
6604 FLAG_V = VFLAG_CLEAR;\r
6605 FLAG_C = CFLAG_CLEAR;\r
6606}\r
6607\r
6608\r
6609M68KMAKE_OP(move, 32, aw, .)\r
6610{\r
6611 uint res = M68KMAKE_GET_OPER_AY_32;\r
6612 uint ea = EA_AW_32();\r
6613\r
6614 m68ki_write_32(ea, res);\r
6615\r
6616 FLAG_N = NFLAG_32(res);\r
6617 FLAG_Z = res;\r
6618 FLAG_V = VFLAG_CLEAR;\r
6619 FLAG_C = CFLAG_CLEAR;\r
6620}\r
6621\r
6622\r
6623M68KMAKE_OP(move, 32, al, d)\r
6624{\r
6625 uint res = DY;\r
6626 uint ea = EA_AL_32();\r
6627\r
6628 m68ki_write_32(ea, res);\r
6629\r
6630 FLAG_N = NFLAG_32(res);\r
6631 FLAG_Z = res;\r
6632 FLAG_V = VFLAG_CLEAR;\r
6633 FLAG_C = CFLAG_CLEAR;\r
6634}\r
6635\r
6636\r
6637M68KMAKE_OP(move, 32, al, a)\r
6638{\r
6639 uint res = AY;\r
6640 uint ea = EA_AL_32();\r
6641\r
6642 m68ki_write_32(ea, res);\r
6643\r
6644 FLAG_N = NFLAG_32(res);\r
6645 FLAG_Z = res;\r
6646 FLAG_V = VFLAG_CLEAR;\r
6647 FLAG_C = CFLAG_CLEAR;\r
6648}\r
6649\r
6650\r
6651M68KMAKE_OP(move, 32, al, .)\r
6652{\r
6653 uint res = M68KMAKE_GET_OPER_AY_32;\r
6654 uint ea = EA_AL_32();\r
6655\r
6656 m68ki_write_32(ea, res);\r
6657\r
6658 FLAG_N = NFLAG_32(res);\r
6659 FLAG_Z = res;\r
6660 FLAG_V = VFLAG_CLEAR;\r
6661 FLAG_C = CFLAG_CLEAR;\r
6662}\r
6663\r
6664\r
6665M68KMAKE_OP(movea, 16, ., d)\r
6666{\r
6667 AX = MAKE_INT_16(DY);\r
6668}\r
6669\r
6670\r
6671M68KMAKE_OP(movea, 16, ., a)\r
6672{\r
6673 AX = MAKE_INT_16(AY);\r
6674}\r
6675\r
6676\r
6677M68KMAKE_OP(movea, 16, ., .)\r
6678{\r
6679 AX = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);\r
6680}\r
6681\r
6682\r
6683M68KMAKE_OP(movea, 32, ., d)\r
6684{\r
6685 AX = DY;\r
6686}\r
6687\r
6688\r
6689M68KMAKE_OP(movea, 32, ., a)\r
6690{\r
6691 AX = AY;\r
6692}\r
6693\r
6694\r
6695M68KMAKE_OP(movea, 32, ., .)\r
6696{\r
6697 AX = M68KMAKE_GET_OPER_AY_32;\r
6698}\r
6699\r
6700\r
6701M68KMAKE_OP(move, 16, frc, d)\r
6702{\r
6703 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))\r
6704 {\r
6705 DY = MASK_OUT_BELOW_16(DY) | m68ki_get_ccr();\r
6706 return;\r
6707 }\r
6708 m68ki_exception_illegal();\r
6709}\r
6710\r
6711\r
6712M68KMAKE_OP(move, 16, frc, .)\r
6713{\r
6714 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))\r
6715 {\r
6716 m68ki_write_16(M68KMAKE_GET_EA_AY_16, m68ki_get_ccr());\r
6717 return;\r
6718 }\r
6719 m68ki_exception_illegal();\r
6720}\r
6721\r
6722\r
6723M68KMAKE_OP(move, 16, toc, d)\r
6724{\r
6725 m68ki_set_ccr(DY);\r
6726}\r
6727\r
6728\r
6729M68KMAKE_OP(move, 16, toc, .)\r
6730{\r
6731 m68ki_set_ccr(M68KMAKE_GET_OPER_AY_16);\r
6732}\r
6733\r
6734\r
6735M68KMAKE_OP(move, 16, frs, d)\r
6736{\r
6737 if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */\r
6738 {\r
6739 DY = MASK_OUT_BELOW_16(DY) | m68ki_get_sr();\r
6740 return;\r
6741 }\r
6742 m68ki_exception_privilege_violation();\r
6743}\r
6744\r
6745\r
6746M68KMAKE_OP(move, 16, frs, .)\r
6747{\r
6748 if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */\r
6749 {\r
6750 uint ea = M68KMAKE_GET_EA_AY_16;\r
6751 m68ki_write_16(ea, m68ki_get_sr());\r
6752 return;\r
6753 }\r
6754 m68ki_exception_privilege_violation();\r
6755}\r
6756\r
6757\r
6758M68KMAKE_OP(move, 16, tos, d)\r
6759{\r
6760 if(FLAG_S)\r
6761 {\r
6762 m68ki_set_sr(DY);\r
6763 return;\r
6764 }\r
6765 m68ki_exception_privilege_violation();\r
6766}\r
6767\r
6768\r
6769M68KMAKE_OP(move, 16, tos, .)\r
6770{\r
6771 if(FLAG_S)\r
6772 {\r
6773 uint new_sr = M68KMAKE_GET_OPER_AY_16;\r
6774 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
6775 m68ki_set_sr(new_sr);\r
6776 return;\r
6777 }\r
6778 m68ki_exception_privilege_violation();\r
6779}\r
6780\r
6781\r
6782M68KMAKE_OP(move, 32, fru, .)\r
6783{\r
6784 if(FLAG_S)\r
6785 {\r
6786 AY = REG_USP;\r
6787 return;\r
6788 }\r
6789 m68ki_exception_privilege_violation();\r
6790}\r
6791\r
6792\r
6793M68KMAKE_OP(move, 32, tou, .)\r
6794{\r
6795 if(FLAG_S)\r
6796 {\r
6797 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
6798 REG_USP = AY;\r
6799 return;\r
6800 }\r
6801 m68ki_exception_privilege_violation();\r
6802}\r
6803\r
6804\r
6805M68KMAKE_OP(movec, 32, cr, .)\r
6806{\r
6807 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))\r
6808 {\r
6809 if(FLAG_S)\r
6810 {\r
6811 uint word2 = OPER_I_16();\r
6812\r
6813 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
6814 switch (word2 & 0xfff)\r
6815 {\r
6816 case 0x000: /* SFC */\r
6817 REG_DA[(word2 >> 12) & 15] = REG_SFC;\r
6818 return;\r
6819 case 0x001: /* DFC */\r
6820 REG_DA[(word2 >> 12) & 15] = REG_DFC;\r
6821 return;\r
6822 case 0x002: /* CACR */\r
6823 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
6824 {\r
6825 REG_DA[(word2 >> 12) & 15] = REG_CACR;\r
6826 return;\r
6827 }\r
6828 return;\r
6829 case 0x800: /* USP */\r
6830 REG_DA[(word2 >> 12) & 15] = REG_USP;\r
6831 return;\r
6832 case 0x801: /* VBR */\r
6833 REG_DA[(word2 >> 12) & 15] = REG_VBR;\r
6834 return;\r
6835 case 0x802: /* CAAR */\r
6836 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
6837 {\r
6838 REG_DA[(word2 >> 12) & 15] = REG_CAAR;\r
6839 return;\r
6840 }\r
6841 m68ki_exception_illegal();\r
6842 break;\r
6843 case 0x803: /* MSP */\r
6844 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
6845 {\r
6846 REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_SP : REG_MSP;\r
6847 return;\r
6848 }\r
6849 m68ki_exception_illegal();\r
6850 return;\r
6851 case 0x804: /* ISP */\r
6852 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
6853 {\r
6854 REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_ISP : REG_SP;\r
6855 return;\r
6856 }\r
6857 m68ki_exception_illegal();\r
6858 return;\r
6859 case 0x003: /* TC */\r
6860 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
6861 {\r
6862 /* TODO */\r
6863 return;\r
6864 }\r
6865 m68ki_exception_illegal();\r
6866 return;\r
6867 case 0x004: /* ITT0 */\r
6868 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
6869 {\r
6870 /* TODO */\r
6871 return;\r
6872 }\r
6873 m68ki_exception_illegal();\r
6874 return;\r
6875 case 0x005: /* ITT1 */\r
6876 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
6877 {\r
6878 /* TODO */\r
6879 return;\r
6880 }\r
6881 m68ki_exception_illegal();\r
6882 return;\r
6883 case 0x006: /* DTT0 */\r
6884 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
6885 {\r
6886 /* TODO */\r
6887 return;\r
6888 }\r
6889 m68ki_exception_illegal();\r
6890 return;\r
6891 case 0x007: /* DTT1 */\r
6892 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
6893 {\r
6894 /* TODO */\r
6895 return;\r
6896 }\r
6897 m68ki_exception_illegal();\r
6898 return;\r
6899 case 0x805: /* MMUSR */\r
6900 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
6901 {\r
6902 /* TODO */\r
6903 return;\r
6904 }\r
6905 m68ki_exception_illegal();\r
6906 return;\r
6907 case 0x806: /* URP */\r
6908 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
6909 {\r
6910 /* TODO */\r
6911 return;\r
6912 }\r
6913 m68ki_exception_illegal();\r
6914 return;\r
6915 case 0x807: /* SRP */\r
6916 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
6917 {\r
6918 /* TODO */\r
6919 return;\r
6920 }\r
6921 m68ki_exception_illegal();\r
6922 return;\r
6923 default:\r
6924 m68ki_exception_illegal();\r
6925 return;\r
6926 }\r
6927 }\r
6928 m68ki_exception_privilege_violation();\r
6929 return;\r
6930 }\r
6931 m68ki_exception_illegal();\r
6932}\r
6933\r
6934\r
6935M68KMAKE_OP(movec, 32, rc, .)\r
6936{\r
6937 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))\r
6938 {\r
6939 if(FLAG_S)\r
6940 {\r
6941 uint word2 = OPER_I_16();\r
6942\r
6943 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
6944 switch (word2 & 0xfff)\r
6945 {\r
6946 case 0x000: /* SFC */\r
6947 REG_SFC = REG_DA[(word2 >> 12) & 15] & 7;\r
6948 return;\r
6949 case 0x001: /* DFC */\r
6950 REG_DFC = REG_DA[(word2 >> 12) & 15] & 7;\r
6951 return;\r
6952 case 0x002: /* CACR */\r
6953 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
6954 {\r
c6a4c892 6955 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
6956 {\r
6957 REG_CACR = REG_DA[(word2 >> 12) & 15];\r
6958 }\r
6959 else\r
6960 {\r
6961 /* non 68040 can only set the lower 4 bits (C,CE,F,E) */\r
6962 REG_CACR = REG_DA[(word2 >> 12) & 15] & 0x0f;\r
6963 }\r
cc68a136 6964 return;\r
6965 }\r
6966 m68ki_exception_illegal();\r
6967 return;\r
6968 case 0x800: /* USP */\r
6969 REG_USP = REG_DA[(word2 >> 12) & 15];\r
6970 return;\r
6971 case 0x801: /* VBR */\r
6972 REG_VBR = REG_DA[(word2 >> 12) & 15];\r
6973 return;\r
6974 case 0x802: /* CAAR */\r
6975 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
6976 {\r
6977 REG_CAAR = REG_DA[(word2 >> 12) & 15];\r
6978 return;\r
6979 }\r
6980 m68ki_exception_illegal();\r
6981 return;\r
6982 case 0x803: /* MSP */\r
6983 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
6984 {\r
6985 /* we are in supervisor mode so just check for M flag */\r
6986 if(!FLAG_M)\r
6987 {\r
6988 REG_MSP = REG_DA[(word2 >> 12) & 15];\r
6989 return;\r
6990 }\r
6991 REG_SP = REG_DA[(word2 >> 12) & 15];\r
6992 return;\r
6993 }\r
6994 m68ki_exception_illegal();\r
6995 return;\r
6996 case 0x804: /* ISP */\r
6997 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
6998 {\r
6999 if(!FLAG_M)\r
7000 {\r
7001 REG_SP = REG_DA[(word2 >> 12) & 15];\r
7002 return;\r
7003 }\r
7004 REG_ISP = REG_DA[(word2 >> 12) & 15];\r
7005 return;\r
7006 }\r
7007 m68ki_exception_illegal();\r
7008 return;\r
7009 case 0x003: /* TC */\r
7010 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
7011 {\r
7012 /* TODO */\r
7013 return;\r
7014 }\r
7015 m68ki_exception_illegal();\r
7016 return;\r
7017 case 0x004: /* ITT0 */\r
7018 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
7019 {\r
7020 /* TODO */\r
7021 return;\r
7022 }\r
7023 m68ki_exception_illegal();\r
7024 return;\r
7025 case 0x005: /* ITT1 */\r
7026 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
7027 {\r
7028 /* TODO */\r
7029 return;\r
7030 }\r
7031 m68ki_exception_illegal();\r
7032 return;\r
7033 case 0x006: /* DTT0 */\r
7034 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
7035 {\r
7036 /* TODO */\r
7037 return;\r
7038 }\r
7039 m68ki_exception_illegal();\r
7040 return;\r
7041 case 0x007: /* DTT1 */\r
7042 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
7043 {\r
7044 /* TODO */\r
7045 return;\r
7046 }\r
7047 m68ki_exception_illegal();\r
7048 return;\r
7049 case 0x805: /* MMUSR */\r
7050 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
7051 {\r
7052 /* TODO */\r
7053 return;\r
7054 }\r
7055 m68ki_exception_illegal();\r
7056 return;\r
7057 case 0x806: /* URP */\r
7058 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
7059 {\r
7060 /* TODO */\r
7061 return;\r
7062 }\r
7063 m68ki_exception_illegal();\r
7064 return;\r
7065 case 0x807: /* SRP */\r
7066 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
7067 {\r
7068 /* TODO */\r
7069 return;\r
7070 }\r
7071 m68ki_exception_illegal();\r
7072 return;\r
7073 default:\r
7074 m68ki_exception_illegal();\r
7075 return;\r
7076 }\r
7077 }\r
7078 m68ki_exception_privilege_violation();\r
7079 return;\r
7080 }\r
7081 m68ki_exception_illegal();\r
7082}\r
7083\r
7084\r
7085M68KMAKE_OP(movem, 16, re, pd)\r
7086{\r
7087 uint i = 0;\r
7088 uint register_list = OPER_I_16();\r
7089 uint ea = AY;\r
7090 uint count = 0;\r
7091\r
7092 for(; i < 16; i++)\r
7093 if(register_list & (1 << i))\r
7094 {\r
7095 ea -= 2;\r
7096 m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[15-i]));\r
7097 count++;\r
7098 }\r
7099 AY = ea;\r
7100\r
7101 USE_CYCLES(count<<CYC_MOVEM_W);\r
7102}\r
7103\r
7104\r
7105M68KMAKE_OP(movem, 16, re, .)\r
7106{\r
7107 uint i = 0;\r
7108 uint register_list = OPER_I_16();\r
7109 uint ea = M68KMAKE_GET_EA_AY_16;\r
7110 uint count = 0;\r
7111\r
7112 for(; i < 16; i++)\r
7113 if(register_list & (1 << i))\r
7114 {\r
7115 m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[i]));\r
7116 ea += 2;\r
7117 count++;\r
7118 }\r
7119\r
7120 USE_CYCLES(count<<CYC_MOVEM_W);\r
7121}\r
7122\r
7123\r
7124M68KMAKE_OP(movem, 32, re, pd)\r
7125{\r
7126 uint i = 0;\r
7127 uint register_list = OPER_I_16();\r
7128 uint ea = AY;\r
7129 uint count = 0;\r
7130\r
7131 for(; i < 16; i++)\r
7132 if(register_list & (1 << i))\r
7133 {\r
7134 ea -= 4;\r
c6a4c892 7135 m68ki_write_16(ea+2, REG_DA[15-i] & 0xFFFF );\r
7136 m68ki_write_16(ea, (REG_DA[15-i] >> 16) & 0xFFFF );\r
cc68a136 7137 count++;\r
7138 }\r
7139 AY = ea;\r
7140\r
7141 USE_CYCLES(count<<CYC_MOVEM_L);\r
7142}\r
7143\r
7144\r
7145M68KMAKE_OP(movem, 32, re, .)\r
7146{\r
7147 uint i = 0;\r
7148 uint register_list = OPER_I_16();\r
7149 uint ea = M68KMAKE_GET_EA_AY_32;\r
7150 uint count = 0;\r
7151\r
7152 for(; i < 16; i++)\r
7153 if(register_list & (1 << i))\r
7154 {\r
7155 m68ki_write_32(ea, REG_DA[i]);\r
7156 ea += 4;\r
7157 count++;\r
7158 }\r
7159\r
7160 USE_CYCLES(count<<CYC_MOVEM_L);\r
7161}\r
7162\r
7163\r
7164M68KMAKE_OP(movem, 16, er, pi)\r
7165{\r
7166 uint i = 0;\r
7167 uint register_list = OPER_I_16();\r
7168 uint ea = AY;\r
7169 uint count = 0;\r
7170\r
7171 for(; i < 16; i++)\r
7172 if(register_list & (1 << i))\r
7173 {\r
7174 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));\r
7175 ea += 2;\r
7176 count++;\r
7177 }\r
7178 AY = ea;\r
7179\r
7180 USE_CYCLES(count<<CYC_MOVEM_W);\r
7181}\r
7182\r
7183\r
7184M68KMAKE_OP(movem, 16, er, pcdi)\r
7185{\r
7186 uint i = 0;\r
7187 uint register_list = OPER_I_16();\r
7188 uint ea = EA_PCDI_16();\r
7189 uint count = 0;\r
7190\r
7191 for(; i < 16; i++)\r
7192 if(register_list & (1 << i))\r
7193 {\r
7194 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_pcrel_16(ea)));\r
7195 ea += 2;\r
7196 count++;\r
7197 }\r
7198\r
7199 USE_CYCLES(count<<CYC_MOVEM_W);\r
7200}\r
7201\r
7202\r
7203M68KMAKE_OP(movem, 16, er, pcix)\r
7204{\r
7205 uint i = 0;\r
7206 uint register_list = OPER_I_16();\r
7207 uint ea = EA_PCIX_16();\r
7208 uint count = 0;\r
7209\r
7210 for(; i < 16; i++)\r
7211 if(register_list & (1 << i))\r
7212 {\r
7213 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_pcrel_16(ea)));\r
7214 ea += 2;\r
7215 count++;\r
7216 }\r
7217\r
7218 USE_CYCLES(count<<CYC_MOVEM_W);\r
7219}\r
7220\r
7221\r
7222M68KMAKE_OP(movem, 16, er, .)\r
7223{\r
7224 uint i = 0;\r
7225 uint register_list = OPER_I_16();\r
7226 uint ea = M68KMAKE_GET_EA_AY_16;\r
7227 uint count = 0;\r
7228\r
7229 for(; i < 16; i++)\r
7230 if(register_list & (1 << i))\r
7231 {\r
7232 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));\r
7233 ea += 2;\r
7234 count++;\r
7235 }\r
7236\r
7237 USE_CYCLES(count<<CYC_MOVEM_W);\r
7238}\r
7239\r
7240\r
7241M68KMAKE_OP(movem, 32, er, pi)\r
7242{\r
7243 uint i = 0;\r
7244 uint register_list = OPER_I_16();\r
7245 uint ea = AY;\r
7246 uint count = 0;\r
7247\r
7248 for(; i < 16; i++)\r
7249 if(register_list & (1 << i))\r
7250 {\r
7251 REG_DA[i] = m68ki_read_32(ea);\r
7252 ea += 4;\r
7253 count++;\r
7254 }\r
7255 AY = ea;\r
7256\r
7257 USE_CYCLES(count<<CYC_MOVEM_L);\r
7258}\r
7259\r
7260\r
7261M68KMAKE_OP(movem, 32, er, pcdi)\r
7262{\r
7263 uint i = 0;\r
7264 uint register_list = OPER_I_16();\r
7265 uint ea = EA_PCDI_32();\r
7266 uint count = 0;\r
7267\r
7268 for(; i < 16; i++)\r
7269 if(register_list & (1 << i))\r
7270 {\r
7271 REG_DA[i] = m68ki_read_pcrel_32(ea);\r
7272 ea += 4;\r
7273 count++;\r
7274 }\r
7275\r
7276 USE_CYCLES(count<<CYC_MOVEM_L);\r
7277}\r
7278\r
7279\r
7280M68KMAKE_OP(movem, 32, er, pcix)\r
7281{\r
7282 uint i = 0;\r
7283 uint register_list = OPER_I_16();\r
7284 uint ea = EA_PCIX_32();\r
7285 uint count = 0;\r
7286\r
7287 for(; i < 16; i++)\r
7288 if(register_list & (1 << i))\r
7289 {\r
7290 REG_DA[i] = m68ki_read_pcrel_32(ea);\r
7291 ea += 4;\r
7292 count++;\r
7293 }\r
7294\r
7295 USE_CYCLES(count<<CYC_MOVEM_L);\r
7296}\r
7297\r
7298\r
7299M68KMAKE_OP(movem, 32, er, .)\r
7300{\r
7301 uint i = 0;\r
7302 uint register_list = OPER_I_16();\r
7303 uint ea = M68KMAKE_GET_EA_AY_32;\r
7304 uint count = 0;\r
7305\r
7306 for(; i < 16; i++)\r
7307 if(register_list & (1 << i))\r
7308 {\r
7309 REG_DA[i] = m68ki_read_32(ea);\r
7310 ea += 4;\r
7311 count++;\r
7312 }\r
7313\r
7314 USE_CYCLES(count<<CYC_MOVEM_L);\r
7315}\r
7316\r
7317\r
7318M68KMAKE_OP(movep, 16, re, .)\r
7319{\r
7320 uint ea = EA_AY_DI_16();\r
7321 uint src = DX;\r
7322\r
7323 m68ki_write_8(ea, MASK_OUT_ABOVE_8(src >> 8));\r
7324 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src));\r
7325}\r
7326\r
7327\r
7328M68KMAKE_OP(movep, 32, re, .)\r
7329{\r
7330 uint ea = EA_AY_DI_32();\r
7331 uint src = DX;\r
7332\r
7333 m68ki_write_8(ea, MASK_OUT_ABOVE_8(src >> 24));\r
7334 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 16));\r
7335 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 8));\r
7336 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src));\r
7337}\r
7338\r
7339\r
7340M68KMAKE_OP(movep, 16, er, .)\r
7341{\r
7342 uint ea = EA_AY_DI_16();\r
7343 uint* r_dst = &DX;\r
7344\r
7345 *r_dst = MASK_OUT_BELOW_16(*r_dst) | ((m68ki_read_8(ea) << 8) + m68ki_read_8(ea + 2));\r
7346}\r
7347\r
7348\r
7349M68KMAKE_OP(movep, 32, er, .)\r
7350{\r
7351 uint ea = EA_AY_DI_32();\r
7352\r
7353 DX = (m68ki_read_8(ea) << 24) + (m68ki_read_8(ea + 2) << 16)\r
7354 + (m68ki_read_8(ea + 4) << 8) + m68ki_read_8(ea + 6);\r
7355}\r
7356\r
7357\r
7358M68KMAKE_OP(moves, 8, ., .)\r
7359{\r
7360 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))\r
7361 {\r
7362 if(FLAG_S)\r
7363 {\r
7364 uint word2 = OPER_I_16();\r
7365 uint ea = M68KMAKE_GET_EA_AY_8;\r
7366\r
7367 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
7368 if(BIT_B(word2)) /* Register to memory */\r
7369 {\r
7370 m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15]));\r
7371 return;\r
7372 }\r
7373 if(BIT_F(word2)) /* Memory to address register */\r
7374 {\r
7375 REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC));\r
7376 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))\r
7377 USE_CYCLES(2);\r
7378 return;\r
7379 }\r
7380 /* Memory to data register */\r
7381 REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC);\r
7382 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))\r
7383 USE_CYCLES(2);\r
7384 return;\r
7385 }\r
7386 m68ki_exception_privilege_violation();\r
7387 return;\r
7388 }\r
7389 m68ki_exception_illegal();\r
7390}\r
7391\r
7392\r
7393M68KMAKE_OP(moves, 16, ., .)\r
7394{\r
7395 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))\r
7396 {\r
7397 if(FLAG_S)\r
7398 {\r
7399 uint word2 = OPER_I_16();\r
7400 uint ea = M68KMAKE_GET_EA_AY_16;\r
7401\r
7402 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
7403 if(BIT_B(word2)) /* Register to memory */\r
7404 {\r
7405 m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15]));\r
7406 return;\r
7407 }\r
7408 if(BIT_F(word2)) /* Memory to address register */\r
7409 {\r
7410 REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC));\r
7411 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))\r
7412 USE_CYCLES(2);\r
7413 return;\r
7414 }\r
7415 /* Memory to data register */\r
7416 REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC);\r
7417 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))\r
7418 USE_CYCLES(2);\r
7419 return;\r
7420 }\r
7421 m68ki_exception_privilege_violation();\r
7422 return;\r
7423 }\r
7424 m68ki_exception_illegal();\r
7425}\r
7426\r
7427\r
7428M68KMAKE_OP(moves, 32, ., .)\r
7429{\r
7430 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))\r
7431 {\r
7432 if(FLAG_S)\r
7433 {\r
7434 uint word2 = OPER_I_16();\r
7435 uint ea = M68KMAKE_GET_EA_AY_32;\r
7436\r
7437 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
7438 if(BIT_B(word2)) /* Register to memory */\r
7439 {\r
7440 m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]);\r
7441 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))\r
7442 USE_CYCLES(2);\r
7443 return;\r
7444 }\r
7445 /* Memory to register */\r
7446 REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC);\r
7447 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))\r
7448 USE_CYCLES(2);\r
7449 return;\r
7450 }\r
7451 m68ki_exception_privilege_violation();\r
7452 return;\r
7453 }\r
7454 m68ki_exception_illegal();\r
7455}\r
7456\r
7457\r
7458M68KMAKE_OP(moveq, 32, ., .)\r
7459{\r
7460 uint res = DX = MAKE_INT_8(MASK_OUT_ABOVE_8(REG_IR));\r
7461\r
7462 FLAG_N = NFLAG_32(res);\r
7463 FLAG_Z = res;\r
7464 FLAG_V = VFLAG_CLEAR;\r
7465 FLAG_C = CFLAG_CLEAR;\r
7466}\r
7467\r
7468\r
7469M68KMAKE_OP(move16, 32, ., .)\r
7470{\r
7471 UINT16 w2 = OPER_I_16();\r
7472 int ax = REG_IR & 7;\r
7473 int ay = (w2 >> 12) & 7;\r
7474\r
7475 m68ki_write_32(REG_A[ay], m68ki_read_32(REG_A[ax]));\r
7476 m68ki_write_32(REG_A[ay]+4, m68ki_read_32(REG_A[ax]+4));\r
7477 m68ki_write_32(REG_A[ay]+8, m68ki_read_32(REG_A[ax]+8));\r
7478 m68ki_write_32(REG_A[ay]+12, m68ki_read_32(REG_A[ax]+12));\r
7479\r
7480 REG_A[ax] += 16;\r
7481 REG_A[ay] += 16;\r
7482}\r
7483\r
7484\r
7485M68KMAKE_OP(muls, 16, ., d)\r
7486{\r
7487 uint* r_dst = &DX;\r
7488 uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(DY) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));\r
7489\r
7490 *r_dst = res;\r
7491\r
7492 FLAG_Z = res;\r
7493 FLAG_N = NFLAG_32(res);\r
7494 FLAG_V = VFLAG_CLEAR;\r
7495 FLAG_C = CFLAG_CLEAR;\r
7496}\r
7497\r
7498\r
7499M68KMAKE_OP(muls, 16, ., .)\r
7500{\r
7501 uint* r_dst = &DX;\r
7502 uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(M68KMAKE_GET_OPER_AY_16) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));\r
7503\r
7504 *r_dst = res;\r
7505\r
7506 FLAG_Z = res;\r
7507 FLAG_N = NFLAG_32(res);\r
7508 FLAG_V = VFLAG_CLEAR;\r
7509 FLAG_C = CFLAG_CLEAR;\r
7510}\r
7511\r
7512\r
7513M68KMAKE_OP(mulu, 16, ., d)\r
7514{\r
7515 uint* r_dst = &DX;\r
7516 uint res = MASK_OUT_ABOVE_16(DY) * MASK_OUT_ABOVE_16(*r_dst);\r
7517\r
7518 *r_dst = res;\r
7519\r
7520 FLAG_Z = res;\r
7521 FLAG_N = NFLAG_32(res);\r
7522 FLAG_V = VFLAG_CLEAR;\r
7523 FLAG_C = CFLAG_CLEAR;\r
7524}\r
7525\r
7526\r
7527M68KMAKE_OP(mulu, 16, ., .)\r
7528{\r
7529 uint* r_dst = &DX;\r
7530 uint res = M68KMAKE_GET_OPER_AY_16 * MASK_OUT_ABOVE_16(*r_dst);\r
7531\r
7532 *r_dst = res;\r
7533\r
7534 FLAG_Z = res;\r
7535 FLAG_N = NFLAG_32(res);\r
7536 FLAG_V = VFLAG_CLEAR;\r
7537 FLAG_C = CFLAG_CLEAR;\r
7538}\r
7539\r
7540\r
7541M68KMAKE_OP(mull, 32, ., d)\r
7542{\r
7543#if M68K_USE_64_BIT\r
7544\r
7545 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
7546 {\r
7547 uint word2 = OPER_I_16();\r
7548 uint64 src = DY;\r
7549 uint64 dst = REG_D[(word2 >> 12) & 7];\r
7550 uint64 res;\r
7551\r
7552 FLAG_C = CFLAG_CLEAR;\r
7553\r
7554 if(BIT_B(word2)) /* signed */\r
7555 {\r
7556 res = (sint64)((sint32)src) * (sint64)((sint32)dst);\r
7557 if(!BIT_A(word2))\r
7558 {\r
7559 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
7560 FLAG_N = NFLAG_32(res);\r
7561 FLAG_V = ((sint64)res != (sint32)res)<<7;\r
7562 REG_D[(word2 >> 12) & 7] = FLAG_Z;\r
7563 return;\r
7564 }\r
7565 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);\r
7566 FLAG_N = NFLAG_64(res);\r
7567 FLAG_V = VFLAG_CLEAR;\r
7568 REG_D[word2 & 7] = (res >> 32);\r
7569 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);\r
7570 return;\r
7571 }\r
7572\r
7573 res = src * dst;\r
7574 if(!BIT_A(word2))\r
7575 {\r
7576 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
7577 FLAG_N = NFLAG_32(res);\r
7578 FLAG_V = (res > 0xffffffff)<<7;\r
7579 REG_D[(word2 >> 12) & 7] = FLAG_Z;\r
7580 return;\r
7581 }\r
7582 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);\r
7583 FLAG_N = NFLAG_64(res);\r
7584 FLAG_V = VFLAG_CLEAR;\r
7585 REG_D[word2 & 7] = (res >> 32);\r
7586 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);\r
7587 return;\r
7588 }\r
7589 m68ki_exception_illegal();\r
7590\r
7591#else\r
7592\r
7593 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
7594 {\r
7595 uint word2 = OPER_I_16();\r
7596 uint src = DY;\r
7597 uint dst = REG_D[(word2 >> 12) & 7];\r
7598 uint neg = GET_MSB_32(src ^ dst);\r
7599 uint src1;\r
7600 uint src2;\r
7601 uint dst1;\r
7602 uint dst2;\r
7603 uint r1;\r
7604 uint r2;\r
7605 uint r3;\r
7606 uint r4;\r
7607 uint lo;\r
7608 uint hi;\r
7609\r
7610 FLAG_C = CFLAG_CLEAR;\r
7611\r
7612 if(BIT_B(word2)) /* signed */\r
7613 {\r
7614 if(GET_MSB_32(src))\r
7615 src = (uint)MASK_OUT_ABOVE_32(-(sint)src);\r
7616 if(GET_MSB_32(dst))\r
7617 dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);\r
7618 }\r
7619\r
7620 src1 = MASK_OUT_ABOVE_16(src);\r
7621 src2 = src>>16;\r
7622 dst1 = MASK_OUT_ABOVE_16(dst);\r
7623 dst2 = dst>>16;\r
7624\r
7625\r
7626 r1 = src1 * dst1;\r
7627 r2 = src1 * dst2;\r
7628 r3 = src2 * dst1;\r
7629 r4 = src2 * dst2;\r
7630\r
7631 lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);\r
7632 hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);\r
7633\r
7634 if(BIT_B(word2) && neg)\r
7635 {\r
7636 hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));\r
7637 lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);\r
7638 }\r
7639\r
7640 if(BIT_A(word2))\r
7641 {\r
7642 REG_D[word2 & 7] = hi;\r
7643 REG_D[(word2 >> 12) & 7] = lo;\r
7644 FLAG_N = NFLAG_32(hi);\r
7645 FLAG_Z = hi | lo;\r
7646 FLAG_V = VFLAG_CLEAR;\r
7647 return;\r
7648 }\r
7649\r
7650 REG_D[(word2 >> 12) & 7] = lo;\r
7651 FLAG_N = NFLAG_32(lo);\r
7652 FLAG_Z = lo;\r
7653 if(BIT_B(word2))\r
7654 FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;\r
7655 else\r
7656 FLAG_V = (hi != 0) << 7;\r
7657 return;\r
7658 }\r
7659 m68ki_exception_illegal();\r
7660\r
7661#endif\r
7662}\r
7663\r
7664\r
7665M68KMAKE_OP(mull, 32, ., .)\r
7666{\r
7667#if M68K_USE_64_BIT\r
7668\r
7669 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
7670 {\r
7671 uint word2 = OPER_I_16();\r
7672 uint64 src = M68KMAKE_GET_OPER_AY_32;\r
7673 uint64 dst = REG_D[(word2 >> 12) & 7];\r
7674 uint64 res;\r
7675\r
7676 FLAG_C = CFLAG_CLEAR;\r
7677\r
7678 if(BIT_B(word2)) /* signed */\r
7679 {\r
7680 res = (sint64)((sint32)src) * (sint64)((sint32)dst);\r
7681 if(!BIT_A(word2))\r
7682 {\r
7683 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
7684 FLAG_N = NFLAG_32(res);\r
7685 FLAG_V = ((sint64)res != (sint32)res)<<7;\r
7686 REG_D[(word2 >> 12) & 7] = FLAG_Z;\r
7687 return;\r
7688 }\r
7689 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);\r
7690 FLAG_N = NFLAG_64(res);\r
7691 FLAG_V = VFLAG_CLEAR;\r
7692 REG_D[word2 & 7] = (res >> 32);\r
7693 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);\r
7694 return;\r
7695 }\r
7696\r
7697 res = src * dst;\r
7698 if(!BIT_A(word2))\r
7699 {\r
7700 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
7701 FLAG_N = NFLAG_32(res);\r
7702 FLAG_V = (res > 0xffffffff)<<7;\r
7703 REG_D[(word2 >> 12) & 7] = FLAG_Z;\r
7704 return;\r
7705 }\r
7706 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);\r
7707 FLAG_N = NFLAG_64(res);\r
7708 FLAG_V = VFLAG_CLEAR;\r
7709 REG_D[word2 & 7] = (res >> 32);\r
7710 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);\r
7711 return;\r
7712 }\r
7713 m68ki_exception_illegal();\r
7714\r
7715#else\r
7716\r
7717 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
7718 {\r
7719 uint word2 = OPER_I_16();\r
7720 uint src = M68KMAKE_GET_OPER_AY_32;\r
7721 uint dst = REG_D[(word2 >> 12) & 7];\r
7722 uint neg = GET_MSB_32(src ^ dst);\r
7723 uint src1;\r
7724 uint src2;\r
7725 uint dst1;\r
7726 uint dst2;\r
7727 uint r1;\r
7728 uint r2;\r
7729 uint r3;\r
7730 uint r4;\r
7731 uint lo;\r
7732 uint hi;\r
7733\r
7734 FLAG_C = CFLAG_CLEAR;\r
7735\r
7736 if(BIT_B(word2)) /* signed */\r
7737 {\r
7738 if(GET_MSB_32(src))\r
7739 src = (uint)MASK_OUT_ABOVE_32(-(sint)src);\r
7740 if(GET_MSB_32(dst))\r
7741 dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);\r
7742 }\r
7743\r
7744 src1 = MASK_OUT_ABOVE_16(src);\r
7745 src2 = src>>16;\r
7746 dst1 = MASK_OUT_ABOVE_16(dst);\r
7747 dst2 = dst>>16;\r
7748\r
7749\r
7750 r1 = src1 * dst1;\r
7751 r2 = src1 * dst2;\r
7752 r3 = src2 * dst1;\r
7753 r4 = src2 * dst2;\r
7754\r
7755 lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);\r
7756 hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);\r
7757\r
7758 if(BIT_B(word2) && neg)\r
7759 {\r
7760 hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));\r
7761 lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);\r
7762 }\r
7763\r
7764 if(BIT_A(word2))\r
7765 {\r
7766 REG_D[word2 & 7] = hi;\r
7767 REG_D[(word2 >> 12) & 7] = lo;\r
7768 FLAG_N = NFLAG_32(hi);\r
7769 FLAG_Z = hi | lo;\r
7770 FLAG_V = VFLAG_CLEAR;\r
7771 return;\r
7772 }\r
7773\r
7774 REG_D[(word2 >> 12) & 7] = lo;\r
7775 FLAG_N = NFLAG_32(lo);\r
7776 FLAG_Z = lo;\r
7777 if(BIT_B(word2))\r
7778 FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;\r
7779 else\r
7780 FLAG_V = (hi != 0) << 7;\r
7781 return;\r
7782 }\r
7783 m68ki_exception_illegal();\r
7784\r
7785#endif\r
7786}\r
7787\r
7788\r
7789M68KMAKE_OP(nbcd, 8, ., d)\r
7790{\r
7791 uint* r_dst = &DY;\r
7792 uint dst = *r_dst;\r
7793 uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1());\r
7794\r
7795 if(res != 0x9a)\r
7796 {\r
7797 FLAG_V = ~res; /* Undefined V behavior */\r
7798\r
7799 if((res & 0x0f) == 0xa)\r
7800 res = (res & 0xf0) + 0x10;\r
7801\r
7802 res = MASK_OUT_ABOVE_8(res);\r
7803\r
7804 FLAG_V &= res; /* Undefined V behavior part II */\r
7805\r
7806 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
7807\r
7808 FLAG_Z |= res;\r
7809 FLAG_C = CFLAG_SET;\r
7810 FLAG_X = XFLAG_SET;\r
7811 }\r
7812 else\r
7813 {\r
7814 FLAG_V = VFLAG_CLEAR;\r
7815 FLAG_C = CFLAG_CLEAR;\r
7816 FLAG_X = XFLAG_CLEAR;\r
7817 }\r
7818 FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
7819}\r
7820\r
7821\r
7822M68KMAKE_OP(nbcd, 8, ., .)\r
7823{\r
7824 uint ea = M68KMAKE_GET_EA_AY_8;\r
7825 uint dst = m68ki_read_8(ea);\r
7826 uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1());\r
7827\r
7828 if(res != 0x9a)\r
7829 {\r
7830 FLAG_V = ~res; /* Undefined V behavior */\r
7831\r
7832 if((res & 0x0f) == 0xa)\r
7833 res = (res & 0xf0) + 0x10;\r
7834\r
7835 res = MASK_OUT_ABOVE_8(res);\r
7836\r
7837 FLAG_V &= res; /* Undefined V behavior part II */\r
7838\r
7839 m68ki_write_8(ea, MASK_OUT_ABOVE_8(res));\r
7840\r
7841 FLAG_Z |= res;\r
7842 FLAG_C = CFLAG_SET;\r
7843 FLAG_X = XFLAG_SET;\r
7844 }\r
7845 else\r
7846 {\r
7847 FLAG_V = VFLAG_CLEAR;\r
7848 FLAG_C = CFLAG_CLEAR;\r
7849 FLAG_X = XFLAG_CLEAR;\r
7850 }\r
7851 FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
7852}\r
7853\r
7854\r
7855M68KMAKE_OP(neg, 8, ., d)\r
7856{\r
7857 uint* r_dst = &DY;\r
7858 uint res = 0 - MASK_OUT_ABOVE_8(*r_dst);\r
7859\r
7860 FLAG_N = NFLAG_8(res);\r
7861 FLAG_C = FLAG_X = CFLAG_8(res);\r
7862 FLAG_V = *r_dst & res;\r
7863 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
7864\r
7865 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;\r
7866}\r
7867\r
7868\r
7869M68KMAKE_OP(neg, 8, ., .)\r
7870{\r
7871 uint ea = M68KMAKE_GET_EA_AY_8;\r
7872 uint src = m68ki_read_8(ea);\r
7873 uint res = 0 - src;\r
7874\r
7875 FLAG_N = NFLAG_8(res);\r
7876 FLAG_C = FLAG_X = CFLAG_8(res);\r
7877 FLAG_V = src & res;\r
7878 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
7879\r
7880 m68ki_write_8(ea, FLAG_Z);\r
7881}\r
7882\r
7883\r
7884M68KMAKE_OP(neg, 16, ., d)\r
7885{\r
7886 uint* r_dst = &DY;\r
7887 uint res = 0 - MASK_OUT_ABOVE_16(*r_dst);\r
7888\r
7889 FLAG_N = NFLAG_16(res);\r
7890 FLAG_C = FLAG_X = CFLAG_16(res);\r
7891 FLAG_V = (*r_dst & res)>>8;\r
7892 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
7893\r
7894 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
7895}\r
7896\r
7897\r
7898M68KMAKE_OP(neg, 16, ., .)\r
7899{\r
7900 uint ea = M68KMAKE_GET_EA_AY_16;\r
7901 uint src = m68ki_read_16(ea);\r
7902 uint res = 0 - src;\r
7903\r
7904 FLAG_N = NFLAG_16(res);\r
7905 FLAG_C = FLAG_X = CFLAG_16(res);\r
7906 FLAG_V = (src & res)>>8;\r
7907 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
7908\r
7909 m68ki_write_16(ea, FLAG_Z);\r
7910}\r
7911\r
7912\r
7913M68KMAKE_OP(neg, 32, ., d)\r
7914{\r
7915 uint* r_dst = &DY;\r
7916 uint res = 0 - *r_dst;\r
7917\r
7918 FLAG_N = NFLAG_32(res);\r
7919 FLAG_C = FLAG_X = CFLAG_SUB_32(*r_dst, 0, res);\r
7920 FLAG_V = (*r_dst & res)>>24;\r
7921 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
7922\r
7923 *r_dst = FLAG_Z;\r
7924}\r
7925\r
7926\r
7927M68KMAKE_OP(neg, 32, ., .)\r
7928{\r
7929 uint ea = M68KMAKE_GET_EA_AY_32;\r
7930 uint src = m68ki_read_32(ea);\r
7931 uint res = 0 - src;\r
7932\r
7933 FLAG_N = NFLAG_32(res);\r
7934 FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res);\r
7935 FLAG_V = (src & res)>>24;\r
7936 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
7937\r
7938 m68ki_write_32(ea, FLAG_Z);\r
7939}\r
7940\r
7941\r
7942M68KMAKE_OP(negx, 8, ., d)\r
7943{\r
7944 uint* r_dst = &DY;\r
7945 uint res = 0 - MASK_OUT_ABOVE_8(*r_dst) - XFLAG_AS_1();\r
7946\r
7947 FLAG_N = NFLAG_8(res);\r
7948 FLAG_X = FLAG_C = CFLAG_8(res);\r
7949 FLAG_V = *r_dst & res;\r
7950\r
7951 res = MASK_OUT_ABOVE_8(res);\r
7952 FLAG_Z |= res;\r
7953\r
7954 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
7955}\r
7956\r
7957\r
7958M68KMAKE_OP(negx, 8, ., .)\r
7959{\r
7960 uint ea = M68KMAKE_GET_EA_AY_8;\r
7961 uint src = m68ki_read_8(ea);\r
7962 uint res = 0 - src - XFLAG_AS_1();\r
7963\r
7964 FLAG_N = NFLAG_8(res);\r
7965 FLAG_X = FLAG_C = CFLAG_8(res);\r
7966 FLAG_V = src & res;\r
7967\r
7968 res = MASK_OUT_ABOVE_8(res);\r
7969 FLAG_Z |= res;\r
7970\r
7971 m68ki_write_8(ea, res);\r
7972}\r
7973\r
7974\r
7975M68KMAKE_OP(negx, 16, ., d)\r
7976{\r
7977 uint* r_dst = &DY;\r
7978 uint res = 0 - MASK_OUT_ABOVE_16(*r_dst) - XFLAG_AS_1();\r
7979\r
7980 FLAG_N = NFLAG_16(res);\r
7981 FLAG_X = FLAG_C = CFLAG_16(res);\r
7982 FLAG_V = (*r_dst & res)>>8;\r
7983\r
7984 res = MASK_OUT_ABOVE_16(res);\r
7985 FLAG_Z |= res;\r
7986\r
7987 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
7988}\r
7989\r
7990\r
7991M68KMAKE_OP(negx, 16, ., .)\r
7992{\r
7993 uint ea = M68KMAKE_GET_EA_AY_16;\r
7994 uint src = m68ki_read_16(ea);\r
7995 uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1();\r
7996\r
7997 FLAG_N = NFLAG_16(res);\r
7998 FLAG_X = FLAG_C = CFLAG_16(res);\r
7999 FLAG_V = (src & res)>>8;\r
8000\r
8001 res = MASK_OUT_ABOVE_16(res);\r
8002 FLAG_Z |= res;\r
8003\r
8004 m68ki_write_16(ea, res);\r
8005}\r
8006\r
8007\r
8008M68KMAKE_OP(negx, 32, ., d)\r
8009{\r
8010 uint* r_dst = &DY;\r
8011 uint res = 0 - MASK_OUT_ABOVE_32(*r_dst) - XFLAG_AS_1();\r
8012\r
8013 FLAG_N = NFLAG_32(res);\r
8014 FLAG_X = FLAG_C = CFLAG_SUB_32(*r_dst, 0, res);\r
8015 FLAG_V = (*r_dst & res)>>24;\r
8016\r
8017 res = MASK_OUT_ABOVE_32(res);\r
8018 FLAG_Z |= res;\r
8019\r
8020 *r_dst = res;\r
8021}\r
8022\r
8023\r
8024M68KMAKE_OP(negx, 32, ., .)\r
8025{\r
8026 uint ea = M68KMAKE_GET_EA_AY_32;\r
8027 uint src = m68ki_read_32(ea);\r
8028 uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1();\r
8029\r
8030 FLAG_N = NFLAG_32(res);\r
8031 FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res);\r
8032 FLAG_V = (src & res)>>24;\r
8033\r
8034 res = MASK_OUT_ABOVE_32(res);\r
8035 FLAG_Z |= res;\r
8036\r
8037 m68ki_write_32(ea, res);\r
8038}\r
8039\r
8040\r
8041M68KMAKE_OP(nop, 0, ., .)\r
8042{\r
8043 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
8044}\r
8045\r
8046\r
8047M68KMAKE_OP(not, 8, ., d)\r
8048{\r
8049 uint* r_dst = &DY;\r
8050 uint res = MASK_OUT_ABOVE_8(~*r_dst);\r
8051\r
8052 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
8053\r
8054 FLAG_N = NFLAG_8(res);\r
8055 FLAG_Z = res;\r
8056 FLAG_C = CFLAG_CLEAR;\r
8057 FLAG_V = VFLAG_CLEAR;\r
8058}\r
8059\r
8060\r
8061M68KMAKE_OP(not, 8, ., .)\r
8062{\r
8063 uint ea = M68KMAKE_GET_EA_AY_8;\r
8064 uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));\r
8065\r
8066 m68ki_write_8(ea, res);\r
8067\r
8068 FLAG_N = NFLAG_8(res);\r
8069 FLAG_Z = res;\r
8070 FLAG_C = CFLAG_CLEAR;\r
8071 FLAG_V = VFLAG_CLEAR;\r
8072}\r
8073\r
8074\r
8075M68KMAKE_OP(not, 16, ., d)\r
8076{\r
8077 uint* r_dst = &DY;\r
8078 uint res = MASK_OUT_ABOVE_16(~*r_dst);\r
8079\r
8080 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
8081\r
8082 FLAG_N = NFLAG_16(res);\r
8083 FLAG_Z = res;\r
8084 FLAG_C = CFLAG_CLEAR;\r
8085 FLAG_V = VFLAG_CLEAR;\r
8086}\r
8087\r
8088\r
8089M68KMAKE_OP(not, 16, ., .)\r
8090{\r
8091 uint ea = M68KMAKE_GET_EA_AY_16;\r
8092 uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea));\r
8093\r
8094 m68ki_write_16(ea, res);\r
8095\r
8096 FLAG_N = NFLAG_16(res);\r
8097 FLAG_Z = res;\r
8098 FLAG_C = CFLAG_CLEAR;\r
8099 FLAG_V = VFLAG_CLEAR;\r
8100}\r
8101\r
8102\r
8103M68KMAKE_OP(not, 32, ., d)\r
8104{\r
8105 uint* r_dst = &DY;\r
8106 uint res = *r_dst = MASK_OUT_ABOVE_32(~*r_dst);\r
8107\r
8108 FLAG_N = NFLAG_32(res);\r
8109 FLAG_Z = res;\r
8110 FLAG_C = CFLAG_CLEAR;\r
8111 FLAG_V = VFLAG_CLEAR;\r
8112}\r
8113\r
8114\r
8115M68KMAKE_OP(not, 32, ., .)\r
8116{\r
8117 uint ea = M68KMAKE_GET_EA_AY_32;\r
8118 uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea));\r
8119\r
8120 m68ki_write_32(ea, res);\r
8121\r
8122 FLAG_N = NFLAG_32(res);\r
8123 FLAG_Z = res;\r
8124 FLAG_C = CFLAG_CLEAR;\r
8125 FLAG_V = VFLAG_CLEAR;\r
8126}\r
8127\r
8128\r
8129M68KMAKE_OP(or, 8, er, d)\r
8130{\r
8131 uint res = MASK_OUT_ABOVE_8((DX |= MASK_OUT_ABOVE_8(DY)));\r
8132\r
8133 FLAG_N = NFLAG_8(res);\r
8134 FLAG_Z = res;\r
8135 FLAG_C = CFLAG_CLEAR;\r
8136 FLAG_V = VFLAG_CLEAR;\r
8137}\r
8138\r
8139\r
8140M68KMAKE_OP(or, 8, er, .)\r
8141{\r
8142 uint res = MASK_OUT_ABOVE_8((DX |= M68KMAKE_GET_OPER_AY_8));\r
8143\r
8144 FLAG_N = NFLAG_8(res);\r
8145 FLAG_Z = res;\r
8146 FLAG_C = CFLAG_CLEAR;\r
8147 FLAG_V = VFLAG_CLEAR;\r
8148}\r
8149\r
8150\r
8151M68KMAKE_OP(or, 16, er, d)\r
8152{\r
8153 uint res = MASK_OUT_ABOVE_16((DX |= MASK_OUT_ABOVE_16(DY)));\r
8154\r
8155 FLAG_N = NFLAG_16(res);\r
8156 FLAG_Z = res;\r
8157 FLAG_C = CFLAG_CLEAR;\r
8158 FLAG_V = VFLAG_CLEAR;\r
8159}\r
8160\r
8161\r
8162M68KMAKE_OP(or, 16, er, .)\r
8163{\r
8164 uint res = MASK_OUT_ABOVE_16((DX |= M68KMAKE_GET_OPER_AY_16));\r
8165\r
8166 FLAG_N = NFLAG_16(res);\r
8167 FLAG_Z = res;\r
8168 FLAG_C = CFLAG_CLEAR;\r
8169 FLAG_V = VFLAG_CLEAR;\r
8170}\r
8171\r
8172\r
8173M68KMAKE_OP(or, 32, er, d)\r
8174{\r
8175 uint res = DX |= DY;\r
8176\r
8177 FLAG_N = NFLAG_32(res);\r
8178 FLAG_Z = res;\r
8179 FLAG_C = CFLAG_CLEAR;\r
8180 FLAG_V = VFLAG_CLEAR;\r
8181}\r
8182\r
8183\r
8184M68KMAKE_OP(or, 32, er, .)\r
8185{\r
8186 uint res = DX |= M68KMAKE_GET_OPER_AY_32;\r
8187\r
8188 FLAG_N = NFLAG_32(res);\r
8189 FLAG_Z = res;\r
8190 FLAG_C = CFLAG_CLEAR;\r
8191 FLAG_V = VFLAG_CLEAR;\r
8192}\r
8193\r
8194\r
8195M68KMAKE_OP(or, 8, re, .)\r
8196{\r
8197 uint ea = M68KMAKE_GET_EA_AY_8;\r
8198 uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));\r
8199\r
8200 m68ki_write_8(ea, res);\r
8201\r
8202 FLAG_N = NFLAG_8(res);\r
8203 FLAG_Z = res;\r
8204 FLAG_C = CFLAG_CLEAR;\r
8205 FLAG_V = VFLAG_CLEAR;\r
8206}\r
8207\r
8208\r
8209M68KMAKE_OP(or, 16, re, .)\r
8210{\r
8211 uint ea = M68KMAKE_GET_EA_AY_16;\r
8212 uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea));\r
8213\r
8214 m68ki_write_16(ea, res);\r
8215\r
8216 FLAG_N = NFLAG_16(res);\r
8217 FLAG_Z = res;\r
8218 FLAG_C = CFLAG_CLEAR;\r
8219 FLAG_V = VFLAG_CLEAR;\r
8220}\r
8221\r
8222\r
8223M68KMAKE_OP(or, 32, re, .)\r
8224{\r
8225 uint ea = M68KMAKE_GET_EA_AY_32;\r
8226 uint res = DX | m68ki_read_32(ea);\r
8227\r
8228 m68ki_write_32(ea, res);\r
8229\r
8230 FLAG_N = NFLAG_32(res);\r
8231 FLAG_Z = res;\r
8232 FLAG_C = CFLAG_CLEAR;\r
8233 FLAG_V = VFLAG_CLEAR;\r
8234}\r
8235\r
8236\r
8237M68KMAKE_OP(ori, 8, ., d)\r
8238{\r
8239 uint res = MASK_OUT_ABOVE_8((DY |= OPER_I_8()));\r
8240\r
8241 FLAG_N = NFLAG_8(res);\r
8242 FLAG_Z = res;\r
8243 FLAG_C = CFLAG_CLEAR;\r
8244 FLAG_V = VFLAG_CLEAR;\r
8245}\r
8246\r
8247\r
8248M68KMAKE_OP(ori, 8, ., .)\r
8249{\r
8250 uint src = OPER_I_8();\r
8251 uint ea = M68KMAKE_GET_EA_AY_8;\r
8252 uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));\r
8253\r
8254 m68ki_write_8(ea, res);\r
8255\r
8256 FLAG_N = NFLAG_8(res);\r
8257 FLAG_Z = res;\r
8258 FLAG_C = CFLAG_CLEAR;\r
8259 FLAG_V = VFLAG_CLEAR;\r
8260}\r
8261\r
8262\r
8263M68KMAKE_OP(ori, 16, ., d)\r
8264{\r
8265 uint res = MASK_OUT_ABOVE_16(DY |= OPER_I_16());\r
8266\r
8267 FLAG_N = NFLAG_16(res);\r
8268 FLAG_Z = res;\r
8269 FLAG_C = CFLAG_CLEAR;\r
8270 FLAG_V = VFLAG_CLEAR;\r
8271}\r
8272\r
8273\r
8274M68KMAKE_OP(ori, 16, ., .)\r
8275{\r
8276 uint src = OPER_I_16();\r
8277 uint ea = M68KMAKE_GET_EA_AY_16;\r
8278 uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea));\r
8279\r
8280 m68ki_write_16(ea, res);\r
8281\r
8282 FLAG_N = NFLAG_16(res);\r
8283 FLAG_Z = res;\r
8284 FLAG_C = CFLAG_CLEAR;\r
8285 FLAG_V = VFLAG_CLEAR;\r
8286}\r
8287\r
8288\r
8289M68KMAKE_OP(ori, 32, ., d)\r
8290{\r
8291 uint res = DY |= OPER_I_32();\r
8292\r
8293 FLAG_N = NFLAG_32(res);\r
8294 FLAG_Z = res;\r
8295 FLAG_C = CFLAG_CLEAR;\r
8296 FLAG_V = VFLAG_CLEAR;\r
8297}\r
8298\r
8299\r
8300M68KMAKE_OP(ori, 32, ., .)\r
8301{\r
8302 uint src = OPER_I_32();\r
8303 uint ea = M68KMAKE_GET_EA_AY_32;\r
8304 uint res = src | m68ki_read_32(ea);\r
8305\r
8306 m68ki_write_32(ea, res);\r
8307\r
8308 FLAG_N = NFLAG_32(res);\r
8309 FLAG_Z = res;\r
8310 FLAG_C = CFLAG_CLEAR;\r
8311 FLAG_V = VFLAG_CLEAR;\r
8312}\r
8313\r
8314\r
8315M68KMAKE_OP(ori, 16, toc, .)\r
8316{\r
8317 m68ki_set_ccr(m68ki_get_ccr() | OPER_I_16());\r
8318}\r
8319\r
8320\r
8321M68KMAKE_OP(ori, 16, tos, .)\r
8322{\r
8323 if(FLAG_S)\r
8324 {\r
8325 uint src = OPER_I_16();\r
8326 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
8327 m68ki_set_sr(m68ki_get_sr() | src);\r
8328 return;\r
8329 }\r
8330 m68ki_exception_privilege_violation();\r
8331}\r
8332\r
8333\r
8334M68KMAKE_OP(pack, 16, rr, .)\r
8335{\r
8336 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
8337 {\r
8338 /* Note: DX and DY are reversed in Motorola's docs */\r
8339 uint src = DY + OPER_I_16();\r
8340 uint* r_dst = &DX;\r
8341\r
8342 *r_dst = MASK_OUT_BELOW_8(*r_dst) | ((src >> 4) & 0x00f0) | (src & 0x000f);\r
8343 return;\r
8344 }\r
8345 m68ki_exception_illegal();\r
8346}\r
8347\r
8348\r
8349M68KMAKE_OP(pack, 16, mm, ax7)\r
8350{\r
8351 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
8352 {\r
8353 /* Note: AX and AY are reversed in Motorola's docs */\r
8354 uint ea_src = EA_AY_PD_8();\r
8355 uint src = m68ki_read_8(ea_src);\r
8356 ea_src = EA_AY_PD_8();\r
8357 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();\r
8358\r
8359 m68ki_write_8(EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));\r
8360 return;\r
8361 }\r
8362 m68ki_exception_illegal();\r
8363}\r
8364\r
8365\r
8366M68KMAKE_OP(pack, 16, mm, ay7)\r
8367{\r
8368 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
8369 {\r
8370 /* Note: AX and AY are reversed in Motorola's docs */\r
8371 uint ea_src = EA_A7_PD_8();\r
8372 uint src = m68ki_read_8(ea_src);\r
8373 ea_src = EA_A7_PD_8();\r
8374 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();\r
8375\r
8376 m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));\r
8377 return;\r
8378 }\r
8379 m68ki_exception_illegal();\r
8380}\r
8381\r
8382\r
8383M68KMAKE_OP(pack, 16, mm, axy7)\r
8384{\r
8385 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
8386 {\r
8387 uint ea_src = EA_A7_PD_8();\r
8388 uint src = m68ki_read_8(ea_src);\r
8389 ea_src = EA_A7_PD_8();\r
8390 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();\r
8391\r
8392 m68ki_write_8(EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));\r
8393 return;\r
8394 }\r
8395 m68ki_exception_illegal();\r
8396}\r
8397\r
8398\r
8399M68KMAKE_OP(pack, 16, mm, .)\r
8400{\r
8401 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
8402 {\r
8403 /* Note: AX and AY are reversed in Motorola's docs */\r
8404 uint ea_src = EA_AY_PD_8();\r
8405 uint src = m68ki_read_8(ea_src);\r
8406 ea_src = EA_AY_PD_8();\r
8407 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();\r
8408\r
8409 m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));\r
8410 return;\r
8411 }\r
8412 m68ki_exception_illegal();\r
8413}\r
8414\r
8415\r
8416M68KMAKE_OP(pea, 32, ., .)\r
8417{\r
8418 uint ea = M68KMAKE_GET_EA_AY_32;\r
8419\r
8420 m68ki_push_32(ea);\r
8421}\r
8422\r
8423\r
8424M68KMAKE_OP(pflush, 32, ., .)\r
8425{\r
8426 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
8427 {\r
8428 // Nothing to do, unless address translation cache is emulated\r
8429 return;\r
8430 }\r
8431 m68ki_exception_illegal();\r
8432}\r
8433\r
8434\r
8435M68KMAKE_OP(reset, 0, ., .)\r
8436{\r
8437 if(FLAG_S)\r
8438 {\r
8439 m68ki_output_reset(); /* auto-disable (see m68kcpu.h) */\r
8440 USE_CYCLES(CYC_RESET);\r
8441 return;\r
8442 }\r
8443 m68ki_exception_privilege_violation();\r
8444}\r
8445\r
8446\r
8447M68KMAKE_OP(ror, 8, s, .)\r
8448{\r
8449 uint* r_dst = &DY;\r
8450 uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
8451 uint shift = orig_shift & 7;\r
8452 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
8453 uint res = ROR_8(src, shift);\r
8454\r
8455 if(orig_shift != 0)\r
8456 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8457\r
8458 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
8459\r
8460 FLAG_N = NFLAG_8(res);\r
8461 FLAG_Z = res;\r
8462 FLAG_C = src << (9-orig_shift);\r
8463 FLAG_V = VFLAG_CLEAR;\r
8464}\r
8465\r
8466\r
8467M68KMAKE_OP(ror, 16, s, .)\r
8468{\r
8469 uint* r_dst = &DY;\r
8470 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
8471 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
8472 uint res = ROR_16(src, shift);\r
8473\r
8474 if(shift != 0)\r
8475 USE_CYCLES(shift<<CYC_SHIFT);\r
8476\r
8477 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
8478\r
8479 FLAG_N = NFLAG_16(res);\r
8480 FLAG_Z = res;\r
8481 FLAG_C = src << (9-shift);\r
8482 FLAG_V = VFLAG_CLEAR;\r
8483}\r
8484\r
8485\r
8486M68KMAKE_OP(ror, 32, s, .)\r
8487{\r
8488 uint* r_dst = &DY;\r
8489 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
8490 uint64 src = *r_dst;\r
8491 uint res = ROR_32(src, shift);\r
8492\r
8493 if(shift != 0)\r
8494 USE_CYCLES(shift<<CYC_SHIFT);\r
8495\r
8496 *r_dst = res;\r
8497\r
8498 FLAG_N = NFLAG_32(res);\r
8499 FLAG_Z = res;\r
8500 FLAG_C = src << (9-shift);\r
8501 FLAG_V = VFLAG_CLEAR;\r
8502}\r
8503\r
8504\r
8505M68KMAKE_OP(ror, 8, r, .)\r
8506{\r
8507 uint* r_dst = &DY;\r
8508 uint orig_shift = DX & 0x3f;\r
8509 uint shift = orig_shift & 7;\r
8510 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
8511 uint res = ROR_8(src, shift);\r
8512\r
8513 if(orig_shift != 0)\r
8514 {\r
8515 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8516\r
8517 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
8518 FLAG_C = src << (8-((shift-1)&7));\r
8519 FLAG_N = NFLAG_8(res);\r
8520 FLAG_Z = res;\r
8521 FLAG_V = VFLAG_CLEAR;\r
8522 return;\r
8523 }\r
8524\r
8525 FLAG_C = CFLAG_CLEAR;\r
8526 FLAG_N = NFLAG_8(src);\r
8527 FLAG_Z = src;\r
8528 FLAG_V = VFLAG_CLEAR;\r
8529}\r
8530\r
8531\r
8532M68KMAKE_OP(ror, 16, r, .)\r
8533{\r
8534 uint* r_dst = &DY;\r
8535 uint orig_shift = DX & 0x3f;\r
8536 uint shift = orig_shift & 15;\r
8537 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
8538 uint res = ROR_16(src, shift);\r
8539\r
8540 if(orig_shift != 0)\r
8541 {\r
8542 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8543\r
8544 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
8545 FLAG_C = (src >> ((shift - 1) & 15)) << 8;\r
8546 FLAG_N = NFLAG_16(res);\r
8547 FLAG_Z = res;\r
8548 FLAG_V = VFLAG_CLEAR;\r
8549 return;\r
8550 }\r
8551\r
8552 FLAG_C = CFLAG_CLEAR;\r
8553 FLAG_N = NFLAG_16(src);\r
8554 FLAG_Z = src;\r
8555 FLAG_V = VFLAG_CLEAR;\r
8556}\r
8557\r
8558\r
8559M68KMAKE_OP(ror, 32, r, .)\r
8560{\r
8561 uint* r_dst = &DY;\r
8562 uint orig_shift = DX & 0x3f;\r
8563 uint shift = orig_shift & 31;\r
8564 uint64 src = *r_dst;\r
8565 uint res = ROR_32(src, shift);\r
8566\r
8567 if(orig_shift != 0)\r
8568 {\r
8569 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8570\r
8571 *r_dst = res;\r
8572 FLAG_C = (src >> ((shift - 1) & 31)) << 8;\r
8573 FLAG_N = NFLAG_32(res);\r
8574 FLAG_Z = res;\r
8575 FLAG_V = VFLAG_CLEAR;\r
8576 return;\r
8577 }\r
8578\r
8579 FLAG_C = CFLAG_CLEAR;\r
8580 FLAG_N = NFLAG_32(src);\r
8581 FLAG_Z = src;\r
8582 FLAG_V = VFLAG_CLEAR;\r
8583}\r
8584\r
8585\r
8586M68KMAKE_OP(ror, 16, ., .)\r
8587{\r
8588 uint ea = M68KMAKE_GET_EA_AY_16;\r
8589 uint src = m68ki_read_16(ea);\r
8590 uint res = ROR_16(src, 1);\r
8591\r
8592 m68ki_write_16(ea, res);\r
8593\r
8594 FLAG_N = NFLAG_16(res);\r
8595 FLAG_Z = res;\r
8596 FLAG_C = src << 8;\r
8597 FLAG_V = VFLAG_CLEAR;\r
8598}\r
8599\r
8600\r
8601M68KMAKE_OP(rol, 8, s, .)\r
8602{\r
8603 uint* r_dst = &DY;\r
8604 uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
8605 uint shift = orig_shift & 7;\r
8606 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
8607 uint res = ROL_8(src, shift);\r
8608\r
8609 if(orig_shift != 0)\r
8610 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8611\r
8612 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
8613\r
8614 FLAG_N = NFLAG_8(res);\r
8615 FLAG_Z = res;\r
8616 FLAG_C = src << orig_shift;\r
8617 FLAG_V = VFLAG_CLEAR;\r
8618}\r
8619\r
8620\r
8621M68KMAKE_OP(rol, 16, s, .)\r
8622{\r
8623 uint* r_dst = &DY;\r
8624 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
8625 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
8626 uint res = ROL_16(src, shift);\r
8627\r
8628 if(shift != 0)\r
8629 USE_CYCLES(shift<<CYC_SHIFT);\r
8630\r
8631 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
8632\r
8633 FLAG_N = NFLAG_16(res);\r
8634 FLAG_Z = res;\r
8635 FLAG_C = src >> (8-shift);\r
8636 FLAG_V = VFLAG_CLEAR;\r
8637}\r
8638\r
8639\r
8640M68KMAKE_OP(rol, 32, s, .)\r
8641{\r
8642 uint* r_dst = &DY;\r
8643 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
8644 uint64 src = *r_dst;\r
8645 uint res = ROL_32(src, shift);\r
8646\r
8647 if(shift != 0)\r
8648 USE_CYCLES(shift<<CYC_SHIFT);\r
8649\r
8650 *r_dst = res;\r
8651\r
8652 FLAG_N = NFLAG_32(res);\r
8653 FLAG_Z = res;\r
8654 FLAG_C = src >> (24-shift);\r
8655 FLAG_V = VFLAG_CLEAR;\r
8656}\r
8657\r
8658\r
8659M68KMAKE_OP(rol, 8, r, .)\r
8660{\r
8661 uint* r_dst = &DY;\r
8662 uint orig_shift = DX & 0x3f;\r
8663 uint shift = orig_shift & 7;\r
8664 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
8665 uint res = ROL_8(src, shift);\r
8666\r
8667 if(orig_shift != 0)\r
8668 {\r
8669 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8670\r
8671 if(shift != 0)\r
8672 {\r
8673 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
8674 FLAG_C = src << shift;\r
8675 FLAG_N = NFLAG_8(res);\r
8676 FLAG_Z = res;\r
8677 FLAG_V = VFLAG_CLEAR;\r
8678 return;\r
8679 }\r
8680 FLAG_C = (src & 1)<<8;\r
8681 FLAG_N = NFLAG_8(src);\r
8682 FLAG_Z = src;\r
8683 FLAG_V = VFLAG_CLEAR;\r
8684 return;\r
8685 }\r
8686\r
8687 FLAG_C = CFLAG_CLEAR;\r
8688 FLAG_N = NFLAG_8(src);\r
8689 FLAG_Z = src;\r
8690 FLAG_V = VFLAG_CLEAR;\r
8691}\r
8692\r
8693\r
8694M68KMAKE_OP(rol, 16, r, .)\r
8695{\r
8696 uint* r_dst = &DY;\r
8697 uint orig_shift = DX & 0x3f;\r
8698 uint shift = orig_shift & 15;\r
8699 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
8700 uint res = MASK_OUT_ABOVE_16(ROL_16(src, shift));\r
8701\r
8702 if(orig_shift != 0)\r
8703 {\r
8704 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8705\r
8706 if(shift != 0)\r
8707 {\r
8708 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
8709 FLAG_C = (src << shift) >> 8;\r
8710 FLAG_N = NFLAG_16(res);\r
8711 FLAG_Z = res;\r
8712 FLAG_V = VFLAG_CLEAR;\r
8713 return;\r
8714 }\r
8715 FLAG_C = (src & 1)<<8;\r
8716 FLAG_N = NFLAG_16(src);\r
8717 FLAG_Z = src;\r
8718 FLAG_V = VFLAG_CLEAR;\r
8719 return;\r
8720 }\r
8721\r
8722 FLAG_C = CFLAG_CLEAR;\r
8723 FLAG_N = NFLAG_16(src);\r
8724 FLAG_Z = src;\r
8725 FLAG_V = VFLAG_CLEAR;\r
8726}\r
8727\r
8728\r
8729M68KMAKE_OP(rol, 32, r, .)\r
8730{\r
8731 uint* r_dst = &DY;\r
8732 uint orig_shift = DX & 0x3f;\r
8733 uint shift = orig_shift & 31;\r
8734 uint64 src = *r_dst;\r
8735 uint res = ROL_32(src, shift);\r
8736\r
8737 if(orig_shift != 0)\r
8738 {\r
8739 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8740\r
8741 *r_dst = res;\r
8742\r
c6a4c892 8743 FLAG_C = (src >> ((32 - shift) & 0x1f)) << 8;\r
cc68a136 8744 FLAG_N = NFLAG_32(res);\r
8745 FLAG_Z = res;\r
8746 FLAG_V = VFLAG_CLEAR;\r
8747 return;\r
8748 }\r
8749\r
8750 FLAG_C = CFLAG_CLEAR;\r
8751 FLAG_N = NFLAG_32(src);\r
8752 FLAG_Z = src;\r
8753 FLAG_V = VFLAG_CLEAR;\r
8754}\r
8755\r
8756\r
8757M68KMAKE_OP(rol, 16, ., .)\r
8758{\r
8759 uint ea = M68KMAKE_GET_EA_AY_16;\r
8760 uint src = m68ki_read_16(ea);\r
8761 uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1));\r
8762\r
8763 m68ki_write_16(ea, res);\r
8764\r
8765 FLAG_N = NFLAG_16(res);\r
8766 FLAG_Z = res;\r
8767 FLAG_C = src >> 7;\r
8768 FLAG_V = VFLAG_CLEAR;\r
8769}\r
8770\r
8771\r
8772M68KMAKE_OP(roxr, 8, s, .)\r
8773{\r
8774 uint* r_dst = &DY;\r
8775 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
8776 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
8777 uint res = ROR_9(src | (XFLAG_AS_1() << 8), shift);\r
8778\r
8779 if(shift != 0)\r
8780 USE_CYCLES(shift<<CYC_SHIFT);\r
8781\r
8782 FLAG_C = FLAG_X = res;\r
8783 res = MASK_OUT_ABOVE_8(res);\r
8784\r
8785 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
8786\r
8787 FLAG_N = NFLAG_8(res);\r
8788 FLAG_Z = res;\r
8789 FLAG_V = VFLAG_CLEAR;\r
8790}\r
8791\r
8792\r
8793M68KMAKE_OP(roxr, 16, s, .)\r
8794{\r
8795 uint* r_dst = &DY;\r
8796 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
8797 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
8798 uint res = ROR_17(src | (XFLAG_AS_1() << 16), shift);\r
8799\r
8800 if(shift != 0)\r
8801 USE_CYCLES(shift<<CYC_SHIFT);\r
8802\r
8803 FLAG_C = FLAG_X = res >> 8;\r
8804 res = MASK_OUT_ABOVE_16(res);\r
8805\r
8806 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
8807\r
8808 FLAG_N = NFLAG_16(res);\r
8809 FLAG_Z = res;\r
8810 FLAG_V = VFLAG_CLEAR;\r
8811}\r
8812\r
8813\r
8814M68KMAKE_OP(roxr, 32, s, .)\r
8815{\r
8816#if M68K_USE_64_BIT\r
8817\r
8818 uint* r_dst = &DY;\r
8819 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
8820 uint64 src = *r_dst;\r
8821 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);\r
8822\r
8823 if(shift != 0)\r
8824 USE_CYCLES(shift<<CYC_SHIFT);\r
8825\r
8826 res = ROR_33_64(res, shift);\r
8827\r
8828 FLAG_C = FLAG_X = res >> 24;\r
8829 res = MASK_OUT_ABOVE_32(res);\r
8830\r
8831 *r_dst = res;\r
8832\r
8833 FLAG_N = NFLAG_32(res);\r
8834 FLAG_Z = res;\r
8835 FLAG_V = VFLAG_CLEAR;\r
8836\r
8837#else\r
8838\r
8839 uint* r_dst = &DY;\r
8840 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
8841 uint src = *r_dst;\r
8842 uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift)));\r
8843 uint new_x_flag = src & (1 << (shift - 1));\r
8844\r
8845 if(shift != 0)\r
8846 USE_CYCLES(shift<<CYC_SHIFT);\r
8847\r
8848 *r_dst = res;\r
8849\r
8850 FLAG_C = FLAG_X = (new_x_flag != 0)<<8;\r
8851 FLAG_N = NFLAG_32(res);\r
8852 FLAG_Z = res;\r
8853 FLAG_V = VFLAG_CLEAR;\r
8854\r
8855#endif\r
8856}\r
8857\r
8858\r
8859M68KMAKE_OP(roxr, 8, r, .)\r
8860{\r
8861 uint* r_dst = &DY;\r
8862 uint orig_shift = DX & 0x3f;\r
8863\r
8864 if(orig_shift != 0)\r
8865 {\r
8866 uint shift = orig_shift % 9;\r
8867 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
8868 uint res = ROR_9(src | (XFLAG_AS_1() << 8), shift);\r
8869\r
8870 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8871\r
8872 FLAG_C = FLAG_X = res;\r
8873 res = MASK_OUT_ABOVE_8(res);\r
8874\r
8875 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
8876 FLAG_N = NFLAG_8(res);\r
8877 FLAG_Z = res;\r
8878 FLAG_V = VFLAG_CLEAR;\r
8879 return;\r
8880 }\r
8881\r
8882 FLAG_C = FLAG_X;\r
8883 FLAG_N = NFLAG_8(*r_dst);\r
8884 FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);\r
8885 FLAG_V = VFLAG_CLEAR;\r
8886}\r
8887\r
8888\r
8889M68KMAKE_OP(roxr, 16, r, .)\r
8890{\r
8891 uint* r_dst = &DY;\r
8892 uint orig_shift = DX & 0x3f;\r
8893\r
8894 if(orig_shift != 0)\r
8895 {\r
8896 uint shift = orig_shift % 17;\r
8897 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
8898 uint res = ROR_17(src | (XFLAG_AS_1() << 16), shift);\r
8899\r
8900 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8901\r
8902 FLAG_C = FLAG_X = res >> 8;\r
8903 res = MASK_OUT_ABOVE_16(res);\r
8904\r
8905 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
8906 FLAG_N = NFLAG_16(res);\r
8907 FLAG_Z = res;\r
8908 FLAG_V = VFLAG_CLEAR;\r
8909 return;\r
8910 }\r
8911\r
8912 FLAG_C = FLAG_X;\r
8913 FLAG_N = NFLAG_16(*r_dst);\r
8914 FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);\r
8915 FLAG_V = VFLAG_CLEAR;\r
8916}\r
8917\r
8918\r
8919M68KMAKE_OP(roxr, 32, r, .)\r
8920{\r
8921#if M68K_USE_64_BIT\r
8922\r
8923 uint* r_dst = &DY;\r
8924 uint orig_shift = DX & 0x3f;\r
8925\r
8926 if(orig_shift != 0)\r
8927 {\r
8928 uint shift = orig_shift % 33;\r
8929 uint64 src = *r_dst;\r
8930 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);\r
8931\r
8932 res = ROR_33_64(res, shift);\r
8933\r
8934 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8935\r
8936 FLAG_C = FLAG_X = res >> 24;\r
8937 res = MASK_OUT_ABOVE_32(res);\r
8938\r
8939 *r_dst = res;\r
8940 FLAG_N = NFLAG_32(res);\r
8941 FLAG_Z = res;\r
8942 FLAG_V = VFLAG_CLEAR;\r
8943 return;\r
8944 }\r
8945\r
8946 FLAG_C = FLAG_X;\r
8947 FLAG_N = NFLAG_32(*r_dst);\r
8948 FLAG_Z = *r_dst;\r
8949 FLAG_V = VFLAG_CLEAR;\r
8950\r
8951#else\r
8952\r
8953 uint* r_dst = &DY;\r
8954 uint orig_shift = DX & 0x3f;\r
8955 uint shift = orig_shift % 33;\r
8956 uint src = *r_dst;\r
8957 uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift)));\r
8958 uint new_x_flag = src & (1 << (shift - 1));\r
8959\r
8960 if(orig_shift != 0)\r
8961 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8962\r
8963 if(shift != 0)\r
8964 {\r
8965 *r_dst = res;\r
8966 FLAG_X = (new_x_flag != 0)<<8;\r
8967 }\r
8968 else\r
8969 res = src;\r
8970 FLAG_C = FLAG_X;\r
8971 FLAG_N = NFLAG_32(res);\r
8972 FLAG_Z = res;\r
8973 FLAG_V = VFLAG_CLEAR;\r
8974\r
8975#endif\r
8976}\r
8977\r
8978\r
8979M68KMAKE_OP(roxr, 16, ., .)\r
8980{\r
8981 uint ea = M68KMAKE_GET_EA_AY_16;\r
8982 uint src = m68ki_read_16(ea);\r
8983 uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1);\r
8984\r
8985 FLAG_C = FLAG_X = res >> 8;\r
8986 res = MASK_OUT_ABOVE_16(res);\r
8987\r
8988 m68ki_write_16(ea, res);\r
8989\r
8990 FLAG_N = NFLAG_16(res);\r
8991 FLAG_Z = res;\r
8992 FLAG_V = VFLAG_CLEAR;\r
8993}\r
8994\r
8995\r
8996M68KMAKE_OP(roxl, 8, s, .)\r
8997{\r
8998 uint* r_dst = &DY;\r
8999 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
9000 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
9001 uint res = ROL_9(src | (XFLAG_AS_1() << 8), shift);\r
9002\r
9003 if(shift != 0)\r
9004 USE_CYCLES(shift<<CYC_SHIFT);\r
9005\r
9006 FLAG_C = FLAG_X = res;\r
9007 res = MASK_OUT_ABOVE_8(res);\r
9008\r
9009 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
9010\r
9011 FLAG_N = NFLAG_8(res);\r
9012 FLAG_Z = res;\r
9013 FLAG_V = VFLAG_CLEAR;\r
9014}\r
9015\r
9016\r
9017M68KMAKE_OP(roxl, 16, s, .)\r
9018{\r
9019 uint* r_dst = &DY;\r
9020 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
9021 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
9022 uint res = ROL_17(src | (XFLAG_AS_1() << 16), shift);\r
9023\r
9024 if(shift != 0)\r
9025 USE_CYCLES(shift<<CYC_SHIFT);\r
9026\r
9027 FLAG_C = FLAG_X = res >> 8;\r
9028 res = MASK_OUT_ABOVE_16(res);\r
9029\r
9030 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
9031\r
9032 FLAG_N = NFLAG_16(res);\r
9033 FLAG_Z = res;\r
9034 FLAG_V = VFLAG_CLEAR;\r
9035}\r
9036\r
9037\r
9038M68KMAKE_OP(roxl, 32, s, .)\r
9039{\r
9040#if M68K_USE_64_BIT\r
9041\r
9042 uint* r_dst = &DY;\r
9043 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
9044 uint64 src = *r_dst;\r
9045 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);\r
9046\r
9047 if(shift != 0)\r
9048 USE_CYCLES(shift<<CYC_SHIFT);\r
9049\r
9050 res = ROL_33_64(res, shift);\r
9051\r
9052 FLAG_C = FLAG_X = res >> 24;\r
9053 res = MASK_OUT_ABOVE_32(res);\r
9054\r
9055 *r_dst = res;\r
9056\r
9057 FLAG_N = NFLAG_32(res);\r
9058 FLAG_Z = res;\r
9059 FLAG_V = VFLAG_CLEAR;\r
9060\r
9061#else\r
9062\r
9063 uint* r_dst = &DY;\r
9064 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
9065 uint src = *r_dst;\r
9066 uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1)));\r
9067 uint new_x_flag = src & (1 << (32 - shift));\r
9068\r
9069 if(shift != 0)\r
9070 USE_CYCLES(shift<<CYC_SHIFT);\r
9071\r
9072 *r_dst = res;\r
9073\r
9074 FLAG_C = FLAG_X = (new_x_flag != 0)<<8;\r
9075 FLAG_N = NFLAG_32(res);\r
9076 FLAG_Z = res;\r
9077 FLAG_V = VFLAG_CLEAR;\r
9078\r
9079#endif\r
9080}\r
9081\r
9082\r
9083M68KMAKE_OP(roxl, 8, r, .)\r
9084{\r
9085 uint* r_dst = &DY;\r
9086 uint orig_shift = DX & 0x3f;\r
9087\r
9088\r
9089 if(orig_shift != 0)\r
9090 {\r
9091 uint shift = orig_shift % 9;\r
9092 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
9093 uint res = ROL_9(src | (XFLAG_AS_1() << 8), shift);\r
9094\r
9095 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
9096\r
9097 FLAG_C = FLAG_X = res;\r
9098 res = MASK_OUT_ABOVE_8(res);\r
9099\r
9100 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
9101 FLAG_N = NFLAG_8(res);\r
9102 FLAG_Z = res;\r
9103 FLAG_V = VFLAG_CLEAR;\r
9104 return;\r
9105 }\r
9106\r
9107 FLAG_C = FLAG_X;\r
9108 FLAG_N = NFLAG_8(*r_dst);\r
9109 FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);\r
9110 FLAG_V = VFLAG_CLEAR;\r
9111}\r
9112\r
9113\r
9114M68KMAKE_OP(roxl, 16, r, .)\r
9115{\r
9116 uint* r_dst = &DY;\r
9117 uint orig_shift = DX & 0x3f;\r
9118\r
9119 if(orig_shift != 0)\r
9120 {\r
9121 uint shift = orig_shift % 17;\r
9122 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
9123 uint res = ROL_17(src | (XFLAG_AS_1() << 16), shift);\r
9124\r
9125 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
9126\r
9127 FLAG_C = FLAG_X = res >> 8;\r
9128 res = MASK_OUT_ABOVE_16(res);\r
9129\r
9130 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
9131 FLAG_N = NFLAG_16(res);\r
9132 FLAG_Z = res;\r
9133 FLAG_V = VFLAG_CLEAR;\r
9134 return;\r
9135 }\r
9136\r
9137 FLAG_C = FLAG_X;\r
9138 FLAG_N = NFLAG_16(*r_dst);\r
9139 FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);\r
9140 FLAG_V = VFLAG_CLEAR;\r
9141}\r
9142\r
9143\r
9144M68KMAKE_OP(roxl, 32, r, .)\r
9145{\r
9146#if M68K_USE_64_BIT\r
9147\r
9148 uint* r_dst = &DY;\r
9149 uint orig_shift = DX & 0x3f;\r
9150\r
9151 if(orig_shift != 0)\r
9152 {\r
9153 uint shift = orig_shift % 33;\r
9154 uint64 src = *r_dst;\r
9155 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);\r
9156\r
9157 res = ROL_33_64(res, shift);\r
9158\r
9159 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
9160\r
9161 FLAG_C = FLAG_X = res >> 24;\r
9162 res = MASK_OUT_ABOVE_32(res);\r
9163\r
9164 *r_dst = res;\r
9165 FLAG_N = NFLAG_32(res);\r
9166 FLAG_Z = res;\r
9167 FLAG_V = VFLAG_CLEAR;\r
9168 return;\r
9169 }\r
9170\r
9171 FLAG_C = FLAG_X;\r
9172 FLAG_N = NFLAG_32(*r_dst);\r
9173 FLAG_Z = *r_dst;\r
9174 FLAG_V = VFLAG_CLEAR;\r
9175\r
9176#else\r
9177\r
9178 uint* r_dst = &DY;\r
9179 uint orig_shift = DX & 0x3f;\r
9180 uint shift = orig_shift % 33;\r
9181 uint src = *r_dst;\r
9182 uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1)));\r
9183 uint new_x_flag = src & (1 << (32 - shift));\r
9184\r
9185 if(orig_shift != 0)\r
9186 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
9187\r
9188 if(shift != 0)\r
9189 {\r
9190 *r_dst = res;\r
9191 FLAG_X = (new_x_flag != 0)<<8;\r
9192 }\r
9193 else\r
9194 res = src;\r
9195 FLAG_C = FLAG_X;\r
9196 FLAG_N = NFLAG_32(res);\r
9197 FLAG_Z = res;\r
9198 FLAG_V = VFLAG_CLEAR;\r
9199\r
9200#endif\r
9201}\r
9202\r
9203\r
9204M68KMAKE_OP(roxl, 16, ., .)\r
9205{\r
9206 uint ea = M68KMAKE_GET_EA_AY_16;\r
9207 uint src = m68ki_read_16(ea);\r
9208 uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1);\r
9209\r
9210 FLAG_C = FLAG_X = res >> 8;\r
9211 res = MASK_OUT_ABOVE_16(res);\r
9212\r
9213 m68ki_write_16(ea, res);\r
9214\r
9215 FLAG_N = NFLAG_16(res);\r
9216 FLAG_Z = res;\r
9217 FLAG_V = VFLAG_CLEAR;\r
9218}\r
9219\r
9220\r
9221M68KMAKE_OP(rtd, 32, ., .)\r
9222{\r
9223 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))\r
9224 {\r
9225 uint new_pc = m68ki_pull_32();\r
9226\r
9227 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
9228 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));\r
9229 m68ki_jump(new_pc);\r
9230 return;\r
9231 }\r
9232 m68ki_exception_illegal();\r
9233}\r
9234\r
9235\r
9236M68KMAKE_OP(rte, 32, ., .)\r
9237{\r
9238 if(FLAG_S)\r
9239 {\r
9240 uint new_sr;\r
9241 uint new_pc;\r
9242 uint format_word;\r
9243\r
9244 m68ki_rte_callback(); /* auto-disable (see m68kcpu.h) */\r
9245 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
9246\r
9247 if(CPU_TYPE_IS_000(CPU_TYPE))\r
9248 {\r
9249 new_sr = m68ki_pull_16();\r
9250 new_pc = m68ki_pull_32();\r
9251 m68ki_jump(new_pc);\r
9252 m68ki_set_sr(new_sr);\r
9253\r
9254 CPU_INSTR_MODE = INSTRUCTION_YES;\r
9255 CPU_RUN_MODE = RUN_MODE_NORMAL;\r
9256\r
9257 return;\r
9258 }\r
9259\r
9260 if(CPU_TYPE_IS_010(CPU_TYPE))\r
9261 {\r
9262 format_word = m68ki_read_16(REG_A[7]+6) >> 12;\r
9263 if(format_word == 0)\r
9264 {\r
9265 new_sr = m68ki_pull_16();\r
9266 new_pc = m68ki_pull_32();\r
9267 m68ki_fake_pull_16(); /* format word */\r
9268 m68ki_jump(new_pc);\r
9269 m68ki_set_sr(new_sr);\r
9270 CPU_INSTR_MODE = INSTRUCTION_YES;\r
9271 CPU_RUN_MODE = RUN_MODE_NORMAL;\r
9272 return;\r
9273 }\r
9274 CPU_INSTR_MODE = INSTRUCTION_YES;\r
9275 CPU_RUN_MODE = RUN_MODE_NORMAL;\r
9276 /* Not handling bus fault (9) */\r
9277 m68ki_exception_format_error();\r
9278 return;\r
9279 }\r
9280\r
9281 /* Otherwise it's 020 */\r
9282rte_loop:\r
9283 format_word = m68ki_read_16(REG_A[7]+6) >> 12;\r
9284 switch(format_word)\r
9285 {\r
9286 case 0: /* Normal */\r
9287 new_sr = m68ki_pull_16();\r
9288 new_pc = m68ki_pull_32();\r
9289 m68ki_fake_pull_16(); /* format word */\r
9290 m68ki_jump(new_pc);\r
9291 m68ki_set_sr(new_sr);\r
9292 CPU_INSTR_MODE = INSTRUCTION_YES;\r
9293 CPU_RUN_MODE = RUN_MODE_NORMAL;\r
9294 return;\r
9295 case 1: /* Throwaway */\r
9296 new_sr = m68ki_pull_16();\r
9297 m68ki_fake_pull_32(); /* program counter */\r
9298 m68ki_fake_pull_16(); /* format word */\r
9299 m68ki_set_sr_noint(new_sr);\r
9300 goto rte_loop;\r
9301 case 2: /* Trap */\r
9302 new_sr = m68ki_pull_16();\r
9303 new_pc = m68ki_pull_32();\r
9304 m68ki_fake_pull_16(); /* format word */\r
9305 m68ki_fake_pull_32(); /* address */\r
9306 m68ki_jump(new_pc);\r
9307 m68ki_set_sr(new_sr);\r
9308 CPU_INSTR_MODE = INSTRUCTION_YES;\r
9309 CPU_RUN_MODE = RUN_MODE_NORMAL;\r
9310 return;\r
9311 }\r
9312 /* Not handling long or short bus fault */\r
9313 CPU_INSTR_MODE = INSTRUCTION_YES;\r
9314 CPU_RUN_MODE = RUN_MODE_NORMAL;\r
9315 m68ki_exception_format_error();\r
9316 return;\r
9317 }\r
9318 m68ki_exception_privilege_violation();\r
9319}\r
9320\r
9321\r
9322M68KMAKE_OP(rtm, 32, ., .)\r
9323{\r
9324 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))\r
9325 {\r
9326 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
9327 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",\r
9328 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,\r
9329 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));\r
9330 return;\r
9331 }\r
9332 m68ki_exception_illegal();\r
9333}\r
9334\r
9335\r
9336M68KMAKE_OP(rtr, 32, ., .)\r
9337{\r
9338 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
9339 m68ki_set_ccr(m68ki_pull_16());\r
9340 m68ki_jump(m68ki_pull_32());\r
9341}\r
9342\r
9343\r
9344M68KMAKE_OP(rts, 32, ., .)\r
9345{\r
9346 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
9347 m68ki_jump(m68ki_pull_32());\r
9348}\r
9349\r
9350\r
9351M68KMAKE_OP(sbcd, 8, rr, .)\r
9352{\r
9353 uint* r_dst = &DX;\r
9354 uint src = DY;\r
9355 uint dst = *r_dst;\r
9356 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();\r
9357\r
9358// FLAG_V = ~res; /* Undefined V behavior */\r
9359 FLAG_V = VFLAG_CLEAR; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to assume cleared. */\r
9360\r
9361 if(res > 9)\r
9362 res -= 6;\r
9363 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);\r
9364 if(res > 0x99)\r
9365 {\r
9366 res += 0xa0;\r
9367 FLAG_X = FLAG_C = CFLAG_SET;\r
9368 FLAG_N = NFLAG_SET; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to follow carry. */\r
9369 }\r
9370 else\r
9371 FLAG_N = FLAG_X = FLAG_C = 0;\r
9372\r
9373 res = MASK_OUT_ABOVE_8(res);\r
9374\r
9375// FLAG_V &= res; /* Undefined V behavior part II */\r
9376// FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
9377 FLAG_Z |= res;\r
9378\r
9379 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
9380}\r
9381\r
9382\r
9383M68KMAKE_OP(sbcd, 8, mm, ax7)\r
9384{\r
9385 uint src = OPER_AY_PD_8();\r
9386 uint ea = EA_A7_PD_8();\r
9387 uint dst = m68ki_read_8(ea);\r
9388 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();\r
9389\r
9390// FLAG_V = ~res; /* Undefined V behavior */\r
9391 FLAG_V = VFLAG_CLEAR; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to return zero. */\r
9392\r
9393 if(res > 9)\r
9394 res -= 6;\r
9395 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);\r
9396 if(res > 0x99)\r
9397 {\r
9398 res += 0xa0;\r
9399 FLAG_X = FLAG_C = CFLAG_SET;\r
9400 FLAG_N = NFLAG_SET; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to follow carry. */\r
9401 }\r
9402 else\r
9403 FLAG_N = FLAG_X = FLAG_C = 0;\r
9404\r
9405 res = MASK_OUT_ABOVE_8(res);\r
9406\r
9407// FLAG_V &= res; /* Undefined V behavior part II */\r
9408// FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
9409 FLAG_Z |= res;\r
9410\r
9411 m68ki_write_8(ea, res);\r
9412}\r
9413\r
9414\r
9415M68KMAKE_OP(sbcd, 8, mm, ay7)\r
9416{\r
9417 uint src = OPER_A7_PD_8();\r
9418 uint ea = EA_AX_PD_8();\r
9419 uint dst = m68ki_read_8(ea);\r
9420 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();\r
9421\r
9422// FLAG_V = ~res; /* Undefined V behavior */\r
9423 FLAG_V = VFLAG_CLEAR; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to return zero. */\r
9424\r
9425 if(res > 9)\r
9426 res -= 6;\r
9427 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);\r
9428 if(res > 0x99)\r
9429 {\r
9430 res += 0xa0;\r
9431 FLAG_X = FLAG_C = CFLAG_SET;\r
9432 FLAG_N = NFLAG_SET; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to follow carry. */\r
9433 }\r
9434 else\r
9435 FLAG_N = FLAG_X = FLAG_C = 0;\r
9436\r
9437 res = MASK_OUT_ABOVE_8(res);\r
9438\r
9439// FLAG_V &= res; /* Undefined V behavior part II */\r
9440// FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
9441 FLAG_Z |= res;\r
9442\r
9443 m68ki_write_8(ea, res);\r
9444}\r
9445\r
9446\r
9447M68KMAKE_OP(sbcd, 8, mm, axy7)\r
9448{\r
9449 uint src = OPER_A7_PD_8();\r
9450 uint ea = EA_A7_PD_8();\r
9451 uint dst = m68ki_read_8(ea);\r
9452 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();\r
9453\r
9454// FLAG_V = ~res; /* Undefined V behavior */\r
9455 FLAG_V = VFLAG_CLEAR; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to return zero. */\r
9456\r
9457 if(res > 9)\r
9458 res -= 6;\r
9459 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);\r
9460 if(res > 0x99)\r
9461 {\r
9462 res += 0xa0;\r
9463 FLAG_X = FLAG_C = CFLAG_SET;\r
9464 FLAG_N = NFLAG_SET; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to follow carry. */\r
9465 }\r
9466 else\r
9467 FLAG_N = FLAG_X = FLAG_C = 0;\r
9468\r
9469 res = MASK_OUT_ABOVE_8(res);\r
9470\r
9471// FLAG_V &= res; /* Undefined V behavior part II */\r
9472// FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
9473 FLAG_Z |= res;\r
9474\r
9475 m68ki_write_8(ea, res);\r
9476}\r
9477\r
9478\r
9479M68KMAKE_OP(sbcd, 8, mm, .)\r
9480{\r
9481 uint src = OPER_AY_PD_8();\r
9482 uint ea = EA_AX_PD_8();\r
9483 uint dst = m68ki_read_8(ea);\r
9484 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();\r
9485\r
9486// FLAG_V = ~res; /* Undefined V behavior */\r
9487 FLAG_V = VFLAG_CLEAR; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to return zero. */\r
9488\r
9489 if(res > 9)\r
9490 res -= 6;\r
9491 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);\r
9492 if(res > 0x99)\r
9493 {\r
9494 res += 0xa0;\r
9495 FLAG_X = FLAG_C = CFLAG_SET;\r
9496 FLAG_N = NFLAG_SET; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to follow carry. */\r
9497 }\r
9498 else\r
9499 FLAG_N = FLAG_X = FLAG_C = 0;\r
9500\r
9501 res = MASK_OUT_ABOVE_8(res);\r
9502\r
9503// FLAG_V &= res; /* Undefined V behavior part II */\r
9504// FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
9505 FLAG_Z |= res;\r
9506\r
9507 m68ki_write_8(ea, res);\r
9508}\r
9509\r
9510\r
9511M68KMAKE_OP(st, 8, ., d)\r
9512{\r
9513 DY |= 0xff;\r
9514}\r
9515\r
9516\r
9517M68KMAKE_OP(st, 8, ., .)\r
9518{\r
9519 m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0xff);\r
9520}\r
9521\r
9522\r
9523M68KMAKE_OP(sf, 8, ., d)\r
9524{\r
9525 DY &= 0xffffff00;\r
9526}\r
9527\r
9528\r
9529M68KMAKE_OP(sf, 8, ., .)\r
9530{\r
9531 m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0);\r
9532}\r
9533\r
9534\r
9535M68KMAKE_OP(scc, 8, ., d)\r
9536{\r
9537 if(M68KMAKE_CC)\r
9538 {\r
9539 DY |= 0xff;\r
9540 USE_CYCLES(CYC_SCC_R_TRUE);\r
9541 return;\r
9542 }\r
9543 DY &= 0xffffff00;\r
9544}\r
9545\r
9546\r
9547M68KMAKE_OP(scc, 8, ., .)\r
9548{\r
9549 m68ki_write_8(M68KMAKE_GET_EA_AY_8, M68KMAKE_CC ? 0xff : 0);\r
9550}\r
9551\r
9552\r
9553M68KMAKE_OP(stop, 0, ., .)\r
9554{\r
9555 if(FLAG_S)\r
9556 {\r
9557 uint new_sr = OPER_I_16();\r
9558 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
9559 CPU_STOPPED |= STOP_LEVEL_STOP;\r
9560 m68ki_set_sr(new_sr);\r
9561 m68ki_remaining_cycles = 0;\r
9562 return;\r
9563 }\r
9564 m68ki_exception_privilege_violation();\r
9565}\r
9566\r
9567\r
9568M68KMAKE_OP(sub, 8, er, d)\r
9569{\r
9570 uint* r_dst = &DX;\r
9571 uint src = MASK_OUT_ABOVE_8(DY);\r
9572 uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
9573 uint res = dst - src;\r
9574\r
9575 FLAG_N = NFLAG_8(res);\r
9576 FLAG_X = FLAG_C = CFLAG_8(res);\r
9577 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
9578 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
9579\r
9580 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;\r
9581}\r
9582\r
9583\r
9584M68KMAKE_OP(sub, 8, er, .)\r
9585{\r
9586 uint* r_dst = &DX;\r
9587 uint src = M68KMAKE_GET_OPER_AY_8;\r
9588 uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
9589 uint res = dst - src;\r
9590\r
9591 FLAG_N = NFLAG_8(res);\r
9592 FLAG_X = FLAG_C = CFLAG_8(res);\r
9593 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
9594 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
9595\r
9596 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;\r
9597}\r
9598\r
9599\r
9600M68KMAKE_OP(sub, 16, er, d)\r
9601{\r
9602 uint* r_dst = &DX;\r
9603 uint src = MASK_OUT_ABOVE_16(DY);\r
9604 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
9605 uint res = dst - src;\r
9606\r
9607 FLAG_N = NFLAG_16(res);\r
9608 FLAG_X = FLAG_C = CFLAG_16(res);\r
9609 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
9610 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
9611\r
9612 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
9613}\r
9614\r
9615\r
9616M68KMAKE_OP(sub, 16, er, a)\r
9617{\r
9618 uint* r_dst = &DX;\r
9619 uint src = MASK_OUT_ABOVE_16(AY);\r
9620 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
9621 uint res = dst - src;\r
9622\r
9623 FLAG_N = NFLAG_16(res);\r
9624 FLAG_X = FLAG_C = CFLAG_16(res);\r
9625 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
9626 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
9627\r
9628 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
9629}\r
9630\r
9631\r
9632M68KMAKE_OP(sub, 16, er, .)\r
9633{\r
9634 uint* r_dst = &DX;\r
9635 uint src = M68KMAKE_GET_OPER_AY_16;\r
9636 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
9637 uint res = dst - src;\r
9638\r
9639 FLAG_N = NFLAG_16(res);\r
9640 FLAG_X = FLAG_C = CFLAG_16(res);\r
9641 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
9642 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
9643\r
9644 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
9645}\r
9646\r
9647\r
9648M68KMAKE_OP(sub, 32, er, d)\r
9649{\r
9650 uint* r_dst = &DX;\r
9651 uint src = DY;\r
9652 uint dst = *r_dst;\r
9653 uint res = dst - src;\r
9654\r
9655 FLAG_N = NFLAG_32(res);\r
9656 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
9657 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
9658 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
9659\r
9660 *r_dst = FLAG_Z;\r
9661}\r
9662\r
9663\r
9664M68KMAKE_OP(sub, 32, er, a)\r
9665{\r
9666 uint* r_dst = &DX;\r
9667 uint src = AY;\r
9668 uint dst = *r_dst;\r
9669 uint res = dst - src;\r
9670\r
9671 FLAG_N = NFLAG_32(res);\r
9672 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
9673 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
9674 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
9675\r
9676 *r_dst = FLAG_Z;\r
9677}\r
9678\r
9679\r
9680M68KMAKE_OP(sub, 32, er, .)\r
9681{\r
9682 uint* r_dst = &DX;\r
9683 uint src = M68KMAKE_GET_OPER_AY_32;\r
9684 uint dst = *r_dst;\r
9685 uint res = dst - src;\r
9686\r
9687 FLAG_N = NFLAG_32(res);\r
9688 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
9689 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
9690 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
9691\r
9692 *r_dst = FLAG_Z;\r
9693}\r
9694\r
9695\r
9696M68KMAKE_OP(sub, 8, re, .)\r
9697{\r
9698 uint ea = M68KMAKE_GET_EA_AY_8;\r
9699 uint src = MASK_OUT_ABOVE_8(DX);\r
9700 uint dst = m68ki_read_8(ea);\r
9701 uint res = dst - src;\r
9702\r
9703 FLAG_N = NFLAG_8(res);\r
9704 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
9705 FLAG_X = FLAG_C = CFLAG_8(res);\r
9706 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
9707\r
9708 m68ki_write_8(ea, FLAG_Z);\r
9709}\r
9710\r
9711\r
9712M68KMAKE_OP(sub, 16, re, .)\r
9713{\r
9714 uint ea = M68KMAKE_GET_EA_AY_16;\r
9715 uint src = MASK_OUT_ABOVE_16(DX);\r
9716 uint dst = m68ki_read_16(ea);\r
9717 uint res = dst - src;\r
9718\r
9719 FLAG_N = NFLAG_16(res);\r
9720 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
9721 FLAG_X = FLAG_C = CFLAG_16(res);\r
9722 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
9723\r
9724 m68ki_write_16(ea, FLAG_Z);\r
9725}\r
9726\r
9727\r
9728M68KMAKE_OP(sub, 32, re, .)\r
9729{\r
9730 uint ea = M68KMAKE_GET_EA_AY_32;\r
9731 uint src = DX;\r
9732 uint dst = m68ki_read_32(ea);\r
9733 uint res = dst - src;\r
9734\r
9735 FLAG_N = NFLAG_32(res);\r
9736 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
9737 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
9738 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
9739\r
9740 m68ki_write_32(ea, FLAG_Z);\r
9741}\r
9742\r
9743\r
9744M68KMAKE_OP(suba, 16, ., d)\r
9745{\r
9746 uint* r_dst = &AX;\r
9747\r
9748 *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(DY));\r
9749}\r
9750\r
9751\r
9752M68KMAKE_OP(suba, 16, ., a)\r
9753{\r
9754 uint* r_dst = &AX;\r
9755\r
9756 *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(AY));\r
9757}\r
9758\r
9759\r
9760M68KMAKE_OP(suba, 16, ., .)\r
9761{\r
9762 uint* r_dst = &AX;\r
c6a4c892 9763 uint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);\r
cc68a136 9764\r
c6a4c892 9765 *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);\r
cc68a136 9766}\r
9767\r
9768\r
9769M68KMAKE_OP(suba, 32, ., d)\r
9770{\r
9771 uint* r_dst = &AX;\r
9772\r
9773 *r_dst = MASK_OUT_ABOVE_32(*r_dst - DY);\r
9774}\r
9775\r
9776\r
9777M68KMAKE_OP(suba, 32, ., a)\r
9778{\r
9779 uint* r_dst = &AX;\r
9780\r
9781 *r_dst = MASK_OUT_ABOVE_32(*r_dst - AY);\r
9782}\r
9783\r
9784\r
9785M68KMAKE_OP(suba, 32, ., .)\r
9786{\r
9787 uint* r_dst = &AX;\r
9788\r
9789 *r_dst = MASK_OUT_ABOVE_32(*r_dst - M68KMAKE_GET_OPER_AY_32);\r
9790}\r
9791\r
9792\r
9793M68KMAKE_OP(subi, 8, ., d)\r
9794{\r
9795 uint* r_dst = &DY;\r
9796 uint src = OPER_I_8();\r
9797 uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
9798 uint res = dst - src;\r
9799\r
9800 FLAG_N = NFLAG_8(res);\r
9801 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
9802 FLAG_X = FLAG_C = CFLAG_8(res);\r
9803 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
9804\r
9805 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;\r
9806}\r
9807\r
9808\r
9809M68KMAKE_OP(subi, 8, ., .)\r
9810{\r
9811 uint src = OPER_I_8();\r
9812 uint ea = M68KMAKE_GET_EA_AY_8;\r
9813 uint dst = m68ki_read_8(ea);\r
9814 uint res = dst - src;\r
9815\r
9816 FLAG_N = NFLAG_8(res);\r
9817 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
9818 FLAG_X = FLAG_C = CFLAG_8(res);\r
9819 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
9820\r
9821 m68ki_write_8(ea, FLAG_Z);\r
9822}\r
9823\r
9824\r
9825M68KMAKE_OP(subi, 16, ., d)\r
9826{\r
9827 uint* r_dst = &DY;\r
9828 uint src = OPER_I_16();\r
9829 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
9830 uint res = dst - src;\r
9831\r
9832 FLAG_N = NFLAG_16(res);\r
9833 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
9834 FLAG_X = FLAG_C = CFLAG_16(res);\r
9835 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
9836\r
9837 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
9838}\r
9839\r
9840\r
9841M68KMAKE_OP(subi, 16, ., .)\r
9842{\r
9843 uint src = OPER_I_16();\r
9844 uint ea = M68KMAKE_GET_EA_AY_16;\r
9845 uint dst = m68ki_read_16(ea);\r
9846 uint res = dst - src;\r
9847\r
9848 FLAG_N = NFLAG_16(res);\r
9849 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
9850 FLAG_X = FLAG_C = CFLAG_16(res);\r
9851 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
9852\r
9853 m68ki_write_16(ea, FLAG_Z);\r
9854}\r
9855\r
9856\r
9857M68KMAKE_OP(subi, 32, ., d)\r
9858{\r
9859 uint* r_dst = &DY;\r
9860 uint src = OPER_I_32();\r
9861 uint dst = *r_dst;\r
9862 uint res = dst - src;\r
9863\r
9864 FLAG_N = NFLAG_32(res);\r
9865 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
9866 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
9867 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
9868\r
9869 *r_dst = FLAG_Z;\r
9870}\r
9871\r
9872\r
9873M68KMAKE_OP(subi, 32, ., .)\r
9874{\r
9875 uint src = OPER_I_32();\r
9876 uint ea = M68KMAKE_GET_EA_AY_32;\r
9877 uint dst = m68ki_read_32(ea);\r
9878 uint res = dst - src;\r
9879\r
9880 FLAG_N = NFLAG_32(res);\r
9881 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
9882 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
9883 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
9884\r
9885 m68ki_write_32(ea, FLAG_Z);\r
9886}\r
9887\r
9888\r
9889M68KMAKE_OP(subq, 8, ., d)\r
9890{\r
9891 uint* r_dst = &DY;\r
9892 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
9893 uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
9894 uint res = dst - src;\r
9895\r
9896 FLAG_N = NFLAG_8(res);\r
9897 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
9898 FLAG_X = FLAG_C = CFLAG_8(res);\r
9899 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
9900\r
9901 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;\r
9902}\r
9903\r
9904\r
9905M68KMAKE_OP(subq, 8, ., .)\r
9906{\r
9907 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
9908 uint ea = M68KMAKE_GET_EA_AY_8;\r
9909 uint dst = m68ki_read_8(ea);\r
9910 uint res = dst - src;\r
9911\r
9912 FLAG_N = NFLAG_8(res);\r
9913 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
9914 FLAG_X = FLAG_C = CFLAG_8(res);\r
9915 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
9916\r
9917 m68ki_write_8(ea, FLAG_Z);\r
9918}\r
9919\r
9920\r
9921M68KMAKE_OP(subq, 16, ., d)\r
9922{\r
9923 uint* r_dst = &DY;\r
9924 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
9925 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
9926 uint res = dst - src;\r
9927\r
9928 FLAG_N = NFLAG_16(res);\r
9929 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
9930 FLAG_X = FLAG_C = CFLAG_16(res);\r
9931 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
9932\r
9933 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
9934}\r
9935\r
9936\r
9937M68KMAKE_OP(subq, 16, ., a)\r
9938{\r
9939 uint* r_dst = &AY;\r
9940\r
9941 *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1));\r
9942}\r
9943\r
9944\r
9945M68KMAKE_OP(subq, 16, ., .)\r
9946{\r
9947 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
9948 uint ea = M68KMAKE_GET_EA_AY_16;\r
9949 uint dst = m68ki_read_16(ea);\r
9950 uint res = dst - src;\r
9951\r
9952 FLAG_N = NFLAG_16(res);\r
9953 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
9954 FLAG_X = FLAG_C = CFLAG_16(res);\r
9955 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
9956\r
9957 m68ki_write_16(ea, FLAG_Z);\r
9958}\r
9959\r
9960\r
9961M68KMAKE_OP(subq, 32, ., d)\r
9962{\r
9963 uint* r_dst = &DY;\r
9964 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
9965 uint dst = *r_dst;\r
9966 uint res = dst - src;\r
9967\r
9968 FLAG_N = NFLAG_32(res);\r
9969 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
9970 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
9971 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
9972\r
9973 *r_dst = FLAG_Z;\r
9974}\r
9975\r
9976\r
9977M68KMAKE_OP(subq, 32, ., a)\r
9978{\r
9979 uint* r_dst = &AY;\r
9980\r
9981 *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1));\r
9982}\r
9983\r
9984\r
9985M68KMAKE_OP(subq, 32, ., .)\r
9986{\r
9987 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
9988 uint ea = M68KMAKE_GET_EA_AY_32;\r
9989 uint dst = m68ki_read_32(ea);\r
9990 uint res = dst - src;\r
9991\r
9992 FLAG_N = NFLAG_32(res);\r
9993 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
9994 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
9995 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
9996\r
9997 m68ki_write_32(ea, FLAG_Z);\r
9998}\r
9999\r
10000\r
10001M68KMAKE_OP(subx, 8, rr, .)\r
10002{\r
10003 uint* r_dst = &DX;\r
10004 uint src = MASK_OUT_ABOVE_8(DY);\r
10005 uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
10006 uint res = dst - src - XFLAG_AS_1();\r
10007\r
10008 FLAG_N = NFLAG_8(res);\r
10009 FLAG_X = FLAG_C = CFLAG_8(res);\r
10010 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
10011\r
10012 res = MASK_OUT_ABOVE_8(res);\r
10013 FLAG_Z |= res;\r
10014\r
10015 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
10016}\r
10017\r
10018\r
10019M68KMAKE_OP(subx, 16, rr, .)\r
10020{\r
10021 uint* r_dst = &DX;\r
10022 uint src = MASK_OUT_ABOVE_16(DY);\r
10023 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
10024 uint res = dst - src - XFLAG_AS_1();\r
10025\r
10026 FLAG_N = NFLAG_16(res);\r
10027 FLAG_X = FLAG_C = CFLAG_16(res);\r
10028 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
10029\r
10030 res = MASK_OUT_ABOVE_16(res);\r
10031 FLAG_Z |= res;\r
10032\r
10033 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
10034}\r
10035\r
10036\r
10037M68KMAKE_OP(subx, 32, rr, .)\r
10038{\r
10039 uint* r_dst = &DX;\r
10040 uint src = DY;\r
10041 uint dst = *r_dst;\r
10042 uint res = dst - src - XFLAG_AS_1();\r
10043\r
10044 FLAG_N = NFLAG_32(res);\r
10045 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
10046 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
10047\r
10048 res = MASK_OUT_ABOVE_32(res);\r
10049 FLAG_Z |= res;\r
10050\r
10051 *r_dst = res;\r
10052}\r
10053\r
10054\r
10055M68KMAKE_OP(subx, 8, mm, ax7)\r
10056{\r
10057 uint src = OPER_AY_PD_8();\r
10058 uint ea = EA_A7_PD_8();\r
10059 uint dst = m68ki_read_8(ea);\r
10060 uint res = dst - src - XFLAG_AS_1();\r
10061\r
10062 FLAG_N = NFLAG_8(res);\r
10063 FLAG_X = FLAG_C = CFLAG_8(res);\r
10064 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
10065\r
10066 res = MASK_OUT_ABOVE_8(res);\r
10067 FLAG_Z |= res;\r
10068\r
10069 m68ki_write_8(ea, res);\r
10070}\r
10071\r
10072\r
10073M68KMAKE_OP(subx, 8, mm, ay7)\r
10074{\r
10075 uint src = OPER_A7_PD_8();\r
10076 uint ea = EA_AX_PD_8();\r
10077 uint dst = m68ki_read_8(ea);\r
10078 uint res = dst - src - XFLAG_AS_1();\r
10079\r
10080 FLAG_N = NFLAG_8(res);\r
10081 FLAG_X = FLAG_C = CFLAG_8(res);\r
10082 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
10083\r
10084 res = MASK_OUT_ABOVE_8(res);\r
10085 FLAG_Z |= res;\r
10086\r
10087 m68ki_write_8(ea, res);\r
10088}\r
10089\r
10090\r
10091M68KMAKE_OP(subx, 8, mm, axy7)\r
10092{\r
10093 uint src = OPER_A7_PD_8();\r
10094 uint ea = EA_A7_PD_8();\r
10095 uint dst = m68ki_read_8(ea);\r
10096 uint res = dst - src - XFLAG_AS_1();\r
10097\r
10098 FLAG_N = NFLAG_8(res);\r
10099 FLAG_X = FLAG_C = CFLAG_8(res);\r
10100 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
10101\r
10102 res = MASK_OUT_ABOVE_8(res);\r
10103 FLAG_Z |= res;\r
10104\r
10105 m68ki_write_8(ea, res);\r
10106}\r
10107\r
10108\r
10109M68KMAKE_OP(subx, 8, mm, .)\r
10110{\r
10111 uint src = OPER_AY_PD_8();\r
10112 uint ea = EA_AX_PD_8();\r
10113 uint dst = m68ki_read_8(ea);\r
10114 uint res = dst - src - XFLAG_AS_1();\r
10115\r
10116 FLAG_N = NFLAG_8(res);\r
10117 FLAG_X = FLAG_C = CFLAG_8(res);\r
10118 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
10119\r
10120 res = MASK_OUT_ABOVE_8(res);\r
10121 FLAG_Z |= res;\r
10122\r
10123 m68ki_write_8(ea, res);\r
10124}\r
10125\r
10126\r
10127M68KMAKE_OP(subx, 16, mm, .)\r
10128{\r
10129 uint src = OPER_AY_PD_16();\r
10130 uint ea = EA_AX_PD_16();\r
10131 uint dst = m68ki_read_16(ea);\r
10132 uint res = dst - src - XFLAG_AS_1();\r
10133\r
10134 FLAG_N = NFLAG_16(res);\r
10135 FLAG_X = FLAG_C = CFLAG_16(res);\r
10136 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
10137\r
10138 res = MASK_OUT_ABOVE_16(res);\r
10139 FLAG_Z |= res;\r
10140\r
10141 m68ki_write_16(ea, res);\r
10142}\r
10143\r
10144\r
10145M68KMAKE_OP(subx, 32, mm, .)\r
10146{\r
10147 uint src = OPER_AY_PD_32();\r
10148 uint ea = EA_AX_PD_32();\r
10149 uint dst = m68ki_read_32(ea);\r
10150 uint res = dst - src - XFLAG_AS_1();\r
10151\r
10152 FLAG_N = NFLAG_32(res);\r
10153 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
10154 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
10155\r
10156 res = MASK_OUT_ABOVE_32(res);\r
10157 FLAG_Z |= res;\r
10158\r
10159 m68ki_write_32(ea, res);\r
10160}\r
10161\r
10162\r
10163M68KMAKE_OP(swap, 32, ., .)\r
10164{\r
10165 uint* r_dst = &DY;\r
10166\r
10167 FLAG_Z = MASK_OUT_ABOVE_32(*r_dst<<16);\r
10168 *r_dst = (*r_dst>>16) | FLAG_Z;\r
10169\r
10170 FLAG_Z = *r_dst;\r
10171 FLAG_N = NFLAG_32(*r_dst);\r
10172 FLAG_C = CFLAG_CLEAR;\r
10173 FLAG_V = VFLAG_CLEAR;\r
10174}\r
10175\r
10176\r
10177M68KMAKE_OP(tas, 8, ., d)\r
10178{\r
10179 uint* r_dst = &DY;\r
10180\r
10181 FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);\r
10182 FLAG_N = NFLAG_8(*r_dst);\r
10183 FLAG_V = VFLAG_CLEAR;\r
10184 FLAG_C = CFLAG_CLEAR;\r
10185 *r_dst |= 0x80;\r
10186}\r
10187\r
10188\r
10189M68KMAKE_OP(tas, 8, ., .)\r
10190{\r
10191 uint ea = M68KMAKE_GET_EA_AY_8;\r
10192 uint dst = m68ki_read_8(ea);\r
c6a4c892 10193 uint allow_writeback;\r
cc68a136 10194\r
10195 FLAG_Z = dst;\r
10196 FLAG_N = NFLAG_8(dst);\r
10197 FLAG_V = VFLAG_CLEAR;\r
10198 FLAG_C = CFLAG_CLEAR;\r
c6a4c892 10199\r
10200 /* The Genesis/Megadrive games Gargoyles and Ex-Mutants need the TAS writeback\r
10201 disabled in order to function properly. Some Amiga software may also rely\r
10202 on this, but only when accessing specific addresses so additional functionality\r
10203 will be needed. */\r
10204 allow_writeback = m68ki_tas_callback();\r
10205\r
10206 if (allow_writeback==1) m68ki_write_8(ea, dst | 0x80);\r
cc68a136 10207}\r
10208\r
10209\r
10210M68KMAKE_OP(trap, 0, ., .)\r
10211{\r
10212 /* Trap#n stacks exception frame type 0 */\r
10213 m68ki_exception_trapN(EXCEPTION_TRAP_BASE + (REG_IR & 0xf)); /* HJB 990403 */\r
10214}\r
10215\r
10216\r
10217M68KMAKE_OP(trapt, 0, ., .)\r
10218{\r
10219 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10220 {\r
10221 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */\r
10222 return;\r
10223 }\r
10224 m68ki_exception_illegal();\r
10225}\r
10226\r
10227\r
10228M68KMAKE_OP(trapt, 16, ., .)\r
10229{\r
10230 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10231 {\r
10232 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */\r
10233 return;\r
10234 }\r
10235 m68ki_exception_illegal();\r
10236}\r
10237\r
10238\r
10239M68KMAKE_OP(trapt, 32, ., .)\r
10240{\r
10241 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10242 {\r
10243 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */\r
10244 return;\r
10245 }\r
10246 m68ki_exception_illegal();\r
10247}\r
10248\r
10249\r
10250M68KMAKE_OP(trapf, 0, ., .)\r
10251{\r
10252 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10253 {\r
10254 return;\r
10255 }\r
10256 m68ki_exception_illegal();\r
10257}\r
10258\r
10259\r
10260M68KMAKE_OP(trapf, 16, ., .)\r
10261{\r
10262 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10263 {\r
10264 REG_PC += 2;\r
10265 return;\r
10266 }\r
10267 m68ki_exception_illegal();\r
10268}\r
10269\r
10270\r
10271M68KMAKE_OP(trapf, 32, ., .)\r
10272{\r
10273 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10274 {\r
10275 REG_PC += 4;\r
10276 return;\r
10277 }\r
10278 m68ki_exception_illegal();\r
10279}\r
10280\r
10281\r
10282M68KMAKE_OP(trapcc, 0, ., .)\r
10283{\r
10284 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10285 {\r
10286 if(M68KMAKE_CC)\r
10287 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */\r
10288 return;\r
10289 }\r
10290 m68ki_exception_illegal();\r
10291}\r
10292\r
10293\r
10294M68KMAKE_OP(trapcc, 16, ., .)\r
10295{\r
10296 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10297 {\r
10298 if(M68KMAKE_CC)\r
10299 {\r
10300 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */\r
10301 return;\r
10302 }\r
10303 REG_PC += 2;\r
10304 return;\r
10305 }\r
10306 m68ki_exception_illegal();\r
10307}\r
10308\r
10309\r
10310M68KMAKE_OP(trapcc, 32, ., .)\r
10311{\r
10312 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10313 {\r
10314 if(M68KMAKE_CC)\r
10315 {\r
10316 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */\r
10317 return;\r
10318 }\r
10319 REG_PC += 4;\r
10320 return;\r
10321 }\r
10322 m68ki_exception_illegal();\r
10323}\r
10324\r
10325\r
10326M68KMAKE_OP(trapv, 0, ., .)\r
10327{\r
10328 if(COND_VC())\r
10329 {\r
10330 return;\r
10331 }\r
10332 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */\r
10333}\r
10334\r
10335\r
10336M68KMAKE_OP(tst, 8, ., d)\r
10337{\r
10338 uint res = MASK_OUT_ABOVE_8(DY);\r
10339\r
10340 FLAG_N = NFLAG_8(res);\r
10341 FLAG_Z = res;\r
10342 FLAG_V = VFLAG_CLEAR;\r
10343 FLAG_C = CFLAG_CLEAR;\r
10344}\r
10345\r
10346\r
10347M68KMAKE_OP(tst, 8, ., .)\r
10348{\r
10349 uint res = M68KMAKE_GET_OPER_AY_8;\r
10350\r
10351 FLAG_N = NFLAG_8(res);\r
10352 FLAG_Z = res;\r
10353 FLAG_V = VFLAG_CLEAR;\r
10354 FLAG_C = CFLAG_CLEAR;\r
10355}\r
10356\r
10357\r
10358M68KMAKE_OP(tst, 8, ., pcdi)\r
10359{\r
10360 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10361 {\r
10362 uint res = OPER_PCDI_8();\r
10363\r
10364 FLAG_N = NFLAG_8(res);\r
10365 FLAG_Z = res;\r
10366 FLAG_V = VFLAG_CLEAR;\r
10367 FLAG_C = CFLAG_CLEAR;\r
10368 return;\r
10369 }\r
10370 m68ki_exception_illegal();\r
10371}\r
10372\r
10373\r
10374M68KMAKE_OP(tst, 8, ., pcix)\r
10375{\r
10376 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10377 {\r
10378 uint res = OPER_PCIX_8();\r
10379\r
10380 FLAG_N = NFLAG_8(res);\r
10381 FLAG_Z = res;\r
10382 FLAG_V = VFLAG_CLEAR;\r
10383 FLAG_C = CFLAG_CLEAR;\r
10384 return;\r
10385 }\r
10386 m68ki_exception_illegal();\r
10387}\r
10388\r
10389\r
10390M68KMAKE_OP(tst, 8, ., i)\r
10391{\r
10392 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10393 {\r
10394 uint res = OPER_I_8();\r
10395\r
10396 FLAG_N = NFLAG_8(res);\r
10397 FLAG_Z = res;\r
10398 FLAG_V = VFLAG_CLEAR;\r
10399 FLAG_C = CFLAG_CLEAR;\r
10400 return;\r
10401 }\r
10402 m68ki_exception_illegal();\r
10403}\r
10404\r
10405\r
10406M68KMAKE_OP(tst, 16, ., d)\r
10407{\r
10408 uint res = MASK_OUT_ABOVE_16(DY);\r
10409\r
10410 FLAG_N = NFLAG_16(res);\r
10411 FLAG_Z = res;\r
10412 FLAG_V = VFLAG_CLEAR;\r
10413 FLAG_C = CFLAG_CLEAR;\r
10414}\r
10415\r
10416\r
10417M68KMAKE_OP(tst, 16, ., a)\r
10418{\r
10419 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10420 {\r
10421 uint res = MAKE_INT_16(AY);\r
10422\r
10423 FLAG_N = NFLAG_16(res);\r
10424 FLAG_Z = res;\r
10425 FLAG_V = VFLAG_CLEAR;\r
10426 FLAG_C = CFLAG_CLEAR;\r
10427 return;\r
10428 }\r
10429 m68ki_exception_illegal();\r
10430}\r
10431\r
10432\r
10433M68KMAKE_OP(tst, 16, ., .)\r
10434{\r
10435 uint res = M68KMAKE_GET_OPER_AY_16;\r
10436\r
10437 FLAG_N = NFLAG_16(res);\r
10438 FLAG_Z = res;\r
10439 FLAG_V = VFLAG_CLEAR;\r
10440 FLAG_C = CFLAG_CLEAR;\r
10441}\r
10442\r
10443\r
10444M68KMAKE_OP(tst, 16, ., pcdi)\r
10445{\r
10446 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10447 {\r
10448 uint res = OPER_PCDI_16();\r
10449\r
10450 FLAG_N = NFLAG_16(res);\r
10451 FLAG_Z = res;\r
10452 FLAG_V = VFLAG_CLEAR;\r
10453 FLAG_C = CFLAG_CLEAR;\r
10454 return;\r
10455 }\r
10456 m68ki_exception_illegal();\r
10457}\r
10458\r
10459\r
10460M68KMAKE_OP(tst, 16, ., pcix)\r
10461{\r
10462 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10463 {\r
10464 uint res = OPER_PCIX_16();\r
10465\r
10466 FLAG_N = NFLAG_16(res);\r
10467 FLAG_Z = res;\r
10468 FLAG_V = VFLAG_CLEAR;\r
10469 FLAG_C = CFLAG_CLEAR;\r
10470 return;\r
10471 }\r
10472 m68ki_exception_illegal();\r
10473}\r
10474\r
10475\r
10476M68KMAKE_OP(tst, 16, ., i)\r
10477{\r
10478 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10479 {\r
10480 uint res = OPER_I_16();\r
10481\r
10482 FLAG_N = NFLAG_16(res);\r
10483 FLAG_Z = res;\r
10484 FLAG_V = VFLAG_CLEAR;\r
10485 FLAG_C = CFLAG_CLEAR;\r
10486 return;\r
10487 }\r
10488 m68ki_exception_illegal();\r
10489}\r
10490\r
10491\r
10492M68KMAKE_OP(tst, 32, ., d)\r
10493{\r
10494 uint res = DY;\r
10495\r
10496 FLAG_N = NFLAG_32(res);\r
10497 FLAG_Z = res;\r
10498 FLAG_V = VFLAG_CLEAR;\r
10499 FLAG_C = CFLAG_CLEAR;\r
10500}\r
10501\r
10502\r
10503M68KMAKE_OP(tst, 32, ., a)\r
10504{\r
10505 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10506 {\r
10507 uint res = AY;\r
10508\r
10509 FLAG_N = NFLAG_32(res);\r
10510 FLAG_Z = res;\r
10511 FLAG_V = VFLAG_CLEAR;\r
10512 FLAG_C = CFLAG_CLEAR;\r
10513 return;\r
10514 }\r
10515 m68ki_exception_illegal();\r
10516}\r
10517\r
10518\r
10519M68KMAKE_OP(tst, 32, ., .)\r
10520{\r
10521 uint res = M68KMAKE_GET_OPER_AY_32;\r
10522\r
10523 FLAG_N = NFLAG_32(res);\r
10524 FLAG_Z = res;\r
10525 FLAG_V = VFLAG_CLEAR;\r
10526 FLAG_C = CFLAG_CLEAR;\r
10527}\r
10528\r
10529\r
10530M68KMAKE_OP(tst, 32, ., pcdi)\r
10531{\r
10532 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10533 {\r
10534 uint res = OPER_PCDI_32();\r
10535\r
10536 FLAG_N = NFLAG_32(res);\r
10537 FLAG_Z = res;\r
10538 FLAG_V = VFLAG_CLEAR;\r
10539 FLAG_C = CFLAG_CLEAR;\r
10540 return;\r
10541 }\r
10542 m68ki_exception_illegal();\r
10543}\r
10544\r
10545\r
10546M68KMAKE_OP(tst, 32, ., pcix)\r
10547{\r
10548 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10549 {\r
10550 uint res = OPER_PCIX_32();\r
10551\r
10552 FLAG_N = NFLAG_32(res);\r
10553 FLAG_Z = res;\r
10554 FLAG_V = VFLAG_CLEAR;\r
10555 FLAG_C = CFLAG_CLEAR;\r
10556 return;\r
10557 }\r
10558 m68ki_exception_illegal();\r
10559}\r
10560\r
10561\r
10562M68KMAKE_OP(tst, 32, ., i)\r
10563{\r
10564 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10565 {\r
10566 uint res = OPER_I_32();\r
10567\r
10568 FLAG_N = NFLAG_32(res);\r
10569 FLAG_Z = res;\r
10570 FLAG_V = VFLAG_CLEAR;\r
10571 FLAG_C = CFLAG_CLEAR;\r
10572 return;\r
10573 }\r
10574 m68ki_exception_illegal();\r
10575}\r
10576\r
10577\r
10578M68KMAKE_OP(unlk, 32, ., a7)\r
10579{\r
10580 REG_A[7] = m68ki_read_32(REG_A[7]);\r
10581}\r
10582\r
10583\r
10584M68KMAKE_OP(unlk, 32, ., .)\r
10585{\r
10586 uint* r_dst = &AY;\r
10587\r
10588 REG_A[7] = *r_dst;\r
10589 *r_dst = m68ki_pull_32();\r
10590}\r
10591\r
10592\r
10593M68KMAKE_OP(unpk, 16, rr, .)\r
10594{\r
10595 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10596 {\r
10597 /* Note: DX and DY are reversed in Motorola's docs */\r
10598 uint src = DY;\r
10599 uint* r_dst = &DX;\r
10600\r
10601 *r_dst = MASK_OUT_BELOW_16(*r_dst) | (((((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16()) & 0xffff);\r
10602 return;\r
10603 }\r
10604 m68ki_exception_illegal();\r
10605}\r
10606\r
10607\r
10608M68KMAKE_OP(unpk, 16, mm, ax7)\r
10609{\r
10610 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10611 {\r
10612 /* Note: AX and AY are reversed in Motorola's docs */\r
10613 uint src = OPER_AY_PD_8();\r
10614 uint ea_dst;\r
10615\r
10616 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();\r
10617 ea_dst = EA_A7_PD_8();\r
10618 m68ki_write_8(ea_dst, (src >> 8) & 0xff);\r
10619 ea_dst = EA_A7_PD_8();\r
10620 m68ki_write_8(ea_dst, src & 0xff);\r
10621 return;\r
10622 }\r
10623 m68ki_exception_illegal();\r
10624}\r
10625\r
10626\r
10627M68KMAKE_OP(unpk, 16, mm, ay7)\r
10628{\r
10629 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10630 {\r
10631 /* Note: AX and AY are reversed in Motorola's docs */\r
10632 uint src = OPER_A7_PD_8();\r
10633 uint ea_dst;\r
10634\r
10635 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();\r
10636 ea_dst = EA_AX_PD_8();\r
10637 m68ki_write_8(ea_dst, (src >> 8) & 0xff);\r
10638 ea_dst = EA_AX_PD_8();\r
10639 m68ki_write_8(ea_dst, src & 0xff);\r
10640 return;\r
10641 }\r
10642 m68ki_exception_illegal();\r
10643}\r
10644\r
10645\r
10646M68KMAKE_OP(unpk, 16, mm, axy7)\r
10647{\r
10648 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10649 {\r
10650 uint src = OPER_A7_PD_8();\r
10651 uint ea_dst;\r
10652\r
10653 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();\r
10654 ea_dst = EA_A7_PD_8();\r
10655 m68ki_write_8(ea_dst, (src >> 8) & 0xff);\r
10656 ea_dst = EA_A7_PD_8();\r
10657 m68ki_write_8(ea_dst, src & 0xff);\r
10658 return;\r
10659 }\r
10660 m68ki_exception_illegal();\r
10661}\r
10662\r
10663\r
10664M68KMAKE_OP(unpk, 16, mm, .)\r
10665{\r
10666 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10667 {\r
10668 /* Note: AX and AY are reversed in Motorola's docs */\r
10669 uint src = OPER_AY_PD_8();\r
10670 uint ea_dst;\r
10671\r
10672 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();\r
10673 ea_dst = EA_AX_PD_8();\r
10674 m68ki_write_8(ea_dst, (src >> 8) & 0xff);\r
10675 ea_dst = EA_AX_PD_8();\r
10676 m68ki_write_8(ea_dst, src & 0xff);\r
10677 return;\r
10678 }\r
10679 m68ki_exception_illegal();\r
10680}\r
10681\r
10682\r
10683\r
10684XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\r
10685M68KMAKE_END\r
fast MegaDrive/MegaCD/32X emulator