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renderer patch for DBZ - Buyuu Retsuden
[picodrive.git] / cpu / musashi / m68k_in.c
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cc68a136 1/*\r
2must fix:\r
3 callm\r
4 chk\r
5*/\r
6/* ======================================================================== */\r
7/* ========================= LICENSING & COPYRIGHT ======================== */\r
8/* ======================================================================== */\r
9/*\r
10 * MUSASHI\r
c6a4c892 11 * Version 3.31\r
cc68a136 12 *\r
13 * A portable Motorola M680x0 processor emulation engine.\r
c6a4c892 14 * Copyright 1998-2007 Karl Stenerud. All rights reserved.\r
cc68a136 15 *\r
16 * This code may be freely used for non-commercial purposes as long as this\r
17 * copyright notice remains unaltered in the source code and any binary files\r
18 * containing this code in compiled form.\r
19 *\r
20 * All other lisencing terms must be negotiated with the author\r
21 * (Karl Stenerud).\r
22 *\r
23 * The latest version of this code can be obtained at:\r
24 * http://kstenerud.cjb.net\r
25 */\r
26\r
27/* Special thanks to Bart Trzynadlowski for his insight into the\r
28 * undocumented features of this chip:\r
29 *\r
30 * http://dynarec.com/~bart/files/68knotes.txt\r
31 */\r
32\r
33\r
34/* Input file for m68kmake\r
35 * -----------------------\r
36 *\r
37 * All sections begin with 80 X's in a row followed by an end-of-line\r
38 * sequence.\r
39 * After this, m68kmake will expect to find one of the following section\r
40 * identifiers:\r
41 * M68KMAKE_PROTOTYPE_HEADER - header for opcode handler prototypes\r
42 * M68KMAKE_PROTOTYPE_FOOTER - footer for opcode handler prototypes\r
43 * M68KMAKE_TABLE_HEADER - header for opcode handler jumptable\r
44 * M68KMAKE_TABLE_FOOTER - footer for opcode handler jumptable\r
45 * M68KMAKE_TABLE_BODY - the table itself\r
46 * M68KMAKE_OPCODE_HANDLER_HEADER - header for opcode handler implementation\r
47 * M68KMAKE_OPCODE_HANDLER_FOOTER - footer for opcode handler implementation\r
48 * M68KMAKE_OPCODE_HANDLER_BODY - body section for opcode handler implementation\r
49 *\r
50 * NOTE: M68KMAKE_OPCODE_HANDLER_BODY must be last in the file and\r
51 * M68KMAKE_TABLE_BODY must be second last in the file.\r
52 *\r
53 * The M68KMAKE_OPHANDLER_BODY section contains the opcode handler\r
54 * primitives themselves. Each opcode handler begins with:\r
55 * M68KMAKE_OP(A, B, C, D)\r
56 *\r
57 * where A is the opcode handler name, B is the size of the operation,\r
58 * C denotes any special processing mode, and D denotes a specific\r
59 * addressing mode.\r
60 * For C and D where nothing is specified, use "."\r
61 *\r
62 * Example:\r
63 * M68KMAKE_OP(abcd, 8, rr, .) abcd, size 8, register to register, default EA\r
64 * M68KMAKE_OP(abcd, 8, mm, ax7) abcd, size 8, memory to memory, register X is A7\r
65 * M68KMAKE_OP(tst, 16, ., pcix) tst, size 16, PCIX addressing\r
66 *\r
67 * All opcode handler primitives end with a closing curly brace "}" at column 1\r
68 *\r
69 * NOTE: Do not place a M68KMAKE_OP() directive inside the opcode handler,\r
70 * and do not put a closing curly brace at column 1 unless it is\r
71 * marking the end of the handler!\r
72 *\r
73 * Inside the handler, m68kmake will recognize M68KMAKE_GET_OPER_xx_xx,\r
74 * M68KMAKE_GET_EA_xx_xx, and M68KMAKE_CC directives, and create multiple\r
75 * opcode handlers to handle variations in the opcode handler.\r
76 * Note: M68KMAKE_CC will only be interpreted in condition code opcodes.\r
77 * As well, M68KMAKE_GET_EA_xx_xx and M68KMAKE_GET_OPER_xx_xx will only\r
78 * be interpreted on instructions where the corresponding table entry\r
79 * specifies multiple effective addressing modes.\r
80 * Example:\r
81 * clr 32 . . 0100001010...... A+-DXWL... U U U 12 6 4\r
82 *\r
83 * This table entry says that the clr.l opcde has 7 variations (A+-DXWL).\r
84 * It is run in user or supervisor mode for all CPUs, and uses 12 cycles for\r
85 * 68000, 6 cycles for 68010, and 4 cycles for 68020.\r
86 */\r
87\r
88XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\r
89M68KMAKE_PROTOTYPE_HEADER\r
90\r
91#ifndef M68KOPS__HEADER\r
92#define M68KOPS__HEADER\r
93\r
94/* ======================================================================== */\r
95/* ============================ OPCODE HANDLERS =========================== */\r
96/* ======================================================================== */\r
97\r
98\r
99\r
100XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\r
101M68KMAKE_PROTOTYPE_FOOTER\r
102\r
103\r
104/* Build the opcode handler table */\r
105void m68ki_build_opcode_table(void);\r
106\r
107extern void (*m68ki_instruction_jump_table[0x10000])(void); /* opcode handler jump table */\r
108extern unsigned char m68ki_cycles[][0x10000];\r
109\r
110\r
111/* ======================================================================== */\r
112/* ============================== END OF FILE ============================= */\r
113/* ======================================================================== */\r
114\r
115#endif /* M68KOPS__HEADER */\r
116\r
117\r
118\r
119XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\r
120M68KMAKE_TABLE_HEADER\r
121\r
122/* ======================================================================== */\r
123/* ========================= OPCODE TABLE BUILDER ========================= */\r
124/* ======================================================================== */\r
125\r
126#include "m68kops.h"\r
127\r
128#define NUM_CPU_TYPES 4\r
129\r
130void (*m68ki_instruction_jump_table[0x10000])(void); /* opcode handler jump table */\r
131unsigned char m68ki_cycles[NUM_CPU_TYPES][0x10000]; /* Cycles used by CPU type */\r
132\r
133/* This is used to generate the opcode handler jump table */\r
134typedef struct\r
135{\r
136 void (*opcode_handler)(void); /* handler function */\r
137 unsigned int mask; /* mask on opcode */\r
138 unsigned int match; /* what to match after masking */\r
139 unsigned char cycles[NUM_CPU_TYPES]; /* cycles each cpu type takes */\r
140} opcode_handler_struct;\r
141\r
142\r
143/* Opcode handler table */\r
144static opcode_handler_struct m68k_opcode_handler_table[] =\r
145{\r
146/* function mask match 000 010 020 040 */\r
147\r
148\r
149\r
150XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\r
151M68KMAKE_TABLE_FOOTER\r
152\r
153 {0, 0, 0, {0, 0, 0, 0}}\r
154};\r
155\r
156\r
157/* Build the opcode handler jump table */\r
158void m68ki_build_opcode_table(void)\r
159{\r
160 opcode_handler_struct *ostruct;\r
161 int instr;\r
162 int i;\r
163 int j;\r
164 int k;\r
165\r
166 for(i = 0; i < 0x10000; i++)\r
167 {\r
168 /* default to illegal */\r
169 m68ki_instruction_jump_table[i] = m68k_op_illegal;\r
170 for(k=0;k<NUM_CPU_TYPES;k++)\r
171 m68ki_cycles[k][i] = 0;\r
172 }\r
173\r
174 ostruct = m68k_opcode_handler_table;\r
175 while(ostruct->mask != 0xff00)\r
176 {\r
177 for(i = 0;i < 0x10000;i++)\r
178 {\r
179 if((i & ostruct->mask) == ostruct->match)\r
180 {\r
181 m68ki_instruction_jump_table[i] = ostruct->opcode_handler;\r
182 for(k=0;k<NUM_CPU_TYPES;k++)\r
183 m68ki_cycles[k][i] = ostruct->cycles[k];\r
184 }\r
185 }\r
186 ostruct++;\r
187 }\r
188 while(ostruct->mask == 0xff00)\r
189 {\r
190 for(i = 0;i <= 0xff;i++)\r
191 {\r
192 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;\r
193 for(k=0;k<NUM_CPU_TYPES;k++)\r
194 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];\r
195 }\r
196 ostruct++;\r
197 }\r
198 while(ostruct->mask == 0xf1f8)\r
199 {\r
200 for(i = 0;i < 8;i++)\r
201 {\r
202 for(j = 0;j < 8;j++)\r
203 {\r
204 instr = ostruct->match | (i << 9) | j;\r
205 m68ki_instruction_jump_table[instr] = ostruct->opcode_handler;\r
206 for(k=0;k<NUM_CPU_TYPES;k++)\r
207 m68ki_cycles[k][instr] = ostruct->cycles[k];\r
208 }\r
209 }\r
210 ostruct++;\r
211 }\r
212 while(ostruct->mask == 0xfff0)\r
213 {\r
214 for(i = 0;i <= 0x0f;i++)\r
215 {\r
216 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;\r
217 for(k=0;k<NUM_CPU_TYPES;k++)\r
218 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];\r
219 }\r
220 ostruct++;\r
221 }\r
222 while(ostruct->mask == 0xf1ff)\r
223 {\r
224 for(i = 0;i <= 0x07;i++)\r
225 {\r
226 m68ki_instruction_jump_table[ostruct->match | (i << 9)] = ostruct->opcode_handler;\r
227 for(k=0;k<NUM_CPU_TYPES;k++)\r
228 m68ki_cycles[k][ostruct->match | (i << 9)] = ostruct->cycles[k];\r
229 }\r
230 ostruct++;\r
231 }\r
232 while(ostruct->mask == 0xfff8)\r
233 {\r
234 for(i = 0;i <= 0x07;i++)\r
235 {\r
236 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;\r
237 for(k=0;k<NUM_CPU_TYPES;k++)\r
238 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];\r
239 }\r
240 ostruct++;\r
241 }\r
242 while(ostruct->mask == 0xffff)\r
243 {\r
244 m68ki_instruction_jump_table[ostruct->match] = ostruct->opcode_handler;\r
245 for(k=0;k<NUM_CPU_TYPES;k++)\r
246 m68ki_cycles[k][ostruct->match] = ostruct->cycles[k];\r
247 ostruct++;\r
248 }\r
249}\r
250\r
251\r
252/* ======================================================================== */\r
253/* ============================== END OF FILE ============================= */\r
254/* ======================================================================== */\r
255\r
256\r
257\r
258XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\r
259M68KMAKE_OPCODE_HANDLER_HEADER\r
260\r
261#include "m68kcpu.h"\r
c6a4c892 262extern void m68040_fpu_op0(void);\r
263extern void m68040_fpu_op1(void);\r
cc68a136 264\r
265/* ======================================================================== */\r
266/* ========================= INSTRUCTION HANDLERS ========================= */\r
267/* ======================================================================== */\r
268\r
269\r
270\r
271XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\r
272M68KMAKE_OPCODE_HANDLER_FOOTER\r
273\r
274/* ======================================================================== */\r
275/* ============================== END OF FILE ============================= */\r
276/* ======================================================================== */\r
277\r
278\r
279\r
280XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\r
281M68KMAKE_TABLE_BODY\r
282\r
283The following table is arranged as follows:\r
284\r
285name: Opcode mnemonic\r
286\r
287size: Operation size\r
288\r
289spec proc: Special processing mode:\r
290 .: normal\r
291 s: static operand\r
292 r: register operand\r
293 rr: register to register\r
294 mm: memory to memory\r
295 er: effective address to register\r
296 re: register to effective address\r
297 dd: data register to data register\r
298 da: data register to address register\r
299 aa: address register to address register\r
300 cr: control register to register\r
301 rc: register to control register\r
302 toc: to condition code register\r
303 tos: to status register\r
304 tou: to user stack pointer\r
305 frc: from condition code register\r
306 frs: from status register\r
307 fru: from user stack pointer\r
308 * for move.x, the special processing mode is a specific\r
309 destination effective addressing mode.\r
310\r
311spec ea: Specific effective addressing mode:\r
312 .: normal\r
313 i: immediate\r
314 d: data register\r
315 a: address register\r
316 ai: address register indirect\r
317 pi: address register indirect with postincrement\r
318 pd: address register indirect with predecrement\r
319 di: address register indirect with displacement\r
320 ix: address register indirect with index\r
321 aw: absolute word address\r
322 al: absolute long address\r
323 pcdi: program counter relative with displacement\r
324 pcix: program counter relative with index\r
325 a7: register specified in instruction is A7\r
326 ax7: register field X of instruction is A7\r
327 ay7: register field Y of instruction is A7\r
328 axy7: register fields X and Y of instruction are A7\r
329\r
330bit pattern: Pattern to recognize this opcode. "." means don't care.\r
331\r
332allowed ea: List of allowed addressing modes:\r
333 .: not present\r
334 A: address register indirect\r
335 +: ARI (address register indirect) with postincrement\r
336 -: ARI with predecrement\r
337 D: ARI with displacement\r
338 X: ARI with index\r
339 W: absolute word address\r
340 L: absolute long address\r
341 d: program counter indirect with displacement\r
342 x: program counter indirect with index\r
343 I: immediate\r
344mode: CPU operating mode for each cpu type. U = user or supervisor,\r
345 S = supervisor only, "." = opcode not present.\r
346\r
347cpu cycles: Base number of cycles required to execute this opcode on the\r
348 specified CPU type.\r
349 Use "." if CPU does not have this opcode.\r
350\r
351\r
352\r
353 spec spec allowed ea mode cpu cycles\r
354name size proc ea bit pattern A+-DXWLdxI 0 1 2 4 000 010 020 040 comments\r
355====== ==== ==== ==== ================ ========== = = = = === === === === =============\r
356M68KMAKE_TABLE_START\r
3571010 0 . . 1010............ .......... U U U U 4 4 4 4\r
3581111 0 . . 1111............ .......... U U U U 4 4 4 4\r
c6a4c892 359040fpu0 32 . . 11110010........ .......... . . . U . . . 0\r
360040fpu1 32 . . 11110011........ .......... . . . U . . . 0\r
cc68a136 361abcd 8 rr . 1100...100000... .......... U U U U 6 6 4 4\r
362abcd 8 mm ax7 1100111100001... .......... U U U U 18 18 16 16\r
363abcd 8 mm ay7 1100...100001111 .......... U U U U 18 18 16 16\r
364abcd 8 mm axy7 1100111100001111 .......... U U U U 18 18 16 16\r
365abcd 8 mm . 1100...100001... .......... U U U U 18 18 16 16\r
366add 8 er d 1101...000000... .......... U U U U 4 4 2 2\r
367add 8 er . 1101...000...... A+-DXWLdxI U U U U 4 4 2 2\r
368add 16 er d 1101...001000... .......... U U U U 4 4 2 2\r
369add 16 er a 1101...001001... .......... U U U U 4 4 2 2\r
370add 16 er . 1101...001...... A+-DXWLdxI U U U U 4 4 2 2\r
371add 32 er d 1101...010000... .......... U U U U 6 6 2 2\r
372add 32 er a 1101...010001... .......... U U U U 6 6 2 2\r
373add 32 er . 1101...010...... A+-DXWLdxI U U U U 6 6 2 2\r
374add 8 re . 1101...100...... A+-DXWL... U U U U 8 8 4 4\r
375add 16 re . 1101...101...... A+-DXWL... U U U U 8 8 4 4\r
376add 32 re . 1101...110...... A+-DXWL... U U U U 12 12 4 4\r
377adda 16 . d 1101...011000... .......... U U U U 8 8 2 2\r
378adda 16 . a 1101...011001... .......... U U U U 8 8 2 2\r
379adda 16 . . 1101...011...... A+-DXWLdxI U U U U 8 8 2 2\r
380adda 32 . d 1101...111000... .......... U U U U 6 6 2 2\r
381adda 32 . a 1101...111001... .......... U U U U 6 6 2 2\r
382adda 32 . . 1101...111...... A+-DXWLdxI U U U U 6 6 2 2\r
383addi 8 . d 0000011000000... .......... U U U U 8 8 2 2\r
384addi 8 . . 0000011000...... A+-DXWL... U U U U 12 12 4 4\r
385addi 16 . d 0000011001000... .......... U U U U 8 8 2 2\r
386addi 16 . . 0000011001...... A+-DXWL... U U U U 12 12 4 4\r
387addi 32 . d 0000011010000... .......... U U U U 16 14 2 2\r
388addi 32 . . 0000011010...... A+-DXWL... U U U U 20 20 4 4\r
389addq 8 . d 0101...000000... .......... U U U U 4 4 2 2\r
390addq 8 . . 0101...000...... A+-DXWL... U U U U 8 8 4 4\r
391addq 16 . d 0101...001000... .......... U U U U 4 4 2 2\r
392addq 16 . a 0101...001001... .......... U U U U 4 4 2 2\r
393addq 16 . . 0101...001...... A+-DXWL... U U U U 8 8 4 4\r
394addq 32 . d 0101...010000... .......... U U U U 8 8 2 2\r
395addq 32 . a 0101...010001... .......... U U U U 8 8 2 2\r
396addq 32 . . 0101...010...... A+-DXWL... U U U U 12 12 4 4\r
397addx 8 rr . 1101...100000... .......... U U U U 4 4 2 2\r
398addx 16 rr . 1101...101000... .......... U U U U 4 4 2 2\r
399addx 32 rr . 1101...110000... .......... U U U U 8 6 2 2\r
400addx 8 mm ax7 1101111100001... .......... U U U U 18 18 12 12\r
401addx 8 mm ay7 1101...100001111 .......... U U U U 18 18 12 12\r
402addx 8 mm axy7 1101111100001111 .......... U U U U 18 18 12 12\r
403addx 8 mm . 1101...100001... .......... U U U U 18 18 12 12\r
404addx 16 mm . 1101...101001... .......... U U U U 18 18 12 12\r
405addx 32 mm . 1101...110001... .......... U U U U 30 30 12 12\r
406and 8 er d 1100...000000... .......... U U U U 4 4 2 2\r
407and 8 er . 1100...000...... A+-DXWLdxI U U U U 4 4 2 2\r
408and 16 er d 1100...001000... .......... U U U U 4 4 2 2\r
409and 16 er . 1100...001...... A+-DXWLdxI U U U U 4 4 2 2\r
410and 32 er d 1100...010000... .......... U U U U 6 6 2 2\r
411and 32 er . 1100...010...... A+-DXWLdxI U U U U 6 6 2 2\r
412and 8 re . 1100...100...... A+-DXWL... U U U U 8 8 4 4\r
413and 16 re . 1100...101...... A+-DXWL... U U U U 8 8 4 4\r
414and 32 re . 1100...110...... A+-DXWL... U U U U 12 12 4 4\r
415andi 16 toc . 0000001000111100 .......... U U U U 20 16 12 12\r
416andi 16 tos . 0000001001111100 .......... S S S S 20 16 12 12\r
417andi 8 . d 0000001000000... .......... U U U U 8 8 2 2\r
418andi 8 . . 0000001000...... A+-DXWL... U U U U 12 12 4 4\r
419andi 16 . d 0000001001000... .......... U U U U 8 8 2 2\r
420andi 16 . . 0000001001...... A+-DXWL... U U U U 12 12 4 4\r
421andi 32 . d 0000001010000... .......... U U U U 14 14 2 2\r
422andi 32 . . 0000001010...... A+-DXWL... U U U U 20 20 4 4\r
423asr 8 s . 1110...000000... .......... U U U U 6 6 6 6\r
424asr 16 s . 1110...001000... .......... U U U U 6 6 6 6\r
425asr 32 s . 1110...010000... .......... U U U U 8 8 6 6\r
426asr 8 r . 1110...000100... .......... U U U U 6 6 6 6\r
427asr 16 r . 1110...001100... .......... U U U U 6 6 6 6\r
428asr 32 r . 1110...010100... .......... U U U U 8 8 6 6\r
429asr 16 . . 1110000011...... A+-DXWL... U U U U 8 8 5 5\r
430asl 8 s . 1110...100000... .......... U U U U 6 6 8 8\r
431asl 16 s . 1110...101000... .......... U U U U 6 6 8 8\r
432asl 32 s . 1110...110000... .......... U U U U 8 8 8 8\r
433asl 8 r . 1110...100100... .......... U U U U 6 6 8 8\r
434asl 16 r . 1110...101100... .......... U U U U 6 6 8 8\r
435asl 32 r . 1110...110100... .......... U U U U 8 8 8 8\r
436asl 16 . . 1110000111...... A+-DXWL... U U U U 8 8 6 6\r
437bcc 8 . . 0110............ .......... U U U U 10 10 6 6\r
438bcc 16 . . 0110....00000000 .......... U U U U 10 10 6 6\r
439bcc 32 . . 0110....11111111 .......... U U U U 10 10 6 6\r
440bchg 8 r . 0000...101...... A+-DXWL... U U U U 8 8 4 4\r
441bchg 32 r d 0000...101000... .......... U U U U 8 8 4 4\r
442bchg 8 s . 0000100001...... A+-DXWL... U U U U 12 12 4 4\r
443bchg 32 s d 0000100001000... .......... U U U U 12 12 4 4\r
444bclr 8 r . 0000...110...... A+-DXWL... U U U U 8 10 4 4\r
445bclr 32 r d 0000...110000... .......... U U U U 10 10 4 4\r
446bclr 8 s . 0000100010...... A+-DXWL... U U U U 12 12 4 4\r
447bclr 32 s d 0000100010000... .......... U U U U 14 14 4 4\r
448bfchg 32 . d 1110101011000... .......... . . U U . . 12 12 timing not quite correct\r
449bfchg 32 . . 1110101011...... A..DXWL... . . U U . . 20 20\r
450bfclr 32 . d 1110110011000... .......... . . U U . . 12 12\r
451bfclr 32 . . 1110110011...... A..DXWL... . . U U . . 20 20\r
452bfexts 32 . d 1110101111000... .......... . . U U . . 8 8\r
453bfexts 32 . . 1110101111...... A..DXWLdx. . . U U . . 15 15\r
454bfextu 32 . d 1110100111000... .......... . . U U . . 8 8\r
455bfextu 32 . . 1110100111...... A..DXWLdx. . . U U . . 15 15\r
456bfffo 32 . d 1110110111000... .......... . . U U . . 18 18\r
457bfffo 32 . . 1110110111...... A..DXWLdx. . . U U . . 28 28\r
458bfins 32 . d 1110111111000... .......... . . U U . . 10 10\r
459bfins 32 . . 1110111111...... A..DXWL... . . U U . . 17 17\r
460bfset 32 . d 1110111011000... .......... . . U U . . 12 12\r
461bfset 32 . . 1110111011...... A..DXWL... . . U U . . 20 20\r
462bftst 32 . d 1110100011000... .......... . . U U . . 6 6\r
463bftst 32 . . 1110100011...... A..DXWLdx. . . U U . . 13 13\r
464bkpt 0 . . 0100100001001... .......... . U U U . 10 10 10\r
465bra 8 . . 01100000........ .......... U U U U 10 10 10 10\r
466bra 16 . . 0110000000000000 .......... U U U U 10 10 10 10\r
467bra 32 . . 0110000011111111 .......... U U U U 10 10 10 10\r
468bset 32 r d 0000...111000... .......... U U U U 8 8 4 4\r
469bset 8 r . 0000...111...... A+-DXWL... U U U U 8 8 4 4\r
470bset 8 s . 0000100011...... A+-DXWL... U U U U 12 12 4 4\r
471bset 32 s d 0000100011000... .......... U U U U 12 12 4 4\r
472bsr 8 . . 01100001........ .......... U U U U 18 18 7 7\r
473bsr 16 . . 0110000100000000 .......... U U U U 18 18 7 7\r
474bsr 32 . . 0110000111111111 .......... U U U U 18 18 7 7\r
475btst 8 r . 0000...100...... A+-DXWLdxI U U U U 4 4 4 4\r
476btst 32 r d 0000...100000... .......... U U U U 6 6 4 4\r
477btst 8 s . 0000100000...... A+-DXWLdx. U U U U 8 8 4 4\r
478btst 32 s d 0000100000000... .......... U U U U 10 10 4 4\r
479callm 32 . . 0000011011...... A..DXWLdx. . . U U . . 60 60 not properly emulated\r
480cas 8 . . 0000101011...... A+-DXWL... . . U U . . 12 12\r
481cas 16 . . 0000110011...... A+-DXWL... . . U U . . 12 12\r
482cas 32 . . 0000111011...... A+-DXWL... . . U U . . 12 12\r
483cas2 16 . . 0000110011111100 .......... . . U U . . 12 12\r
484cas2 32 . . 0000111011111100 .......... . . U U . . 12 12\r
485chk 16 . d 0100...110000... .......... U U U U 10 8 8 8\r
486chk 16 . . 0100...110...... A+-DXWLdxI U U U U 10 8 8 8\r
487chk 32 . d 0100...100000... .......... . . U U . . 8 8\r
488chk 32 . . 0100...100...... A+-DXWLdxI . . U U . . 8 8\r
489chk2cmp2 8 . pcdi 0000000011111010 .......... . . U U . . 23 23\r
490chk2cmp2 8 . pcix 0000000011111011 .......... . . U U . . 23 23\r
491chk2cmp2 8 . . 0000000011...... A..DXWL... . . U U . . 18 18\r
492chk2cmp2 16 . pcdi 0000001011111010 .......... . . U U . . 23 23\r
493chk2cmp2 16 . pcix 0000001011111011 .......... . . U U . . 23 23\r
494chk2cmp2 16 . . 0000001011...... A..DXWL... . . U U . . 18 18\r
495chk2cmp2 32 . pcdi 0000010011111010 .......... . . U U . . 23 23\r
496chk2cmp2 32 . pcix 0000010011111011 .......... . . U U . . 23 23\r
497chk2cmp2 32 . . 0000010011...... A..DXWL... . . U U . . 18 18\r
498clr 8 . d 0100001000000... .......... U U U U 4 4 2 2\r
499clr 8 . . 0100001000...... A+-DXWL... U U U U 6 4 4 4 notaz hack: changed 000 cycles 8 -> 6 like in starscream for Fatal Rewind\r
500clr 16 . d 0100001001000... .......... U U U U 4 4 2 2\r
c6a4c892 501clr 16 . . 0100001001...... A+-DXWL... U U U U 6 4 4 4 notaz hack: ditto\r
cc68a136 502clr 32 . d 0100001010000... .......... U U U U 6 6 2 2\r
503clr 32 . . 0100001010...... A+-DXWL... U U U U 12 6 4 4\r
504cmp 8 . d 1011...000000... .......... U U U U 4 4 2 2\r
505cmp 8 . . 1011...000...... A+-DXWLdxI U U U U 4 4 2 2\r
506cmp 16 . d 1011...001000... .......... U U U U 4 4 2 2\r
507cmp 16 . a 1011...001001... .......... U U U U 4 4 2 2\r
508cmp 16 . . 1011...001...... A+-DXWLdxI U U U U 4 4 2 2\r
509cmp 32 . d 1011...010000... .......... U U U U 6 6 2 2\r
510cmp 32 . a 1011...010001... .......... U U U U 6 6 2 2\r
511cmp 32 . . 1011...010...... A+-DXWLdxI U U U U 6 6 2 2\r
512cmpa 16 . d 1011...011000... .......... U U U U 6 6 4 4\r
513cmpa 16 . a 1011...011001... .......... U U U U 6 6 4 4\r
514cmpa 16 . . 1011...011...... A+-DXWLdxI U U U U 6 6 4 4\r
515cmpa 32 . d 1011...111000... .......... U U U U 6 6 4 4\r
516cmpa 32 . a 1011...111001... .......... U U U U 6 6 4 4\r
517cmpa 32 . . 1011...111...... A+-DXWLdxI U U U U 6 6 4 4\r
518cmpi 8 . d 0000110000000... .......... U U U U 8 8 2 2\r
519cmpi 8 . . 0000110000...... A+-DXWL... U U U U 8 8 2 2\r
520cmpi 8 . pcdi 0000110000111010 .......... . . U U . . 7 7\r
521cmpi 8 . pcix 0000110000111011 .......... . . U U . . 9 9\r
522cmpi 16 . d 0000110001000... .......... U U U U 8 8 2 2\r
523cmpi 16 . . 0000110001...... A+-DXWL... U U U U 8 8 2 2\r
524cmpi 16 . pcdi 0000110001111010 .......... . . U U . . 7 7\r
525cmpi 16 . pcix 0000110001111011 .......... . . U U . . 9 9\r
526cmpi 32 . d 0000110010000... .......... U U U U 14 12 2 2\r
527cmpi 32 . . 0000110010...... A+-DXWL... U U U U 12 12 2 2\r
528cmpi 32 . pcdi 0000110010111010 .......... . . U U . . 7 7\r
529cmpi 32 . pcix 0000110010111011 .......... . . U U . . 9 9\r
530cmpm 8 . ax7 1011111100001... .......... U U U U 12 12 9 9\r
531cmpm 8 . ay7 1011...100001111 .......... U U U U 12 12 9 9\r
532cmpm 8 . axy7 1011111100001111 .......... U U U U 12 12 9 9\r
533cmpm 8 . . 1011...100001... .......... U U U U 12 12 9 9\r
534cmpm 16 . . 1011...101001... .......... U U U U 12 12 9 9\r
535cmpm 32 . . 1011...110001... .......... U U U U 20 20 9 9\r
536cpbcc 32 . . 1111...01....... .......... . . U . . . 4 . unemulated\r
537cpdbcc 32 . . 1111...001001... .......... . . U . . . 4 . unemulated\r
538cpgen 32 . . 1111...000...... .......... . . U . . . 4 . unemulated\r
539cpscc 32 . . 1111...001...... .......... . . U . . . 4 . unemulated\r
540cptrapcc 32 . . 1111...001111... .......... . . U . . . 4 . unemulated\r
541dbt 16 . . 0101000011001... .......... U U U U 12 12 6 6\r
542dbf 16 . . 0101000111001... .......... U U U U 12 12 6 6\r
543dbcc 16 . . 0101....11001... .......... U U U U 12 12 6 6\r
544divs 16 . d 1000...111000... .......... U U U U 158 122 56 56\r
545divs 16 . . 1000...111...... A+-DXWLdxI U U U U 158 122 56 56\r
546divu 16 . d 1000...011000... .......... U U U U 140 108 44 44\r
547divu 16 . . 1000...011...... A+-DXWLdxI U U U U 140 108 44 44\r
548divl 32 . d 0100110001000... .......... . . U U . . 84 84\r
549divl 32 . . 0100110001...... A+-DXWLdxI . . U U . . 84 84\r
550eor 8 . d 1011...100000... .......... U U U U 4 4 2 2\r
551eor 8 . . 1011...100...... A+-DXWL... U U U U 8 8 4 4\r
552eor 16 . d 1011...101000... .......... U U U U 4 4 2 2\r
553eor 16 . . 1011...101...... A+-DXWL... U U U U 8 8 4 4\r
554eor 32 . d 1011...110000... .......... U U U U 8 6 2 2\r
555eor 32 . . 1011...110...... A+-DXWL... U U U U 12 12 4 4\r
556eori 16 toc . 0000101000111100 .......... U U U U 20 16 12 12\r
557eori 16 tos . 0000101001111100 .......... S S S S 20 16 12 12\r
558eori 8 . d 0000101000000... .......... U U U U 8 8 2 2\r
559eori 8 . . 0000101000...... A+-DXWL... U U U U 12 12 4 4\r
560eori 16 . d 0000101001000... .......... U U U U 8 8 2 2\r
561eori 16 . . 0000101001...... A+-DXWL... U U U U 12 12 4 4\r
562eori 32 . d 0000101010000... .......... U U U U 16 14 2 2\r
563eori 32 . . 0000101010...... A+-DXWL... U U U U 20 20 4 4\r
564exg 32 dd . 1100...101000... .......... U U U U 6 6 2 2\r
565exg 32 aa . 1100...101001... .......... U U U U 6 6 2 2\r
566exg 32 da . 1100...110001... .......... U U U U 6 6 2 2\r
567ext 16 . . 0100100010000... .......... U U U U 4 4 4 4\r
568ext 32 . . 0100100011000... .......... U U U U 4 4 4 4\r
569extb 32 . . 0100100111000... .......... . . U U . . 4 4\r
570illegal 0 . . 0100101011111100 .......... U U U U 4 4 4 4\r
571jmp 32 . . 0100111011...... A..DXWLdx. U U U U 4 4 0 0\r
572jsr 32 . . 0100111010...... A..DXWLdx. U U U U 12 12 0 0\r
573lea 32 . . 0100...111...... A..DXWLdx. U U U U 0 0 2 2\r
574link 16 . a7 0100111001010111 .......... U U U U 16 16 5 5\r
575link 16 . . 0100111001010... .......... U U U U 16 16 5 5\r
576link 32 . a7 0100100000001111 .......... . . U U . . 6 6\r
577link 32 . . 0100100000001... .......... . . U U . . 6 6\r
578lsr 8 s . 1110...000001... .......... U U U U 6 6 4 4\r
579lsr 16 s . 1110...001001... .......... U U U U 6 6 4 4\r
580lsr 32 s . 1110...010001... .......... U U U U 8 8 4 4\r
581lsr 8 r . 1110...000101... .......... U U U U 6 6 6 6\r
582lsr 16 r . 1110...001101... .......... U U U U 6 6 6 6\r
583lsr 32 r . 1110...010101... .......... U U U U 8 8 6 6\r
584lsr 16 . . 1110001011...... A+-DXWL... U U U U 8 8 5 5\r
585lsl 8 s . 1110...100001... .......... U U U U 6 6 4 4\r
586lsl 16 s . 1110...101001... .......... U U U U 6 6 4 4\r
587lsl 32 s . 1110...110001... .......... U U U U 8 8 4 4\r
588lsl 8 r . 1110...100101... .......... U U U U 6 6 6 6\r
589lsl 16 r . 1110...101101... .......... U U U U 6 6 6 6\r
590lsl 32 r . 1110...110101... .......... U U U U 8 8 6 6\r
591lsl 16 . . 1110001111...... A+-DXWL... U U U U 8 8 5 5\r
592move 8 d d 0001...000000... .......... U U U U 4 4 2 2\r
593move 8 d . 0001...000...... A+-DXWLdxI U U U U 4 4 2 2\r
594move 8 ai d 0001...010000... .......... U U U U 8 8 4 4\r
595move 8 ai . 0001...010...... A+-DXWLdxI U U U U 8 8 4 4\r
596move 8 pi d 0001...011000... .......... U U U U 8 8 4 4\r
597move 8 pi . 0001...011...... A+-DXWLdxI U U U U 8 8 4 4\r
598move 8 pi7 d 0001111011000... .......... U U U U 8 8 4 4\r
599move 8 pi7 . 0001111011...... A+-DXWLdxI U U U U 8 8 4 4\r
600move 8 pd d 0001...100000... .......... U U U U 8 8 5 5\r
601move 8 pd . 0001...100...... A+-DXWLdxI U U U U 8 8 5 5\r
602move 8 pd7 d 0001111100000... .......... U U U U 8 8 5 5\r
603move 8 pd7 . 0001111100...... A+-DXWLdxI U U U U 8 8 5 5\r
604move 8 di d 0001...101000... .......... U U U U 12 12 5 5\r
605move 8 di . 0001...101...... A+-DXWLdxI U U U U 12 12 5 5\r
606move 8 ix d 0001...110000... .......... U U U U 14 14 7 7\r
607move 8 ix . 0001...110...... A+-DXWLdxI U U U U 14 14 7 7\r
608move 8 aw d 0001000111000... .......... U U U U 12 12 4 4\r
609move 8 aw . 0001000111...... A+-DXWLdxI U U U U 12 12 4 4\r
610move 8 al d 0001001111000... .......... U U U U 16 16 6 6\r
611move 8 al . 0001001111...... A+-DXWLdxI U U U U 16 16 6 6\r
612move 16 d d 0011...000000... .......... U U U U 4 4 2 2\r
613move 16 d a 0011...000001... .......... U U U U 4 4 2 2\r
614move 16 d . 0011...000...... A+-DXWLdxI U U U U 4 4 2 2\r
615move 16 ai d 0011...010000... .......... U U U U 8 8 4 4\r
616move 16 ai a 0011...010001... .......... U U U U 8 8 4 4\r
617move 16 ai . 0011...010...... A+-DXWLdxI U U U U 8 8 4 4\r
618move 16 pi d 0011...011000... .......... U U U U 8 8 4 4\r
619move 16 pi a 0011...011001... .......... U U U U 8 8 4 4\r
620move 16 pi . 0011...011...... A+-DXWLdxI U U U U 8 8 4 4\r
621move 16 pd d 0011...100000... .......... U U U U 8 8 5 5\r
622move 16 pd a 0011...100001... .......... U U U U 8 8 5 5\r
623move 16 pd . 0011...100...... A+-DXWLdxI U U U U 8 8 5 5\r
624move 16 di d 0011...101000... .......... U U U U 12 12 5 5\r
625move 16 di a 0011...101001... .......... U U U U 12 12 5 5\r
626move 16 di . 0011...101...... A+-DXWLdxI U U U U 12 12 5 5\r
627move 16 ix d 0011...110000... .......... U U U U 14 14 7 7\r
628move 16 ix a 0011...110001... .......... U U U U 14 14 7 7\r
629move 16 ix . 0011...110...... A+-DXWLdxI U U U U 14 14 7 7\r
630move 16 aw d 0011000111000... .......... U U U U 12 12 4 4\r
631move 16 aw a 0011000111001... .......... U U U U 12 12 4 4\r
632move 16 aw . 0011000111...... A+-DXWLdxI U U U U 12 12 4 4\r
633move 16 al d 0011001111000... .......... U U U U 16 16 6 6\r
634move 16 al a 0011001111001... .......... U U U U 16 16 6 6\r
635move 16 al . 0011001111...... A+-DXWLdxI U U U U 16 16 6 6\r
636move 32 d d 0010...000000... .......... U U U U 4 4 2 2\r
637move 32 d a 0010...000001... .......... U U U U 4 4 2 2\r
638move 32 d . 0010...000...... A+-DXWLdxI U U U U 4 4 2 2\r
639move 32 ai d 0010...010000... .......... U U U U 12 12 4 4\r
640move 32 ai a 0010...010001... .......... U U U U 12 12 4 4\r
641move 32 ai . 0010...010...... A+-DXWLdxI U U U U 12 12 4 4\r
642move 32 pi d 0010...011000... .......... U U U U 12 12 4 4\r
643move 32 pi a 0010...011001... .......... U U U U 12 12 4 4\r
644move 32 pi . 0010...011...... A+-DXWLdxI U U U U 12 12 4 4\r
645move 32 pd d 0010...100000... .......... U U U U 12 14 5 5\r
646move 32 pd a 0010...100001... .......... U U U U 12 14 5 5\r
647move 32 pd . 0010...100...... A+-DXWLdxI U U U U 12 14 5 5\r
648move 32 di d 0010...101000... .......... U U U U 16 16 5 5\r
649move 32 di a 0010...101001... .......... U U U U 16 16 5 5\r
650move 32 di . 0010...101...... A+-DXWLdxI U U U U 16 16 5 5\r
651move 32 ix d 0010...110000... .......... U U U U 18 18 7 7\r
652move 32 ix a 0010...110001... .......... U U U U 18 18 7 7\r
653move 32 ix . 0010...110...... A+-DXWLdxI U U U U 18 18 7 7\r
654move 32 aw d 0010000111000... .......... U U U U 16 16 4 4\r
655move 32 aw a 0010000111001... .......... U U U U 16 16 4 4\r
656move 32 aw . 0010000111...... A+-DXWLdxI U U U U 16 16 4 4\r
657move 32 al d 0010001111000... .......... U U U U 20 20 6 6\r
658move 32 al a 0010001111001... .......... U U U U 20 20 6 6\r
659move 32 al . 0010001111...... A+-DXWLdxI U U U U 20 20 6 6\r
660movea 16 . d 0011...001000... .......... U U U U 4 4 2 2\r
661movea 16 . a 0011...001001... .......... U U U U 4 4 2 2\r
662movea 16 . . 0011...001...... A+-DXWLdxI U U U U 4 4 2 2\r
663movea 32 . d 0010...001000... .......... U U U U 4 4 2 2\r
664movea 32 . a 0010...001001... .......... U U U U 4 4 2 2\r
665movea 32 . . 0010...001...... A+-DXWLdxI U U U U 4 4 2 2\r
666move 16 frc d 0100001011000... .......... . U U U . 4 4 4\r
667move 16 frc . 0100001011...... A+-DXWL... . U U U . 8 4 4\r
668move 16 toc d 0100010011000... .......... U U U U 12 12 4 4\r
669move 16 toc . 0100010011...... A+-DXWLdxI U U U U 12 12 4 4\r
670move 16 frs d 0100000011000... .......... U S S S 6 4 8 8 U only for 000\r
671move 16 frs . 0100000011...... A+-DXWL... U S S S 8 8 8 8 U only for 000\r
672move 16 tos d 0100011011000... .......... S S S S 12 12 8 8\r
673move 16 tos . 0100011011...... A+-DXWLdxI S S S S 12 12 8 8\r
674move 32 fru . 0100111001101... .......... S S S S 4 6 2 2\r
675move 32 tou . 0100111001100... .......... S S S S 4 6 2 2\r
676movec 32 cr . 0100111001111010 .......... . S S S . 12 6 6\r
677movec 32 rc . 0100111001111011 .......... . S S S . 10 12 12\r
678movem 16 re pd 0100100010100... .......... U U U U 8 8 4 4\r
679movem 16 re . 0100100010...... A..DXWL... U U U U 8 8 4 4\r
680movem 32 re pd 0100100011100... .......... U U U U 8 8 4 4\r
681movem 32 re . 0100100011...... A..DXWL... U U U U 8 8 4 4\r
682movem 16 er pi 0100110010011... .......... U U U U 12 12 8 8\r
683movem 16 er pcdi 0100110010111010 .......... U U U U 16 16 9 9\r
684movem 16 er pcix 0100110010111011 .......... U U U U 18 18 11 11\r
685movem 16 er . 0100110010...... A..DXWL... U U U U 12 12 8 8\r
686movem 32 er pi 0100110011011... .......... U U U U 12 12 8 8\r
687movem 32 er pcdi 0100110011111010 .......... U U U U 16 16 9 9\r
688movem 32 er pcix 0100110011111011 .......... U U U U 18 18 11 11\r
689movem 32 er . 0100110011...... A..DXWL... U U U U 12 12 8 8\r
690movep 16 er . 0000...100001... .......... U U U U 16 16 12 12\r
691movep 32 er . 0000...101001... .......... U U U U 24 24 18 18\r
692movep 16 re . 0000...110001... .......... U U U U 16 16 11 11\r
693movep 32 re . 0000...111001... .......... U U U U 24 24 17 17\r
694moveq 32 . . 0111...0........ .......... U U U U 4 4 2 2\r
695moves 8 . . 0000111000...... A+-DXWL... . S S S . 14 5 5\r
696moves 16 . . 0000111001...... A+-DXWL... . S S S . 14 5 5\r
697moves 32 . . 0000111010...... A+-DXWL... . S S S . 16 5 5\r
698move16 32 . . 1111011000100... .......... . . . U . . . 4 TODO: correct timing\r
699muls 16 . d 1100...111000... .......... U U U U 54 32 27 27\r
700muls 16 . . 1100...111...... A+-DXWLdxI U U U U 54 32 27 27\r
701mulu 16 . d 1100...011000... .......... U U U U 54 30 27 27\r
702mulu 16 . . 1100...011...... A+-DXWLdxI U U U U 54 30 27 27\r
703mull 32 . d 0100110000000... .......... . . U U . . 43 43\r
704mull 32 . . 0100110000...... A+-DXWLdxI . . U U . . 43 43\r
705nbcd 8 . d 0100100000000... .......... U U U U 6 6 6 6\r
706nbcd 8 . . 0100100000...... A+-DXWL... U U U U 8 8 6 6\r
707neg 8 . d 0100010000000... .......... U U U U 4 4 2 2\r
708neg 8 . . 0100010000...... A+-DXWL... U U U U 8 8 4 4\r
709neg 16 . d 0100010001000... .......... U U U U 4 4 2 2\r
710neg 16 . . 0100010001...... A+-DXWL... U U U U 8 8 4 4\r
711neg 32 . d 0100010010000... .......... U U U U 6 6 2 2\r
712neg 32 . . 0100010010...... A+-DXWL... U U U U 12 12 4 4\r
713negx 8 . d 0100000000000... .......... U U U U 4 4 2 2\r
714negx 8 . . 0100000000...... A+-DXWL... U U U U 8 8 4 4\r
715negx 16 . d 0100000001000... .......... U U U U 4 4 2 2\r
716negx 16 . . 0100000001...... A+-DXWL... U U U U 8 8 4 4\r
717negx 32 . d 0100000010000... .......... U U U U 6 6 2 2\r
718negx 32 . . 0100000010...... A+-DXWL... U U U U 12 12 4 4\r
719nop 0 . . 0100111001110001 .......... U U U U 4 4 2 2\r
720not 8 . d 0100011000000... .......... U U U U 4 4 2 2\r
721not 8 . . 0100011000...... A+-DXWL... U U U U 8 8 4 4\r
722not 16 . d 0100011001000... .......... U U U U 4 4 2 2\r
723not 16 . . 0100011001...... A+-DXWL... U U U U 8 8 4 4\r
724not 32 . d 0100011010000... .......... U U U U 6 6 2 2\r
725not 32 . . 0100011010...... A+-DXWL... U U U U 12 12 4 4\r
726or 8 er d 1000...000000... .......... U U U U 4 4 2 2\r
727or 8 er . 1000...000...... A+-DXWLdxI U U U U 4 4 2 2\r
728or 16 er d 1000...001000... .......... U U U U 4 4 2 2\r
729or 16 er . 1000...001...... A+-DXWLdxI U U U U 4 4 2 2\r
730or 32 er d 1000...010000... .......... U U U U 6 6 2 2\r
731or 32 er . 1000...010...... A+-DXWLdxI U U U U 6 6 2 2\r
732or 8 re . 1000...100...... A+-DXWL... U U U U 8 8 4 4\r
733or 16 re . 1000...101...... A+-DXWL... U U U U 8 8 4 4\r
734or 32 re . 1000...110...... A+-DXWL... U U U U 12 12 4 4\r
735ori 16 toc . 0000000000111100 .......... U U U U 20 16 12 12\r
736ori 16 tos . 0000000001111100 .......... S S S S 20 16 12 12\r
737ori 8 . d 0000000000000... .......... U U U U 8 8 2 2\r
738ori 8 . . 0000000000...... A+-DXWL... U U U U 12 12 4 4\r
739ori 16 . d 0000000001000... .......... U U U U 8 8 2 2\r
740ori 16 . . 0000000001...... A+-DXWL... U U U U 12 12 4 4\r
741ori 32 . d 0000000010000... .......... U U U U 16 14 2 2\r
742ori 32 . . 0000000010...... A+-DXWL... U U U U 20 20 4 4\r
743pack 16 rr . 1000...101000... .......... . . U U . . 6 6\r
744pack 16 mm ax7 1000111101001... .......... . . U U . . 13 13\r
745pack 16 mm ay7 1000...101001111 .......... . . U U . . 13 13\r
746pack 16 mm axy7 1000111101001111 .......... . . U U . . 13 13\r
747pack 16 mm . 1000...101001... .......... . . U U . . 13 13\r
748pea 32 . . 0100100001...... A..DXWLdx. U U U U 6 6 5 5\r
749pflush 32 . . 1111010100011000 .......... . . . S . . . 4 TODO: correct timing\r
750reset 0 . . 0100111001110000 .......... S S S S 0 0 0 0\r
751ror 8 s . 1110...000011... .......... U U U U 6 6 8 8\r
752ror 16 s . 1110...001011... .......... U U U U 6 6 8 8\r
753ror 32 s . 1110...010011... .......... U U U U 8 8 8 8\r
754ror 8 r . 1110...000111... .......... U U U U 6 6 8 8\r
755ror 16 r . 1110...001111... .......... U U U U 6 6 8 8\r
756ror 32 r . 1110...010111... .......... U U U U 8 8 8 8\r
757ror 16 . . 1110011011...... A+-DXWL... U U U U 8 8 7 7\r
758rol 8 s . 1110...100011... .......... U U U U 6 6 8 8\r
759rol 16 s . 1110...101011... .......... U U U U 6 6 8 8\r
760rol 32 s . 1110...110011... .......... U U U U 8 8 8 8\r
761rol 8 r . 1110...100111... .......... U U U U 6 6 8 8\r
762rol 16 r . 1110...101111... .......... U U U U 6 6 8 8\r
763rol 32 r . 1110...110111... .......... U U U U 8 8 8 8\r
764rol 16 . . 1110011111...... A+-DXWL... U U U U 8 8 7 7\r
765roxr 8 s . 1110...000010... .......... U U U U 6 6 12 12\r
766roxr 16 s . 1110...001010... .......... U U U U 6 6 12 12\r
767roxr 32 s . 1110...010010... .......... U U U U 8 8 12 12\r
768roxr 8 r . 1110...000110... .......... U U U U 6 6 12 12\r
769roxr 16 r . 1110...001110... .......... U U U U 6 6 12 12\r
770roxr 32 r . 1110...010110... .......... U U U U 8 8 12 12\r
771roxr 16 . . 1110010011...... A+-DXWL... U U U U 8 8 5 5\r
772roxl 8 s . 1110...100010... .......... U U U U 6 6 12 12\r
773roxl 16 s . 1110...101010... .......... U U U U 6 6 12 12\r
774roxl 32 s . 1110...110010... .......... U U U U 8 8 12 12\r
775roxl 8 r . 1110...100110... .......... U U U U 6 6 12 12\r
776roxl 16 r . 1110...101110... .......... U U U U 6 6 12 12\r
777roxl 32 r . 1110...110110... .......... U U U U 8 8 12 12\r
778roxl 16 . . 1110010111...... A+-DXWL... U U U U 8 8 5 5\r
779rtd 32 . . 0100111001110100 .......... . U U U . 16 10 10\r
780rte 32 . . 0100111001110011 .......... S S S S 20 24 20 20 bus fault not emulated\r
781rtm 32 . . 000001101100.... .......... . . U U . . 19 19 not properly emulated\r
782rtr 32 . . 0100111001110111 .......... U U U U 20 20 14 14\r
783rts 32 . . 0100111001110101 .......... U U U U 16 16 10 10\r
784sbcd 8 rr . 1000...100000... .......... U U U U 6 6 4 4\r
785sbcd 8 mm ax7 1000111100001... .......... U U U U 18 18 16 16\r
786sbcd 8 mm ay7 1000...100001111 .......... U U U U 18 18 16 16\r
787sbcd 8 mm axy7 1000111100001111 .......... U U U U 18 18 16 16\r
788sbcd 8 mm . 1000...100001... .......... U U U U 18 18 16 16\r
789st 8 . d 0101000011000... .......... U U U U 6 4 4 4\r
790st 8 . . 0101000011...... A+-DXWL... U U U U 8 8 6 6\r
791sf 8 . d 0101000111000... .......... U U U U 4 4 4 4\r
792sf 8 . . 0101000111...... A+-DXWL... U U U U 8 8 6 6\r
793scc 8 . d 0101....11000... .......... U U U U 4 4 4 4\r
794scc 8 . . 0101....11...... A+-DXWL... U U U U 8 8 6 6\r
795stop 0 . . 0100111001110010 .......... S S S S 4 4 8 8\r
796sub 8 er d 1001...000000... .......... U U U U 4 4 2 2\r
797sub 8 er . 1001...000...... A+-DXWLdxI U U U U 4 4 2 2\r
798sub 16 er d 1001...001000... .......... U U U U 4 4 2 2\r
799sub 16 er a 1001...001001... .......... U U U U 4 4 2 2\r
800sub 16 er . 1001...001...... A+-DXWLdxI U U U U 4 4 2 2\r
801sub 32 er d 1001...010000... .......... U U U U 6 6 2 2\r
802sub 32 er a 1001...010001... .......... U U U U 6 6 2 2\r
803sub 32 er . 1001...010...... A+-DXWLdxI U U U U 6 6 2 2\r
804sub 8 re . 1001...100...... A+-DXWL... U U U U 8 8 4 4\r
805sub 16 re . 1001...101...... A+-DXWL... U U U U 8 8 4 4\r
806sub 32 re . 1001...110...... A+-DXWL... U U U U 12 12 4 4\r
807suba 16 . d 1001...011000... .......... U U U U 8 8 2 2\r
808suba 16 . a 1001...011001... .......... U U U U 8 8 2 2\r
809suba 16 . . 1001...011...... A+-DXWLdxI U U U U 8 8 2 2\r
810suba 32 . d 1001...111000... .......... U U U U 6 6 2 2\r
811suba 32 . a 1001...111001... .......... U U U U 6 6 2 2\r
812suba 32 . . 1001...111...... A+-DXWLdxI U U U U 6 6 2 2\r
813subi 8 . d 0000010000000... .......... U U U U 8 8 2 2\r
814subi 8 . . 0000010000...... A+-DXWL... U U U U 12 12 4 4\r
815subi 16 . d 0000010001000... .......... U U U U 8 8 2 2\r
816subi 16 . . 0000010001...... A+-DXWL... U U U U 12 12 4 4\r
817subi 32 . d 0000010010000... .......... U U U U 16 14 2 2\r
818subi 32 . . 0000010010...... A+-DXWL... U U U U 20 20 4 4\r
819subq 8 . d 0101...100000... .......... U U U U 4 4 2 2\r
820subq 8 . . 0101...100...... A+-DXWL... U U U U 8 8 4 4\r
821subq 16 . d 0101...101000... .......... U U U U 4 4 2 2\r
822subq 16 . a 0101...101001... .......... U U U U 8 4 2 2\r
823subq 16 . . 0101...101...... A+-DXWL... U U U U 8 8 4 4\r
824subq 32 . d 0101...110000... .......... U U U U 8 8 2 2\r
825subq 32 . a 0101...110001... .......... U U U U 8 8 2 2\r
826subq 32 . . 0101...110...... A+-DXWL... U U U U 12 12 4 4\r
827subx 8 rr . 1001...100000... .......... U U U U 4 4 2 2\r
828subx 16 rr . 1001...101000... .......... U U U U 4 4 2 2\r
829subx 32 rr . 1001...110000... .......... U U U U 8 6 2 2\r
830subx 8 mm ax7 1001111100001... .......... U U U U 18 18 12 12\r
831subx 8 mm ay7 1001...100001111 .......... U U U U 18 18 12 12\r
832subx 8 mm axy7 1001111100001111 .......... U U U U 18 18 12 12\r
833subx 8 mm . 1001...100001... .......... U U U U 18 18 12 12\r
834subx 16 mm . 1001...101001... .......... U U U U 18 18 12 12\r
835subx 32 mm . 1001...110001... .......... U U U U 30 30 12 12\r
836swap 32 . . 0100100001000... .......... U U U U 4 4 4 4\r
837tas 8 . d 0100101011000... .......... U U U U 4 4 4 4\r
838tas 8 . . 0100101011...... A+-DXWL... U U U U 14 14 12 12\r
839trap 0 . . 010011100100.... .......... U U U U 4 4 4 4\r
840trapt 0 . . 0101000011111100 .......... . . U U . . 4 4\r
841trapt 16 . . 0101000011111010 .......... . . U U . . 6 6\r
842trapt 32 . . 0101000011111011 .......... . . U U . . 8 8\r
843trapf 0 . . 0101000111111100 .......... . . U U . . 4 4\r
844trapf 16 . . 0101000111111010 .......... . . U U . . 6 6\r
845trapf 32 . . 0101000111111011 .......... . . U U . . 8 8\r
846trapcc 0 . . 0101....11111100 .......... . . U U . . 4 4\r
847trapcc 16 . . 0101....11111010 .......... . . U U . . 6 6\r
848trapcc 32 . . 0101....11111011 .......... . . U U . . 8 8\r
849trapv 0 . . 0100111001110110 .......... U U U U 4 4 4 4\r
850tst 8 . d 0100101000000... .......... U U U U 4 4 2 2\r
851tst 8 . . 0100101000...... A+-DXWL... U U U U 4 4 2 2\r
852tst 8 . pcdi 0100101000111010 .......... . . U U . . 7 7\r
853tst 8 . pcix 0100101000111011 .......... . . U U . . 9 9\r
854tst 8 . i 0100101000111100 .......... . . U U . . 6 6\r
855tst 16 . d 0100101001000... .......... U U U U 4 4 2 2\r
856tst 16 . a 0100101001001... .......... . . U U . . 2 2\r
857tst 16 . . 0100101001...... A+-DXWL... U U U U 4 4 2 2\r
858tst 16 . pcdi 0100101001111010 .......... . . U U . . 7 7\r
859tst 16 . pcix 0100101001111011 .......... . . U U . . 9 9\r
860tst 16 . i 0100101001111100 .......... . . U U . . 6 6\r
861tst 32 . d 0100101010000... .......... U U U U 4 4 2 2\r
862tst 32 . a 0100101010001... .......... . . U U . . 2 2\r
863tst 32 . . 0100101010...... A+-DXWL... U U U U 4 4 2 2\r
864tst 32 . pcdi 0100101010111010 .......... . . U U . . 7 7\r
865tst 32 . pcix 0100101010111011 .......... . . U U . . 9 9\r
866tst 32 . i 0100101010111100 .......... . . U U . . 6 6\r
867unlk 32 . a7 0100111001011111 .......... U U U U 12 12 6 6\r
868unlk 32 . . 0100111001011... .......... U U U U 12 12 6 6\r
869unpk 16 rr . 1000...110000... .......... . . U U . . 8 8\r
870unpk 16 mm ax7 1000111110001... .......... . . U U . . 13 13\r
871unpk 16 mm ay7 1000...110001111 .......... . . U U . . 13 13\r
872unpk 16 mm axy7 1000111110001111 .......... . . U U . . 13 13\r
873unpk 16 mm . 1000...110001... .......... . . U U . . 13 13\r
874\r
875\r
876\r
877XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\r
878M68KMAKE_OPCODE_HANDLER_BODY\r
879\r
880M68KMAKE_OP(1010, 0, ., .)\r
881{\r
882 m68ki_exception_1010();\r
883}\r
884\r
885\r
886M68KMAKE_OP(1111, 0, ., .)\r
887{\r
888 m68ki_exception_1111();\r
889}\r
890\r
891\r
c6a4c892 892M68KMAKE_OP(040fpu0, 32, ., .)\r
893{\r
894 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
895 {\r
896 m68040_fpu_op0();\r
897 return;\r
898 }\r
899 m68ki_exception_1111();\r
900}\r
901\r
902\r
903M68KMAKE_OP(040fpu1, 32, ., .)\r
904{\r
905 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
906 {\r
907 m68040_fpu_op1();\r
908 return;\r
909 }\r
910 m68ki_exception_1111();\r
911}\r
912\r
913\r
914\r
cc68a136 915M68KMAKE_OP(abcd, 8, rr, .)\r
916{\r
917 uint* r_dst = &DX;\r
918 uint src = DY;\r
919 uint dst = *r_dst;\r
920 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();\r
921\r
922 FLAG_V = ~res; /* Undefined V behavior */\r
923\r
924 if(res > 9)\r
925 res += 6;\r
926 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);\r
927 FLAG_X = FLAG_C = (res > 0x99) << 8;\r
928 if(FLAG_C)\r
929 res -= 0xa0;\r
930\r
931 FLAG_V &= res; /* Undefined V behavior part II */\r
932 FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
933\r
934 res = MASK_OUT_ABOVE_8(res);\r
935 FLAG_Z |= res;\r
936\r
937 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
938}\r
939\r
940\r
941M68KMAKE_OP(abcd, 8, mm, ax7)\r
942{\r
943 uint src = OPER_AY_PD_8();\r
944 uint ea = EA_A7_PD_8();\r
945 uint dst = m68ki_read_8(ea);\r
946 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();\r
947\r
948 FLAG_V = ~res; /* Undefined V behavior */\r
949\r
950 if(res > 9)\r
951 res += 6;\r
952 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);\r
953 FLAG_X = FLAG_C = (res > 0x99) << 8;\r
954 if(FLAG_C)\r
955 res -= 0xa0;\r
956\r
957 FLAG_V &= res; /* Undefined V behavior part II */\r
958 FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
959\r
960 res = MASK_OUT_ABOVE_8(res);\r
961 FLAG_Z |= res;\r
962\r
963 m68ki_write_8(ea, res);\r
964}\r
965\r
966\r
967M68KMAKE_OP(abcd, 8, mm, ay7)\r
968{\r
969 uint src = OPER_A7_PD_8();\r
970 uint ea = EA_AX_PD_8();\r
971 uint dst = m68ki_read_8(ea);\r
972 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();\r
973\r
974 FLAG_V = ~res; /* Undefined V behavior */\r
975\r
976 if(res > 9)\r
977 res += 6;\r
978 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);\r
979 FLAG_X = FLAG_C = (res > 0x99) << 8;\r
980 if(FLAG_C)\r
981 res -= 0xa0;\r
982\r
983 FLAG_V &= res; /* Undefined V behavior part II */\r
984 FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
985\r
986 res = MASK_OUT_ABOVE_8(res);\r
987 FLAG_Z |= res;\r
988\r
989 m68ki_write_8(ea, res);\r
990}\r
991\r
992\r
993M68KMAKE_OP(abcd, 8, mm, axy7)\r
994{\r
995 uint src = OPER_A7_PD_8();\r
996 uint ea = EA_A7_PD_8();\r
997 uint dst = m68ki_read_8(ea);\r
998 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();\r
999\r
1000 FLAG_V = ~res; /* Undefined V behavior */\r
1001\r
1002 if(res > 9)\r
1003 res += 6;\r
1004 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);\r
1005 FLAG_X = FLAG_C = (res > 0x99) << 8;\r
1006 if(FLAG_C)\r
1007 res -= 0xa0;\r
1008\r
1009 FLAG_V &= res; /* Undefined V behavior part II */\r
1010 FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
1011\r
1012 res = MASK_OUT_ABOVE_8(res);\r
1013 FLAG_Z |= res;\r
1014\r
1015 m68ki_write_8(ea, res);\r
1016}\r
1017\r
1018\r
1019M68KMAKE_OP(abcd, 8, mm, .)\r
1020{\r
1021 uint src = OPER_AY_PD_8();\r
1022 uint ea = EA_AX_PD_8();\r
1023 uint dst = m68ki_read_8(ea);\r
1024 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();\r
1025\r
1026 FLAG_V = ~res; /* Undefined V behavior */\r
1027\r
1028 if(res > 9)\r
1029 res += 6;\r
1030 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);\r
1031 FLAG_X = FLAG_C = (res > 0x99) << 8;\r
1032 if(FLAG_C)\r
1033 res -= 0xa0;\r
1034\r
1035 FLAG_V &= res; /* Undefined V behavior part II */\r
1036 FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
1037\r
1038 res = MASK_OUT_ABOVE_8(res);\r
1039 FLAG_Z |= res;\r
1040\r
1041 m68ki_write_8(ea, res);\r
1042}\r
1043\r
1044\r
1045M68KMAKE_OP(add, 8, er, d)\r
1046{\r
1047 uint* r_dst = &DX;\r
1048 uint src = MASK_OUT_ABOVE_8(DY);\r
1049 uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
1050 uint res = src + dst;\r
1051\r
1052 FLAG_N = NFLAG_8(res);\r
1053 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1054 FLAG_X = FLAG_C = CFLAG_8(res);\r
1055 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
1056\r
1057 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;\r
1058}\r
1059\r
1060\r
1061M68KMAKE_OP(add, 8, er, .)\r
1062{\r
1063 uint* r_dst = &DX;\r
1064 uint src = M68KMAKE_GET_OPER_AY_8;\r
1065 uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
1066 uint res = src + dst;\r
1067\r
1068 FLAG_N = NFLAG_8(res);\r
1069 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1070 FLAG_X = FLAG_C = CFLAG_8(res);\r
1071 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
1072\r
1073 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;\r
1074}\r
1075\r
1076\r
1077M68KMAKE_OP(add, 16, er, d)\r
1078{\r
1079 uint* r_dst = &DX;\r
1080 uint src = MASK_OUT_ABOVE_16(DY);\r
1081 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
1082 uint res = src + dst;\r
1083\r
1084 FLAG_N = NFLAG_16(res);\r
1085 FLAG_V = VFLAG_ADD_16(src, dst, res);\r
1086 FLAG_X = FLAG_C = CFLAG_16(res);\r
1087 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
1088\r
1089 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
1090}\r
1091\r
1092\r
1093M68KMAKE_OP(add, 16, er, a)\r
1094{\r
1095 uint* r_dst = &DX;\r
1096 uint src = MASK_OUT_ABOVE_16(AY);\r
1097 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
1098 uint res = src + dst;\r
1099\r
1100 FLAG_N = NFLAG_16(res);\r
1101 FLAG_V = VFLAG_ADD_16(src, dst, res);\r
1102 FLAG_X = FLAG_C = CFLAG_16(res);\r
1103 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
1104\r
1105 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
1106}\r
1107\r
1108\r
1109M68KMAKE_OP(add, 16, er, .)\r
1110{\r
1111 uint* r_dst = &DX;\r
1112 uint src = M68KMAKE_GET_OPER_AY_16;\r
1113 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
1114 uint res = src + dst;\r
1115\r
1116 FLAG_N = NFLAG_16(res);\r
1117 FLAG_V = VFLAG_ADD_16(src, dst, res);\r
1118 FLAG_X = FLAG_C = CFLAG_16(res);\r
1119 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
1120\r
1121 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
1122}\r
1123\r
1124\r
1125M68KMAKE_OP(add, 32, er, d)\r
1126{\r
1127 uint* r_dst = &DX;\r
1128 uint src = DY;\r
1129 uint dst = *r_dst;\r
1130 uint res = src + dst;\r
1131\r
1132 FLAG_N = NFLAG_32(res);\r
1133 FLAG_V = VFLAG_ADD_32(src, dst, res);\r
1134 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
1135 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
1136\r
1137 *r_dst = FLAG_Z;\r
1138}\r
1139\r
1140\r
1141M68KMAKE_OP(add, 32, er, a)\r
1142{\r
1143 uint* r_dst = &DX;\r
1144 uint src = AY;\r
1145 uint dst = *r_dst;\r
1146 uint res = src + dst;\r
1147\r
1148 FLAG_N = NFLAG_32(res);\r
1149 FLAG_V = VFLAG_ADD_32(src, dst, res);\r
1150 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
1151 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
1152\r
1153 *r_dst = FLAG_Z;\r
1154}\r
1155\r
1156\r
1157M68KMAKE_OP(add, 32, er, .)\r
1158{\r
1159 uint* r_dst = &DX;\r
1160 uint src = M68KMAKE_GET_OPER_AY_32;\r
1161 uint dst = *r_dst;\r
1162 uint res = src + dst;\r
1163\r
1164 FLAG_N = NFLAG_32(res);\r
1165 FLAG_V = VFLAG_ADD_32(src, dst, res);\r
1166 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
1167 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
1168\r
1169 *r_dst = FLAG_Z;\r
1170}\r
1171\r
1172\r
1173M68KMAKE_OP(add, 8, re, .)\r
1174{\r
1175 uint ea = M68KMAKE_GET_EA_AY_8;\r
1176 uint src = MASK_OUT_ABOVE_8(DX);\r
1177 uint dst = m68ki_read_8(ea);\r
1178 uint res = src + dst;\r
1179\r
1180 FLAG_N = NFLAG_8(res);\r
1181 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1182 FLAG_X = FLAG_C = CFLAG_8(res);\r
1183 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
1184\r
1185 m68ki_write_8(ea, FLAG_Z);\r
1186}\r
1187\r
1188\r
1189M68KMAKE_OP(add, 16, re, .)\r
1190{\r
1191 uint ea = M68KMAKE_GET_EA_AY_16;\r
1192 uint src = MASK_OUT_ABOVE_16(DX);\r
1193 uint dst = m68ki_read_16(ea);\r
1194 uint res = src + dst;\r
1195\r
1196 FLAG_N = NFLAG_16(res);\r
1197 FLAG_V = VFLAG_ADD_16(src, dst, res);\r
1198 FLAG_X = FLAG_C = CFLAG_16(res);\r
1199 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
1200\r
1201 m68ki_write_16(ea, FLAG_Z);\r
1202}\r
1203\r
1204\r
1205M68KMAKE_OP(add, 32, re, .)\r
1206{\r
1207 uint ea = M68KMAKE_GET_EA_AY_32;\r
1208 uint src = DX;\r
1209 uint dst = m68ki_read_32(ea);\r
1210 uint res = src + dst;\r
1211\r
1212 FLAG_N = NFLAG_32(res);\r
1213 FLAG_V = VFLAG_ADD_32(src, dst, res);\r
1214 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
1215 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
1216\r
1217 m68ki_write_32(ea, FLAG_Z);\r
1218}\r
1219\r
1220\r
1221M68KMAKE_OP(adda, 16, ., d)\r
1222{\r
1223 uint* r_dst = &AX;\r
1224\r
1225 *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(DY));\r
1226}\r
1227\r
1228\r
1229M68KMAKE_OP(adda, 16, ., a)\r
1230{\r
1231 uint* r_dst = &AX;\r
1232\r
1233 *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(AY));\r
1234}\r
1235\r
1236\r
1237M68KMAKE_OP(adda, 16, ., .)\r
1238{\r
1239 uint* r_dst = &AX;\r
c6a4c892 1240 uint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);\r
cc68a136 1241\r
c6a4c892 1242 *r_dst = MASK_OUT_ABOVE_32(*r_dst + src);\r
cc68a136 1243}\r
1244\r
1245\r
1246M68KMAKE_OP(adda, 32, ., d)\r
1247{\r
1248 uint* r_dst = &AX;\r
1249\r
1250 *r_dst = MASK_OUT_ABOVE_32(*r_dst + DY);\r
1251}\r
1252\r
1253\r
1254M68KMAKE_OP(adda, 32, ., a)\r
1255{\r
1256 uint* r_dst = &AX;\r
1257\r
1258 *r_dst = MASK_OUT_ABOVE_32(*r_dst + AY);\r
1259}\r
1260\r
1261\r
1262M68KMAKE_OP(adda, 32, ., .)\r
1263{\r
1264 uint* r_dst = &AX;\r
3335750a 1265 uint src = M68KMAKE_GET_OPER_AY_32; // notaz\r
cc68a136 1266\r
3335750a 1267 *r_dst = MASK_OUT_ABOVE_32(*r_dst + src);\r
cc68a136 1268}\r
1269\r
1270\r
1271M68KMAKE_OP(addi, 8, ., d)\r
1272{\r
1273 uint* r_dst = &DY;\r
1274 uint src = OPER_I_8();\r
1275 uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
1276 uint res = src + dst;\r
1277\r
1278 FLAG_N = NFLAG_8(res);\r
1279 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1280 FLAG_X = FLAG_C = CFLAG_8(res);\r
1281 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
1282\r
1283 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;\r
1284}\r
1285\r
1286\r
1287M68KMAKE_OP(addi, 8, ., .)\r
1288{\r
1289 uint src = OPER_I_8();\r
1290 uint ea = M68KMAKE_GET_EA_AY_8;\r
1291 uint dst = m68ki_read_8(ea);\r
1292 uint res = src + dst;\r
1293\r
1294 FLAG_N = NFLAG_8(res);\r
1295 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1296 FLAG_X = FLAG_C = CFLAG_8(res);\r
1297 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
1298\r
1299 m68ki_write_8(ea, FLAG_Z);\r
1300}\r
1301\r
1302\r
1303M68KMAKE_OP(addi, 16, ., d)\r
1304{\r
1305 uint* r_dst = &DY;\r
1306 uint src = OPER_I_16();\r
1307 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
1308 uint res = src + dst;\r
1309\r
1310 FLAG_N = NFLAG_16(res);\r
1311 FLAG_V = VFLAG_ADD_16(src, dst, res);\r
1312 FLAG_X = FLAG_C = CFLAG_16(res);\r
1313 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
1314\r
1315 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
1316}\r
1317\r
1318\r
1319M68KMAKE_OP(addi, 16, ., .)\r
1320{\r
1321 uint src = OPER_I_16();\r
1322 uint ea = M68KMAKE_GET_EA_AY_16;\r
1323 uint dst = m68ki_read_16(ea);\r
1324 uint res = src + dst;\r
1325\r
1326 FLAG_N = NFLAG_16(res);\r
1327 FLAG_V = VFLAG_ADD_16(src, dst, res);\r
1328 FLAG_X = FLAG_C = CFLAG_16(res);\r
1329 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
1330\r
1331 m68ki_write_16(ea, FLAG_Z);\r
1332}\r
1333\r
1334\r
1335M68KMAKE_OP(addi, 32, ., d)\r
1336{\r
1337 uint* r_dst = &DY;\r
1338 uint src = OPER_I_32();\r
1339 uint dst = *r_dst;\r
1340 uint res = src + dst;\r
1341\r
1342 FLAG_N = NFLAG_32(res);\r
1343 FLAG_V = VFLAG_ADD_32(src, dst, res);\r
1344 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
1345 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
1346\r
1347 *r_dst = FLAG_Z;\r
1348}\r
1349\r
1350\r
1351M68KMAKE_OP(addi, 32, ., .)\r
1352{\r
1353 uint src = OPER_I_32();\r
1354 uint ea = M68KMAKE_GET_EA_AY_32;\r
1355 uint dst = m68ki_read_32(ea);\r
1356 uint res = src + dst;\r
1357\r
1358 FLAG_N = NFLAG_32(res);\r
1359 FLAG_V = VFLAG_ADD_32(src, dst, res);\r
1360 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
1361 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
1362\r
1363 m68ki_write_32(ea, FLAG_Z);\r
1364}\r
1365\r
1366\r
1367M68KMAKE_OP(addq, 8, ., d)\r
1368{\r
1369 uint* r_dst = &DY;\r
1370 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
1371 uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
1372 uint res = src + dst;\r
1373\r
1374 FLAG_N = NFLAG_8(res);\r
1375 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1376 FLAG_X = FLAG_C = CFLAG_8(res);\r
1377 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
1378\r
1379 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;\r
1380}\r
1381\r
1382\r
1383M68KMAKE_OP(addq, 8, ., .)\r
1384{\r
1385 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
1386 uint ea = M68KMAKE_GET_EA_AY_8;\r
1387 uint dst = m68ki_read_8(ea);\r
1388 uint res = src + dst;\r
1389\r
1390 FLAG_N = NFLAG_8(res);\r
1391 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1392 FLAG_X = FLAG_C = CFLAG_8(res);\r
1393 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
1394\r
1395 m68ki_write_8(ea, FLAG_Z);\r
1396}\r
1397\r
1398\r
1399M68KMAKE_OP(addq, 16, ., d)\r
1400{\r
1401 uint* r_dst = &DY;\r
1402 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
1403 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
1404 uint res = src + dst;\r
1405\r
1406 FLAG_N = NFLAG_16(res);\r
1407 FLAG_V = VFLAG_ADD_16(src, dst, res);\r
1408 FLAG_X = FLAG_C = CFLAG_16(res);\r
1409 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
1410\r
1411 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
1412}\r
1413\r
1414\r
1415M68KMAKE_OP(addq, 16, ., a)\r
1416{\r
1417 uint* r_dst = &AY;\r
1418\r
1419 *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1);\r
1420}\r
1421\r
1422\r
1423M68KMAKE_OP(addq, 16, ., .)\r
1424{\r
1425 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
1426 uint ea = M68KMAKE_GET_EA_AY_16;\r
1427 uint dst = m68ki_read_16(ea);\r
1428 uint res = src + dst;\r
1429\r
1430 FLAG_N = NFLAG_16(res);\r
1431 FLAG_V = VFLAG_ADD_16(src, dst, res);\r
1432 FLAG_X = FLAG_C = CFLAG_16(res);\r
1433 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
1434\r
1435 m68ki_write_16(ea, FLAG_Z);\r
1436}\r
1437\r
1438\r
1439M68KMAKE_OP(addq, 32, ., d)\r
1440{\r
1441 uint* r_dst = &DY;\r
1442 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
1443 uint dst = *r_dst;\r
1444 uint res = src + dst;\r
1445\r
1446 FLAG_N = NFLAG_32(res);\r
1447 FLAG_V = VFLAG_ADD_32(src, dst, res);\r
1448 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
1449 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
1450\r
1451 *r_dst = FLAG_Z;\r
1452}\r
1453\r
1454\r
1455M68KMAKE_OP(addq, 32, ., a)\r
1456{\r
1457 uint* r_dst = &AY;\r
1458\r
1459 *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1);\r
1460}\r
1461\r
1462\r
1463M68KMAKE_OP(addq, 32, ., .)\r
1464{\r
1465 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
1466 uint ea = M68KMAKE_GET_EA_AY_32;\r
1467 uint dst = m68ki_read_32(ea);\r
1468 uint res = src + dst;\r
1469\r
1470\r
1471 FLAG_N = NFLAG_32(res);\r
1472 FLAG_V = VFLAG_ADD_32(src, dst, res);\r
1473 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
1474 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
1475\r
1476 m68ki_write_32(ea, FLAG_Z);\r
1477}\r
1478\r
1479\r
1480M68KMAKE_OP(addx, 8, rr, .)\r
1481{\r
1482 uint* r_dst = &DX;\r
1483 uint src = MASK_OUT_ABOVE_8(DY);\r
1484 uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
1485 uint res = src + dst + XFLAG_AS_1();\r
1486\r
1487 FLAG_N = NFLAG_8(res);\r
1488 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1489 FLAG_X = FLAG_C = CFLAG_8(res);\r
1490\r
1491 res = MASK_OUT_ABOVE_8(res);\r
1492 FLAG_Z |= res;\r
1493\r
1494 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
1495}\r
1496\r
1497\r
1498M68KMAKE_OP(addx, 16, rr, .)\r
1499{\r
1500 uint* r_dst = &DX;\r
1501 uint src = MASK_OUT_ABOVE_16(DY);\r
1502 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
1503 uint res = src + dst + XFLAG_AS_1();\r
1504\r
1505 FLAG_N = NFLAG_16(res);\r
1506 FLAG_V = VFLAG_ADD_16(src, dst, res);\r
1507 FLAG_X = FLAG_C = CFLAG_16(res);\r
1508\r
1509 res = MASK_OUT_ABOVE_16(res);\r
1510 FLAG_Z |= res;\r
1511\r
1512 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
1513}\r
1514\r
1515\r
1516M68KMAKE_OP(addx, 32, rr, .)\r
1517{\r
1518 uint* r_dst = &DX;\r
1519 uint src = DY;\r
1520 uint dst = *r_dst;\r
1521 uint res = src + dst + XFLAG_AS_1();\r
1522\r
1523 FLAG_N = NFLAG_32(res);\r
1524 FLAG_V = VFLAG_ADD_32(src, dst, res);\r
1525 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
1526\r
1527 res = MASK_OUT_ABOVE_32(res);\r
1528 FLAG_Z |= res;\r
1529\r
1530 *r_dst = res;\r
1531}\r
1532\r
1533\r
1534M68KMAKE_OP(addx, 8, mm, ax7)\r
1535{\r
1536 uint src = OPER_AY_PD_8();\r
1537 uint ea = EA_A7_PD_8();\r
1538 uint dst = m68ki_read_8(ea);\r
1539 uint res = src + dst + XFLAG_AS_1();\r
1540\r
1541 FLAG_N = NFLAG_8(res);\r
1542 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1543 FLAG_X = FLAG_C = CFLAG_8(res);\r
1544\r
1545 res = MASK_OUT_ABOVE_8(res);\r
1546 FLAG_Z |= res;\r
1547\r
1548 m68ki_write_8(ea, res);\r
1549}\r
1550\r
1551\r
1552M68KMAKE_OP(addx, 8, mm, ay7)\r
1553{\r
1554 uint src = OPER_A7_PD_8();\r
1555 uint ea = EA_AX_PD_8();\r
1556 uint dst = m68ki_read_8(ea);\r
1557 uint res = src + dst + XFLAG_AS_1();\r
1558\r
1559 FLAG_N = NFLAG_8(res);\r
1560 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1561 FLAG_X = FLAG_C = CFLAG_8(res);\r
1562\r
1563 res = MASK_OUT_ABOVE_8(res);\r
1564 FLAG_Z |= res;\r
1565\r
1566 m68ki_write_8(ea, res);\r
1567}\r
1568\r
1569\r
1570M68KMAKE_OP(addx, 8, mm, axy7)\r
1571{\r
1572 uint src = OPER_A7_PD_8();\r
1573 uint ea = EA_A7_PD_8();\r
1574 uint dst = m68ki_read_8(ea);\r
1575 uint res = src + dst + XFLAG_AS_1();\r
1576\r
1577 FLAG_N = NFLAG_8(res);\r
1578 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1579 FLAG_X = FLAG_C = CFLAG_8(res);\r
1580\r
1581 res = MASK_OUT_ABOVE_8(res);\r
1582 FLAG_Z |= res;\r
1583\r
1584 m68ki_write_8(ea, res);\r
1585}\r
1586\r
1587\r
1588M68KMAKE_OP(addx, 8, mm, .)\r
1589{\r
1590 uint src = OPER_AY_PD_8();\r
1591 uint ea = EA_AX_PD_8();\r
1592 uint dst = m68ki_read_8(ea);\r
1593 uint res = src + dst + XFLAG_AS_1();\r
1594\r
1595 FLAG_N = NFLAG_8(res);\r
1596 FLAG_V = VFLAG_ADD_8(src, dst, res);\r
1597 FLAG_X = FLAG_C = CFLAG_8(res);\r
1598\r
1599 res = MASK_OUT_ABOVE_8(res);\r
1600 FLAG_Z |= res;\r
1601\r
1602 m68ki_write_8(ea, res);\r
1603}\r
1604\r
1605\r
1606M68KMAKE_OP(addx, 16, mm, .)\r
1607{\r
1608 uint src = OPER_AY_PD_16();\r
1609 uint ea = EA_AX_PD_16();\r
1610 uint dst = m68ki_read_16(ea);\r
1611 uint res = src + dst + XFLAG_AS_1();\r
1612\r
1613 FLAG_N = NFLAG_16(res);\r
1614 FLAG_V = VFLAG_ADD_16(src, dst, res);\r
1615 FLAG_X = FLAG_C = CFLAG_16(res);\r
1616\r
1617 res = MASK_OUT_ABOVE_16(res);\r
1618 FLAG_Z |= res;\r
1619\r
1620 m68ki_write_16(ea, res);\r
1621}\r
1622\r
1623\r
1624M68KMAKE_OP(addx, 32, mm, .)\r
1625{\r
1626 uint src = OPER_AY_PD_32();\r
1627 uint ea = EA_AX_PD_32();\r
1628 uint dst = m68ki_read_32(ea);\r
1629 uint res = src + dst + XFLAG_AS_1();\r
1630\r
1631 FLAG_N = NFLAG_32(res);\r
1632 FLAG_V = VFLAG_ADD_32(src, dst, res);\r
1633 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);\r
1634\r
1635 res = MASK_OUT_ABOVE_32(res);\r
1636 FLAG_Z |= res;\r
1637\r
1638 m68ki_write_32(ea, res);\r
1639}\r
1640\r
1641\r
1642M68KMAKE_OP(and, 8, er, d)\r
1643{\r
1644 FLAG_Z = MASK_OUT_ABOVE_8(DX &= (DY | 0xffffff00));\r
1645\r
1646 FLAG_N = NFLAG_8(FLAG_Z);\r
1647 FLAG_C = CFLAG_CLEAR;\r
1648 FLAG_V = VFLAG_CLEAR;\r
1649}\r
1650\r
1651\r
1652M68KMAKE_OP(and, 8, er, .)\r
1653{\r
1654 FLAG_Z = MASK_OUT_ABOVE_8(DX &= (M68KMAKE_GET_OPER_AY_8 | 0xffffff00));\r
1655\r
1656 FLAG_N = NFLAG_8(FLAG_Z);\r
1657 FLAG_C = CFLAG_CLEAR;\r
1658 FLAG_V = VFLAG_CLEAR;\r
1659}\r
1660\r
1661\r
1662M68KMAKE_OP(and, 16, er, d)\r
1663{\r
1664 FLAG_Z = MASK_OUT_ABOVE_16(DX &= (DY | 0xffff0000));\r
1665\r
1666 FLAG_N = NFLAG_16(FLAG_Z);\r
1667 FLAG_C = CFLAG_CLEAR;\r
1668 FLAG_V = VFLAG_CLEAR;\r
1669}\r
1670\r
1671\r
1672M68KMAKE_OP(and, 16, er, .)\r
1673{\r
1674 FLAG_Z = MASK_OUT_ABOVE_16(DX &= (M68KMAKE_GET_OPER_AY_16 | 0xffff0000));\r
1675\r
1676 FLAG_N = NFLAG_16(FLAG_Z);\r
1677 FLAG_C = CFLAG_CLEAR;\r
1678 FLAG_V = VFLAG_CLEAR;\r
1679}\r
1680\r
1681\r
1682M68KMAKE_OP(and, 32, er, d)\r
1683{\r
1684 FLAG_Z = DX &= DY;\r
1685\r
1686 FLAG_N = NFLAG_32(FLAG_Z);\r
1687 FLAG_C = CFLAG_CLEAR;\r
1688 FLAG_V = VFLAG_CLEAR;\r
1689}\r
1690\r
1691\r
1692M68KMAKE_OP(and, 32, er, .)\r
1693{\r
1694 FLAG_Z = DX &= M68KMAKE_GET_OPER_AY_32;\r
1695\r
1696 FLAG_N = NFLAG_32(FLAG_Z);\r
1697 FLAG_C = CFLAG_CLEAR;\r
1698 FLAG_V = VFLAG_CLEAR;\r
1699}\r
1700\r
1701\r
1702M68KMAKE_OP(and, 8, re, .)\r
1703{\r
1704 uint ea = M68KMAKE_GET_EA_AY_8;\r
1705 uint res = DX & m68ki_read_8(ea);\r
1706\r
1707 FLAG_N = NFLAG_8(res);\r
1708 FLAG_C = CFLAG_CLEAR;\r
1709 FLAG_V = VFLAG_CLEAR;\r
1710 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
1711\r
1712 m68ki_write_8(ea, FLAG_Z);\r
1713}\r
1714\r
1715\r
1716M68KMAKE_OP(and, 16, re, .)\r
1717{\r
1718 uint ea = M68KMAKE_GET_EA_AY_16;\r
1719 uint res = DX & m68ki_read_16(ea);\r
1720\r
1721 FLAG_N = NFLAG_16(res);\r
1722 FLAG_C = CFLAG_CLEAR;\r
1723 FLAG_V = VFLAG_CLEAR;\r
1724 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
1725\r
1726 m68ki_write_16(ea, FLAG_Z);\r
1727}\r
1728\r
1729\r
1730M68KMAKE_OP(and, 32, re, .)\r
1731{\r
1732 uint ea = M68KMAKE_GET_EA_AY_32;\r
1733 uint res = DX & m68ki_read_32(ea);\r
1734\r
1735 FLAG_N = NFLAG_32(res);\r
1736 FLAG_Z = res;\r
1737 FLAG_C = CFLAG_CLEAR;\r
1738 FLAG_V = VFLAG_CLEAR;\r
1739\r
1740 m68ki_write_32(ea, res);\r
1741}\r
1742\r
1743\r
1744M68KMAKE_OP(andi, 8, ., d)\r
1745{\r
1746 FLAG_Z = MASK_OUT_ABOVE_8(DY &= (OPER_I_8() | 0xffffff00));\r
1747\r
1748 FLAG_N = NFLAG_8(FLAG_Z);\r
1749 FLAG_C = CFLAG_CLEAR;\r
1750 FLAG_V = VFLAG_CLEAR;\r
1751}\r
1752\r
1753\r
1754M68KMAKE_OP(andi, 8, ., .)\r
1755{\r
1756 uint src = OPER_I_8();\r
1757 uint ea = M68KMAKE_GET_EA_AY_8;\r
1758 uint res = src & m68ki_read_8(ea);\r
1759\r
1760 FLAG_N = NFLAG_8(res);\r
1761 FLAG_Z = res;\r
1762 FLAG_C = CFLAG_CLEAR;\r
1763 FLAG_V = VFLAG_CLEAR;\r
1764\r
1765 m68ki_write_8(ea, res);\r
1766}\r
1767\r
1768\r
1769M68KMAKE_OP(andi, 16, ., d)\r
1770{\r
1771 FLAG_Z = MASK_OUT_ABOVE_16(DY &= (OPER_I_16() | 0xffff0000));\r
1772\r
1773 FLAG_N = NFLAG_16(FLAG_Z);\r
1774 FLAG_C = CFLAG_CLEAR;\r
1775 FLAG_V = VFLAG_CLEAR;\r
1776}\r
1777\r
1778\r
1779M68KMAKE_OP(andi, 16, ., .)\r
1780{\r
1781 uint src = OPER_I_16();\r
1782 uint ea = M68KMAKE_GET_EA_AY_16;\r
1783 uint res = src & m68ki_read_16(ea);\r
1784\r
1785 FLAG_N = NFLAG_16(res);\r
1786 FLAG_Z = res;\r
1787 FLAG_C = CFLAG_CLEAR;\r
1788 FLAG_V = VFLAG_CLEAR;\r
1789\r
1790 m68ki_write_16(ea, res);\r
1791}\r
1792\r
1793\r
1794M68KMAKE_OP(andi, 32, ., d)\r
1795{\r
1796 FLAG_Z = DY &= (OPER_I_32());\r
1797\r
1798 FLAG_N = NFLAG_32(FLAG_Z);\r
1799 FLAG_C = CFLAG_CLEAR;\r
1800 FLAG_V = VFLAG_CLEAR;\r
1801}\r
1802\r
1803\r
1804M68KMAKE_OP(andi, 32, ., .)\r
1805{\r
1806 uint src = OPER_I_32();\r
1807 uint ea = M68KMAKE_GET_EA_AY_32;\r
1808 uint res = src & m68ki_read_32(ea);\r
1809\r
1810 FLAG_N = NFLAG_32(res);\r
1811 FLAG_Z = res;\r
1812 FLAG_C = CFLAG_CLEAR;\r
1813 FLAG_V = VFLAG_CLEAR;\r
1814\r
1815 m68ki_write_32(ea, res);\r
1816}\r
1817\r
1818\r
1819M68KMAKE_OP(andi, 16, toc, .)\r
1820{\r
1821 m68ki_set_ccr(m68ki_get_ccr() & OPER_I_16());\r
1822}\r
1823\r
1824\r
1825M68KMAKE_OP(andi, 16, tos, .)\r
1826{\r
1827 if(FLAG_S)\r
1828 {\r
1829 uint src = OPER_I_16();\r
1830 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
1831 m68ki_set_sr(m68ki_get_sr() & src);\r
1832 return;\r
1833 }\r
1834 m68ki_exception_privilege_violation();\r
1835}\r
1836\r
1837\r
1838M68KMAKE_OP(asr, 8, s, .)\r
1839{\r
1840 uint* r_dst = &DY;\r
1841 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
1842 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
1843 uint res = src >> shift;\r
1844\r
1845 if(shift != 0)\r
1846 USE_CYCLES(shift<<CYC_SHIFT);\r
1847\r
1848 if(GET_MSB_8(src))\r
1849 res |= m68ki_shift_8_table[shift];\r
1850\r
1851 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
1852\r
1853 FLAG_N = NFLAG_8(res);\r
1854 FLAG_Z = res;\r
1855 FLAG_V = VFLAG_CLEAR;\r
1856 FLAG_X = FLAG_C = src << (9-shift);\r
1857}\r
1858\r
1859\r
1860M68KMAKE_OP(asr, 16, s, .)\r
1861{\r
1862 uint* r_dst = &DY;\r
1863 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
1864 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
1865 uint res = src >> shift;\r
1866\r
1867 if(shift != 0)\r
1868 USE_CYCLES(shift<<CYC_SHIFT);\r
1869\r
1870 if(GET_MSB_16(src))\r
1871 res |= m68ki_shift_16_table[shift];\r
1872\r
1873 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
1874\r
1875 FLAG_N = NFLAG_16(res);\r
1876 FLAG_Z = res;\r
1877 FLAG_V = VFLAG_CLEAR;\r
1878 FLAG_X = FLAG_C = src << (9-shift);\r
1879}\r
1880\r
1881\r
1882M68KMAKE_OP(asr, 32, s, .)\r
1883{\r
1884 uint* r_dst = &DY;\r
1885 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
1886 uint src = *r_dst;\r
1887 uint res = src >> shift;\r
1888\r
1889 if(shift != 0)\r
1890 USE_CYCLES(shift<<CYC_SHIFT);\r
1891\r
1892 if(GET_MSB_32(src))\r
1893 res |= m68ki_shift_32_table[shift];\r
1894\r
1895 *r_dst = res;\r
1896\r
1897 FLAG_N = NFLAG_32(res);\r
1898 FLAG_Z = res;\r
1899 FLAG_V = VFLAG_CLEAR;\r
1900 FLAG_X = FLAG_C = src << (9-shift);\r
1901}\r
1902\r
1903\r
1904M68KMAKE_OP(asr, 8, r, .)\r
1905{\r
1906 uint* r_dst = &DY;\r
1907 uint shift = DX & 0x3f;\r
1908 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
1909 uint res = src >> shift;\r
1910\r
1911 if(shift != 0)\r
1912 {\r
1913 USE_CYCLES(shift<<CYC_SHIFT);\r
1914\r
1915 if(shift < 8)\r
1916 {\r
1917 if(GET_MSB_8(src))\r
1918 res |= m68ki_shift_8_table[shift];\r
1919\r
1920 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
1921\r
1922 FLAG_X = FLAG_C = src << (9-shift);\r
1923 FLAG_N = NFLAG_8(res);\r
1924 FLAG_Z = res;\r
1925 FLAG_V = VFLAG_CLEAR;\r
1926 return;\r
1927 }\r
1928\r
1929 if(GET_MSB_8(src))\r
1930 {\r
1931 *r_dst |= 0xff;\r
1932 FLAG_C = CFLAG_SET;\r
1933 FLAG_X = XFLAG_SET;\r
1934 FLAG_N = NFLAG_SET;\r
1935 FLAG_Z = ZFLAG_CLEAR;\r
1936 FLAG_V = VFLAG_CLEAR;\r
1937 return;\r
1938 }\r
1939\r
1940 *r_dst &= 0xffffff00;\r
1941 FLAG_C = CFLAG_CLEAR;\r
1942 FLAG_X = XFLAG_CLEAR;\r
1943 FLAG_N = NFLAG_CLEAR;\r
1944 FLAG_Z = ZFLAG_SET;\r
1945 FLAG_V = VFLAG_CLEAR;\r
1946 return;\r
1947 }\r
1948\r
1949 FLAG_C = CFLAG_CLEAR;\r
1950 FLAG_N = NFLAG_8(src);\r
1951 FLAG_Z = src;\r
1952 FLAG_V = VFLAG_CLEAR;\r
1953}\r
1954\r
1955\r
1956M68KMAKE_OP(asr, 16, r, .)\r
1957{\r
1958 uint* r_dst = &DY;\r
1959 uint shift = DX & 0x3f;\r
1960 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
1961 uint res = src >> shift;\r
1962\r
1963 if(shift != 0)\r
1964 {\r
1965 USE_CYCLES(shift<<CYC_SHIFT);\r
1966\r
1967 if(shift < 16)\r
1968 {\r
1969 if(GET_MSB_16(src))\r
1970 res |= m68ki_shift_16_table[shift];\r
1971\r
1972 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
1973\r
1974 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;\r
1975 FLAG_N = NFLAG_16(res);\r
1976 FLAG_Z = res;\r
1977 FLAG_V = VFLAG_CLEAR;\r
1978 return;\r
1979 }\r
1980\r
1981 if(GET_MSB_16(src))\r
1982 {\r
1983 *r_dst |= 0xffff;\r
1984 FLAG_C = CFLAG_SET;\r
1985 FLAG_X = XFLAG_SET;\r
1986 FLAG_N = NFLAG_SET;\r
1987 FLAG_Z = ZFLAG_CLEAR;\r
1988 FLAG_V = VFLAG_CLEAR;\r
1989 return;\r
1990 }\r
1991\r
1992 *r_dst &= 0xffff0000;\r
1993 FLAG_C = CFLAG_CLEAR;\r
1994 FLAG_X = XFLAG_CLEAR;\r
1995 FLAG_N = NFLAG_CLEAR;\r
1996 FLAG_Z = ZFLAG_SET;\r
1997 FLAG_V = VFLAG_CLEAR;\r
1998 return;\r
1999 }\r
2000\r
2001 FLAG_C = CFLAG_CLEAR;\r
2002 FLAG_N = NFLAG_16(src);\r
2003 FLAG_Z = src;\r
2004 FLAG_V = VFLAG_CLEAR;\r
2005}\r
2006\r
2007\r
2008M68KMAKE_OP(asr, 32, r, .)\r
2009{\r
2010 uint* r_dst = &DY;\r
2011 uint shift = DX & 0x3f;\r
2012 uint src = *r_dst;\r
2013 uint res = src >> shift;\r
2014\r
2015 if(shift != 0)\r
2016 {\r
2017 USE_CYCLES(shift<<CYC_SHIFT);\r
2018\r
2019 if(shift < 32)\r
2020 {\r
2021 if(GET_MSB_32(src))\r
2022 res |= m68ki_shift_32_table[shift];\r
2023\r
2024 *r_dst = res;\r
2025\r
2026 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;\r
2027 FLAG_N = NFLAG_32(res);\r
2028 FLAG_Z = res;\r
2029 FLAG_V = VFLAG_CLEAR;\r
2030 return;\r
2031 }\r
2032\r
2033 if(GET_MSB_32(src))\r
2034 {\r
2035 *r_dst = 0xffffffff;\r
2036 FLAG_C = CFLAG_SET;\r
2037 FLAG_X = XFLAG_SET;\r
2038 FLAG_N = NFLAG_SET;\r
2039 FLAG_Z = ZFLAG_CLEAR;\r
2040 FLAG_V = VFLAG_CLEAR;\r
2041 return;\r
2042 }\r
2043\r
2044 *r_dst = 0;\r
2045 FLAG_C = CFLAG_CLEAR;\r
2046 FLAG_X = XFLAG_CLEAR;\r
2047 FLAG_N = NFLAG_CLEAR;\r
2048 FLAG_Z = ZFLAG_SET;\r
2049 FLAG_V = VFLAG_CLEAR;\r
2050 return;\r
2051 }\r
2052\r
2053 FLAG_C = CFLAG_CLEAR;\r
2054 FLAG_N = NFLAG_32(src);\r
2055 FLAG_Z = src;\r
2056 FLAG_V = VFLAG_CLEAR;\r
2057}\r
2058\r
2059\r
2060M68KMAKE_OP(asr, 16, ., .)\r
2061{\r
2062 uint ea = M68KMAKE_GET_EA_AY_16;\r
2063 uint src = m68ki_read_16(ea);\r
2064 uint res = src >> 1;\r
2065\r
2066 if(GET_MSB_16(src))\r
2067 res |= 0x8000;\r
2068\r
2069 m68ki_write_16(ea, res);\r
2070\r
2071 FLAG_N = NFLAG_16(res);\r
2072 FLAG_Z = res;\r
2073 FLAG_V = VFLAG_CLEAR;\r
2074 FLAG_C = FLAG_X = src << 8;\r
2075}\r
2076\r
2077\r
2078M68KMAKE_OP(asl, 8, s, .)\r
2079{\r
2080 uint* r_dst = &DY;\r
2081 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
2082 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
2083 uint res = MASK_OUT_ABOVE_8(src << shift);\r
2084\r
2085 if(shift != 0)\r
2086 USE_CYCLES(shift<<CYC_SHIFT);\r
2087\r
2088 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
2089\r
2090 FLAG_X = FLAG_C = src << shift;\r
2091 FLAG_N = NFLAG_8(res);\r
2092 FLAG_Z = res;\r
2093 src &= m68ki_shift_8_table[shift + 1];\r
2094 FLAG_V = (!(src == 0 || (src == m68ki_shift_8_table[shift + 1] && shift < 8)))<<7;\r
2095}\r
2096\r
2097\r
2098M68KMAKE_OP(asl, 16, s, .)\r
2099{\r
2100 uint* r_dst = &DY;\r
2101 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
2102 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
2103 uint res = MASK_OUT_ABOVE_16(src << shift);\r
2104\r
2105 if(shift != 0)\r
2106 USE_CYCLES(shift<<CYC_SHIFT);\r
2107\r
2108 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
2109\r
2110 FLAG_N = NFLAG_16(res);\r
2111 FLAG_Z = res;\r
2112 FLAG_X = FLAG_C = src >> (8-shift);\r
2113 src &= m68ki_shift_16_table[shift + 1];\r
2114 FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7;\r
2115}\r
2116\r
2117\r
2118M68KMAKE_OP(asl, 32, s, .)\r
2119{\r
2120 uint* r_dst = &DY;\r
2121 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
2122 uint src = *r_dst;\r
2123 uint res = MASK_OUT_ABOVE_32(src << shift);\r
2124\r
2125 if(shift != 0)\r
2126 USE_CYCLES(shift<<CYC_SHIFT);\r
2127\r
2128 *r_dst = res;\r
2129\r
2130 FLAG_N = NFLAG_32(res);\r
2131 FLAG_Z = res;\r
2132 FLAG_X = FLAG_C = src >> (24-shift);\r
2133 src &= m68ki_shift_32_table[shift + 1];\r
2134 FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7;\r
2135}\r
2136\r
2137\r
2138M68KMAKE_OP(asl, 8, r, .)\r
2139{\r
2140 uint* r_dst = &DY;\r
2141 uint shift = DX & 0x3f;\r
2142 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
2143 uint res = MASK_OUT_ABOVE_8(src << shift);\r
2144\r
2145 if(shift != 0)\r
2146 {\r
2147 USE_CYCLES(shift<<CYC_SHIFT);\r
2148\r
2149 if(shift < 8)\r
2150 {\r
2151 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
2152 FLAG_X = FLAG_C = src << shift;\r
2153 FLAG_N = NFLAG_8(res);\r
2154 FLAG_Z = res;\r
2155 src &= m68ki_shift_8_table[shift + 1];\r
2156 FLAG_V = (!(src == 0 || src == m68ki_shift_8_table[shift + 1]))<<7;\r
2157 return;\r
2158 }\r
2159\r
2160 *r_dst &= 0xffffff00;\r
2161 FLAG_X = FLAG_C = ((shift == 8 ? src & 1 : 0))<<8;\r
2162 FLAG_N = NFLAG_CLEAR;\r
2163 FLAG_Z = ZFLAG_SET;\r
2164 FLAG_V = (!(src == 0))<<7;\r
2165 return;\r
2166 }\r
2167\r
2168 FLAG_C = CFLAG_CLEAR;\r
2169 FLAG_N = NFLAG_8(src);\r
2170 FLAG_Z = src;\r
2171 FLAG_V = VFLAG_CLEAR;\r
2172}\r
2173\r
2174\r
2175M68KMAKE_OP(asl, 16, r, .)\r
2176{\r
2177 uint* r_dst = &DY;\r
2178 uint shift = DX & 0x3f;\r
2179 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
2180 uint res = MASK_OUT_ABOVE_16(src << shift);\r
2181\r
2182 if(shift != 0)\r
2183 {\r
2184 USE_CYCLES(shift<<CYC_SHIFT);\r
2185\r
2186 if(shift < 16)\r
2187 {\r
2188 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
2189 FLAG_X = FLAG_C = (src << shift) >> 8;\r
2190 FLAG_N = NFLAG_16(res);\r
2191 FLAG_Z = res;\r
2192 src &= m68ki_shift_16_table[shift + 1];\r
2193 FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7;\r
2194 return;\r
2195 }\r
2196\r
2197 *r_dst &= 0xffff0000;\r
2198 FLAG_X = FLAG_C = ((shift == 16 ? src & 1 : 0))<<8;\r
2199 FLAG_N = NFLAG_CLEAR;\r
2200 FLAG_Z = ZFLAG_SET;\r
2201 FLAG_V = (!(src == 0))<<7;\r
2202 return;\r
2203 }\r
2204\r
2205 FLAG_C = CFLAG_CLEAR;\r
2206 FLAG_N = NFLAG_16(src);\r
2207 FLAG_Z = src;\r
2208 FLAG_V = VFLAG_CLEAR;\r
2209}\r
2210\r
2211\r
2212M68KMAKE_OP(asl, 32, r, .)\r
2213{\r
2214 uint* r_dst = &DY;\r
2215 uint shift = DX & 0x3f;\r
2216 uint src = *r_dst;\r
2217 uint res = MASK_OUT_ABOVE_32(src << shift);\r
2218\r
2219 if(shift != 0)\r
2220 {\r
2221 USE_CYCLES(shift<<CYC_SHIFT);\r
2222\r
2223 if(shift < 32)\r
2224 {\r
2225 *r_dst = res;\r
2226 FLAG_X = FLAG_C = (src >> (32 - shift)) << 8;\r
2227 FLAG_N = NFLAG_32(res);\r
2228 FLAG_Z = res;\r
2229 src &= m68ki_shift_32_table[shift + 1];\r
2230 FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7;\r
2231 return;\r
2232 }\r
2233\r
2234 *r_dst = 0;\r
2235 FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8;\r
2236 FLAG_N = NFLAG_CLEAR;\r
2237 FLAG_Z = ZFLAG_SET;\r
2238 FLAG_V = (!(src == 0))<<7;\r
2239 return;\r
2240 }\r
2241\r
2242 FLAG_C = CFLAG_CLEAR;\r
2243 FLAG_N = NFLAG_32(src);\r
2244 FLAG_Z = src;\r
2245 FLAG_V = VFLAG_CLEAR;\r
2246}\r
2247\r
2248\r
2249M68KMAKE_OP(asl, 16, ., .)\r
2250{\r
2251 uint ea = M68KMAKE_GET_EA_AY_16;\r
2252 uint src = m68ki_read_16(ea);\r
2253 uint res = MASK_OUT_ABOVE_16(src << 1);\r
2254\r
2255 m68ki_write_16(ea, res);\r
2256\r
2257 FLAG_N = NFLAG_16(res);\r
2258 FLAG_Z = res;\r
2259 FLAG_X = FLAG_C = src >> 7;\r
2260 src &= 0xc000;\r
2261 FLAG_V = (!(src == 0 || src == 0xc000))<<7;\r
2262}\r
2263\r
2264\r
2265M68KMAKE_OP(bcc, 8, ., .)\r
2266{\r
2267 if(M68KMAKE_CC)\r
2268 {\r
2269 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
2270 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));\r
2271 return;\r
2272 }\r
2273 USE_CYCLES(CYC_BCC_NOTAKE_B);\r
2274}\r
2275\r
2276\r
2277M68KMAKE_OP(bcc, 16, ., .)\r
2278{\r
2279 if(M68KMAKE_CC)\r
2280 {\r
2281 uint offset = OPER_I_16();\r
2282 REG_PC -= 2;\r
2283 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
2284 m68ki_branch_16(offset);\r
2285 return;\r
2286 }\r
2287 REG_PC += 2;\r
2288 USE_CYCLES(CYC_BCC_NOTAKE_W);\r
2289}\r
2290\r
2291\r
2292M68KMAKE_OP(bcc, 32, ., .)\r
2293{\r
2294 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2295 {\r
2296 if(M68KMAKE_CC)\r
2297 {\r
2298 uint offset = OPER_I_32();\r
2299 REG_PC -= 4;\r
2300 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
2301 m68ki_branch_32(offset);\r
2302 return;\r
2303 }\r
2304 REG_PC += 4;\r
2305 return;\r
2306 }\r
2307 else\r
2308 {\r
2309 if(M68KMAKE_CC)\r
2310 {\r
2311 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
2312 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));\r
2313 return;\r
2314 }\r
2315 USE_CYCLES(CYC_BCC_NOTAKE_B);\r
2316 }\r
2317}\r
2318\r
2319\r
2320M68KMAKE_OP(bchg, 32, r, d)\r
2321{\r
2322 uint* r_dst = &DY;\r
2323 uint mask = 1 << (DX & 0x1f);\r
2324\r
2325 FLAG_Z = *r_dst & mask;\r
2326 *r_dst ^= mask;\r
2327}\r
2328\r
2329\r
2330M68KMAKE_OP(bchg, 8, r, .)\r
2331{\r
2332 uint ea = M68KMAKE_GET_EA_AY_8;\r
2333 uint src = m68ki_read_8(ea);\r
2334 uint mask = 1 << (DX & 7);\r
2335\r
2336 FLAG_Z = src & mask;\r
2337 m68ki_write_8(ea, src ^ mask);\r
2338}\r
2339\r
2340\r
2341M68KMAKE_OP(bchg, 32, s, d)\r
2342{\r
2343 uint* r_dst = &DY;\r
2344 uint mask = 1 << (OPER_I_8() & 0x1f);\r
2345\r
2346 FLAG_Z = *r_dst & mask;\r
2347 *r_dst ^= mask;\r
2348}\r
2349\r
2350\r
2351M68KMAKE_OP(bchg, 8, s, .)\r
2352{\r
2353 uint mask = 1 << (OPER_I_8() & 7);\r
2354 uint ea = M68KMAKE_GET_EA_AY_8;\r
2355 uint src = m68ki_read_8(ea);\r
2356\r
2357 FLAG_Z = src & mask;\r
2358 m68ki_write_8(ea, src ^ mask);\r
2359}\r
2360\r
2361\r
2362M68KMAKE_OP(bclr, 32, r, d)\r
2363{\r
2364 uint* r_dst = &DY;\r
2365 uint mask = 1 << (DX & 0x1f);\r
2366\r
2367 FLAG_Z = *r_dst & mask;\r
2368 *r_dst &= ~mask;\r
2369}\r
2370\r
2371\r
2372M68KMAKE_OP(bclr, 8, r, .)\r
2373{\r
2374 uint ea = M68KMAKE_GET_EA_AY_8;\r
2375 uint src = m68ki_read_8(ea);\r
2376 uint mask = 1 << (DX & 7);\r
2377\r
2378 FLAG_Z = src & mask;\r
2379 m68ki_write_8(ea, src & ~mask);\r
2380}\r
2381\r
2382\r
2383M68KMAKE_OP(bclr, 32, s, d)\r
2384{\r
2385 uint* r_dst = &DY;\r
2386 uint mask = 1 << (OPER_I_8() & 0x1f);\r
2387\r
2388 FLAG_Z = *r_dst & mask;\r
2389 *r_dst &= ~mask;\r
2390}\r
2391\r
2392\r
2393M68KMAKE_OP(bclr, 8, s, .)\r
2394{\r
2395 uint mask = 1 << (OPER_I_8() & 7);\r
2396 uint ea = M68KMAKE_GET_EA_AY_8;\r
2397 uint src = m68ki_read_8(ea);\r
2398\r
2399 FLAG_Z = src & mask;\r
2400 m68ki_write_8(ea, src & ~mask);\r
2401}\r
2402\r
2403\r
2404M68KMAKE_OP(bfchg, 32, ., d)\r
2405{\r
2406 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2407 {\r
2408 uint word2 = OPER_I_16();\r
2409 uint offset = (word2>>6)&31;\r
2410 uint width = word2;\r
2411 uint* data = &DY;\r
2412 uint64 mask;\r
2413\r
2414\r
2415 if(BIT_B(word2))\r
2416 offset = REG_D[offset&7];\r
2417 if(BIT_5(word2))\r
2418 width = REG_D[width&7];\r
2419\r
2420 offset &= 31;\r
2421 width = ((width-1) & 31) + 1;\r
2422\r
2423 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
2424 mask = ROR_32(mask, offset);\r
2425\r
2426 FLAG_N = NFLAG_32(*data<<offset);\r
2427 FLAG_Z = *data & mask;\r
2428 FLAG_V = VFLAG_CLEAR;\r
2429 FLAG_C = CFLAG_CLEAR;\r
2430\r
2431 *data ^= mask;\r
2432\r
2433 return;\r
2434 }\r
2435 m68ki_exception_illegal();\r
2436}\r
2437\r
2438\r
2439M68KMAKE_OP(bfchg, 32, ., .)\r
2440{\r
2441 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2442 {\r
2443 uint word2 = OPER_I_16();\r
2444 sint offset = (word2>>6)&31;\r
2445 uint width = word2;\r
2446 uint mask_base;\r
2447 uint data_long;\r
2448 uint mask_long;\r
2449 uint data_byte = 0;\r
2450 uint mask_byte = 0;\r
2451 uint ea = M68KMAKE_GET_EA_AY_8;\r
2452\r
2453\r
2454 if(BIT_B(word2))\r
2455 offset = MAKE_INT_32(REG_D[offset&7]);\r
2456 if(BIT_5(word2))\r
2457 width = REG_D[width&7];\r
2458\r
2459 /* Offset is signed so we have to use ugly math =( */\r
2460 ea += offset / 8;\r
2461 offset %= 8;\r
2462 if(offset < 0)\r
2463 {\r
2464 offset += 8;\r
2465 ea--;\r
2466 }\r
2467 width = ((width-1) & 31) + 1;\r
2468\r
2469 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
2470 mask_long = mask_base >> offset;\r
2471\r
2472 data_long = m68ki_read_32(ea);\r
2473 FLAG_N = NFLAG_32(data_long << offset);\r
2474 FLAG_Z = data_long & mask_long;\r
2475 FLAG_V = VFLAG_CLEAR;\r
2476 FLAG_C = CFLAG_CLEAR;\r
2477\r
2478 m68ki_write_32(ea, data_long ^ mask_long);\r
2479\r
2480 if((width + offset) > 32)\r
2481 {\r
2482 mask_byte = MASK_OUT_ABOVE_8(mask_base);\r
2483 data_byte = m68ki_read_8(ea+4);\r
2484 FLAG_Z |= (data_byte & mask_byte);\r
2485 m68ki_write_8(ea+4, data_byte ^ mask_byte);\r
2486 }\r
2487 return;\r
2488 }\r
2489 m68ki_exception_illegal();\r
2490}\r
2491\r
2492\r
2493M68KMAKE_OP(bfclr, 32, ., d)\r
2494{\r
2495 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2496 {\r
2497 uint word2 = OPER_I_16();\r
2498 uint offset = (word2>>6)&31;\r
2499 uint width = word2;\r
2500 uint* data = &DY;\r
2501 uint64 mask;\r
2502\r
2503\r
2504 if(BIT_B(word2))\r
2505 offset = REG_D[offset&7];\r
2506 if(BIT_5(word2))\r
2507 width = REG_D[width&7];\r
2508\r
2509\r
2510 offset &= 31;\r
2511 width = ((width-1) & 31) + 1;\r
2512\r
2513\r
2514 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
2515 mask = ROR_32(mask, offset);\r
2516\r
2517 FLAG_N = NFLAG_32(*data<<offset);\r
2518 FLAG_Z = *data & mask;\r
2519 FLAG_V = VFLAG_CLEAR;\r
2520 FLAG_C = CFLAG_CLEAR;\r
2521\r
2522 *data &= ~mask;\r
2523\r
2524 return;\r
2525 }\r
2526 m68ki_exception_illegal();\r
2527}\r
2528\r
2529\r
2530M68KMAKE_OP(bfclr, 32, ., .)\r
2531{\r
2532 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2533 {\r
2534 uint word2 = OPER_I_16();\r
2535 sint offset = (word2>>6)&31;\r
2536 uint width = word2;\r
2537 uint mask_base;\r
2538 uint data_long;\r
2539 uint mask_long;\r
2540 uint data_byte = 0;\r
2541 uint mask_byte = 0;\r
2542 uint ea = M68KMAKE_GET_EA_AY_8;\r
2543\r
2544\r
2545 if(BIT_B(word2))\r
2546 offset = MAKE_INT_32(REG_D[offset&7]);\r
2547 if(BIT_5(word2))\r
2548 width = REG_D[width&7];\r
2549\r
2550 /* Offset is signed so we have to use ugly math =( */\r
2551 ea += offset / 8;\r
2552 offset %= 8;\r
2553 if(offset < 0)\r
2554 {\r
2555 offset += 8;\r
2556 ea--;\r
2557 }\r
2558 width = ((width-1) & 31) + 1;\r
2559\r
2560 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
2561 mask_long = mask_base >> offset;\r
2562\r
2563 data_long = m68ki_read_32(ea);\r
2564 FLAG_N = NFLAG_32(data_long << offset);\r
2565 FLAG_Z = data_long & mask_long;\r
2566 FLAG_V = VFLAG_CLEAR;\r
2567 FLAG_C = CFLAG_CLEAR;\r
2568\r
2569 m68ki_write_32(ea, data_long & ~mask_long);\r
2570\r
2571 if((width + offset) > 32)\r
2572 {\r
2573 mask_byte = MASK_OUT_ABOVE_8(mask_base);\r
2574 data_byte = m68ki_read_8(ea+4);\r
2575 FLAG_Z |= (data_byte & mask_byte);\r
2576 m68ki_write_8(ea+4, data_byte & ~mask_byte);\r
2577 }\r
2578 return;\r
2579 }\r
2580 m68ki_exception_illegal();\r
2581}\r
2582\r
2583\r
2584M68KMAKE_OP(bfexts, 32, ., d)\r
2585{\r
2586 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2587 {\r
2588 uint word2 = OPER_I_16();\r
2589 uint offset = (word2>>6)&31;\r
2590 uint width = word2;\r
2591 uint64 data = DY;\r
2592\r
2593\r
2594 if(BIT_B(word2))\r
2595 offset = REG_D[offset&7];\r
2596 if(BIT_5(word2))\r
2597 width = REG_D[width&7];\r
2598\r
2599 offset &= 31;\r
2600 width = ((width-1) & 31) + 1;\r
2601\r
2602 data = ROL_32(data, offset);\r
2603 FLAG_N = NFLAG_32(data);\r
2604 data = MAKE_INT_32(data) >> (32 - width);\r
2605\r
2606 FLAG_Z = data;\r
2607 FLAG_V = VFLAG_CLEAR;\r
2608 FLAG_C = CFLAG_CLEAR;\r
2609\r
2610 REG_D[(word2>>12)&7] = data;\r
2611\r
2612 return;\r
2613 }\r
2614 m68ki_exception_illegal();\r
2615}\r
2616\r
2617\r
2618M68KMAKE_OP(bfexts, 32, ., .)\r
2619{\r
2620 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2621 {\r
2622 uint word2 = OPER_I_16();\r
2623 sint offset = (word2>>6)&31;\r
2624 uint width = word2;\r
2625 uint data;\r
2626 uint ea = M68KMAKE_GET_EA_AY_8;\r
2627\r
2628\r
2629 if(BIT_B(word2))\r
2630 offset = MAKE_INT_32(REG_D[offset&7]);\r
2631 if(BIT_5(word2))\r
2632 width = REG_D[width&7];\r
2633\r
2634 /* Offset is signed so we have to use ugly math =( */\r
2635 ea += offset / 8;\r
2636 offset %= 8;\r
2637 if(offset < 0)\r
2638 {\r
2639 offset += 8;\r
2640 ea--;\r
2641 }\r
2642 width = ((width-1) & 31) + 1;\r
2643\r
2644 data = m68ki_read_32(ea);\r
2645\r
2646 data = MASK_OUT_ABOVE_32(data<<offset);\r
2647\r
2648 if((offset+width) > 32)\r
2649 data |= (m68ki_read_8(ea+4) << offset) >> 8;\r
2650\r
2651 FLAG_N = NFLAG_32(data);\r
2652 data = MAKE_INT_32(data) >> (32 - width);\r
2653\r
2654 FLAG_Z = data;\r
2655 FLAG_V = VFLAG_CLEAR;\r
2656 FLAG_C = CFLAG_CLEAR;\r
2657\r
2658 REG_D[(word2 >> 12) & 7] = data;\r
2659\r
2660 return;\r
2661 }\r
2662 m68ki_exception_illegal();\r
2663}\r
2664\r
2665\r
2666M68KMAKE_OP(bfextu, 32, ., d)\r
2667{\r
2668 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2669 {\r
2670 uint word2 = OPER_I_16();\r
2671 uint offset = (word2>>6)&31;\r
2672 uint width = word2;\r
2673 uint64 data = DY;\r
2674\r
2675\r
2676 if(BIT_B(word2))\r
2677 offset = REG_D[offset&7];\r
2678 if(BIT_5(word2))\r
2679 width = REG_D[width&7];\r
2680\r
2681 offset &= 31;\r
2682 width = ((width-1) & 31) + 1;\r
2683\r
2684 data = ROL_32(data, offset);\r
2685 FLAG_N = NFLAG_32(data);\r
2686 data >>= 32 - width;\r
2687\r
2688 FLAG_Z = data;\r
2689 FLAG_V = VFLAG_CLEAR;\r
2690 FLAG_C = CFLAG_CLEAR;\r
2691\r
2692 REG_D[(word2>>12)&7] = data;\r
2693\r
2694 return;\r
2695 }\r
2696 m68ki_exception_illegal();\r
2697}\r
2698\r
2699\r
2700M68KMAKE_OP(bfextu, 32, ., .)\r
2701{\r
2702 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2703 {\r
2704 uint word2 = OPER_I_16();\r
2705 sint offset = (word2>>6)&31;\r
2706 uint width = word2;\r
2707 uint data;\r
2708 uint ea = M68KMAKE_GET_EA_AY_8;\r
2709\r
2710\r
2711 if(BIT_B(word2))\r
2712 offset = MAKE_INT_32(REG_D[offset&7]);\r
2713 if(BIT_5(word2))\r
2714 width = REG_D[width&7];\r
2715\r
2716 /* Offset is signed so we have to use ugly math =( */\r
2717 ea += offset / 8;\r
2718 offset %= 8;\r
2719 if(offset < 0)\r
2720 {\r
2721 offset += 8;\r
2722 ea--;\r
2723 }\r
2724 width = ((width-1) & 31) + 1;\r
2725\r
2726 data = m68ki_read_32(ea);\r
2727 data = MASK_OUT_ABOVE_32(data<<offset);\r
2728\r
2729 if((offset+width) > 32)\r
2730 data |= (m68ki_read_8(ea+4) << offset) >> 8;\r
2731\r
2732 FLAG_N = NFLAG_32(data);\r
2733 data >>= (32 - width);\r
2734\r
2735 FLAG_Z = data;\r
2736 FLAG_V = VFLAG_CLEAR;\r
2737 FLAG_C = CFLAG_CLEAR;\r
2738\r
2739 REG_D[(word2 >> 12) & 7] = data;\r
2740\r
2741 return;\r
2742 }\r
2743 m68ki_exception_illegal();\r
2744}\r
2745\r
2746\r
2747M68KMAKE_OP(bfffo, 32, ., d)\r
2748{\r
2749 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2750 {\r
2751 uint word2 = OPER_I_16();\r
2752 uint offset = (word2>>6)&31;\r
2753 uint width = word2;\r
2754 uint64 data = DY;\r
2755 uint bit;\r
2756\r
2757\r
2758 if(BIT_B(word2))\r
2759 offset = REG_D[offset&7];\r
2760 if(BIT_5(word2))\r
2761 width = REG_D[width&7];\r
2762\r
2763 offset &= 31;\r
2764 width = ((width-1) & 31) + 1;\r
2765\r
2766 data = ROL_32(data, offset);\r
2767 FLAG_N = NFLAG_32(data);\r
2768 data >>= 32 - width;\r
2769\r
2770 FLAG_Z = data;\r
2771 FLAG_V = VFLAG_CLEAR;\r
2772 FLAG_C = CFLAG_CLEAR;\r
2773\r
2774 for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)\r
2775 offset++;\r
2776\r
2777 REG_D[(word2>>12)&7] = offset;\r
2778\r
2779 return;\r
2780 }\r
2781 m68ki_exception_illegal();\r
2782}\r
2783\r
2784\r
2785M68KMAKE_OP(bfffo, 32, ., .)\r
2786{\r
2787 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2788 {\r
2789 uint word2 = OPER_I_16();\r
2790 sint offset = (word2>>6)&31;\r
2791 sint local_offset;\r
2792 uint width = word2;\r
2793 uint data;\r
2794 uint bit;\r
2795 uint ea = M68KMAKE_GET_EA_AY_8;\r
2796\r
2797\r
2798 if(BIT_B(word2))\r
2799 offset = MAKE_INT_32(REG_D[offset&7]);\r
2800 if(BIT_5(word2))\r
2801 width = REG_D[width&7];\r
2802\r
2803 /* Offset is signed so we have to use ugly math =( */\r
2804 ea += offset / 8;\r
2805 local_offset = offset % 8;\r
2806 if(local_offset < 0)\r
2807 {\r
2808 local_offset += 8;\r
2809 ea--;\r
2810 }\r
2811 width = ((width-1) & 31) + 1;\r
2812\r
2813 data = m68ki_read_32(ea);\r
2814 data = MASK_OUT_ABOVE_32(data<<local_offset);\r
2815\r
2816 if((local_offset+width) > 32)\r
2817 data |= (m68ki_read_8(ea+4) << local_offset) >> 8;\r
2818\r
2819 FLAG_N = NFLAG_32(data);\r
2820 data >>= (32 - width);\r
2821\r
2822 FLAG_Z = data;\r
2823 FLAG_V = VFLAG_CLEAR;\r
2824 FLAG_C = CFLAG_CLEAR;\r
2825\r
2826 for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)\r
2827 offset++;\r
2828\r
2829 REG_D[(word2>>12)&7] = offset;\r
2830\r
2831 return;\r
2832 }\r
2833 m68ki_exception_illegal();\r
2834}\r
2835\r
2836\r
2837M68KMAKE_OP(bfins, 32, ., d)\r
2838{\r
2839 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2840 {\r
2841 uint word2 = OPER_I_16();\r
2842 uint offset = (word2>>6)&31;\r
2843 uint width = word2;\r
2844 uint* data = &DY;\r
2845 uint64 mask;\r
2846 uint64 insert = REG_D[(word2>>12)&7];\r
2847\r
2848\r
2849 if(BIT_B(word2))\r
2850 offset = REG_D[offset&7];\r
2851 if(BIT_5(word2))\r
2852 width = REG_D[width&7];\r
2853\r
2854\r
2855 offset &= 31;\r
2856 width = ((width-1) & 31) + 1;\r
2857\r
2858\r
2859 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
2860 mask = ROR_32(mask, offset);\r
2861\r
2862 insert = MASK_OUT_ABOVE_32(insert << (32 - width));\r
2863 FLAG_N = NFLAG_32(insert);\r
2864 FLAG_Z = insert;\r
2865 insert = ROR_32(insert, offset);\r
2866\r
2867 FLAG_V = VFLAG_CLEAR;\r
2868 FLAG_C = CFLAG_CLEAR;\r
2869\r
2870 *data &= ~mask;\r
2871 *data |= insert;\r
2872\r
2873 return;\r
2874 }\r
2875 m68ki_exception_illegal();\r
2876}\r
2877\r
2878\r
2879M68KMAKE_OP(bfins, 32, ., .)\r
2880{\r
2881 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2882 {\r
2883 uint word2 = OPER_I_16();\r
2884 sint offset = (word2>>6)&31;\r
2885 uint width = word2;\r
2886 uint insert_base = REG_D[(word2>>12)&7];\r
2887 uint insert_long;\r
2888 uint insert_byte;\r
2889 uint mask_base;\r
2890 uint data_long;\r
2891 uint mask_long;\r
2892 uint data_byte = 0;\r
2893 uint mask_byte = 0;\r
2894 uint ea = M68KMAKE_GET_EA_AY_8;\r
2895\r
2896\r
2897 if(BIT_B(word2))\r
2898 offset = MAKE_INT_32(REG_D[offset&7]);\r
2899 if(BIT_5(word2))\r
2900 width = REG_D[width&7];\r
2901\r
2902 /* Offset is signed so we have to use ugly math =( */\r
2903 ea += offset / 8;\r
2904 offset %= 8;\r
2905 if(offset < 0)\r
2906 {\r
2907 offset += 8;\r
2908 ea--;\r
2909 }\r
2910 width = ((width-1) & 31) + 1;\r
2911\r
2912 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
2913 mask_long = mask_base >> offset;\r
2914\r
2915 insert_base = MASK_OUT_ABOVE_32(insert_base << (32 - width));\r
2916 FLAG_N = NFLAG_32(insert_base);\r
2917 FLAG_Z = insert_base;\r
2918 insert_long = insert_base >> offset;\r
2919\r
2920 data_long = m68ki_read_32(ea);\r
2921 FLAG_V = VFLAG_CLEAR;\r
2922 FLAG_C = CFLAG_CLEAR;\r
2923\r
2924 m68ki_write_32(ea, (data_long & ~mask_long) | insert_long);\r
2925\r
2926 if((width + offset) > 32)\r
2927 {\r
2928 mask_byte = MASK_OUT_ABOVE_8(mask_base);\r
2929 insert_byte = MASK_OUT_ABOVE_8(insert_base);\r
2930 data_byte = m68ki_read_8(ea+4);\r
2931 FLAG_Z |= (data_byte & mask_byte);\r
2932 m68ki_write_8(ea+4, (data_byte & ~mask_byte) | insert_byte);\r
2933 }\r
2934 return;\r
2935 }\r
2936 m68ki_exception_illegal();\r
2937}\r
2938\r
2939\r
2940M68KMAKE_OP(bfset, 32, ., d)\r
2941{\r
2942 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2943 {\r
2944 uint word2 = OPER_I_16();\r
2945 uint offset = (word2>>6)&31;\r
2946 uint width = word2;\r
2947 uint* data = &DY;\r
2948 uint64 mask;\r
2949\r
2950\r
2951 if(BIT_B(word2))\r
2952 offset = REG_D[offset&7];\r
2953 if(BIT_5(word2))\r
2954 width = REG_D[width&7];\r
2955\r
2956\r
2957 offset &= 31;\r
2958 width = ((width-1) & 31) + 1;\r
2959\r
2960\r
2961 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
2962 mask = ROR_32(mask, offset);\r
2963\r
2964 FLAG_N = NFLAG_32(*data<<offset);\r
2965 FLAG_Z = *data & mask;\r
2966 FLAG_V = VFLAG_CLEAR;\r
2967 FLAG_C = CFLAG_CLEAR;\r
2968\r
2969 *data |= mask;\r
2970\r
2971 return;\r
2972 }\r
2973 m68ki_exception_illegal();\r
2974}\r
2975\r
2976\r
2977M68KMAKE_OP(bfset, 32, ., .)\r
2978{\r
2979 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
2980 {\r
2981 uint word2 = OPER_I_16();\r
2982 sint offset = (word2>>6)&31;\r
2983 uint width = word2;\r
2984 uint mask_base;\r
2985 uint data_long;\r
2986 uint mask_long;\r
2987 uint data_byte = 0;\r
2988 uint mask_byte = 0;\r
2989 uint ea = M68KMAKE_GET_EA_AY_8;\r
2990\r
2991\r
2992 if(BIT_B(word2))\r
2993 offset = MAKE_INT_32(REG_D[offset&7]);\r
2994 if(BIT_5(word2))\r
2995 width = REG_D[width&7];\r
2996\r
2997 /* Offset is signed so we have to use ugly math =( */\r
2998 ea += offset / 8;\r
2999 offset %= 8;\r
3000 if(offset < 0)\r
3001 {\r
3002 offset += 8;\r
3003 ea--;\r
3004 }\r
3005 width = ((width-1) & 31) + 1;\r
3006\r
3007\r
3008 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
3009 mask_long = mask_base >> offset;\r
3010\r
3011 data_long = m68ki_read_32(ea);\r
3012 FLAG_N = NFLAG_32(data_long << offset);\r
3013 FLAG_Z = data_long & mask_long;\r
3014 FLAG_V = VFLAG_CLEAR;\r
3015 FLAG_C = CFLAG_CLEAR;\r
3016\r
3017 m68ki_write_32(ea, data_long | mask_long);\r
3018\r
3019 if((width + offset) > 32)\r
3020 {\r
3021 mask_byte = MASK_OUT_ABOVE_8(mask_base);\r
3022 data_byte = m68ki_read_8(ea+4);\r
3023 FLAG_Z |= (data_byte & mask_byte);\r
3024 m68ki_write_8(ea+4, data_byte | mask_byte);\r
3025 }\r
3026 return;\r
3027 }\r
3028 m68ki_exception_illegal();\r
3029}\r
3030\r
3031\r
3032M68KMAKE_OP(bftst, 32, ., d)\r
3033{\r
3034 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3035 {\r
3036 uint word2 = OPER_I_16();\r
3037 uint offset = (word2>>6)&31;\r
3038 uint width = word2;\r
3039 uint* data = &DY;\r
3040 uint64 mask;\r
3041\r
3042\r
3043 if(BIT_B(word2))\r
3044 offset = REG_D[offset&7];\r
3045 if(BIT_5(word2))\r
3046 width = REG_D[width&7];\r
3047\r
3048\r
3049 offset &= 31;\r
3050 width = ((width-1) & 31) + 1;\r
3051\r
3052\r
3053 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
3054 mask = ROR_32(mask, offset);\r
3055\r
3056 FLAG_N = NFLAG_32(*data<<offset);\r
3057 FLAG_Z = *data & mask;\r
3058 FLAG_V = VFLAG_CLEAR;\r
3059 FLAG_C = CFLAG_CLEAR;\r
3060\r
3061 return;\r
3062 }\r
3063 m68ki_exception_illegal();\r
3064}\r
3065\r
3066\r
3067M68KMAKE_OP(bftst, 32, ., .)\r
3068{\r
3069 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3070 {\r
3071 uint word2 = OPER_I_16();\r
3072 sint offset = (word2>>6)&31;\r
3073 uint width = word2;\r
3074 uint mask_base;\r
3075 uint data_long;\r
3076 uint mask_long;\r
3077 uint data_byte = 0;\r
3078 uint mask_byte = 0;\r
3079 uint ea = M68KMAKE_GET_EA_AY_8;\r
3080\r
3081 if(BIT_B(word2))\r
3082 offset = MAKE_INT_32(REG_D[offset&7]);\r
3083 if(BIT_5(word2))\r
3084 width = REG_D[width&7];\r
3085\r
3086 /* Offset is signed so we have to use ugly math =( */\r
3087 ea += offset / 8;\r
3088 offset %= 8;\r
3089 if(offset < 0)\r
3090 {\r
3091 offset += 8;\r
3092 ea--;\r
3093 }\r
3094 width = ((width-1) & 31) + 1;\r
3095\r
3096\r
3097 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));\r
3098 mask_long = mask_base >> offset;\r
3099\r
3100 data_long = m68ki_read_32(ea);\r
3101 FLAG_N = ((data_long & (0x80000000 >> offset))<<offset)>>24;\r
3102 FLAG_Z = data_long & mask_long;\r
3103 FLAG_V = VFLAG_CLEAR;\r
3104 FLAG_C = CFLAG_CLEAR;\r
3105\r
3106 if((width + offset) > 32)\r
3107 {\r
3108 mask_byte = MASK_OUT_ABOVE_8(mask_base);\r
3109 data_byte = m68ki_read_8(ea+4);\r
3110 FLAG_Z |= (data_byte & mask_byte);\r
3111 }\r
3112 return;\r
3113 }\r
3114 m68ki_exception_illegal();\r
3115}\r
3116\r
3117\r
3118M68KMAKE_OP(bkpt, 0, ., .)\r
3119{\r
3120 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))\r
3121 {\r
3122 m68ki_bkpt_ack(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE) ? REG_IR & 7 : 0); /* auto-disable (see m68kcpu.h) */\r
3123 }\r
3124 m68ki_exception_illegal();\r
3125}\r
3126\r
3127\r
3128M68KMAKE_OP(bra, 8, ., .)\r
3129{\r
3130 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3131 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));\r
c6a4c892 3132 if(REG_PC == REG_PPC)\r
3133 USE_ALL_CYCLES();\r
cc68a136 3134}\r
3135\r
3136\r
3137M68KMAKE_OP(bra, 16, ., .)\r
3138{\r
3139 uint offset = OPER_I_16();\r
3140 REG_PC -= 2;\r
3141 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3142 m68ki_branch_16(offset);\r
c6a4c892 3143 if(REG_PC == REG_PPC)\r
3144 USE_ALL_CYCLES();\r
cc68a136 3145}\r
3146\r
3147\r
3148M68KMAKE_OP(bra, 32, ., .)\r
3149{\r
3150 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3151 {\r
3152 uint offset = OPER_I_32();\r
3153 REG_PC -= 4;\r
3154 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3155 m68ki_branch_32(offset);\r
3156 if(REG_PC == REG_PPC)\r
3157 USE_ALL_CYCLES();\r
3158 return;\r
3159 }\r
3160 else\r
3161 {\r
3162 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3163 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));\r
c6a4c892 3164 if(REG_PC == REG_PPC)\r
3165 USE_ALL_CYCLES();\r
cc68a136 3166 }\r
3167}\r
3168\r
3169\r
3170M68KMAKE_OP(bset, 32, r, d)\r
3171{\r
3172 uint* r_dst = &DY;\r
3173 uint mask = 1 << (DX & 0x1f);\r
3174\r
3175 FLAG_Z = *r_dst & mask;\r
3176 *r_dst |= mask;\r
3177}\r
3178\r
3179\r
3180M68KMAKE_OP(bset, 8, r, .)\r
3181{\r
3182 uint ea = M68KMAKE_GET_EA_AY_8;\r
3183 uint src = m68ki_read_8(ea);\r
3184 uint mask = 1 << (DX & 7);\r
3185\r
3186 FLAG_Z = src & mask;\r
3187 m68ki_write_8(ea, src | mask);\r
3188}\r
3189\r
3190\r
3191M68KMAKE_OP(bset, 32, s, d)\r
3192{\r
3193 uint* r_dst = &DY;\r
3194 uint mask = 1 << (OPER_I_8() & 0x1f);\r
3195\r
3196 FLAG_Z = *r_dst & mask;\r
3197 *r_dst |= mask;\r
3198}\r
3199\r
3200\r
3201M68KMAKE_OP(bset, 8, s, .)\r
3202{\r
3203 uint mask = 1 << (OPER_I_8() & 7);\r
3204 uint ea = M68KMAKE_GET_EA_AY_8;\r
3205 uint src = m68ki_read_8(ea);\r
3206\r
3207 FLAG_Z = src & mask;\r
3208 m68ki_write_8(ea, src | mask);\r
3209}\r
3210\r
3211\r
3212M68KMAKE_OP(bsr, 8, ., .)\r
3213{\r
3214 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3215 m68ki_push_32(REG_PC);\r
3216 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));\r
3217}\r
3218\r
3219\r
3220M68KMAKE_OP(bsr, 16, ., .)\r
3221{\r
3222 uint offset = OPER_I_16();\r
3223 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3224 m68ki_push_32(REG_PC);\r
3225 REG_PC -= 2;\r
3226 m68ki_branch_16(offset);\r
3227}\r
3228\r
3229\r
3230M68KMAKE_OP(bsr, 32, ., .)\r
3231{\r
3232 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3233 {\r
3234 uint offset = OPER_I_32();\r
3235 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3236 m68ki_push_32(REG_PC);\r
3237 REG_PC -= 4;\r
3238 m68ki_branch_32(offset);\r
3239 return;\r
3240 }\r
3241 else\r
3242 {\r
3243 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3244 m68ki_push_32(REG_PC);\r
3245 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));\r
3246 }\r
3247}\r
3248\r
3249\r
3250M68KMAKE_OP(btst, 32, r, d)\r
3251{\r
3252 FLAG_Z = DY & (1 << (DX & 0x1f));\r
3253}\r
3254\r
3255\r
3256M68KMAKE_OP(btst, 8, r, .)\r
3257{\r
3258 FLAG_Z = M68KMAKE_GET_OPER_AY_8 & (1 << (DX & 7));\r
3259}\r
3260\r
3261\r
3262M68KMAKE_OP(btst, 32, s, d)\r
3263{\r
3264 FLAG_Z = DY & (1 << (OPER_I_8() & 0x1f));\r
3265}\r
3266\r
3267\r
3268M68KMAKE_OP(btst, 8, s, .)\r
3269{\r
3270 uint bit = OPER_I_8() & 7;\r
3271\r
3272 FLAG_Z = M68KMAKE_GET_OPER_AY_8 & (1 << bit);\r
3273}\r
3274\r
3275\r
3276M68KMAKE_OP(callm, 32, ., .)\r
3277{\r
3278 /* note: watch out for pcrelative modes */\r
3279 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))\r
3280 {\r
3281 uint ea = M68KMAKE_GET_EA_AY_32;\r
3282\r
3283 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3284 REG_PC += 2;\r
3285(void)ea; /* just to avoid an 'unused variable' warning */\r
3286 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",\r
3287 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,\r
3288 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));\r
3289 return;\r
3290 }\r
3291 m68ki_exception_illegal();\r
3292}\r
3293\r
3294\r
3295M68KMAKE_OP(cas, 8, ., .)\r
3296{\r
3297 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3298 {\r
3299 uint word2 = OPER_I_16();\r
3300 uint ea = M68KMAKE_GET_EA_AY_8;\r
3301 uint dest = m68ki_read_8(ea);\r
3302 uint* compare = &REG_D[word2 & 7];\r
3303 uint res = dest - MASK_OUT_ABOVE_8(*compare);\r
3304\r
3305 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3306 FLAG_N = NFLAG_8(res);\r
3307 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
3308 FLAG_V = VFLAG_SUB_8(*compare, dest, res);\r
3309 FLAG_C = CFLAG_8(res);\r
3310\r
3311 if(COND_NE())\r
3312 *compare = MASK_OUT_BELOW_8(*compare) | dest;\r
3313 else\r
3314 {\r
3315 USE_CYCLES(3);\r
3316 m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7]));\r
3317 }\r
3318 return;\r
3319 }\r
3320 m68ki_exception_illegal();\r
3321}\r
3322\r
3323\r
3324M68KMAKE_OP(cas, 16, ., .)\r
3325{\r
3326 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3327 {\r
3328 uint word2 = OPER_I_16();\r
3329 uint ea = M68KMAKE_GET_EA_AY_16;\r
3330 uint dest = m68ki_read_16(ea);\r
3331 uint* compare = &REG_D[word2 & 7];\r
3332 uint res = dest - MASK_OUT_ABOVE_16(*compare);\r
3333\r
3334 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3335 FLAG_N = NFLAG_16(res);\r
3336 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
3337 FLAG_V = VFLAG_SUB_16(*compare, dest, res);\r
3338 FLAG_C = CFLAG_16(res);\r
3339\r
3340 if(COND_NE())\r
3341 *compare = MASK_OUT_BELOW_16(*compare) | dest;\r
3342 else\r
3343 {\r
3344 USE_CYCLES(3);\r
3345 m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7]));\r
3346 }\r
3347 return;\r
3348 }\r
3349 m68ki_exception_illegal();\r
3350}\r
3351\r
3352\r
3353M68KMAKE_OP(cas, 32, ., .)\r
3354{\r
3355 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3356 {\r
3357 uint word2 = OPER_I_16();\r
3358 uint ea = M68KMAKE_GET_EA_AY_32;\r
3359 uint dest = m68ki_read_32(ea);\r
3360 uint* compare = &REG_D[word2 & 7];\r
3361 uint res = dest - *compare;\r
3362\r
3363 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3364 FLAG_N = NFLAG_32(res);\r
3365 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
3366 FLAG_V = VFLAG_SUB_32(*compare, dest, res);\r
3367 FLAG_C = CFLAG_SUB_32(*compare, dest, res);\r
3368\r
3369 if(COND_NE())\r
3370 *compare = dest;\r
3371 else\r
3372 {\r
3373 USE_CYCLES(3);\r
3374 m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]);\r
3375 }\r
3376 return;\r
3377 }\r
3378 m68ki_exception_illegal();\r
3379}\r
3380\r
3381\r
3382M68KMAKE_OP(cas2, 16, ., .)\r
3383{\r
3384 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3385 {\r
3386 uint word2 = OPER_I_32();\r
3387 uint* compare1 = &REG_D[(word2 >> 16) & 7];\r
3388 uint ea1 = REG_DA[(word2 >> 28) & 15];\r
3389 uint dest1 = m68ki_read_16(ea1);\r
3390 uint res1 = dest1 - MASK_OUT_ABOVE_16(*compare1);\r
3391 uint* compare2 = &REG_D[word2 & 7];\r
3392 uint ea2 = REG_DA[(word2 >> 12) & 15];\r
3393 uint dest2 = m68ki_read_16(ea2);\r
3394 uint res2;\r
3395\r
3396 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3397 FLAG_N = NFLAG_16(res1);\r
3398 FLAG_Z = MASK_OUT_ABOVE_16(res1);\r
3399 FLAG_V = VFLAG_SUB_16(*compare1, dest1, res1);\r
3400 FLAG_C = CFLAG_16(res1);\r
3401\r
3402 if(COND_EQ())\r
3403 {\r
3404 res2 = dest2 - MASK_OUT_ABOVE_16(*compare2);\r
3405\r
3406 FLAG_N = NFLAG_16(res2);\r
3407 FLAG_Z = MASK_OUT_ABOVE_16(res2);\r
3408 FLAG_V = VFLAG_SUB_16(*compare2, dest2, res2);\r
3409 FLAG_C = CFLAG_16(res2);\r
3410\r
3411 if(COND_EQ())\r
3412 {\r
3413 USE_CYCLES(3);\r
3414 m68ki_write_16(ea1, REG_D[(word2 >> 22) & 7]);\r
3415 m68ki_write_16(ea2, REG_D[(word2 >> 6) & 7]);\r
3416 return;\r
3417 }\r
3418 }\r
3419 *compare1 = BIT_1F(word2) ? MAKE_INT_16(dest1) : MASK_OUT_BELOW_16(*compare1) | dest1;\r
3420 *compare2 = BIT_F(word2) ? MAKE_INT_16(dest2) : MASK_OUT_BELOW_16(*compare2) | dest2;\r
3421 return;\r
3422 }\r
3423 m68ki_exception_illegal();\r
3424}\r
3425\r
3426\r
3427M68KMAKE_OP(cas2, 32, ., .)\r
3428{\r
3429 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3430 {\r
3431 uint word2 = OPER_I_32();\r
3432 uint* compare1 = &REG_D[(word2 >> 16) & 7];\r
3433 uint ea1 = REG_DA[(word2 >> 28) & 15];\r
3434 uint dest1 = m68ki_read_32(ea1);\r
3435 uint res1 = dest1 - *compare1;\r
3436 uint* compare2 = &REG_D[word2 & 7];\r
3437 uint ea2 = REG_DA[(word2 >> 12) & 15];\r
3438 uint dest2 = m68ki_read_32(ea2);\r
3439 uint res2;\r
3440\r
3441 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
3442 FLAG_N = NFLAG_32(res1);\r
3443 FLAG_Z = MASK_OUT_ABOVE_32(res1);\r
3444 FLAG_V = VFLAG_SUB_32(*compare1, dest1, res1);\r
3445 FLAG_C = CFLAG_SUB_32(*compare1, dest1, res1);\r
3446\r
3447 if(COND_EQ())\r
3448 {\r
3449 res2 = dest2 - *compare2;\r
3450\r
3451 FLAG_N = NFLAG_32(res2);\r
3452 FLAG_Z = MASK_OUT_ABOVE_32(res2);\r
3453 FLAG_V = VFLAG_SUB_32(*compare2, dest2, res2);\r
3454 FLAG_C = CFLAG_SUB_32(*compare2, dest2, res2);\r
3455\r
3456 if(COND_EQ())\r
3457 {\r
3458 USE_CYCLES(3);\r
3459 m68ki_write_32(ea1, REG_D[(word2 >> 22) & 7]);\r
3460 m68ki_write_32(ea2, REG_D[(word2 >> 6) & 7]);\r
3461 return;\r
3462 }\r
3463 }\r
3464 *compare1 = dest1;\r
3465 *compare2 = dest2;\r
3466 return;\r
3467 }\r
3468 m68ki_exception_illegal();\r
3469}\r
3470\r
3471\r
3472M68KMAKE_OP(chk, 16, ., d)\r
3473{\r
3474 sint src = MAKE_INT_16(DX);\r
3475 sint bound = MAKE_INT_16(DY);\r
3476\r
3477 FLAG_Z = ZFLAG_16(src); /* Undocumented */\r
3478 FLAG_V = VFLAG_CLEAR; /* Undocumented */\r
3479 FLAG_C = CFLAG_CLEAR; /* Undocumented */\r
3480\r
3481 if(src >= 0 && src <= bound)\r
3482 {\r
3483 return;\r
3484 }\r
3485 FLAG_N = (src < 0)<<7;\r
3486 m68ki_exception_trap(EXCEPTION_CHK);\r
3487}\r
3488\r
3489\r
3490M68KMAKE_OP(chk, 16, ., .)\r
3491{\r
3492 sint src = MAKE_INT_16(DX);\r
3493 sint bound = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);\r
3494\r
3495 FLAG_Z = ZFLAG_16(src); /* Undocumented */\r
3496 FLAG_V = VFLAG_CLEAR; /* Undocumented */\r
3497 FLAG_C = CFLAG_CLEAR; /* Undocumented */\r
3498\r
3499 if(src >= 0 && src <= bound)\r
3500 {\r
3501 return;\r
3502 }\r
3503 FLAG_N = (src < 0)<<7;\r
3504 m68ki_exception_trap(EXCEPTION_CHK);\r
3505}\r
3506\r
3507\r
3508M68KMAKE_OP(chk, 32, ., d)\r
3509{\r
3510 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3511 {\r
3512 sint src = MAKE_INT_32(DX);\r
3513 sint bound = MAKE_INT_32(DY);\r
3514\r
3515 FLAG_Z = ZFLAG_32(src); /* Undocumented */\r
3516 FLAG_V = VFLAG_CLEAR; /* Undocumented */\r
3517 FLAG_C = CFLAG_CLEAR; /* Undocumented */\r
3518\r
3519 if(src >= 0 && src <= bound)\r
3520 {\r
3521 return;\r
3522 }\r
3523 FLAG_N = (src < 0)<<7;\r
3524 m68ki_exception_trap(EXCEPTION_CHK);\r
3525 return;\r
3526 }\r
3527 m68ki_exception_illegal();\r
3528}\r
3529\r
3530\r
3531M68KMAKE_OP(chk, 32, ., .)\r
3532{\r
3533 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3534 {\r
3535 sint src = MAKE_INT_32(DX);\r
3536 sint bound = MAKE_INT_32(M68KMAKE_GET_OPER_AY_32);\r
3537\r
3538 FLAG_Z = ZFLAG_32(src); /* Undocumented */\r
3539 FLAG_V = VFLAG_CLEAR; /* Undocumented */\r
3540 FLAG_C = CFLAG_CLEAR; /* Undocumented */\r
3541\r
3542 if(src >= 0 && src <= bound)\r
3543 {\r
3544 return;\r
3545 }\r
3546 FLAG_N = (src < 0)<<7;\r
3547 m68ki_exception_trap(EXCEPTION_CHK);\r
3548 return;\r
3549 }\r
3550 m68ki_exception_illegal();\r
3551}\r
3552\r
3553\r
3554M68KMAKE_OP(chk2cmp2, 8, ., pcdi)\r
3555{\r
3556 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3557 {\r
3558 uint word2 = OPER_I_16();\r
3559 uint compare = REG_DA[(word2 >> 12) & 15]&0xff;\r
3560 uint ea = EA_PCDI_8();\r
3561 uint lower_bound = m68ki_read_pcrel_8(ea);\r
3562 uint upper_bound = m68ki_read_pcrel_8(ea + 1);\r
3563\r
3564 if(!BIT_F(word2))\r
3565 FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound);\r
3566 else\r
3567 FLAG_C = compare - lower_bound;\r
3568 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));\r
3569 if(COND_CS())\r
3570 {\r
3571 if(BIT_B(word2))\r
3572 m68ki_exception_trap(EXCEPTION_CHK);\r
3573 return;\r
3574 }\r
3575\r
3576 FLAG_C = upper_bound - compare;\r
3577 if(COND_CS() && BIT_B(word2))\r
3578 m68ki_exception_trap(EXCEPTION_CHK);\r
3579 return;\r
3580 }\r
3581 m68ki_exception_illegal();\r
3582}\r
3583\r
3584\r
3585M68KMAKE_OP(chk2cmp2, 8, ., pcix)\r
3586{\r
3587 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3588 {\r
3589 uint word2 = OPER_I_16();\r
3590 uint compare = REG_DA[(word2 >> 12) & 15]&0xff;\r
3591 uint ea = EA_PCIX_8();\r
3592 uint lower_bound = m68ki_read_pcrel_8(ea);\r
3593 uint upper_bound = m68ki_read_pcrel_8(ea + 1);\r
3594\r
3595 if(!BIT_F(word2))\r
3596 FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound);\r
3597 else\r
3598 FLAG_C = compare - lower_bound;\r
3599 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));\r
3600 if(COND_CS())\r
3601 {\r
3602 if(BIT_B(word2))\r
3603 m68ki_exception_trap(EXCEPTION_CHK);\r
3604 return;\r
3605 }\r
3606\r
3607 FLAG_C = upper_bound - compare;\r
3608 if(COND_CS() && BIT_B(word2))\r
3609 m68ki_exception_trap(EXCEPTION_CHK);\r
3610 return;\r
3611 }\r
3612 m68ki_exception_illegal();\r
3613}\r
3614\r
3615\r
3616M68KMAKE_OP(chk2cmp2, 8, ., .)\r
3617{\r
3618 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3619 {\r
3620 uint word2 = OPER_I_16();\r
3621 uint compare = REG_DA[(word2 >> 12) & 15]&0xff;\r
3622 uint ea = M68KMAKE_GET_EA_AY_8;\r
3623 uint lower_bound = m68ki_read_8(ea);\r
3624 uint upper_bound = m68ki_read_8(ea + 1);\r
3625\r
3626 if(!BIT_F(word2))\r
3627 FLAG_C = MAKE_INT_8(compare) - MAKE_INT_8(lower_bound);\r
3628 else\r
3629 FLAG_C = compare - lower_bound;\r
3630 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));\r
3631 if(COND_CS())\r
3632 {\r
3633 if(BIT_B(word2))\r
3634 m68ki_exception_trap(EXCEPTION_CHK);\r
3635 return;\r
3636 }\r
3637\r
3638 FLAG_C = upper_bound - compare;\r
3639 if(COND_CS() && BIT_B(word2))\r
3640 m68ki_exception_trap(EXCEPTION_CHK);\r
3641 return;\r
3642 }\r
3643 m68ki_exception_illegal();\r
3644}\r
3645\r
3646\r
3647M68KMAKE_OP(chk2cmp2, 16, ., pcdi)\r
3648{\r
3649 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3650 {\r
3651 uint word2 = OPER_I_16();\r
3652 uint compare = REG_DA[(word2 >> 12) & 15]&0xffff;\r
3653 uint ea = EA_PCDI_16();\r
3654 uint lower_bound = m68ki_read_pcrel_16(ea);\r
3655 uint upper_bound = m68ki_read_pcrel_16(ea + 2);\r
3656\r
3657 if(!BIT_F(word2))\r
3658 FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound);\r
3659 else\r
3660 FLAG_C = compare - lower_bound;\r
3661 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));\r
3662 FLAG_C = CFLAG_16(FLAG_C);\r
3663 if(COND_CS())\r
3664 {\r
3665 if(BIT_B(word2))\r
3666 m68ki_exception_trap(EXCEPTION_CHK);\r
3667 return;\r
3668 }\r
3669\r
3670 if(!BIT_F(word2))\r
3671 FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare);\r
3672 else\r
3673 FLAG_C = upper_bound - compare;\r
3674 FLAG_C = CFLAG_16(FLAG_C);\r
3675 if(COND_CS() && BIT_B(word2))\r
3676 m68ki_exception_trap(EXCEPTION_CHK);\r
3677 return;\r
3678 }\r
3679 m68ki_exception_illegal();\r
3680}\r
3681\r
3682\r
3683M68KMAKE_OP(chk2cmp2, 16, ., pcix)\r
3684{\r
3685 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3686 {\r
3687 uint word2 = OPER_I_16();\r
3688 uint compare = REG_DA[(word2 >> 12) & 15]&0xffff;\r
3689 uint ea = EA_PCIX_16();\r
3690 uint lower_bound = m68ki_read_pcrel_16(ea);\r
3691 uint upper_bound = m68ki_read_pcrel_16(ea + 2);\r
3692\r
3693 if(!BIT_F(word2))\r
3694 FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound);\r
3695 else\r
3696 FLAG_C = compare - lower_bound;\r
3697 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));\r
3698 FLAG_C = CFLAG_16(FLAG_C);\r
3699 if(COND_CS())\r
3700 {\r
3701 if(BIT_B(word2))\r
3702 m68ki_exception_trap(EXCEPTION_CHK);\r
3703 return;\r
3704 }\r
3705\r
3706 if(!BIT_F(word2))\r
3707 FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare);\r
3708 else\r
3709 FLAG_C = upper_bound - compare;\r
3710 FLAG_C = CFLAG_16(FLAG_C);\r
3711 if(COND_CS() && BIT_B(word2))\r
3712 m68ki_exception_trap(EXCEPTION_CHK);\r
3713 return;\r
3714 }\r
3715 m68ki_exception_illegal();\r
3716}\r
3717\r
3718\r
3719M68KMAKE_OP(chk2cmp2, 16, ., .)\r
3720{\r
3721 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3722 {\r
3723 uint word2 = OPER_I_16();\r
3724 uint compare = REG_DA[(word2 >> 12) & 15]&0xffff;\r
3725 uint ea = M68KMAKE_GET_EA_AY_16;\r
3726 uint lower_bound = m68ki_read_16(ea);\r
3727 uint upper_bound = m68ki_read_16(ea + 2);\r
3728\r
3729 if(!BIT_F(word2))\r
3730 FLAG_C = MAKE_INT_16(compare) - MAKE_INT_16(lower_bound);\r
3731 else\r
3732 FLAG_C = compare - lower_bound;\r
3733\r
3734 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));\r
3735 FLAG_C = CFLAG_16(FLAG_C);\r
3736 if(COND_CS())\r
3737 {\r
3738 if(BIT_B(word2))\r
3739 m68ki_exception_trap(EXCEPTION_CHK);\r
3740 return;\r
3741 }\r
3742 if(!BIT_F(word2))\r
3743 FLAG_C = MAKE_INT_16(upper_bound) - MAKE_INT_16(compare);\r
3744 else\r
3745 FLAG_C = upper_bound - compare;\r
3746\r
3747 FLAG_C = CFLAG_16(FLAG_C);\r
3748 if(COND_CS() && BIT_B(word2))\r
3749 m68ki_exception_trap(EXCEPTION_CHK);\r
3750 return;\r
3751 }\r
3752 m68ki_exception_illegal();\r
3753}\r
3754\r
3755\r
3756M68KMAKE_OP(chk2cmp2, 32, ., pcdi)\r
3757{\r
3758 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3759 {\r
3760 uint word2 = OPER_I_16();\r
3761 uint compare = REG_DA[(word2 >> 12) & 15];\r
3762 uint ea = EA_PCDI_32();\r
3763 uint lower_bound = m68ki_read_pcrel_32(ea);\r
3764 uint upper_bound = m68ki_read_pcrel_32(ea + 4);\r
3765\r
3766 FLAG_C = compare - lower_bound;\r
3767 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));\r
3768 FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);\r
3769 if(COND_CS())\r
3770 {\r
3771 if(BIT_B(word2))\r
3772 m68ki_exception_trap(EXCEPTION_CHK);\r
3773 return;\r
3774 }\r
3775\r
3776 FLAG_C = upper_bound - compare;\r
3777 FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);\r
3778 if(COND_CS() && BIT_B(word2))\r
3779 m68ki_exception_trap(EXCEPTION_CHK);\r
3780 return;\r
3781 }\r
3782 m68ki_exception_illegal();\r
3783}\r
3784\r
3785\r
3786M68KMAKE_OP(chk2cmp2, 32, ., pcix)\r
3787{\r
3788 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3789 {\r
3790 uint word2 = OPER_I_16();\r
3791 uint compare = REG_DA[(word2 >> 12) & 15];\r
3792 uint ea = EA_PCIX_32();\r
3793 uint lower_bound = m68ki_read_pcrel_32(ea);\r
3794 uint upper_bound = m68ki_read_pcrel_32(ea + 4);\r
3795\r
3796 FLAG_C = compare - lower_bound;\r
3797 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));\r
3798 FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);\r
3799 if(COND_CS())\r
3800 {\r
3801 if(BIT_B(word2))\r
3802 m68ki_exception_trap(EXCEPTION_CHK);\r
3803 return;\r
3804 }\r
3805\r
3806 FLAG_C = upper_bound - compare;\r
3807 FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);\r
3808 if(COND_CS() && BIT_B(word2))\r
3809 m68ki_exception_trap(EXCEPTION_CHK);\r
3810 return;\r
3811 }\r
3812 m68ki_exception_illegal();\r
3813}\r
3814\r
3815\r
3816M68KMAKE_OP(chk2cmp2, 32, ., .)\r
3817{\r
3818 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
3819 {\r
3820 uint word2 = OPER_I_16();\r
3821 uint compare = REG_DA[(word2 >> 12) & 15];\r
3822 uint ea = M68KMAKE_GET_EA_AY_32;\r
3823 uint lower_bound = m68ki_read_32(ea);\r
3824 uint upper_bound = m68ki_read_32(ea + 4);\r
3825\r
3826 FLAG_C = compare - lower_bound;\r
3827 FLAG_Z = !((upper_bound==compare) | (lower_bound==compare));\r
3828 FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);\r
3829 if(COND_CS())\r
3830 {\r
3831 if(BIT_B(word2))\r
3832 m68ki_exception_trap(EXCEPTION_CHK);\r
3833 return;\r
3834 }\r
3835\r
3836 FLAG_C = upper_bound - compare;\r
3837 FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);\r
3838 if(COND_CS() && BIT_B(word2))\r
3839 m68ki_exception_trap(EXCEPTION_CHK);\r
3840 return;\r
3841 }\r
3842 m68ki_exception_illegal();\r
3843}\r
3844\r
3845\r
3846M68KMAKE_OP(clr, 8, ., d)\r
3847{\r
3848 DY &= 0xffffff00;\r
3849\r
3850 FLAG_N = NFLAG_CLEAR;\r
3851 FLAG_V = VFLAG_CLEAR;\r
3852 FLAG_C = CFLAG_CLEAR;\r
3853 FLAG_Z = ZFLAG_SET;\r
3854}\r
3855\r
3856\r
3857M68KMAKE_OP(clr, 8, ., .)\r
3858{\r
3859 m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0);\r
3860\r
3861 FLAG_N = NFLAG_CLEAR;\r
3862 FLAG_V = VFLAG_CLEAR;\r
3863 FLAG_C = CFLAG_CLEAR;\r
3864 FLAG_Z = ZFLAG_SET;\r
3865}\r
3866\r
3867\r
3868M68KMAKE_OP(clr, 16, ., d)\r
3869{\r
3870 DY &= 0xffff0000;\r
3871\r
3872 FLAG_N = NFLAG_CLEAR;\r
3873 FLAG_V = VFLAG_CLEAR;\r
3874 FLAG_C = CFLAG_CLEAR;\r
3875 FLAG_Z = ZFLAG_SET;\r
3876}\r
3877\r
3878\r
3879M68KMAKE_OP(clr, 16, ., .)\r
3880{\r
3881 m68ki_write_16(M68KMAKE_GET_EA_AY_16, 0);\r
3882\r
3883 FLAG_N = NFLAG_CLEAR;\r
3884 FLAG_V = VFLAG_CLEAR;\r
3885 FLAG_C = CFLAG_CLEAR;\r
3886 FLAG_Z = ZFLAG_SET;\r
3887}\r
3888\r
3889\r
3890M68KMAKE_OP(clr, 32, ., d)\r
3891{\r
3892 DY = 0;\r
3893\r
3894 FLAG_N = NFLAG_CLEAR;\r
3895 FLAG_V = VFLAG_CLEAR;\r
3896 FLAG_C = CFLAG_CLEAR;\r
3897 FLAG_Z = ZFLAG_SET;\r
3898}\r
3899\r
3900\r
3901M68KMAKE_OP(clr, 32, ., .)\r
3902{\r
3903 m68ki_write_32(M68KMAKE_GET_EA_AY_32, 0);\r
3904\r
3905 FLAG_N = NFLAG_CLEAR;\r
3906 FLAG_V = VFLAG_CLEAR;\r
3907 FLAG_C = CFLAG_CLEAR;\r
3908 FLAG_Z = ZFLAG_SET;\r
3909}\r
3910\r
3911\r
3912M68KMAKE_OP(cmp, 8, ., d)\r
3913{\r
3914 uint src = MASK_OUT_ABOVE_8(DY);\r
3915 uint dst = MASK_OUT_ABOVE_8(DX);\r
3916 uint res = dst - src;\r
3917\r
3918 FLAG_N = NFLAG_8(res);\r
3919 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
3920 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
3921 FLAG_C = CFLAG_8(res);\r
3922}\r
3923\r
3924\r
3925M68KMAKE_OP(cmp, 8, ., .)\r
3926{\r
3927 uint src = M68KMAKE_GET_OPER_AY_8;\r
3928 uint dst = MASK_OUT_ABOVE_8(DX);\r
3929 uint res = dst - src;\r
3930\r
3931 FLAG_N = NFLAG_8(res);\r
3932 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
3933 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
3934 FLAG_C = CFLAG_8(res);\r
3935}\r
3936\r
3937\r
3938M68KMAKE_OP(cmp, 16, ., d)\r
3939{\r
3940 uint src = MASK_OUT_ABOVE_16(DY);\r
3941 uint dst = MASK_OUT_ABOVE_16(DX);\r
3942 uint res = dst - src;\r
3943\r
3944 FLAG_N = NFLAG_16(res);\r
3945 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
3946 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
3947 FLAG_C = CFLAG_16(res);\r
3948}\r
3949\r
3950\r
3951M68KMAKE_OP(cmp, 16, ., a)\r
3952{\r
3953 uint src = MASK_OUT_ABOVE_16(AY);\r
3954 uint dst = MASK_OUT_ABOVE_16(DX);\r
3955 uint res = dst - src;\r
3956\r
3957 FLAG_N = NFLAG_16(res);\r
3958 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
3959 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
3960 FLAG_C = CFLAG_16(res);\r
3961}\r
3962\r
3963\r
3964M68KMAKE_OP(cmp, 16, ., .)\r
3965{\r
3966 uint src = M68KMAKE_GET_OPER_AY_16;\r
3967 uint dst = MASK_OUT_ABOVE_16(DX);\r
3968 uint res = dst - src;\r
3969\r
3970 FLAG_N = NFLAG_16(res);\r
3971 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
3972 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
3973 FLAG_C = CFLAG_16(res);\r
3974}\r
3975\r
3976\r
3977M68KMAKE_OP(cmp, 32, ., d)\r
3978{\r
3979 uint src = DY;\r
3980 uint dst = DX;\r
3981 uint res = dst - src;\r
3982\r
3983 FLAG_N = NFLAG_32(res);\r
3984 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
3985 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
3986 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
3987}\r
3988\r
3989\r
3990M68KMAKE_OP(cmp, 32, ., a)\r
3991{\r
3992 uint src = AY;\r
3993 uint dst = DX;\r
3994 uint res = dst - src;\r
3995\r
3996 FLAG_N = NFLAG_32(res);\r
3997 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
3998 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
3999 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4000}\r
4001\r
4002\r
4003M68KMAKE_OP(cmp, 32, ., .)\r
4004{\r
4005 uint src = M68KMAKE_GET_OPER_AY_32;\r
4006 uint dst = DX;\r
4007 uint res = dst - src;\r
4008\r
4009 FLAG_N = NFLAG_32(res);\r
4010 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4011 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4012 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4013}\r
4014\r
4015\r
4016M68KMAKE_OP(cmpa, 16, ., d)\r
4017{\r
4018 uint src = MAKE_INT_16(DY);\r
4019 uint dst = AX;\r
4020 uint res = dst - src;\r
4021\r
4022 FLAG_N = NFLAG_32(res);\r
4023 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4024 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4025 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4026}\r
4027\r
4028\r
4029M68KMAKE_OP(cmpa, 16, ., a)\r
4030{\r
4031 uint src = MAKE_INT_16(AY);\r
4032 uint dst = AX;\r
4033 uint res = dst - src;\r
4034\r
4035 FLAG_N = NFLAG_32(res);\r
4036 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4037 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4038 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4039}\r
4040\r
4041\r
4042M68KMAKE_OP(cmpa, 16, ., .)\r
4043{\r
4044 uint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);\r
4045 uint dst = AX;\r
4046 uint res = dst - src;\r
4047\r
4048 FLAG_N = NFLAG_32(res);\r
4049 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4050 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4051 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4052}\r
4053\r
4054\r
4055M68KMAKE_OP(cmpa, 32, ., d)\r
4056{\r
4057 uint src = DY;\r
4058 uint dst = AX;\r
4059 uint res = dst - src;\r
4060\r
4061 FLAG_N = NFLAG_32(res);\r
4062 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4063 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4064 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4065}\r
4066\r
4067\r
4068M68KMAKE_OP(cmpa, 32, ., a)\r
4069{\r
4070 uint src = AY;\r
4071 uint dst = AX;\r
4072 uint res = dst - src;\r
4073\r
4074 FLAG_N = NFLAG_32(res);\r
4075 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4076 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4077 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4078}\r
4079\r
4080\r
4081M68KMAKE_OP(cmpa, 32, ., .)\r
4082{\r
4083 uint src = M68KMAKE_GET_OPER_AY_32;\r
4084 uint dst = AX;\r
4085 uint res = dst - src;\r
4086\r
4087 FLAG_N = NFLAG_32(res);\r
4088 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4089 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4090 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4091}\r
4092\r
4093\r
4094M68KMAKE_OP(cmpi, 8, ., d)\r
4095{\r
4096 uint src = OPER_I_8();\r
4097 uint dst = MASK_OUT_ABOVE_8(DY);\r
4098 uint res = dst - src;\r
4099\r
4100 FLAG_N = NFLAG_8(res);\r
4101 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
4102 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
4103 FLAG_C = CFLAG_8(res);\r
4104}\r
4105\r
4106\r
4107M68KMAKE_OP(cmpi, 8, ., .)\r
4108{\r
4109 uint src = OPER_I_8();\r
4110 uint dst = M68KMAKE_GET_OPER_AY_8;\r
4111 uint res = dst - src;\r
4112\r
4113 FLAG_N = NFLAG_8(res);\r
4114 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
4115 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
4116 FLAG_C = CFLAG_8(res);\r
4117}\r
4118\r
4119\r
4120M68KMAKE_OP(cmpi, 8, ., pcdi)\r
4121{\r
4122 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4123 {\r
4124 uint src = OPER_I_8();\r
4125 uint dst = OPER_PCDI_8();\r
4126 uint res = dst - src;\r
4127\r
4128 FLAG_N = NFLAG_8(res);\r
4129 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
4130 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
4131 FLAG_C = CFLAG_8(res);\r
4132 return;\r
4133 }\r
4134 m68ki_exception_illegal();\r
4135}\r
4136\r
4137\r
4138M68KMAKE_OP(cmpi, 8, ., pcix)\r
4139{\r
4140 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4141 {\r
4142 uint src = OPER_I_8();\r
4143 uint dst = OPER_PCIX_8();\r
4144 uint res = dst - src;\r
4145\r
4146 FLAG_N = NFLAG_8(res);\r
4147 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
4148 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
4149 FLAG_C = CFLAG_8(res);\r
4150 return;\r
4151 }\r
4152 m68ki_exception_illegal();\r
4153}\r
4154\r
4155\r
4156M68KMAKE_OP(cmpi, 16, ., d)\r
4157{\r
4158 uint src = OPER_I_16();\r
4159 uint dst = MASK_OUT_ABOVE_16(DY);\r
4160 uint res = dst - src;\r
4161\r
4162 FLAG_N = NFLAG_16(res);\r
4163 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
4164 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
4165 FLAG_C = CFLAG_16(res);\r
4166}\r
4167\r
4168\r
4169M68KMAKE_OP(cmpi, 16, ., .)\r
4170{\r
4171 uint src = OPER_I_16();\r
4172 uint dst = M68KMAKE_GET_OPER_AY_16;\r
4173 uint res = dst - src;\r
4174\r
4175 FLAG_N = NFLAG_16(res);\r
4176 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
4177 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
4178 FLAG_C = CFLAG_16(res);\r
4179}\r
4180\r
4181\r
4182M68KMAKE_OP(cmpi, 16, ., pcdi)\r
4183{\r
4184 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4185 {\r
4186 uint src = OPER_I_16();\r
4187 uint dst = OPER_PCDI_16();\r
4188 uint res = dst - src;\r
4189\r
4190 FLAG_N = NFLAG_16(res);\r
4191 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
4192 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
4193 FLAG_C = CFLAG_16(res);\r
4194 return;\r
4195 }\r
4196 m68ki_exception_illegal();\r
4197}\r
4198\r
4199\r
4200M68KMAKE_OP(cmpi, 16, ., pcix)\r
4201{\r
4202 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4203 {\r
4204 uint src = OPER_I_16();\r
4205 uint dst = OPER_PCIX_16();\r
4206 uint res = dst - src;\r
4207\r
4208 FLAG_N = NFLAG_16(res);\r
4209 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
4210 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
4211 FLAG_C = CFLAG_16(res);\r
4212 return;\r
4213 }\r
4214 m68ki_exception_illegal();\r
4215}\r
4216\r
4217\r
4218M68KMAKE_OP(cmpi, 32, ., d)\r
4219{\r
4220 uint src = OPER_I_32();\r
4221 uint dst = DY;\r
4222 uint res = dst - src;\r
4223\r
4224 m68ki_cmpild_callback(src, REG_IR & 7); /* auto-disable (see m68kcpu.h) */\r
4225\r
4226 FLAG_N = NFLAG_32(res);\r
4227 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4228 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4229 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4230}\r
4231\r
4232\r
4233M68KMAKE_OP(cmpi, 32, ., .)\r
4234{\r
4235 uint src = OPER_I_32();\r
4236 uint dst = M68KMAKE_GET_OPER_AY_32;\r
4237 uint res = dst - src;\r
4238\r
4239 FLAG_N = NFLAG_32(res);\r
4240 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4241 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4242 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4243}\r
4244\r
4245\r
4246M68KMAKE_OP(cmpi, 32, ., pcdi)\r
4247{\r
4248 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4249 {\r
4250 uint src = OPER_I_32();\r
4251 uint dst = OPER_PCDI_32();\r
4252 uint res = dst - src;\r
4253\r
4254 FLAG_N = NFLAG_32(res);\r
4255 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4256 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4257 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4258 return;\r
4259 }\r
4260 m68ki_exception_illegal();\r
4261}\r
4262\r
4263\r
4264M68KMAKE_OP(cmpi, 32, ., pcix)\r
4265{\r
4266 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4267 {\r
4268 uint src = OPER_I_32();\r
4269 uint dst = OPER_PCIX_32();\r
4270 uint res = dst - src;\r
4271\r
4272 FLAG_N = NFLAG_32(res);\r
4273 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4274 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4275 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4276 return;\r
4277 }\r
4278 m68ki_exception_illegal();\r
4279}\r
4280\r
4281\r
4282M68KMAKE_OP(cmpm, 8, ., ax7)\r
4283{\r
4284 uint src = OPER_AY_PI_8();\r
4285 uint dst = OPER_A7_PI_8();\r
4286 uint res = dst - src;\r
4287\r
4288 FLAG_N = NFLAG_8(res);\r
4289 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
4290 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
4291 FLAG_C = CFLAG_8(res);\r
4292}\r
4293\r
4294\r
4295M68KMAKE_OP(cmpm, 8, ., ay7)\r
4296{\r
4297 uint src = OPER_A7_PI_8();\r
4298 uint dst = OPER_AX_PI_8();\r
4299 uint res = dst - src;\r
4300\r
4301 FLAG_N = NFLAG_8(res);\r
4302 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
4303 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
4304 FLAG_C = CFLAG_8(res);\r
4305}\r
4306\r
4307\r
4308M68KMAKE_OP(cmpm, 8, ., axy7)\r
4309{\r
4310 uint src = OPER_A7_PI_8();\r
4311 uint dst = OPER_A7_PI_8();\r
4312 uint res = dst - src;\r
4313\r
4314 FLAG_N = NFLAG_8(res);\r
4315 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
4316 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
4317 FLAG_C = CFLAG_8(res);\r
4318}\r
4319\r
4320\r
4321M68KMAKE_OP(cmpm, 8, ., .)\r
4322{\r
4323 uint src = OPER_AY_PI_8();\r
4324 uint dst = OPER_AX_PI_8();\r
4325 uint res = dst - src;\r
4326\r
4327 FLAG_N = NFLAG_8(res);\r
4328 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
4329 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
4330 FLAG_C = CFLAG_8(res);\r
4331}\r
4332\r
4333\r
4334M68KMAKE_OP(cmpm, 16, ., .)\r
4335{\r
4336 uint src = OPER_AY_PI_16();\r
4337 uint dst = OPER_AX_PI_16();\r
4338 uint res = dst - src;\r
4339\r
4340 FLAG_N = NFLAG_16(res);\r
4341 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
4342 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
4343 FLAG_C = CFLAG_16(res);\r
4344}\r
4345\r
4346\r
4347M68KMAKE_OP(cmpm, 32, ., .)\r
4348{\r
4349 uint src = OPER_AY_PI_32();\r
4350 uint dst = OPER_AX_PI_32();\r
4351 uint res = dst - src;\r
4352\r
4353 FLAG_N = NFLAG_32(res);\r
4354 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
4355 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
4356 FLAG_C = CFLAG_SUB_32(src, dst, res);\r
4357}\r
4358\r
4359\r
4360M68KMAKE_OP(cpbcc, 32, ., .)\r
4361{\r
4362 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4363 {\r
4364 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",\r
4365 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,\r
4366 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));\r
4367 return;\r
4368 }\r
4369 m68ki_exception_1111();\r
4370}\r
4371\r
4372\r
4373M68KMAKE_OP(cpdbcc, 32, ., .)\r
4374{\r
4375 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4376 {\r
4377 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",\r
4378 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,\r
4379 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));\r
4380 return;\r
4381 }\r
4382 m68ki_exception_1111();\r
4383}\r
4384\r
4385\r
4386M68KMAKE_OP(cpgen, 32, ., .)\r
4387{\r
4388 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4389 {\r
4390 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",\r
4391 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,\r
4392 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));\r
4393 return;\r
4394 }\r
4395 m68ki_exception_1111();\r
4396}\r
4397\r
4398\r
4399M68KMAKE_OP(cpscc, 32, ., .)\r
4400{\r
4401 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4402 {\r
4403 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",\r
4404 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,\r
4405 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));\r
4406 return;\r
4407 }\r
4408 m68ki_exception_1111();\r
4409}\r
4410\r
4411\r
4412M68KMAKE_OP(cptrapcc, 32, ., .)\r
4413{\r
4414 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4415 {\r
4416 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",\r
4417 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,\r
4418 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));\r
4419 return;\r
4420 }\r
4421 m68ki_exception_1111();\r
4422}\r
4423\r
4424\r
4425M68KMAKE_OP(dbt, 16, ., .)\r
4426{\r
4427 REG_PC += 2;\r
4428}\r
4429\r
4430\r
4431M68KMAKE_OP(dbf, 16, ., .)\r
4432{\r
4433 uint* r_dst = &DY;\r
4434 uint res = MASK_OUT_ABOVE_16(*r_dst - 1);\r
4435\r
4436 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
4437 if(res != 0xffff)\r
4438 {\r
4439 uint offset = OPER_I_16();\r
4440 REG_PC -= 2;\r
4441 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
4442 m68ki_branch_16(offset);\r
4443 USE_CYCLES(CYC_DBCC_F_NOEXP);\r
4444 return;\r
4445 }\r
4446 REG_PC += 2;\r
4447 USE_CYCLES(CYC_DBCC_F_EXP);\r
4448}\r
4449\r
4450\r
4451M68KMAKE_OP(dbcc, 16, ., .)\r
4452{\r
4453 if(M68KMAKE_NOT_CC)\r
4454 {\r
4455 uint* r_dst = &DY;\r
4456 uint res = MASK_OUT_ABOVE_16(*r_dst - 1);\r
4457\r
4458 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
4459 if(res != 0xffff)\r
4460 {\r
4461 uint offset = OPER_I_16();\r
4462 REG_PC -= 2;\r
4463 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
4464 m68ki_branch_16(offset);\r
4465 USE_CYCLES(CYC_DBCC_F_NOEXP);\r
4466 return;\r
4467 }\r
4468 REG_PC += 2;\r
4469 USE_CYCLES(CYC_DBCC_F_EXP);\r
4470 return;\r
4471 }\r
4472 REG_PC += 2;\r
4473}\r
4474\r
4475\r
4476M68KMAKE_OP(divs, 16, ., d)\r
4477{\r
4478 uint* r_dst = &DX;\r
4479 sint src = MAKE_INT_16(DY);\r
4480 sint quotient;\r
4481 sint remainder;\r
4482\r
4483 if(src != 0)\r
4484 {\r
4485 if((uint32)*r_dst == 0x80000000 && src == -1)\r
4486 {\r
4487 FLAG_Z = 0;\r
4488 FLAG_N = NFLAG_CLEAR;\r
4489 FLAG_V = VFLAG_CLEAR;\r
4490 FLAG_C = CFLAG_CLEAR;\r
4491 *r_dst = 0;\r
4492 return;\r
4493 }\r
4494\r
4495 quotient = MAKE_INT_32(*r_dst) / src;\r
4496 remainder = MAKE_INT_32(*r_dst) % src;\r
4497\r
4498 if(quotient == MAKE_INT_16(quotient))\r
4499 {\r
4500 FLAG_Z = quotient;\r
4501 FLAG_N = NFLAG_16(quotient);\r
4502 FLAG_V = VFLAG_CLEAR;\r
4503 FLAG_C = CFLAG_CLEAR;\r
4504 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));\r
4505 return;\r
4506 }\r
4507 FLAG_V = VFLAG_SET;\r
4508 return;\r
4509 }\r
4510 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);\r
4511}\r
4512\r
4513\r
4514M68KMAKE_OP(divs, 16, ., .)\r
4515{\r
4516 uint* r_dst = &DX;\r
4517 sint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);\r
4518 sint quotient;\r
4519 sint remainder;\r
4520\r
4521 if(src != 0)\r
4522 {\r
4523 if((uint32)*r_dst == 0x80000000 && src == -1)\r
4524 {\r
4525 FLAG_Z = 0;\r
4526 FLAG_N = NFLAG_CLEAR;\r
4527 FLAG_V = VFLAG_CLEAR;\r
4528 FLAG_C = CFLAG_CLEAR;\r
4529 *r_dst = 0;\r
4530 return;\r
4531 }\r
4532\r
4533 quotient = MAKE_INT_32(*r_dst) / src;\r
4534 remainder = MAKE_INT_32(*r_dst) % src;\r
4535\r
4536 if(quotient == MAKE_INT_16(quotient))\r
4537 {\r
4538 FLAG_Z = quotient;\r
4539 FLAG_N = NFLAG_16(quotient);\r
4540 FLAG_V = VFLAG_CLEAR;\r
4541 FLAG_C = CFLAG_CLEAR;\r
4542 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));\r
4543 return;\r
4544 }\r
4545 FLAG_V = VFLAG_SET;\r
4546 return;\r
4547 }\r
4548 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);\r
4549}\r
4550\r
4551\r
4552M68KMAKE_OP(divu, 16, ., d)\r
4553{\r
4554 uint* r_dst = &DX;\r
4555 uint src = MASK_OUT_ABOVE_16(DY);\r
4556\r
4557 if(src != 0)\r
4558 {\r
4559 uint quotient = *r_dst / src;\r
4560 uint remainder = *r_dst % src;\r
4561\r
4562 if(quotient < 0x10000)\r
4563 {\r
4564 FLAG_Z = quotient;\r
4565 FLAG_N = NFLAG_16(quotient);\r
4566 FLAG_V = VFLAG_CLEAR;\r
4567 FLAG_C = CFLAG_CLEAR;\r
4568 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));\r
4569 return;\r
4570 }\r
4571 FLAG_V = VFLAG_SET;\r
4572 return;\r
4573 }\r
4574 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);\r
4575}\r
4576\r
4577\r
4578M68KMAKE_OP(divu, 16, ., .)\r
4579{\r
4580 uint* r_dst = &DX;\r
4581 uint src = M68KMAKE_GET_OPER_AY_16;\r
4582\r
4583 if(src != 0)\r
4584 {\r
4585 uint quotient = *r_dst / src;\r
4586 uint remainder = *r_dst % src;\r
4587\r
4588 if(quotient < 0x10000)\r
4589 {\r
4590 FLAG_Z = quotient;\r
4591 FLAG_N = NFLAG_16(quotient);\r
4592 FLAG_V = VFLAG_CLEAR;\r
4593 FLAG_C = CFLAG_CLEAR;\r
4594 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));\r
4595 return;\r
4596 }\r
4597 FLAG_V = VFLAG_SET;\r
4598 return;\r
4599 }\r
4600 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);\r
4601}\r
4602\r
4603\r
4604M68KMAKE_OP(divl, 32, ., d)\r
4605{\r
4606#if M68K_USE_64_BIT\r
4607\r
4608 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4609 {\r
4610 uint word2 = OPER_I_16();\r
4611 uint64 divisor = DY;\r
4612 uint64 dividend = 0;\r
4613 uint64 quotient = 0;\r
4614 uint64 remainder = 0;\r
4615\r
4616 if(divisor != 0)\r
4617 {\r
4618 if(BIT_A(word2)) /* 64 bit */\r
4619 {\r
4620 dividend = REG_D[word2 & 7];\r
4621 dividend <<= 32;\r
4622 dividend |= REG_D[(word2 >> 12) & 7];\r
4623\r
4624 if(BIT_B(word2)) /* signed */\r
4625 {\r
4626 quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor));\r
4627 remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));\r
4628 if((sint64)quotient != (sint64)((sint32)quotient))\r
4629 {\r
4630 FLAG_V = VFLAG_SET;\r
4631 return;\r
4632 }\r
4633 }\r
4634 else /* unsigned */\r
4635 {\r
4636 quotient = dividend / divisor;\r
4637 if(quotient > 0xffffffff)\r
4638 {\r
4639 FLAG_V = VFLAG_SET;\r
4640 return;\r
4641 }\r
4642 remainder = dividend % divisor;\r
4643 }\r
4644 }\r
4645 else /* 32 bit */\r
4646 {\r
4647 dividend = REG_D[(word2 >> 12) & 7];\r
4648 if(BIT_B(word2)) /* signed */\r
4649 {\r
4650 quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));\r
4651 remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));\r
4652 }\r
4653 else /* unsigned */\r
4654 {\r
4655 quotient = dividend / divisor;\r
4656 remainder = dividend % divisor;\r
4657 }\r
4658 }\r
4659\r
4660 REG_D[word2 & 7] = remainder;\r
4661 REG_D[(word2 >> 12) & 7] = quotient;\r
4662\r
4663 FLAG_N = NFLAG_32(quotient);\r
4664 FLAG_Z = quotient;\r
4665 FLAG_V = VFLAG_CLEAR;\r
4666 FLAG_C = CFLAG_CLEAR;\r
4667 return;\r
4668 }\r
4669 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);\r
4670 return;\r
4671 }\r
4672 m68ki_exception_illegal();\r
4673\r
4674#else\r
4675\r
4676 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4677 {\r
4678 uint word2 = OPER_I_16();\r
4679 uint divisor = DY;\r
4680 uint dividend_hi = REG_D[word2 & 7];\r
4681 uint dividend_lo = REG_D[(word2 >> 12) & 7];\r
4682 uint quotient = 0;\r
4683 uint remainder = 0;\r
4684 uint dividend_neg = 0;\r
4685 uint divisor_neg = 0;\r
4686 sint i;\r
4687 uint overflow;\r
4688\r
4689 if(divisor != 0)\r
4690 {\r
4691 /* quad / long : long quotient, long remainder */\r
4692 if(BIT_A(word2))\r
4693 {\r
4694 if(BIT_B(word2)) /* signed */\r
4695 {\r
4696 /* special case in signed divide */\r
4697 if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)\r
4698 {\r
4699 REG_D[word2 & 7] = 0;\r
4700 REG_D[(word2 >> 12) & 7] = 0x80000000;\r
4701\r
4702 FLAG_N = NFLAG_SET;\r
4703 FLAG_Z = ZFLAG_CLEAR;\r
4704 FLAG_V = VFLAG_CLEAR;\r
4705 FLAG_C = CFLAG_CLEAR;\r
4706 return;\r
4707 }\r
4708 if(GET_MSB_32(dividend_hi))\r
4709 {\r
4710 dividend_neg = 1;\r
4711 dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));\r
4712 dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);\r
4713 }\r
4714 if(GET_MSB_32(divisor))\r
4715 {\r
4716 divisor_neg = 1;\r
4717 divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);\r
4718\r
4719 }\r
4720 }\r
4721\r
4722 /* if the upper long is greater than the divisor, we're overflowing. */\r
4723 if(dividend_hi >= divisor)\r
4724 {\r
4725 FLAG_V = VFLAG_SET;\r
4726 return;\r
4727 }\r
4728\r
4729 for(i = 31; i >= 0; i--)\r
4730 {\r
4731 quotient <<= 1;\r
4732 remainder = (remainder << 1) + ((dividend_hi >> i) & 1);\r
4733 if(remainder >= divisor)\r
4734 {\r
4735 remainder -= divisor;\r
4736 quotient++;\r
4737 }\r
4738 }\r
4739 for(i = 31; i >= 0; i--)\r
4740 {\r
4741 quotient <<= 1;\r
4742 overflow = GET_MSB_32(remainder);\r
4743 remainder = (remainder << 1) + ((dividend_lo >> i) & 1);\r
4744 if(remainder >= divisor || overflow)\r
4745 {\r
4746 remainder -= divisor;\r
4747 quotient++;\r
4748 }\r
4749 }\r
4750\r
4751 if(BIT_B(word2)) /* signed */\r
4752 {\r
4753 if(quotient > 0x7fffffff)\r
4754 {\r
4755 FLAG_V = VFLAG_SET;\r
4756 return;\r
4757 }\r
4758 if(dividend_neg)\r
4759 {\r
4760 remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);\r
4761 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);\r
4762 }\r
4763 if(divisor_neg)\r
4764 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);\r
4765 }\r
4766\r
4767 REG_D[word2 & 7] = remainder;\r
4768 REG_D[(word2 >> 12) & 7] = quotient;\r
4769\r
4770 FLAG_N = NFLAG_32(quotient);\r
4771 FLAG_Z = quotient;\r
4772 FLAG_V = VFLAG_CLEAR;\r
4773 FLAG_C = CFLAG_CLEAR;\r
4774 return;\r
4775 }\r
4776\r
4777 /* long / long: long quotient, maybe long remainder */\r
4778 if(BIT_B(word2)) /* signed */\r
4779 {\r
4780 /* Special case in divide */\r
4781 if(dividend_lo == 0x80000000 && divisor == 0xffffffff)\r
4782 {\r
4783 FLAG_N = NFLAG_SET;\r
4784 FLAG_Z = ZFLAG_CLEAR;\r
4785 FLAG_V = VFLAG_CLEAR;\r
4786 FLAG_C = CFLAG_CLEAR;\r
4787 REG_D[(word2 >> 12) & 7] = 0x80000000;\r
4788 REG_D[word2 & 7] = 0;\r
4789 return;\r
4790 }\r
4791 REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);\r
4792 quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);\r
4793 }\r
4794 else\r
4795 {\r
4796 REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);\r
4797 quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);\r
4798 }\r
4799\r
4800 FLAG_N = NFLAG_32(quotient);\r
4801 FLAG_Z = quotient;\r
4802 FLAG_V = VFLAG_CLEAR;\r
4803 FLAG_C = CFLAG_CLEAR;\r
4804 return;\r
4805 }\r
4806 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);\r
4807 return;\r
4808 }\r
4809 m68ki_exception_illegal();\r
4810\r
4811#endif\r
4812}\r
4813\r
4814\r
4815M68KMAKE_OP(divl, 32, ., .)\r
4816{\r
4817#if M68K_USE_64_BIT\r
4818\r
4819 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4820 {\r
4821 uint word2 = OPER_I_16();\r
4822 uint64 divisor = M68KMAKE_GET_OPER_AY_32;\r
4823 uint64 dividend = 0;\r
4824 uint64 quotient = 0;\r
4825 uint64 remainder = 0;\r
4826\r
4827 if(divisor != 0)\r
4828 {\r
4829 if(BIT_A(word2)) /* 64 bit */\r
4830 {\r
4831 dividend = REG_D[word2 & 7];\r
4832 dividend <<= 32;\r
4833 dividend |= REG_D[(word2 >> 12) & 7];\r
4834\r
4835 if(BIT_B(word2)) /* signed */\r
4836 {\r
4837 quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor));\r
4838 remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));\r
4839 if((sint64)quotient != (sint64)((sint32)quotient))\r
4840 {\r
4841 FLAG_V = VFLAG_SET;\r
4842 return;\r
4843 }\r
4844 }\r
4845 else /* unsigned */\r
4846 {\r
4847 quotient = dividend / divisor;\r
4848 if(quotient > 0xffffffff)\r
4849 {\r
4850 FLAG_V = VFLAG_SET;\r
4851 return;\r
4852 }\r
4853 remainder = dividend % divisor;\r
4854 }\r
4855 }\r
4856 else /* 32 bit */\r
4857 {\r
4858 dividend = REG_D[(word2 >> 12) & 7];\r
4859 if(BIT_B(word2)) /* signed */\r
4860 {\r
4861 quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));\r
4862 remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));\r
4863 }\r
4864 else /* unsigned */\r
4865 {\r
4866 quotient = dividend / divisor;\r
4867 remainder = dividend % divisor;\r
4868 }\r
4869 }\r
4870\r
4871 REG_D[word2 & 7] = remainder;\r
4872 REG_D[(word2 >> 12) & 7] = quotient;\r
4873\r
4874 FLAG_N = NFLAG_32(quotient);\r
4875 FLAG_Z = quotient;\r
4876 FLAG_V = VFLAG_CLEAR;\r
4877 FLAG_C = CFLAG_CLEAR;\r
4878 return;\r
4879 }\r
4880 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);\r
4881 return;\r
4882 }\r
4883 m68ki_exception_illegal();\r
4884\r
4885#else\r
4886\r
4887 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
4888 {\r
4889 uint word2 = OPER_I_16();\r
4890 uint divisor = M68KMAKE_GET_OPER_AY_32;\r
4891 uint dividend_hi = REG_D[word2 & 7];\r
4892 uint dividend_lo = REG_D[(word2 >> 12) & 7];\r
4893 uint quotient = 0;\r
4894 uint remainder = 0;\r
4895 uint dividend_neg = 0;\r
4896 uint divisor_neg = 0;\r
4897 sint i;\r
4898 uint overflow;\r
4899\r
4900 if(divisor != 0)\r
4901 {\r
4902 /* quad / long : long quotient, long remainder */\r
4903 if(BIT_A(word2))\r
4904 {\r
4905 if(BIT_B(word2)) /* signed */\r
4906 {\r
4907 /* special case in signed divide */\r
4908 if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)\r
4909 {\r
4910 REG_D[word2 & 7] = 0;\r
4911 REG_D[(word2 >> 12) & 7] = 0x80000000;\r
4912\r
4913 FLAG_N = NFLAG_SET;\r
4914 FLAG_Z = ZFLAG_CLEAR;\r
4915 FLAG_V = VFLAG_CLEAR;\r
4916 FLAG_C = CFLAG_CLEAR;\r
4917 return;\r
4918 }\r
4919 if(GET_MSB_32(dividend_hi))\r
4920 {\r
4921 dividend_neg = 1;\r
4922 dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));\r
4923 dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);\r
4924 }\r
4925 if(GET_MSB_32(divisor))\r
4926 {\r
4927 divisor_neg = 1;\r
4928 divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);\r
4929\r
4930 }\r
4931 }\r
4932\r
4933 /* if the upper long is greater than the divisor, we're overflowing. */\r
4934 if(dividend_hi >= divisor)\r
4935 {\r
4936 FLAG_V = VFLAG_SET;\r
4937 return;\r
4938 }\r
4939\r
4940 for(i = 31; i >= 0; i--)\r
4941 {\r
4942 quotient <<= 1;\r
4943 remainder = (remainder << 1) + ((dividend_hi >> i) & 1);\r
4944 if(remainder >= divisor)\r
4945 {\r
4946 remainder -= divisor;\r
4947 quotient++;\r
4948 }\r
4949 }\r
4950 for(i = 31; i >= 0; i--)\r
4951 {\r
4952 quotient <<= 1;\r
4953 overflow = GET_MSB_32(remainder);\r
4954 remainder = (remainder << 1) + ((dividend_lo >> i) & 1);\r
4955 if(remainder >= divisor || overflow)\r
4956 {\r
4957 remainder -= divisor;\r
4958 quotient++;\r
4959 }\r
4960 }\r
4961\r
4962 if(BIT_B(word2)) /* signed */\r
4963 {\r
4964 if(quotient > 0x7fffffff)\r
4965 {\r
4966 FLAG_V = VFLAG_SET;\r
4967 return;\r
4968 }\r
4969 if(dividend_neg)\r
4970 {\r
4971 remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);\r
4972 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);\r
4973 }\r
4974 if(divisor_neg)\r
4975 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);\r
4976 }\r
4977\r
4978 REG_D[word2 & 7] = remainder;\r
4979 REG_D[(word2 >> 12) & 7] = quotient;\r
4980\r
4981 FLAG_N = NFLAG_32(quotient);\r
4982 FLAG_Z = quotient;\r
4983 FLAG_V = VFLAG_CLEAR;\r
4984 FLAG_C = CFLAG_CLEAR;\r
4985 return;\r
4986 }\r
4987\r
4988 /* long / long: long quotient, maybe long remainder */\r
4989 if(BIT_B(word2)) /* signed */\r
4990 {\r
4991 /* Special case in divide */\r
4992 if(dividend_lo == 0x80000000 && divisor == 0xffffffff)\r
4993 {\r
4994 FLAG_N = NFLAG_SET;\r
4995 FLAG_Z = ZFLAG_CLEAR;\r
4996 FLAG_V = VFLAG_CLEAR;\r
4997 FLAG_C = CFLAG_CLEAR;\r
4998 REG_D[(word2 >> 12) & 7] = 0x80000000;\r
4999 REG_D[word2 & 7] = 0;\r
5000 return;\r
5001 }\r
5002 REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);\r
5003 quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);\r
5004 }\r
5005 else\r
5006 {\r
5007 REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);\r
5008 quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);\r
5009 }\r
5010\r
5011 FLAG_N = NFLAG_32(quotient);\r
5012 FLAG_Z = quotient;\r
5013 FLAG_V = VFLAG_CLEAR;\r
5014 FLAG_C = CFLAG_CLEAR;\r
5015 return;\r
5016 }\r
5017 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);\r
5018 return;\r
5019 }\r
5020 m68ki_exception_illegal();\r
5021\r
5022#endif\r
5023}\r
5024\r
5025\r
5026M68KMAKE_OP(eor, 8, ., d)\r
5027{\r
5028 uint res = MASK_OUT_ABOVE_8(DY ^= MASK_OUT_ABOVE_8(DX));\r
5029\r
5030 FLAG_N = NFLAG_8(res);\r
5031 FLAG_Z = res;\r
5032 FLAG_C = CFLAG_CLEAR;\r
5033 FLAG_V = VFLAG_CLEAR;\r
5034}\r
5035\r
5036\r
5037M68KMAKE_OP(eor, 8, ., .)\r
5038{\r
5039 uint ea = M68KMAKE_GET_EA_AY_8;\r
5040 uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));\r
5041\r
5042 m68ki_write_8(ea, res);\r
5043\r
5044 FLAG_N = NFLAG_8(res);\r
5045 FLAG_Z = res;\r
5046 FLAG_C = CFLAG_CLEAR;\r
5047 FLAG_V = VFLAG_CLEAR;\r
5048}\r
5049\r
5050\r
5051M68KMAKE_OP(eor, 16, ., d)\r
5052{\r
5053 uint res = MASK_OUT_ABOVE_16(DY ^= MASK_OUT_ABOVE_16(DX));\r
5054\r
5055 FLAG_N = NFLAG_16(res);\r
5056 FLAG_Z = res;\r
5057 FLAG_C = CFLAG_CLEAR;\r
5058 FLAG_V = VFLAG_CLEAR;\r
5059}\r
5060\r
5061\r
5062M68KMAKE_OP(eor, 16, ., .)\r
5063{\r
5064 uint ea = M68KMAKE_GET_EA_AY_16;\r
5065 uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea));\r
5066\r
5067 m68ki_write_16(ea, res);\r
5068\r
5069 FLAG_N = NFLAG_16(res);\r
5070 FLAG_Z = res;\r
5071 FLAG_C = CFLAG_CLEAR;\r
5072 FLAG_V = VFLAG_CLEAR;\r
5073}\r
5074\r
5075\r
5076M68KMAKE_OP(eor, 32, ., d)\r
5077{\r
5078 uint res = DY ^= DX;\r
5079\r
5080 FLAG_N = NFLAG_32(res);\r
5081 FLAG_Z = res;\r
5082 FLAG_C = CFLAG_CLEAR;\r
5083 FLAG_V = VFLAG_CLEAR;\r
5084}\r
5085\r
5086\r
5087M68KMAKE_OP(eor, 32, ., .)\r
5088{\r
5089 uint ea = M68KMAKE_GET_EA_AY_32;\r
5090 uint res = DX ^ m68ki_read_32(ea);\r
5091\r
5092 m68ki_write_32(ea, res);\r
5093\r
5094 FLAG_N = NFLAG_32(res);\r
5095 FLAG_Z = res;\r
5096 FLAG_C = CFLAG_CLEAR;\r
5097 FLAG_V = VFLAG_CLEAR;\r
5098}\r
5099\r
5100\r
5101M68KMAKE_OP(eori, 8, ., d)\r
5102{\r
5103 uint res = MASK_OUT_ABOVE_8(DY ^= OPER_I_8());\r
5104\r
5105 FLAG_N = NFLAG_8(res);\r
5106 FLAG_Z = res;\r
5107 FLAG_C = CFLAG_CLEAR;\r
5108 FLAG_V = VFLAG_CLEAR;\r
5109}\r
5110\r
5111\r
5112M68KMAKE_OP(eori, 8, ., .)\r
5113{\r
5114 uint src = OPER_I_8();\r
5115 uint ea = M68KMAKE_GET_EA_AY_8;\r
5116 uint res = src ^ m68ki_read_8(ea);\r
5117\r
5118 m68ki_write_8(ea, res);\r
5119\r
5120 FLAG_N = NFLAG_8(res);\r
5121 FLAG_Z = res;\r
5122 FLAG_C = CFLAG_CLEAR;\r
5123 FLAG_V = VFLAG_CLEAR;\r
5124}\r
5125\r
5126\r
5127M68KMAKE_OP(eori, 16, ., d)\r
5128{\r
5129 uint res = MASK_OUT_ABOVE_16(DY ^= OPER_I_16());\r
5130\r
5131 FLAG_N = NFLAG_16(res);\r
5132 FLAG_Z = res;\r
5133 FLAG_C = CFLAG_CLEAR;\r
5134 FLAG_V = VFLAG_CLEAR;\r
5135}\r
5136\r
5137\r
5138M68KMAKE_OP(eori, 16, ., .)\r
5139{\r
5140 uint src = OPER_I_16();\r
5141 uint ea = M68KMAKE_GET_EA_AY_16;\r
5142 uint res = src ^ m68ki_read_16(ea);\r
5143\r
5144 m68ki_write_16(ea, res);\r
5145\r
5146 FLAG_N = NFLAG_16(res);\r
5147 FLAG_Z = res;\r
5148 FLAG_C = CFLAG_CLEAR;\r
5149 FLAG_V = VFLAG_CLEAR;\r
5150}\r
5151\r
5152\r
5153M68KMAKE_OP(eori, 32, ., d)\r
5154{\r
5155 uint res = DY ^= OPER_I_32();\r
5156\r
5157 FLAG_N = NFLAG_32(res);\r
5158 FLAG_Z = res;\r
5159 FLAG_C = CFLAG_CLEAR;\r
5160 FLAG_V = VFLAG_CLEAR;\r
5161}\r
5162\r
5163\r
5164M68KMAKE_OP(eori, 32, ., .)\r
5165{\r
5166 uint src = OPER_I_32();\r
5167 uint ea = M68KMAKE_GET_EA_AY_32;\r
5168 uint res = src ^ m68ki_read_32(ea);\r
5169\r
5170 m68ki_write_32(ea, res);\r
5171\r
5172 FLAG_N = NFLAG_32(res);\r
5173 FLAG_Z = res;\r
5174 FLAG_C = CFLAG_CLEAR;\r
5175 FLAG_V = VFLAG_CLEAR;\r
5176}\r
5177\r
5178\r
5179M68KMAKE_OP(eori, 16, toc, .)\r
5180{\r
5181 m68ki_set_ccr(m68ki_get_ccr() ^ OPER_I_16());\r
5182}\r
5183\r
5184\r
5185M68KMAKE_OP(eori, 16, tos, .)\r
5186{\r
5187 if(FLAG_S)\r
5188 {\r
5189 uint src = OPER_I_16();\r
5190 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
5191 m68ki_set_sr(m68ki_get_sr() ^ src);\r
5192 return;\r
5193 }\r
5194 m68ki_exception_privilege_violation();\r
5195}\r
5196\r
5197\r
5198M68KMAKE_OP(exg, 32, dd, .)\r
5199{\r
5200 uint* reg_a = &DX;\r
5201 uint* reg_b = &DY;\r
5202 uint tmp = *reg_a;\r
5203 *reg_a = *reg_b;\r
5204 *reg_b = tmp;\r
5205}\r
5206\r
5207\r
5208M68KMAKE_OP(exg, 32, aa, .)\r
5209{\r
5210 uint* reg_a = &AX;\r
5211 uint* reg_b = &AY;\r
5212 uint tmp = *reg_a;\r
5213 *reg_a = *reg_b;\r
5214 *reg_b = tmp;\r
5215}\r
5216\r
5217\r
5218M68KMAKE_OP(exg, 32, da, .)\r
5219{\r
5220 uint* reg_a = &DX;\r
5221 uint* reg_b = &AY;\r
5222 uint tmp = *reg_a;\r
5223 *reg_a = *reg_b;\r
5224 *reg_b = tmp;\r
5225}\r
5226\r
5227\r
5228M68KMAKE_OP(ext, 16, ., .)\r
5229{\r
5230 uint* r_dst = &DY;\r
5231\r
5232 *r_dst = MASK_OUT_BELOW_16(*r_dst) | MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xff00 : 0);\r
5233\r
5234 FLAG_N = NFLAG_16(*r_dst);\r
5235 FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);\r
5236 FLAG_V = VFLAG_CLEAR;\r
5237 FLAG_C = CFLAG_CLEAR;\r
5238}\r
5239\r
5240\r
5241M68KMAKE_OP(ext, 32, ., .)\r
5242{\r
5243 uint* r_dst = &DY;\r
5244\r
5245 *r_dst = MASK_OUT_ABOVE_16(*r_dst) | (GET_MSB_16(*r_dst) ? 0xffff0000 : 0);\r
5246\r
5247 FLAG_N = NFLAG_32(*r_dst);\r
5248 FLAG_Z = *r_dst;\r
5249 FLAG_V = VFLAG_CLEAR;\r
5250 FLAG_C = CFLAG_CLEAR;\r
5251}\r
5252\r
5253\r
5254M68KMAKE_OP(extb, 32, ., .)\r
5255{\r
5256 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
5257 {\r
5258 uint* r_dst = &DY;\r
5259\r
5260 *r_dst = MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xffffff00 : 0);\r
5261\r
5262 FLAG_N = NFLAG_32(*r_dst);\r
5263 FLAG_Z = *r_dst;\r
5264 FLAG_V = VFLAG_CLEAR;\r
5265 FLAG_C = CFLAG_CLEAR;\r
5266 return;\r
5267 }\r
5268 m68ki_exception_illegal();\r
5269}\r
5270\r
5271\r
5272M68KMAKE_OP(illegal, 0, ., .)\r
5273{\r
5274 m68ki_exception_illegal();\r
5275}\r
5276\r
5277M68KMAKE_OP(jmp, 32, ., .)\r
5278{\r
5279 m68ki_jump(M68KMAKE_GET_EA_AY_32);\r
5280 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
5281 if(REG_PC == REG_PPC)\r
5282 USE_ALL_CYCLES();\r
5283}\r
5284\r
5285\r
5286M68KMAKE_OP(jsr, 32, ., .)\r
5287{\r
5288 uint ea = M68KMAKE_GET_EA_AY_32;\r
5289 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
c6a4c892 5290 m68ki_push_32(REG_PC);\r
cc68a136 5291 m68ki_jump(ea);\r
5292}\r
5293\r
5294\r
5295M68KMAKE_OP(lea, 32, ., .)\r
5296{\r
5297 AX = M68KMAKE_GET_EA_AY_32;\r
5298}\r
5299\r
5300\r
5301M68KMAKE_OP(link, 16, ., a7)\r
5302{\r
5303 REG_A[7] -= 4;\r
5304 m68ki_write_32(REG_A[7], REG_A[7]);\r
5305 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));\r
5306}\r
5307\r
5308\r
5309M68KMAKE_OP(link, 16, ., .)\r
5310{\r
5311 uint* r_dst = &AY;\r
5312\r
5313 m68ki_push_32(*r_dst);\r
5314 *r_dst = REG_A[7];\r
5315 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));\r
5316}\r
5317\r
5318\r
5319M68KMAKE_OP(link, 32, ., a7)\r
5320{\r
5321 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
5322 {\r
5323 REG_A[7] -= 4;\r
5324 m68ki_write_32(REG_A[7], REG_A[7]);\r
5325 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32());\r
5326 return;\r
5327 }\r
5328 m68ki_exception_illegal();\r
5329}\r
5330\r
5331\r
5332M68KMAKE_OP(link, 32, ., .)\r
5333{\r
5334 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
5335 {\r
5336 uint* r_dst = &AY;\r
5337\r
5338 m68ki_push_32(*r_dst);\r
5339 *r_dst = REG_A[7];\r
5340 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32());\r
5341 return;\r
5342 }\r
5343 m68ki_exception_illegal();\r
5344}\r
5345\r
5346\r
5347M68KMAKE_OP(lsr, 8, s, .)\r
5348{\r
5349 uint* r_dst = &DY;\r
5350 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
5351 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
5352 uint res = src >> shift;\r
5353\r
5354 if(shift != 0)\r
5355 USE_CYCLES(shift<<CYC_SHIFT);\r
5356\r
5357 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
5358\r
5359 FLAG_N = NFLAG_CLEAR;\r
5360 FLAG_Z = res;\r
5361 FLAG_X = FLAG_C = src << (9-shift);\r
5362 FLAG_V = VFLAG_CLEAR;\r
5363}\r
5364\r
5365\r
5366M68KMAKE_OP(lsr, 16, s, .)\r
5367{\r
5368 uint* r_dst = &DY;\r
5369 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
5370 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
5371 uint res = src >> shift;\r
5372\r
5373 if(shift != 0)\r
5374 USE_CYCLES(shift<<CYC_SHIFT);\r
5375\r
5376 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
5377\r
5378 FLAG_N = NFLAG_CLEAR;\r
5379 FLAG_Z = res;\r
5380 FLAG_X = FLAG_C = src << (9-shift);\r
5381 FLAG_V = VFLAG_CLEAR;\r
5382}\r
5383\r
5384\r
5385M68KMAKE_OP(lsr, 32, s, .)\r
5386{\r
5387 uint* r_dst = &DY;\r
5388 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
5389 uint src = *r_dst;\r
5390 uint res = src >> shift;\r
5391\r
5392 if(shift != 0)\r
5393 USE_CYCLES(shift<<CYC_SHIFT);\r
5394\r
5395 *r_dst = res;\r
5396\r
5397 FLAG_N = NFLAG_CLEAR;\r
5398 FLAG_Z = res;\r
5399 FLAG_X = FLAG_C = src << (9-shift);\r
5400 FLAG_V = VFLAG_CLEAR;\r
5401}\r
5402\r
5403\r
5404M68KMAKE_OP(lsr, 8, r, .)\r
5405{\r
5406 uint* r_dst = &DY;\r
5407 uint shift = DX & 0x3f;\r
5408 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
5409 uint res = src >> shift;\r
5410\r
5411 if(shift != 0)\r
5412 {\r
5413 USE_CYCLES(shift<<CYC_SHIFT);\r
5414\r
5415 if(shift <= 8)\r
5416 {\r
5417 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
5418 FLAG_X = FLAG_C = src << (9-shift);\r
5419 FLAG_N = NFLAG_CLEAR;\r
5420 FLAG_Z = res;\r
5421 FLAG_V = VFLAG_CLEAR;\r
5422 return;\r
5423 }\r
5424\r
5425 *r_dst &= 0xffffff00;\r
5426 FLAG_X = XFLAG_CLEAR;\r
5427 FLAG_C = CFLAG_CLEAR;\r
5428 FLAG_N = NFLAG_CLEAR;\r
5429 FLAG_Z = ZFLAG_SET;\r
5430 FLAG_V = VFLAG_CLEAR;\r
5431 return;\r
5432 }\r
5433\r
5434 FLAG_C = CFLAG_CLEAR;\r
5435 FLAG_N = NFLAG_8(src);\r
5436 FLAG_Z = src;\r
5437 FLAG_V = VFLAG_CLEAR;\r
5438}\r
5439\r
5440\r
5441M68KMAKE_OP(lsr, 16, r, .)\r
5442{\r
5443 uint* r_dst = &DY;\r
5444 uint shift = DX & 0x3f;\r
5445 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
5446 uint res = src >> shift;\r
5447\r
5448 if(shift != 0)\r
5449 {\r
5450 USE_CYCLES(shift<<CYC_SHIFT);\r
5451\r
5452 if(shift <= 16)\r
5453 {\r
5454 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
5455 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;\r
5456 FLAG_N = NFLAG_CLEAR;\r
5457 FLAG_Z = res;\r
5458 FLAG_V = VFLAG_CLEAR;\r
5459 return;\r
5460 }\r
5461\r
5462 *r_dst &= 0xffff0000;\r
5463 FLAG_X = XFLAG_CLEAR;\r
5464 FLAG_C = CFLAG_CLEAR;\r
5465 FLAG_N = NFLAG_CLEAR;\r
5466 FLAG_Z = ZFLAG_SET;\r
5467 FLAG_V = VFLAG_CLEAR;\r
5468 return;\r
5469 }\r
5470\r
5471 FLAG_C = CFLAG_CLEAR;\r
5472 FLAG_N = NFLAG_16(src);\r
5473 FLAG_Z = src;\r
5474 FLAG_V = VFLAG_CLEAR;\r
5475}\r
5476\r
5477\r
5478M68KMAKE_OP(lsr, 32, r, .)\r
5479{\r
5480 uint* r_dst = &DY;\r
5481 uint shift = DX & 0x3f;\r
5482 uint src = *r_dst;\r
5483 uint res = src >> shift;\r
5484\r
5485 if(shift != 0)\r
5486 {\r
5487 USE_CYCLES(shift<<CYC_SHIFT);\r
5488\r
5489 if(shift < 32)\r
5490 {\r
5491 *r_dst = res;\r
5492 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;\r
5493 FLAG_N = NFLAG_CLEAR;\r
5494 FLAG_Z = res;\r
5495 FLAG_V = VFLAG_CLEAR;\r
5496 return;\r
5497 }\r
5498\r
5499 *r_dst = 0;\r
5500 FLAG_X = FLAG_C = (shift == 32 ? GET_MSB_32(src)>>23 : 0);\r
5501 FLAG_N = NFLAG_CLEAR;\r
5502 FLAG_Z = ZFLAG_SET;\r
5503 FLAG_V = VFLAG_CLEAR;\r
5504 return;\r
5505 }\r
5506\r
5507 FLAG_C = CFLAG_CLEAR;\r
5508 FLAG_N = NFLAG_32(src);\r
5509 FLAG_Z = src;\r
5510 FLAG_V = VFLAG_CLEAR;\r
5511}\r
5512\r
5513\r
5514M68KMAKE_OP(lsr, 16, ., .)\r
5515{\r
5516 uint ea = M68KMAKE_GET_EA_AY_16;\r
5517 uint src = m68ki_read_16(ea);\r
5518 uint res = src >> 1;\r
5519\r
5520 m68ki_write_16(ea, res);\r
5521\r
5522 FLAG_N = NFLAG_CLEAR;\r
5523 FLAG_Z = res;\r
5524 FLAG_C = FLAG_X = src << 8;\r
5525 FLAG_V = VFLAG_CLEAR;\r
5526}\r
5527\r
5528\r
5529M68KMAKE_OP(lsl, 8, s, .)\r
5530{\r
5531 uint* r_dst = &DY;\r
5532 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
5533 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
5534 uint res = MASK_OUT_ABOVE_8(src << shift);\r
5535\r
5536 if(shift != 0)\r
5537 USE_CYCLES(shift<<CYC_SHIFT);\r
5538\r
5539 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
5540\r
5541 FLAG_N = NFLAG_8(res);\r
5542 FLAG_Z = res;\r
5543 FLAG_X = FLAG_C = src << shift;\r
5544 FLAG_V = VFLAG_CLEAR;\r
5545}\r
5546\r
5547\r
5548M68KMAKE_OP(lsl, 16, s, .)\r
5549{\r
5550 uint* r_dst = &DY;\r
5551 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
5552 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
5553 uint res = MASK_OUT_ABOVE_16(src << shift);\r
5554\r
5555 if(shift != 0)\r
5556 USE_CYCLES(shift<<CYC_SHIFT);\r
5557\r
5558 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
5559\r
5560 FLAG_N = NFLAG_16(res);\r
5561 FLAG_Z = res;\r
5562 FLAG_X = FLAG_C = src >> (8-shift);\r
5563 FLAG_V = VFLAG_CLEAR;\r
5564}\r
5565\r
5566\r
5567M68KMAKE_OP(lsl, 32, s, .)\r
5568{\r
5569 uint* r_dst = &DY;\r
5570 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
5571 uint src = *r_dst;\r
5572 uint res = MASK_OUT_ABOVE_32(src << shift);\r
5573\r
5574 if(shift != 0)\r
5575 USE_CYCLES(shift<<CYC_SHIFT);\r
5576\r
5577 *r_dst = res;\r
5578\r
5579 FLAG_N = NFLAG_32(res);\r
5580 FLAG_Z = res;\r
5581 FLAG_X = FLAG_C = src >> (24-shift);\r
5582 FLAG_V = VFLAG_CLEAR;\r
5583}\r
5584\r
5585\r
5586M68KMAKE_OP(lsl, 8, r, .)\r
5587{\r
5588 uint* r_dst = &DY;\r
5589 uint shift = DX & 0x3f;\r
5590 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
5591 uint res = MASK_OUT_ABOVE_8(src << shift);\r
5592\r
5593 if(shift != 0)\r
5594 {\r
5595 USE_CYCLES(shift<<CYC_SHIFT);\r
5596\r
5597 if(shift <= 8)\r
5598 {\r
5599 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
5600 FLAG_X = FLAG_C = src << shift;\r
5601 FLAG_N = NFLAG_8(res);\r
5602 FLAG_Z = res;\r
5603 FLAG_V = VFLAG_CLEAR;\r
5604 return;\r
5605 }\r
5606\r
5607 *r_dst &= 0xffffff00;\r
5608 FLAG_X = XFLAG_CLEAR;\r
5609 FLAG_C = CFLAG_CLEAR;\r
5610 FLAG_N = NFLAG_CLEAR;\r
5611 FLAG_Z = ZFLAG_SET;\r
5612 FLAG_V = VFLAG_CLEAR;\r
5613 return;\r
5614 }\r
5615\r
5616 FLAG_C = CFLAG_CLEAR;\r
5617 FLAG_N = NFLAG_8(src);\r
5618 FLAG_Z = src;\r
5619 FLAG_V = VFLAG_CLEAR;\r
5620}\r
5621\r
5622\r
5623M68KMAKE_OP(lsl, 16, r, .)\r
5624{\r
5625 uint* r_dst = &DY;\r
5626 uint shift = DX & 0x3f;\r
5627 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
5628 uint res = MASK_OUT_ABOVE_16(src << shift);\r
5629\r
5630 if(shift != 0)\r
5631 {\r
5632 USE_CYCLES(shift<<CYC_SHIFT);\r
5633\r
5634 if(shift <= 16)\r
5635 {\r
5636 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
5637 FLAG_X = FLAG_C = (src << shift) >> 8;\r
5638 FLAG_N = NFLAG_16(res);\r
5639 FLAG_Z = res;\r
5640 FLAG_V = VFLAG_CLEAR;\r
5641 return;\r
5642 }\r
5643\r
5644 *r_dst &= 0xffff0000;\r
5645 FLAG_X = XFLAG_CLEAR;\r
5646 FLAG_C = CFLAG_CLEAR;\r
5647 FLAG_N = NFLAG_CLEAR;\r
5648 FLAG_Z = ZFLAG_SET;\r
5649 FLAG_V = VFLAG_CLEAR;\r
5650 return;\r
5651 }\r
5652\r
5653 FLAG_C = CFLAG_CLEAR;\r
5654 FLAG_N = NFLAG_16(src);\r
5655 FLAG_Z = src;\r
5656 FLAG_V = VFLAG_CLEAR;\r
5657}\r
5658\r
5659\r
5660M68KMAKE_OP(lsl, 32, r, .)\r
5661{\r
5662 uint* r_dst = &DY;\r
5663 uint shift = DX & 0x3f;\r
5664 uint src = *r_dst;\r
5665 uint res = MASK_OUT_ABOVE_32(src << shift);\r
5666\r
5667 if(shift != 0)\r
5668 {\r
5669 USE_CYCLES(shift<<CYC_SHIFT);\r
5670\r
5671 if(shift < 32)\r
5672 {\r
5673 *r_dst = res;\r
5674 FLAG_X = FLAG_C = (src >> (32 - shift)) << 8;\r
5675 FLAG_N = NFLAG_32(res);\r
5676 FLAG_Z = res;\r
5677 FLAG_V = VFLAG_CLEAR;\r
5678 return;\r
5679 }\r
5680\r
5681 *r_dst = 0;\r
5682 FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8;\r
5683 FLAG_N = NFLAG_CLEAR;\r
5684 FLAG_Z = ZFLAG_SET;\r
5685 FLAG_V = VFLAG_CLEAR;\r
5686 return;\r
5687 }\r
5688\r
5689 FLAG_C = CFLAG_CLEAR;\r
5690 FLAG_N = NFLAG_32(src);\r
5691 FLAG_Z = src;\r
5692 FLAG_V = VFLAG_CLEAR;\r
5693}\r
5694\r
5695\r
5696M68KMAKE_OP(lsl, 16, ., .)\r
5697{\r
5698 uint ea = M68KMAKE_GET_EA_AY_16;\r
5699 uint src = m68ki_read_16(ea);\r
5700 uint res = MASK_OUT_ABOVE_16(src << 1);\r
5701\r
5702 m68ki_write_16(ea, res);\r
5703\r
5704 FLAG_N = NFLAG_16(res);\r
5705 FLAG_Z = res;\r
5706 FLAG_X = FLAG_C = src >> 7;\r
5707 FLAG_V = VFLAG_CLEAR;\r
5708}\r
5709\r
5710\r
5711M68KMAKE_OP(move, 8, d, d)\r
5712{\r
5713 uint res = MASK_OUT_ABOVE_8(DY);\r
5714 uint* r_dst = &DX;\r
5715\r
5716 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
5717\r
5718 FLAG_N = NFLAG_8(res);\r
5719 FLAG_Z = res;\r
5720 FLAG_V = VFLAG_CLEAR;\r
5721 FLAG_C = CFLAG_CLEAR;\r
5722}\r
5723\r
5724\r
5725M68KMAKE_OP(move, 8, d, .)\r
5726{\r
5727 uint res = M68KMAKE_GET_OPER_AY_8;\r
5728 uint* r_dst = &DX;\r
5729\r
5730 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
5731\r
5732 FLAG_N = NFLAG_8(res);\r
5733 FLAG_Z = res;\r
5734 FLAG_V = VFLAG_CLEAR;\r
5735 FLAG_C = CFLAG_CLEAR;\r
5736}\r
5737\r
5738\r
5739M68KMAKE_OP(move, 8, ai, d)\r
5740{\r
5741 uint res = MASK_OUT_ABOVE_8(DY);\r
5742 uint ea = EA_AX_AI_8();\r
5743\r
5744 m68ki_write_8(ea, res);\r
5745\r
5746 FLAG_N = NFLAG_8(res);\r
5747 FLAG_Z = res;\r
5748 FLAG_V = VFLAG_CLEAR;\r
5749 FLAG_C = CFLAG_CLEAR;\r
5750}\r
5751\r
5752\r
5753M68KMAKE_OP(move, 8, ai, .)\r
5754{\r
5755 uint res = M68KMAKE_GET_OPER_AY_8;\r
5756 uint ea = EA_AX_AI_8();\r
5757\r
5758 m68ki_write_8(ea, res);\r
5759\r
5760 FLAG_N = NFLAG_8(res);\r
5761 FLAG_Z = res;\r
5762 FLAG_V = VFLAG_CLEAR;\r
5763 FLAG_C = CFLAG_CLEAR;\r
5764}\r
5765\r
5766\r
5767M68KMAKE_OP(move, 8, pi7, d)\r
5768{\r
5769 uint res = MASK_OUT_ABOVE_8(DY);\r
5770 uint ea = EA_A7_PI_8();\r
5771\r
5772 m68ki_write_8(ea, res);\r
5773\r
5774 FLAG_N = NFLAG_8(res);\r
5775 FLAG_Z = res;\r
5776 FLAG_V = VFLAG_CLEAR;\r
5777 FLAG_C = CFLAG_CLEAR;\r
5778}\r
5779\r
5780\r
5781M68KMAKE_OP(move, 8, pi, d)\r
5782{\r
5783 uint res = MASK_OUT_ABOVE_8(DY);\r
5784 uint ea = EA_AX_PI_8();\r
5785\r
5786 m68ki_write_8(ea, res);\r
5787\r
5788 FLAG_N = NFLAG_8(res);\r
5789 FLAG_Z = res;\r
5790 FLAG_V = VFLAG_CLEAR;\r
5791 FLAG_C = CFLAG_CLEAR;\r
5792}\r
5793\r
5794\r
5795M68KMAKE_OP(move, 8, pi7, .)\r
5796{\r
5797 uint res = M68KMAKE_GET_OPER_AY_8;\r
5798 uint ea = EA_A7_PI_8();\r
5799\r
5800 m68ki_write_8(ea, res);\r
5801\r
5802 FLAG_N = NFLAG_8(res);\r
5803 FLAG_Z = res;\r
5804 FLAG_V = VFLAG_CLEAR;\r
5805 FLAG_C = CFLAG_CLEAR;\r
5806}\r
5807\r
5808\r
5809M68KMAKE_OP(move, 8, pi, .)\r
5810{\r
5811 uint res = M68KMAKE_GET_OPER_AY_8;\r
5812 uint ea = EA_AX_PI_8();\r
5813\r
5814 m68ki_write_8(ea, res);\r
5815\r
5816 FLAG_N = NFLAG_8(res);\r
5817 FLAG_Z = res;\r
5818 FLAG_V = VFLAG_CLEAR;\r
5819 FLAG_C = CFLAG_CLEAR;\r
5820}\r
5821\r
5822\r
5823M68KMAKE_OP(move, 8, pd7, d)\r
5824{\r
5825 uint res = MASK_OUT_ABOVE_8(DY);\r
5826 uint ea = EA_A7_PD_8();\r
5827\r
5828 m68ki_write_8(ea, res);\r
5829\r
5830 FLAG_N = NFLAG_8(res);\r
5831 FLAG_Z = res;\r
5832 FLAG_V = VFLAG_CLEAR;\r
5833 FLAG_C = CFLAG_CLEAR;\r
5834}\r
5835\r
5836\r
5837M68KMAKE_OP(move, 8, pd, d)\r
5838{\r
5839 uint res = MASK_OUT_ABOVE_8(DY);\r
5840 uint ea = EA_AX_PD_8();\r
5841\r
5842 m68ki_write_8(ea, res);\r
5843\r
5844 FLAG_N = NFLAG_8(res);\r
5845 FLAG_Z = res;\r
5846 FLAG_V = VFLAG_CLEAR;\r
5847 FLAG_C = CFLAG_CLEAR;\r
5848}\r
5849\r
5850\r
5851M68KMAKE_OP(move, 8, pd7, .)\r
5852{\r
5853 uint res = M68KMAKE_GET_OPER_AY_8;\r
5854 uint ea = EA_A7_PD_8();\r
5855\r
5856 m68ki_write_8(ea, res);\r
5857\r
5858 FLAG_N = NFLAG_8(res);\r
5859 FLAG_Z = res;\r
5860 FLAG_V = VFLAG_CLEAR;\r
5861 FLAG_C = CFLAG_CLEAR;\r
5862}\r
5863\r
5864\r
5865M68KMAKE_OP(move, 8, pd, .)\r
5866{\r
5867 uint res = M68KMAKE_GET_OPER_AY_8;\r
5868 uint ea = EA_AX_PD_8();\r
5869\r
5870 m68ki_write_8(ea, res);\r
5871\r
5872 FLAG_N = NFLAG_8(res);\r
5873 FLAG_Z = res;\r
5874 FLAG_V = VFLAG_CLEAR;\r
5875 FLAG_C = CFLAG_CLEAR;\r
5876}\r
5877\r
5878\r
5879M68KMAKE_OP(move, 8, di, d)\r
5880{\r
5881 uint res = MASK_OUT_ABOVE_8(DY);\r
5882 uint ea = EA_AX_DI_8();\r
5883\r
5884 m68ki_write_8(ea, res);\r
5885\r
5886 FLAG_N = NFLAG_8(res);\r
5887 FLAG_Z = res;\r
5888 FLAG_V = VFLAG_CLEAR;\r
5889 FLAG_C = CFLAG_CLEAR;\r
5890}\r
5891\r
5892\r
5893M68KMAKE_OP(move, 8, di, .)\r
5894{\r
5895 uint res = M68KMAKE_GET_OPER_AY_8;\r
5896 uint ea = EA_AX_DI_8();\r
5897\r
5898 m68ki_write_8(ea, res);\r
5899\r
5900 FLAG_N = NFLAG_8(res);\r
5901 FLAG_Z = res;\r
5902 FLAG_V = VFLAG_CLEAR;\r
5903 FLAG_C = CFLAG_CLEAR;\r
5904}\r
5905\r
5906\r
5907M68KMAKE_OP(move, 8, ix, d)\r
5908{\r
5909 uint res = MASK_OUT_ABOVE_8(DY);\r
5910 uint ea = EA_AX_IX_8();\r
5911\r
5912 m68ki_write_8(ea, res);\r
5913\r
5914 FLAG_N = NFLAG_8(res);\r
5915 FLAG_Z = res;\r
5916 FLAG_V = VFLAG_CLEAR;\r
5917 FLAG_C = CFLAG_CLEAR;\r
5918}\r
5919\r
5920\r
5921M68KMAKE_OP(move, 8, ix, .)\r
5922{\r
5923 uint res = M68KMAKE_GET_OPER_AY_8;\r
5924 uint ea = EA_AX_IX_8();\r
5925\r
5926 m68ki_write_8(ea, res);\r
5927\r
5928 FLAG_N = NFLAG_8(res);\r
5929 FLAG_Z = res;\r
5930 FLAG_V = VFLAG_CLEAR;\r
5931 FLAG_C = CFLAG_CLEAR;\r
5932}\r
5933\r
5934\r
5935M68KMAKE_OP(move, 8, aw, d)\r
5936{\r
5937 uint res = MASK_OUT_ABOVE_8(DY);\r
5938 uint ea = EA_AW_8();\r
5939\r
5940 m68ki_write_8(ea, res);\r
5941\r
5942 FLAG_N = NFLAG_8(res);\r
5943 FLAG_Z = res;\r
5944 FLAG_V = VFLAG_CLEAR;\r
5945 FLAG_C = CFLAG_CLEAR;\r
5946}\r
5947\r
5948\r
5949M68KMAKE_OP(move, 8, aw, .)\r
5950{\r
5951 uint res = M68KMAKE_GET_OPER_AY_8;\r
5952 uint ea = EA_AW_8();\r
5953\r
5954 m68ki_write_8(ea, res);\r
5955\r
5956 FLAG_N = NFLAG_8(res);\r
5957 FLAG_Z = res;\r
5958 FLAG_V = VFLAG_CLEAR;\r
5959 FLAG_C = CFLAG_CLEAR;\r
5960}\r
5961\r
5962\r
5963M68KMAKE_OP(move, 8, al, d)\r
5964{\r
5965 uint res = MASK_OUT_ABOVE_8(DY);\r
5966 uint ea = EA_AL_8();\r
5967\r
5968 m68ki_write_8(ea, res);\r
5969\r
5970 FLAG_N = NFLAG_8(res);\r
5971 FLAG_Z = res;\r
5972 FLAG_V = VFLAG_CLEAR;\r
5973 FLAG_C = CFLAG_CLEAR;\r
5974}\r
5975\r
5976\r
5977M68KMAKE_OP(move, 8, al, .)\r
5978{\r
5979 uint res = M68KMAKE_GET_OPER_AY_8;\r
5980 uint ea = EA_AL_8();\r
5981\r
5982 m68ki_write_8(ea, res);\r
5983\r
5984 FLAG_N = NFLAG_8(res);\r
5985 FLAG_Z = res;\r
5986 FLAG_V = VFLAG_CLEAR;\r
5987 FLAG_C = CFLAG_CLEAR;\r
5988}\r
5989\r
5990\r
5991M68KMAKE_OP(move, 16, d, d)\r
5992{\r
5993 uint res = MASK_OUT_ABOVE_16(DY);\r
5994 uint* r_dst = &DX;\r
5995\r
5996 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
5997\r
5998 FLAG_N = NFLAG_16(res);\r
5999 FLAG_Z = res;\r
6000 FLAG_V = VFLAG_CLEAR;\r
6001 FLAG_C = CFLAG_CLEAR;\r
6002}\r
6003\r
6004\r
6005M68KMAKE_OP(move, 16, d, a)\r
6006{\r
6007 uint res = MASK_OUT_ABOVE_16(AY);\r
6008 uint* r_dst = &DX;\r
6009\r
6010 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
6011\r
6012 FLAG_N = NFLAG_16(res);\r
6013 FLAG_Z = res;\r
6014 FLAG_V = VFLAG_CLEAR;\r
6015 FLAG_C = CFLAG_CLEAR;\r
6016}\r
6017\r
6018\r
6019M68KMAKE_OP(move, 16, d, .)\r
6020{\r
6021 uint res = M68KMAKE_GET_OPER_AY_16;\r
6022 uint* r_dst = &DX;\r
6023\r
6024 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
6025\r
6026 FLAG_N = NFLAG_16(res);\r
6027 FLAG_Z = res;\r
6028 FLAG_V = VFLAG_CLEAR;\r
6029 FLAG_C = CFLAG_CLEAR;\r
6030}\r
6031\r
6032\r
6033M68KMAKE_OP(move, 16, ai, d)\r
6034{\r
6035 uint res = MASK_OUT_ABOVE_16(DY);\r
6036 uint ea = EA_AX_AI_16();\r
6037\r
6038 m68ki_write_16(ea, res);\r
6039\r
6040 FLAG_N = NFLAG_16(res);\r
6041 FLAG_Z = res;\r
6042 FLAG_V = VFLAG_CLEAR;\r
6043 FLAG_C = CFLAG_CLEAR;\r
6044}\r
6045\r
6046\r
6047M68KMAKE_OP(move, 16, ai, a)\r
6048{\r
6049 uint res = MASK_OUT_ABOVE_16(AY);\r
6050 uint ea = EA_AX_AI_16();\r
6051\r
6052 m68ki_write_16(ea, res);\r
6053\r
6054 FLAG_N = NFLAG_16(res);\r
6055 FLAG_Z = res;\r
6056 FLAG_V = VFLAG_CLEAR;\r
6057 FLAG_C = CFLAG_CLEAR;\r
6058}\r
6059\r
6060\r
6061M68KMAKE_OP(move, 16, ai, .)\r
6062{\r
6063 uint res = M68KMAKE_GET_OPER_AY_16;\r
6064 uint ea = EA_AX_AI_16();\r
6065\r
6066 m68ki_write_16(ea, res);\r
6067\r
6068 FLAG_N = NFLAG_16(res);\r
6069 FLAG_Z = res;\r
6070 FLAG_V = VFLAG_CLEAR;\r
6071 FLAG_C = CFLAG_CLEAR;\r
6072}\r
6073\r
6074\r
6075M68KMAKE_OP(move, 16, pi, d)\r
6076{\r
6077 uint res = MASK_OUT_ABOVE_16(DY);\r
6078 uint ea = EA_AX_PI_16();\r
6079\r
6080 m68ki_write_16(ea, res);\r
6081\r
6082 FLAG_N = NFLAG_16(res);\r
6083 FLAG_Z = res;\r
6084 FLAG_V = VFLAG_CLEAR;\r
6085 FLAG_C = CFLAG_CLEAR;\r
6086}\r
6087\r
6088\r
6089M68KMAKE_OP(move, 16, pi, a)\r
6090{\r
6091 uint res = MASK_OUT_ABOVE_16(AY);\r
6092 uint ea = EA_AX_PI_16();\r
6093\r
6094 m68ki_write_16(ea, res);\r
6095\r
6096 FLAG_N = NFLAG_16(res);\r
6097 FLAG_Z = res;\r
6098 FLAG_V = VFLAG_CLEAR;\r
6099 FLAG_C = CFLAG_CLEAR;\r
6100}\r
6101\r
6102\r
6103M68KMAKE_OP(move, 16, pi, .)\r
6104{\r
6105 uint res = M68KMAKE_GET_OPER_AY_16;\r
6106 uint ea = EA_AX_PI_16();\r
6107\r
6108 m68ki_write_16(ea, res);\r
6109\r
6110 FLAG_N = NFLAG_16(res);\r
6111 FLAG_Z = res;\r
6112 FLAG_V = VFLAG_CLEAR;\r
6113 FLAG_C = CFLAG_CLEAR;\r
6114}\r
6115\r
6116\r
6117M68KMAKE_OP(move, 16, pd, d)\r
6118{\r
6119 uint res = MASK_OUT_ABOVE_16(DY);\r
6120 uint ea = EA_AX_PD_16();\r
6121\r
6122 m68ki_write_16(ea, res);\r
6123\r
6124 FLAG_N = NFLAG_16(res);\r
6125 FLAG_Z = res;\r
6126 FLAG_V = VFLAG_CLEAR;\r
6127 FLAG_C = CFLAG_CLEAR;\r
6128}\r
6129\r
6130\r
6131M68KMAKE_OP(move, 16, pd, a)\r
6132{\r
6133 uint res = MASK_OUT_ABOVE_16(AY);\r
6134 uint ea = EA_AX_PD_16();\r
6135\r
6136 m68ki_write_16(ea, res);\r
6137\r
6138 FLAG_N = NFLAG_16(res);\r
6139 FLAG_Z = res;\r
6140 FLAG_V = VFLAG_CLEAR;\r
6141 FLAG_C = CFLAG_CLEAR;\r
6142}\r
6143\r
6144\r
6145M68KMAKE_OP(move, 16, pd, .)\r
6146{\r
6147 uint res = M68KMAKE_GET_OPER_AY_16;\r
6148 uint ea = EA_AX_PD_16();\r
6149\r
6150 m68ki_write_16(ea, res);\r
6151\r
6152 FLAG_N = NFLAG_16(res);\r
6153 FLAG_Z = res;\r
6154 FLAG_V = VFLAG_CLEAR;\r
6155 FLAG_C = CFLAG_CLEAR;\r
6156}\r
6157\r
6158\r
6159M68KMAKE_OP(move, 16, di, d)\r
6160{\r
6161 uint res = MASK_OUT_ABOVE_16(DY);\r
6162 uint ea = EA_AX_DI_16();\r
6163\r
6164 m68ki_write_16(ea, res);\r
6165\r
6166 FLAG_N = NFLAG_16(res);\r
6167 FLAG_Z = res;\r
6168 FLAG_V = VFLAG_CLEAR;\r
6169 FLAG_C = CFLAG_CLEAR;\r
6170}\r
6171\r
6172\r
6173M68KMAKE_OP(move, 16, di, a)\r
6174{\r
6175 uint res = MASK_OUT_ABOVE_16(AY);\r
6176 uint ea = EA_AX_DI_16();\r
6177\r
6178 m68ki_write_16(ea, res);\r
6179\r
6180 FLAG_N = NFLAG_16(res);\r
6181 FLAG_Z = res;\r
6182 FLAG_V = VFLAG_CLEAR;\r
6183 FLAG_C = CFLAG_CLEAR;\r
6184}\r
6185\r
6186\r
6187M68KMAKE_OP(move, 16, di, .)\r
6188{\r
6189 uint res = M68KMAKE_GET_OPER_AY_16;\r
6190 uint ea = EA_AX_DI_16();\r
6191\r
6192 m68ki_write_16(ea, res);\r
6193\r
6194 FLAG_N = NFLAG_16(res);\r
6195 FLAG_Z = res;\r
6196 FLAG_V = VFLAG_CLEAR;\r
6197 FLAG_C = CFLAG_CLEAR;\r
6198}\r
6199\r
6200\r
6201M68KMAKE_OP(move, 16, ix, d)\r
6202{\r
6203 uint res = MASK_OUT_ABOVE_16(DY);\r
6204 uint ea = EA_AX_IX_16();\r
6205\r
6206 m68ki_write_16(ea, res);\r
6207\r
6208 FLAG_N = NFLAG_16(res);\r
6209 FLAG_Z = res;\r
6210 FLAG_V = VFLAG_CLEAR;\r
6211 FLAG_C = CFLAG_CLEAR;\r
6212}\r
6213\r
6214\r
6215M68KMAKE_OP(move, 16, ix, a)\r
6216{\r
6217 uint res = MASK_OUT_ABOVE_16(AY);\r
6218 uint ea = EA_AX_IX_16();\r
6219\r
6220 m68ki_write_16(ea, res);\r
6221\r
6222 FLAG_N = NFLAG_16(res);\r
6223 FLAG_Z = res;\r
6224 FLAG_V = VFLAG_CLEAR;\r
6225 FLAG_C = CFLAG_CLEAR;\r
6226}\r
6227\r
6228\r
6229M68KMAKE_OP(move, 16, ix, .)\r
6230{\r
6231 uint res = M68KMAKE_GET_OPER_AY_16;\r
6232 uint ea = EA_AX_IX_16();\r
6233\r
6234 m68ki_write_16(ea, res);\r
6235\r
6236 FLAG_N = NFLAG_16(res);\r
6237 FLAG_Z = res;\r
6238 FLAG_V = VFLAG_CLEAR;\r
6239 FLAG_C = CFLAG_CLEAR;\r
6240}\r
6241\r
6242\r
6243M68KMAKE_OP(move, 16, aw, d)\r
6244{\r
6245 uint res = MASK_OUT_ABOVE_16(DY);\r
6246 uint ea = EA_AW_16();\r
6247\r
6248 m68ki_write_16(ea, res);\r
6249\r
6250 FLAG_N = NFLAG_16(res);\r
6251 FLAG_Z = res;\r
6252 FLAG_V = VFLAG_CLEAR;\r
6253 FLAG_C = CFLAG_CLEAR;\r
6254}\r
6255\r
6256\r
6257M68KMAKE_OP(move, 16, aw, a)\r
6258{\r
6259 uint res = MASK_OUT_ABOVE_16(AY);\r
6260 uint ea = EA_AW_16();\r
6261\r
6262 m68ki_write_16(ea, res);\r
6263\r
6264 FLAG_N = NFLAG_16(res);\r
6265 FLAG_Z = res;\r
6266 FLAG_V = VFLAG_CLEAR;\r
6267 FLAG_C = CFLAG_CLEAR;\r
6268}\r
6269\r
6270\r
6271M68KMAKE_OP(move, 16, aw, .)\r
6272{\r
6273 uint res = M68KMAKE_GET_OPER_AY_16;\r
6274 uint ea = EA_AW_16();\r
6275\r
6276 m68ki_write_16(ea, res);\r
6277\r
6278 FLAG_N = NFLAG_16(res);\r
6279 FLAG_Z = res;\r
6280 FLAG_V = VFLAG_CLEAR;\r
6281 FLAG_C = CFLAG_CLEAR;\r
6282}\r
6283\r
6284\r
6285M68KMAKE_OP(move, 16, al, d)\r
6286{\r
6287 uint res = MASK_OUT_ABOVE_16(DY);\r
6288 uint ea = EA_AL_16();\r
6289\r
6290 m68ki_write_16(ea, res);\r
6291\r
6292 FLAG_N = NFLAG_16(res);\r
6293 FLAG_Z = res;\r
6294 FLAG_V = VFLAG_CLEAR;\r
6295 FLAG_C = CFLAG_CLEAR;\r
6296}\r
6297\r
6298\r
6299M68KMAKE_OP(move, 16, al, a)\r
6300{\r
6301 uint res = MASK_OUT_ABOVE_16(AY);\r
6302 uint ea = EA_AL_16();\r
6303\r
6304 m68ki_write_16(ea, res);\r
6305\r
6306 FLAG_N = NFLAG_16(res);\r
6307 FLAG_Z = res;\r
6308 FLAG_V = VFLAG_CLEAR;\r
6309 FLAG_C = CFLAG_CLEAR;\r
6310}\r
6311\r
6312\r
6313M68KMAKE_OP(move, 16, al, .)\r
6314{\r
6315 uint res = M68KMAKE_GET_OPER_AY_16;\r
6316 uint ea = EA_AL_16();\r
6317\r
6318 m68ki_write_16(ea, res);\r
6319\r
6320 FLAG_N = NFLAG_16(res);\r
6321 FLAG_Z = res;\r
6322 FLAG_V = VFLAG_CLEAR;\r
6323 FLAG_C = CFLAG_CLEAR;\r
6324}\r
6325\r
6326\r
6327M68KMAKE_OP(move, 32, d, d)\r
6328{\r
6329 uint res = DY;\r
6330 uint* r_dst = &DX;\r
6331\r
6332 *r_dst = res;\r
6333\r
6334 FLAG_N = NFLAG_32(res);\r
6335 FLAG_Z = res;\r
6336 FLAG_V = VFLAG_CLEAR;\r
6337 FLAG_C = CFLAG_CLEAR;\r
6338}\r
6339\r
6340\r
6341M68KMAKE_OP(move, 32, d, a)\r
6342{\r
6343 uint res = AY;\r
6344 uint* r_dst = &DX;\r
6345\r
6346 *r_dst = res;\r
6347\r
6348 FLAG_N = NFLAG_32(res);\r
6349 FLAG_Z = res;\r
6350 FLAG_V = VFLAG_CLEAR;\r
6351 FLAG_C = CFLAG_CLEAR;\r
6352}\r
6353\r
6354\r
6355M68KMAKE_OP(move, 32, d, .)\r
6356{\r
6357 uint res = M68KMAKE_GET_OPER_AY_32;\r
6358 uint* r_dst = &DX;\r
6359\r
6360 *r_dst = res;\r
6361\r
6362 FLAG_N = NFLAG_32(res);\r
6363 FLAG_Z = res;\r
6364 FLAG_V = VFLAG_CLEAR;\r
6365 FLAG_C = CFLAG_CLEAR;\r
6366}\r
6367\r
6368\r
6369M68KMAKE_OP(move, 32, ai, d)\r
6370{\r
6371 uint res = DY;\r
6372 uint ea = EA_AX_AI_32();\r
6373\r
6374 m68ki_write_32(ea, res);\r
6375\r
6376 FLAG_N = NFLAG_32(res);\r
6377 FLAG_Z = res;\r
6378 FLAG_V = VFLAG_CLEAR;\r
6379 FLAG_C = CFLAG_CLEAR;\r
6380}\r
6381\r
6382\r
6383M68KMAKE_OP(move, 32, ai, a)\r
6384{\r
6385 uint res = AY;\r
6386 uint ea = EA_AX_AI_32();\r
6387\r
6388 m68ki_write_32(ea, res);\r
6389\r
6390 FLAG_N = NFLAG_32(res);\r
6391 FLAG_Z = res;\r
6392 FLAG_V = VFLAG_CLEAR;\r
6393 FLAG_C = CFLAG_CLEAR;\r
6394}\r
6395\r
6396\r
6397M68KMAKE_OP(move, 32, ai, .)\r
6398{\r
6399 uint res = M68KMAKE_GET_OPER_AY_32;\r
6400 uint ea = EA_AX_AI_32();\r
6401\r
6402 m68ki_write_32(ea, res);\r
6403\r
6404 FLAG_N = NFLAG_32(res);\r
6405 FLAG_Z = res;\r
6406 FLAG_V = VFLAG_CLEAR;\r
6407 FLAG_C = CFLAG_CLEAR;\r
6408}\r
6409\r
6410\r
6411M68KMAKE_OP(move, 32, pi, d)\r
6412{\r
6413 uint res = DY;\r
6414 uint ea = EA_AX_PI_32();\r
6415\r
6416 m68ki_write_32(ea, res);\r
6417\r
6418 FLAG_N = NFLAG_32(res);\r
6419 FLAG_Z = res;\r
6420 FLAG_V = VFLAG_CLEAR;\r
6421 FLAG_C = CFLAG_CLEAR;\r
6422}\r
6423\r
6424\r
6425M68KMAKE_OP(move, 32, pi, a)\r
6426{\r
6427 uint res = AY;\r
6428 uint ea = EA_AX_PI_32();\r
6429\r
6430 m68ki_write_32(ea, res);\r
6431\r
6432 FLAG_N = NFLAG_32(res);\r
6433 FLAG_Z = res;\r
6434 FLAG_V = VFLAG_CLEAR;\r
6435 FLAG_C = CFLAG_CLEAR;\r
6436}\r
6437\r
6438\r
6439M68KMAKE_OP(move, 32, pi, .)\r
6440{\r
6441 uint res = M68KMAKE_GET_OPER_AY_32;\r
6442 uint ea = EA_AX_PI_32();\r
6443\r
6444 m68ki_write_32(ea, res);\r
6445\r
6446 FLAG_N = NFLAG_32(res);\r
6447 FLAG_Z = res;\r
6448 FLAG_V = VFLAG_CLEAR;\r
6449 FLAG_C = CFLAG_CLEAR;\r
6450}\r
6451\r
6452\r
6453M68KMAKE_OP(move, 32, pd, d)\r
6454{\r
6455 uint res = DY;\r
6456 uint ea = EA_AX_PD_32();\r
6457\r
c6a4c892 6458 m68ki_write_16(ea+2, res & 0xFFFF );\r
6459 m68ki_write_16(ea, (res >> 16) & 0xFFFF );\r
cc68a136 6460\r
6461 FLAG_N = NFLAG_32(res);\r
6462 FLAG_Z = res;\r
6463 FLAG_V = VFLAG_CLEAR;\r
6464 FLAG_C = CFLAG_CLEAR;\r
6465}\r
6466\r
6467\r
6468M68KMAKE_OP(move, 32, pd, a)\r
6469{\r
6470 uint res = AY;\r
6471 uint ea = EA_AX_PD_32();\r
6472\r
c6a4c892 6473 m68ki_write_16(ea+2, res & 0xFFFF );\r
6474 m68ki_write_16(ea, (res >> 16) & 0xFFFF );\r
cc68a136 6475\r
6476 FLAG_N = NFLAG_32(res);\r
6477 FLAG_Z = res;\r
6478 FLAG_V = VFLAG_CLEAR;\r
6479 FLAG_C = CFLAG_CLEAR;\r
6480}\r
6481\r
6482\r
6483M68KMAKE_OP(move, 32, pd, .)\r
6484{\r
6485 uint res = M68KMAKE_GET_OPER_AY_32;\r
6486 uint ea = EA_AX_PD_32();\r
6487\r
c6a4c892 6488 m68ki_write_16(ea+2, res & 0xFFFF );\r
6489 m68ki_write_16(ea, (res >> 16) & 0xFFFF );\r
cc68a136 6490\r
6491 FLAG_N = NFLAG_32(res);\r
6492 FLAG_Z = res;\r
6493 FLAG_V = VFLAG_CLEAR;\r
6494 FLAG_C = CFLAG_CLEAR;\r
6495}\r
6496\r
6497\r
6498M68KMAKE_OP(move, 32, di, d)\r
6499{\r
6500 uint res = DY;\r
6501 uint ea = EA_AX_DI_32();\r
6502\r
6503 m68ki_write_32(ea, res);\r
6504\r
6505 FLAG_N = NFLAG_32(res);\r
6506 FLAG_Z = res;\r
6507 FLAG_V = VFLAG_CLEAR;\r
6508 FLAG_C = CFLAG_CLEAR;\r
6509}\r
6510\r
6511\r
6512M68KMAKE_OP(move, 32, di, a)\r
6513{\r
6514 uint res = AY;\r
6515 uint ea = EA_AX_DI_32();\r
6516\r
6517 m68ki_write_32(ea, res);\r
6518\r
6519 FLAG_N = NFLAG_32(res);\r
6520 FLAG_Z = res;\r
6521 FLAG_V = VFLAG_CLEAR;\r
6522 FLAG_C = CFLAG_CLEAR;\r
6523}\r
6524\r
6525\r
6526M68KMAKE_OP(move, 32, di, .)\r
6527{\r
6528 uint res = M68KMAKE_GET_OPER_AY_32;\r
6529 uint ea = EA_AX_DI_32();\r
6530\r
6531 m68ki_write_32(ea, res);\r
6532\r
6533 FLAG_N = NFLAG_32(res);\r
6534 FLAG_Z = res;\r
6535 FLAG_V = VFLAG_CLEAR;\r
6536 FLAG_C = CFLAG_CLEAR;\r
6537}\r
6538\r
6539\r
6540M68KMAKE_OP(move, 32, ix, d)\r
6541{\r
6542 uint res = DY;\r
6543 uint ea = EA_AX_IX_32();\r
6544\r
6545 m68ki_write_32(ea, res);\r
6546\r
6547 FLAG_N = NFLAG_32(res);\r
6548 FLAG_Z = res;\r
6549 FLAG_V = VFLAG_CLEAR;\r
6550 FLAG_C = CFLAG_CLEAR;\r
6551}\r
6552\r
6553\r
6554M68KMAKE_OP(move, 32, ix, a)\r
6555{\r
6556 uint res = AY;\r
6557 uint ea = EA_AX_IX_32();\r
6558\r
6559 m68ki_write_32(ea, res);\r
6560\r
6561 FLAG_N = NFLAG_32(res);\r
6562 FLAG_Z = res;\r
6563 FLAG_V = VFLAG_CLEAR;\r
6564 FLAG_C = CFLAG_CLEAR;\r
6565}\r
6566\r
6567\r
6568M68KMAKE_OP(move, 32, ix, .)\r
6569{\r
6570 uint res = M68KMAKE_GET_OPER_AY_32;\r
6571 uint ea = EA_AX_IX_32();\r
6572\r
6573 m68ki_write_32(ea, res);\r
6574\r
6575 FLAG_N = NFLAG_32(res);\r
6576 FLAG_Z = res;\r
6577 FLAG_V = VFLAG_CLEAR;\r
6578 FLAG_C = CFLAG_CLEAR;\r
6579}\r
6580\r
6581\r
6582M68KMAKE_OP(move, 32, aw, d)\r
6583{\r
6584 uint res = DY;\r
6585 uint ea = EA_AW_32();\r
6586\r
6587 m68ki_write_32(ea, res);\r
6588\r
6589 FLAG_N = NFLAG_32(res);\r
6590 FLAG_Z = res;\r
6591 FLAG_V = VFLAG_CLEAR;\r
6592 FLAG_C = CFLAG_CLEAR;\r
6593}\r
6594\r
6595\r
6596M68KMAKE_OP(move, 32, aw, a)\r
6597{\r
6598 uint res = AY;\r
6599 uint ea = EA_AW_32();\r
6600\r
6601 m68ki_write_32(ea, res);\r
6602\r
6603 FLAG_N = NFLAG_32(res);\r
6604 FLAG_Z = res;\r
6605 FLAG_V = VFLAG_CLEAR;\r
6606 FLAG_C = CFLAG_CLEAR;\r
6607}\r
6608\r
6609\r
6610M68KMAKE_OP(move, 32, aw, .)\r
6611{\r
6612 uint res = M68KMAKE_GET_OPER_AY_32;\r
6613 uint ea = EA_AW_32();\r
6614\r
6615 m68ki_write_32(ea, res);\r
6616\r
6617 FLAG_N = NFLAG_32(res);\r
6618 FLAG_Z = res;\r
6619 FLAG_V = VFLAG_CLEAR;\r
6620 FLAG_C = CFLAG_CLEAR;\r
6621}\r
6622\r
6623\r
6624M68KMAKE_OP(move, 32, al, d)\r
6625{\r
6626 uint res = DY;\r
6627 uint ea = EA_AL_32();\r
6628\r
6629 m68ki_write_32(ea, res);\r
6630\r
6631 FLAG_N = NFLAG_32(res);\r
6632 FLAG_Z = res;\r
6633 FLAG_V = VFLAG_CLEAR;\r
6634 FLAG_C = CFLAG_CLEAR;\r
6635}\r
6636\r
6637\r
6638M68KMAKE_OP(move, 32, al, a)\r
6639{\r
6640 uint res = AY;\r
6641 uint ea = EA_AL_32();\r
6642\r
6643 m68ki_write_32(ea, res);\r
6644\r
6645 FLAG_N = NFLAG_32(res);\r
6646 FLAG_Z = res;\r
6647 FLAG_V = VFLAG_CLEAR;\r
6648 FLAG_C = CFLAG_CLEAR;\r
6649}\r
6650\r
6651\r
6652M68KMAKE_OP(move, 32, al, .)\r
6653{\r
6654 uint res = M68KMAKE_GET_OPER_AY_32;\r
6655 uint ea = EA_AL_32();\r
6656\r
6657 m68ki_write_32(ea, res);\r
6658\r
6659 FLAG_N = NFLAG_32(res);\r
6660 FLAG_Z = res;\r
6661 FLAG_V = VFLAG_CLEAR;\r
6662 FLAG_C = CFLAG_CLEAR;\r
6663}\r
6664\r
6665\r
6666M68KMAKE_OP(movea, 16, ., d)\r
6667{\r
6668 AX = MAKE_INT_16(DY);\r
6669}\r
6670\r
6671\r
6672M68KMAKE_OP(movea, 16, ., a)\r
6673{\r
6674 AX = MAKE_INT_16(AY);\r
6675}\r
6676\r
6677\r
6678M68KMAKE_OP(movea, 16, ., .)\r
6679{\r
6680 AX = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);\r
6681}\r
6682\r
6683\r
6684M68KMAKE_OP(movea, 32, ., d)\r
6685{\r
6686 AX = DY;\r
6687}\r
6688\r
6689\r
6690M68KMAKE_OP(movea, 32, ., a)\r
6691{\r
6692 AX = AY;\r
6693}\r
6694\r
6695\r
6696M68KMAKE_OP(movea, 32, ., .)\r
6697{\r
6698 AX = M68KMAKE_GET_OPER_AY_32;\r
6699}\r
6700\r
6701\r
6702M68KMAKE_OP(move, 16, frc, d)\r
6703{\r
6704 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))\r
6705 {\r
6706 DY = MASK_OUT_BELOW_16(DY) | m68ki_get_ccr();\r
6707 return;\r
6708 }\r
6709 m68ki_exception_illegal();\r
6710}\r
6711\r
6712\r
6713M68KMAKE_OP(move, 16, frc, .)\r
6714{\r
6715 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))\r
6716 {\r
6717 m68ki_write_16(M68KMAKE_GET_EA_AY_16, m68ki_get_ccr());\r
6718 return;\r
6719 }\r
6720 m68ki_exception_illegal();\r
6721}\r
6722\r
6723\r
6724M68KMAKE_OP(move, 16, toc, d)\r
6725{\r
6726 m68ki_set_ccr(DY);\r
6727}\r
6728\r
6729\r
6730M68KMAKE_OP(move, 16, toc, .)\r
6731{\r
6732 m68ki_set_ccr(M68KMAKE_GET_OPER_AY_16);\r
6733}\r
6734\r
6735\r
6736M68KMAKE_OP(move, 16, frs, d)\r
6737{\r
6738 if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */\r
6739 {\r
6740 DY = MASK_OUT_BELOW_16(DY) | m68ki_get_sr();\r
6741 return;\r
6742 }\r
6743 m68ki_exception_privilege_violation();\r
6744}\r
6745\r
6746\r
6747M68KMAKE_OP(move, 16, frs, .)\r
6748{\r
6749 if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */\r
6750 {\r
6751 uint ea = M68KMAKE_GET_EA_AY_16;\r
6752 m68ki_write_16(ea, m68ki_get_sr());\r
6753 return;\r
6754 }\r
6755 m68ki_exception_privilege_violation();\r
6756}\r
6757\r
6758\r
6759M68KMAKE_OP(move, 16, tos, d)\r
6760{\r
6761 if(FLAG_S)\r
6762 {\r
6763 m68ki_set_sr(DY);\r
6764 return;\r
6765 }\r
6766 m68ki_exception_privilege_violation();\r
6767}\r
6768\r
6769\r
6770M68KMAKE_OP(move, 16, tos, .)\r
6771{\r
6772 if(FLAG_S)\r
6773 {\r
6774 uint new_sr = M68KMAKE_GET_OPER_AY_16;\r
6775 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
6776 m68ki_set_sr(new_sr);\r
6777 return;\r
6778 }\r
6779 m68ki_exception_privilege_violation();\r
6780}\r
6781\r
6782\r
6783M68KMAKE_OP(move, 32, fru, .)\r
6784{\r
6785 if(FLAG_S)\r
6786 {\r
6787 AY = REG_USP;\r
6788 return;\r
6789 }\r
6790 m68ki_exception_privilege_violation();\r
6791}\r
6792\r
6793\r
6794M68KMAKE_OP(move, 32, tou, .)\r
6795{\r
6796 if(FLAG_S)\r
6797 {\r
6798 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
6799 REG_USP = AY;\r
6800 return;\r
6801 }\r
6802 m68ki_exception_privilege_violation();\r
6803}\r
6804\r
6805\r
6806M68KMAKE_OP(movec, 32, cr, .)\r
6807{\r
6808 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))\r
6809 {\r
6810 if(FLAG_S)\r
6811 {\r
6812 uint word2 = OPER_I_16();\r
6813\r
6814 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
6815 switch (word2 & 0xfff)\r
6816 {\r
6817 case 0x000: /* SFC */\r
6818 REG_DA[(word2 >> 12) & 15] = REG_SFC;\r
6819 return;\r
6820 case 0x001: /* DFC */\r
6821 REG_DA[(word2 >> 12) & 15] = REG_DFC;\r
6822 return;\r
6823 case 0x002: /* CACR */\r
6824 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
6825 {\r
6826 REG_DA[(word2 >> 12) & 15] = REG_CACR;\r
6827 return;\r
6828 }\r
6829 return;\r
6830 case 0x800: /* USP */\r
6831 REG_DA[(word2 >> 12) & 15] = REG_USP;\r
6832 return;\r
6833 case 0x801: /* VBR */\r
6834 REG_DA[(word2 >> 12) & 15] = REG_VBR;\r
6835 return;\r
6836 case 0x802: /* CAAR */\r
6837 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
6838 {\r
6839 REG_DA[(word2 >> 12) & 15] = REG_CAAR;\r
6840 return;\r
6841 }\r
6842 m68ki_exception_illegal();\r
6843 break;\r
6844 case 0x803: /* MSP */\r
6845 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
6846 {\r
6847 REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_SP : REG_MSP;\r
6848 return;\r
6849 }\r
6850 m68ki_exception_illegal();\r
6851 return;\r
6852 case 0x804: /* ISP */\r
6853 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
6854 {\r
6855 REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_ISP : REG_SP;\r
6856 return;\r
6857 }\r
6858 m68ki_exception_illegal();\r
6859 return;\r
6860 case 0x003: /* TC */\r
6861 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
6862 {\r
6863 /* TODO */\r
6864 return;\r
6865 }\r
6866 m68ki_exception_illegal();\r
6867 return;\r
6868 case 0x004: /* ITT0 */\r
6869 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
6870 {\r
6871 /* TODO */\r
6872 return;\r
6873 }\r
6874 m68ki_exception_illegal();\r
6875 return;\r
6876 case 0x005: /* ITT1 */\r
6877 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
6878 {\r
6879 /* TODO */\r
6880 return;\r
6881 }\r
6882 m68ki_exception_illegal();\r
6883 return;\r
6884 case 0x006: /* DTT0 */\r
6885 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
6886 {\r
6887 /* TODO */\r
6888 return;\r
6889 }\r
6890 m68ki_exception_illegal();\r
6891 return;\r
6892 case 0x007: /* DTT1 */\r
6893 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
6894 {\r
6895 /* TODO */\r
6896 return;\r
6897 }\r
6898 m68ki_exception_illegal();\r
6899 return;\r
6900 case 0x805: /* MMUSR */\r
6901 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
6902 {\r
6903 /* TODO */\r
6904 return;\r
6905 }\r
6906 m68ki_exception_illegal();\r
6907 return;\r
6908 case 0x806: /* URP */\r
6909 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
6910 {\r
6911 /* TODO */\r
6912 return;\r
6913 }\r
6914 m68ki_exception_illegal();\r
6915 return;\r
6916 case 0x807: /* SRP */\r
6917 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
6918 {\r
6919 /* TODO */\r
6920 return;\r
6921 }\r
6922 m68ki_exception_illegal();\r
6923 return;\r
6924 default:\r
6925 m68ki_exception_illegal();\r
6926 return;\r
6927 }\r
6928 }\r
6929 m68ki_exception_privilege_violation();\r
6930 return;\r
6931 }\r
6932 m68ki_exception_illegal();\r
6933}\r
6934\r
6935\r
6936M68KMAKE_OP(movec, 32, rc, .)\r
6937{\r
6938 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))\r
6939 {\r
6940 if(FLAG_S)\r
6941 {\r
6942 uint word2 = OPER_I_16();\r
6943\r
6944 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
6945 switch (word2 & 0xfff)\r
6946 {\r
6947 case 0x000: /* SFC */\r
6948 REG_SFC = REG_DA[(word2 >> 12) & 15] & 7;\r
6949 return;\r
6950 case 0x001: /* DFC */\r
6951 REG_DFC = REG_DA[(word2 >> 12) & 15] & 7;\r
6952 return;\r
6953 case 0x002: /* CACR */\r
6954 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
6955 {\r
c6a4c892 6956 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
6957 {\r
6958 REG_CACR = REG_DA[(word2 >> 12) & 15];\r
6959 }\r
6960 else\r
6961 {\r
6962 /* non 68040 can only set the lower 4 bits (C,CE,F,E) */\r
6963 REG_CACR = REG_DA[(word2 >> 12) & 15] & 0x0f;\r
6964 }\r
cc68a136 6965 return;\r
6966 }\r
6967 m68ki_exception_illegal();\r
6968 return;\r
6969 case 0x800: /* USP */\r
6970 REG_USP = REG_DA[(word2 >> 12) & 15];\r
6971 return;\r
6972 case 0x801: /* VBR */\r
6973 REG_VBR = REG_DA[(word2 >> 12) & 15];\r
6974 return;\r
6975 case 0x802: /* CAAR */\r
6976 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
6977 {\r
6978 REG_CAAR = REG_DA[(word2 >> 12) & 15];\r
6979 return;\r
6980 }\r
6981 m68ki_exception_illegal();\r
6982 return;\r
6983 case 0x803: /* MSP */\r
6984 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
6985 {\r
6986 /* we are in supervisor mode so just check for M flag */\r
6987 if(!FLAG_M)\r
6988 {\r
6989 REG_MSP = REG_DA[(word2 >> 12) & 15];\r
6990 return;\r
6991 }\r
6992 REG_SP = REG_DA[(word2 >> 12) & 15];\r
6993 return;\r
6994 }\r
6995 m68ki_exception_illegal();\r
6996 return;\r
6997 case 0x804: /* ISP */\r
6998 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
6999 {\r
7000 if(!FLAG_M)\r
7001 {\r
7002 REG_SP = REG_DA[(word2 >> 12) & 15];\r
7003 return;\r
7004 }\r
7005 REG_ISP = REG_DA[(word2 >> 12) & 15];\r
7006 return;\r
7007 }\r
7008 m68ki_exception_illegal();\r
7009 return;\r
7010 case 0x003: /* TC */\r
7011 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
7012 {\r
7013 /* TODO */\r
7014 return;\r
7015 }\r
7016 m68ki_exception_illegal();\r
7017 return;\r
7018 case 0x004: /* ITT0 */\r
7019 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
7020 {\r
7021 /* TODO */\r
7022 return;\r
7023 }\r
7024 m68ki_exception_illegal();\r
7025 return;\r
7026 case 0x005: /* ITT1 */\r
7027 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
7028 {\r
7029 /* TODO */\r
7030 return;\r
7031 }\r
7032 m68ki_exception_illegal();\r
7033 return;\r
7034 case 0x006: /* DTT0 */\r
7035 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
7036 {\r
7037 /* TODO */\r
7038 return;\r
7039 }\r
7040 m68ki_exception_illegal();\r
7041 return;\r
7042 case 0x007: /* DTT1 */\r
7043 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
7044 {\r
7045 /* TODO */\r
7046 return;\r
7047 }\r
7048 m68ki_exception_illegal();\r
7049 return;\r
7050 case 0x805: /* MMUSR */\r
7051 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
7052 {\r
7053 /* TODO */\r
7054 return;\r
7055 }\r
7056 m68ki_exception_illegal();\r
7057 return;\r
7058 case 0x806: /* URP */\r
7059 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
7060 {\r
7061 /* TODO */\r
7062 return;\r
7063 }\r
7064 m68ki_exception_illegal();\r
7065 return;\r
7066 case 0x807: /* SRP */\r
7067 if (CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
7068 {\r
7069 /* TODO */\r
7070 return;\r
7071 }\r
7072 m68ki_exception_illegal();\r
7073 return;\r
7074 default:\r
7075 m68ki_exception_illegal();\r
7076 return;\r
7077 }\r
7078 }\r
7079 m68ki_exception_privilege_violation();\r
7080 return;\r
7081 }\r
7082 m68ki_exception_illegal();\r
7083}\r
7084\r
7085\r
7086M68KMAKE_OP(movem, 16, re, pd)\r
7087{\r
7088 uint i = 0;\r
7089 uint register_list = OPER_I_16();\r
7090 uint ea = AY;\r
7091 uint count = 0;\r
7092\r
7093 for(; i < 16; i++)\r
7094 if(register_list & (1 << i))\r
7095 {\r
7096 ea -= 2;\r
7097 m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[15-i]));\r
7098 count++;\r
7099 }\r
7100 AY = ea;\r
7101\r
7102 USE_CYCLES(count<<CYC_MOVEM_W);\r
7103}\r
7104\r
7105\r
7106M68KMAKE_OP(movem, 16, re, .)\r
7107{\r
7108 uint i = 0;\r
7109 uint register_list = OPER_I_16();\r
7110 uint ea = M68KMAKE_GET_EA_AY_16;\r
7111 uint count = 0;\r
7112\r
7113 for(; i < 16; i++)\r
7114 if(register_list & (1 << i))\r
7115 {\r
7116 m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[i]));\r
7117 ea += 2;\r
7118 count++;\r
7119 }\r
7120\r
7121 USE_CYCLES(count<<CYC_MOVEM_W);\r
7122}\r
7123\r
7124\r
7125M68KMAKE_OP(movem, 32, re, pd)\r
7126{\r
7127 uint i = 0;\r
7128 uint register_list = OPER_I_16();\r
7129 uint ea = AY;\r
7130 uint count = 0;\r
7131\r
7132 for(; i < 16; i++)\r
7133 if(register_list & (1 << i))\r
7134 {\r
7135 ea -= 4;\r
a5ccbfba 7136 m68ki_write_32(ea, REG_DA[15-i] ); // notaz Cyclone hack\r
3335750a 7137 //m68ki_write_16(ea+2, REG_DA[15-i] & 0xFFFF );\r
7138 //m68ki_write_16(ea, (REG_DA[15-i] >> 16) & 0xFFFF );\r
cc68a136 7139 count++;\r
7140 }\r
7141 AY = ea;\r
7142\r
7143 USE_CYCLES(count<<CYC_MOVEM_L);\r
7144}\r
7145\r
7146\r
7147M68KMAKE_OP(movem, 32, re, .)\r
7148{\r
7149 uint i = 0;\r
7150 uint register_list = OPER_I_16();\r
7151 uint ea = M68KMAKE_GET_EA_AY_32;\r
7152 uint count = 0;\r
7153\r
7154 for(; i < 16; i++)\r
7155 if(register_list & (1 << i))\r
7156 {\r
7157 m68ki_write_32(ea, REG_DA[i]);\r
7158 ea += 4;\r
7159 count++;\r
7160 }\r
7161\r
7162 USE_CYCLES(count<<CYC_MOVEM_L);\r
7163}\r
7164\r
7165\r
7166M68KMAKE_OP(movem, 16, er, pi)\r
7167{\r
7168 uint i = 0;\r
7169 uint register_list = OPER_I_16();\r
7170 uint ea = AY;\r
7171 uint count = 0;\r
7172\r
7173 for(; i < 16; i++)\r
7174 if(register_list & (1 << i))\r
7175 {\r
7176 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));\r
7177 ea += 2;\r
7178 count++;\r
7179 }\r
7180 AY = ea;\r
7181\r
7182 USE_CYCLES(count<<CYC_MOVEM_W);\r
7183}\r
7184\r
7185\r
7186M68KMAKE_OP(movem, 16, er, pcdi)\r
7187{\r
7188 uint i = 0;\r
7189 uint register_list = OPER_I_16();\r
7190 uint ea = EA_PCDI_16();\r
7191 uint count = 0;\r
7192\r
7193 for(; i < 16; i++)\r
7194 if(register_list & (1 << i))\r
7195 {\r
7196 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_pcrel_16(ea)));\r
7197 ea += 2;\r
7198 count++;\r
7199 }\r
7200\r
7201 USE_CYCLES(count<<CYC_MOVEM_W);\r
7202}\r
7203\r
7204\r
7205M68KMAKE_OP(movem, 16, er, pcix)\r
7206{\r
7207 uint i = 0;\r
7208 uint register_list = OPER_I_16();\r
7209 uint ea = EA_PCIX_16();\r
7210 uint count = 0;\r
7211\r
7212 for(; i < 16; i++)\r
7213 if(register_list & (1 << i))\r
7214 {\r
7215 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_pcrel_16(ea)));\r
7216 ea += 2;\r
7217 count++;\r
7218 }\r
7219\r
7220 USE_CYCLES(count<<CYC_MOVEM_W);\r
7221}\r
7222\r
7223\r
7224M68KMAKE_OP(movem, 16, er, .)\r
7225{\r
7226 uint i = 0;\r
7227 uint register_list = OPER_I_16();\r
7228 uint ea = M68KMAKE_GET_EA_AY_16;\r
7229 uint count = 0;\r
7230\r
7231 for(; i < 16; i++)\r
7232 if(register_list & (1 << i))\r
7233 {\r
7234 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));\r
7235 ea += 2;\r
7236 count++;\r
7237 }\r
7238\r
7239 USE_CYCLES(count<<CYC_MOVEM_W);\r
7240}\r
7241\r
7242\r
7243M68KMAKE_OP(movem, 32, er, pi)\r
7244{\r
7245 uint i = 0;\r
7246 uint register_list = OPER_I_16();\r
7247 uint ea = AY;\r
7248 uint count = 0;\r
7249\r
7250 for(; i < 16; i++)\r
7251 if(register_list & (1 << i))\r
7252 {\r
7253 REG_DA[i] = m68ki_read_32(ea);\r
7254 ea += 4;\r
7255 count++;\r
7256 }\r
7257 AY = ea;\r
7258\r
7259 USE_CYCLES(count<<CYC_MOVEM_L);\r
7260}\r
7261\r
7262\r
7263M68KMAKE_OP(movem, 32, er, pcdi)\r
7264{\r
7265 uint i = 0;\r
7266 uint register_list = OPER_I_16();\r
7267 uint ea = EA_PCDI_32();\r
7268 uint count = 0;\r
7269\r
7270 for(; i < 16; i++)\r
7271 if(register_list & (1 << i))\r
7272 {\r
7273 REG_DA[i] = m68ki_read_pcrel_32(ea);\r
7274 ea += 4;\r
7275 count++;\r
7276 }\r
7277\r
7278 USE_CYCLES(count<<CYC_MOVEM_L);\r
7279}\r
7280\r
7281\r
7282M68KMAKE_OP(movem, 32, er, pcix)\r
7283{\r
7284 uint i = 0;\r
7285 uint register_list = OPER_I_16();\r
7286 uint ea = EA_PCIX_32();\r
7287 uint count = 0;\r
7288\r
7289 for(; i < 16; i++)\r
7290 if(register_list & (1 << i))\r
7291 {\r
7292 REG_DA[i] = m68ki_read_pcrel_32(ea);\r
7293 ea += 4;\r
7294 count++;\r
7295 }\r
7296\r
7297 USE_CYCLES(count<<CYC_MOVEM_L);\r
7298}\r
7299\r
7300\r
7301M68KMAKE_OP(movem, 32, er, .)\r
7302{\r
7303 uint i = 0;\r
7304 uint register_list = OPER_I_16();\r
7305 uint ea = M68KMAKE_GET_EA_AY_32;\r
7306 uint count = 0;\r
7307\r
7308 for(; i < 16; i++)\r
7309 if(register_list & (1 << i))\r
7310 {\r
7311 REG_DA[i] = m68ki_read_32(ea);\r
7312 ea += 4;\r
7313 count++;\r
7314 }\r
7315\r
7316 USE_CYCLES(count<<CYC_MOVEM_L);\r
7317}\r
7318\r
7319\r
7320M68KMAKE_OP(movep, 16, re, .)\r
7321{\r
7322 uint ea = EA_AY_DI_16();\r
7323 uint src = DX;\r
7324\r
7325 m68ki_write_8(ea, MASK_OUT_ABOVE_8(src >> 8));\r
7326 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src));\r
7327}\r
7328\r
7329\r
7330M68KMAKE_OP(movep, 32, re, .)\r
7331{\r
7332 uint ea = EA_AY_DI_32();\r
7333 uint src = DX;\r
7334\r
7335 m68ki_write_8(ea, MASK_OUT_ABOVE_8(src >> 24));\r
7336 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 16));\r
7337 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 8));\r
7338 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src));\r
7339}\r
7340\r
7341\r
7342M68KMAKE_OP(movep, 16, er, .)\r
7343{\r
7344 uint ea = EA_AY_DI_16();\r
7345 uint* r_dst = &DX;\r
7346\r
7347 *r_dst = MASK_OUT_BELOW_16(*r_dst) | ((m68ki_read_8(ea) << 8) + m68ki_read_8(ea + 2));\r
7348}\r
7349\r
7350\r
7351M68KMAKE_OP(movep, 32, er, .)\r
7352{\r
7353 uint ea = EA_AY_DI_32();\r
7354\r
7355 DX = (m68ki_read_8(ea) << 24) + (m68ki_read_8(ea + 2) << 16)\r
7356 + (m68ki_read_8(ea + 4) << 8) + m68ki_read_8(ea + 6);\r
7357}\r
7358\r
7359\r
7360M68KMAKE_OP(moves, 8, ., .)\r
7361{\r
7362 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))\r
7363 {\r
7364 if(FLAG_S)\r
7365 {\r
7366 uint word2 = OPER_I_16();\r
7367 uint ea = M68KMAKE_GET_EA_AY_8;\r
7368\r
7369 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
7370 if(BIT_B(word2)) /* Register to memory */\r
7371 {\r
7372 m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15]));\r
7373 return;\r
7374 }\r
7375 if(BIT_F(word2)) /* Memory to address register */\r
7376 {\r
7377 REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC));\r
7378 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))\r
7379 USE_CYCLES(2);\r
7380 return;\r
7381 }\r
7382 /* Memory to data register */\r
7383 REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC);\r
7384 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))\r
7385 USE_CYCLES(2);\r
7386 return;\r
7387 }\r
7388 m68ki_exception_privilege_violation();\r
7389 return;\r
7390 }\r
7391 m68ki_exception_illegal();\r
7392}\r
7393\r
7394\r
7395M68KMAKE_OP(moves, 16, ., .)\r
7396{\r
7397 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))\r
7398 {\r
7399 if(FLAG_S)\r
7400 {\r
7401 uint word2 = OPER_I_16();\r
7402 uint ea = M68KMAKE_GET_EA_AY_16;\r
7403\r
7404 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
7405 if(BIT_B(word2)) /* Register to memory */\r
7406 {\r
7407 m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15]));\r
7408 return;\r
7409 }\r
7410 if(BIT_F(word2)) /* Memory to address register */\r
7411 {\r
7412 REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC));\r
7413 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))\r
7414 USE_CYCLES(2);\r
7415 return;\r
7416 }\r
7417 /* Memory to data register */\r
7418 REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC);\r
7419 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))\r
7420 USE_CYCLES(2);\r
7421 return;\r
7422 }\r
7423 m68ki_exception_privilege_violation();\r
7424 return;\r
7425 }\r
7426 m68ki_exception_illegal();\r
7427}\r
7428\r
7429\r
7430M68KMAKE_OP(moves, 32, ., .)\r
7431{\r
7432 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))\r
7433 {\r
7434 if(FLAG_S)\r
7435 {\r
7436 uint word2 = OPER_I_16();\r
7437 uint ea = M68KMAKE_GET_EA_AY_32;\r
7438\r
7439 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
7440 if(BIT_B(word2)) /* Register to memory */\r
7441 {\r
7442 m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]);\r
7443 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))\r
7444 USE_CYCLES(2);\r
7445 return;\r
7446 }\r
7447 /* Memory to register */\r
7448 REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC);\r
7449 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))\r
7450 USE_CYCLES(2);\r
7451 return;\r
7452 }\r
7453 m68ki_exception_privilege_violation();\r
7454 return;\r
7455 }\r
7456 m68ki_exception_illegal();\r
7457}\r
7458\r
7459\r
7460M68KMAKE_OP(moveq, 32, ., .)\r
7461{\r
7462 uint res = DX = MAKE_INT_8(MASK_OUT_ABOVE_8(REG_IR));\r
7463\r
7464 FLAG_N = NFLAG_32(res);\r
7465 FLAG_Z = res;\r
7466 FLAG_V = VFLAG_CLEAR;\r
7467 FLAG_C = CFLAG_CLEAR;\r
7468}\r
7469\r
7470\r
7471M68KMAKE_OP(move16, 32, ., .)\r
7472{\r
7473 UINT16 w2 = OPER_I_16();\r
7474 int ax = REG_IR & 7;\r
7475 int ay = (w2 >> 12) & 7;\r
7476\r
7477 m68ki_write_32(REG_A[ay], m68ki_read_32(REG_A[ax]));\r
7478 m68ki_write_32(REG_A[ay]+4, m68ki_read_32(REG_A[ax]+4));\r
7479 m68ki_write_32(REG_A[ay]+8, m68ki_read_32(REG_A[ax]+8));\r
7480 m68ki_write_32(REG_A[ay]+12, m68ki_read_32(REG_A[ax]+12));\r
7481\r
7482 REG_A[ax] += 16;\r
7483 REG_A[ay] += 16;\r
7484}\r
7485\r
7486\r
7487M68KMAKE_OP(muls, 16, ., d)\r
7488{\r
7489 uint* r_dst = &DX;\r
7490 uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(DY) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));\r
7491\r
7492 *r_dst = res;\r
7493\r
7494 FLAG_Z = res;\r
7495 FLAG_N = NFLAG_32(res);\r
7496 FLAG_V = VFLAG_CLEAR;\r
7497 FLAG_C = CFLAG_CLEAR;\r
7498}\r
7499\r
7500\r
7501M68KMAKE_OP(muls, 16, ., .)\r
7502{\r
7503 uint* r_dst = &DX;\r
7504 uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(M68KMAKE_GET_OPER_AY_16) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));\r
7505\r
7506 *r_dst = res;\r
7507\r
7508 FLAG_Z = res;\r
7509 FLAG_N = NFLAG_32(res);\r
7510 FLAG_V = VFLAG_CLEAR;\r
7511 FLAG_C = CFLAG_CLEAR;\r
7512}\r
7513\r
7514\r
7515M68KMAKE_OP(mulu, 16, ., d)\r
7516{\r
7517 uint* r_dst = &DX;\r
7518 uint res = MASK_OUT_ABOVE_16(DY) * MASK_OUT_ABOVE_16(*r_dst);\r
7519\r
7520 *r_dst = res;\r
7521\r
7522 FLAG_Z = res;\r
7523 FLAG_N = NFLAG_32(res);\r
7524 FLAG_V = VFLAG_CLEAR;\r
7525 FLAG_C = CFLAG_CLEAR;\r
7526}\r
7527\r
7528\r
7529M68KMAKE_OP(mulu, 16, ., .)\r
7530{\r
7531 uint* r_dst = &DX;\r
7532 uint res = M68KMAKE_GET_OPER_AY_16 * MASK_OUT_ABOVE_16(*r_dst);\r
7533\r
7534 *r_dst = res;\r
7535\r
7536 FLAG_Z = res;\r
7537 FLAG_N = NFLAG_32(res);\r
7538 FLAG_V = VFLAG_CLEAR;\r
7539 FLAG_C = CFLAG_CLEAR;\r
7540}\r
7541\r
7542\r
7543M68KMAKE_OP(mull, 32, ., d)\r
7544{\r
7545#if M68K_USE_64_BIT\r
7546\r
7547 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
7548 {\r
7549 uint word2 = OPER_I_16();\r
7550 uint64 src = DY;\r
7551 uint64 dst = REG_D[(word2 >> 12) & 7];\r
7552 uint64 res;\r
7553\r
7554 FLAG_C = CFLAG_CLEAR;\r
7555\r
7556 if(BIT_B(word2)) /* signed */\r
7557 {\r
7558 res = (sint64)((sint32)src) * (sint64)((sint32)dst);\r
7559 if(!BIT_A(word2))\r
7560 {\r
7561 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
7562 FLAG_N = NFLAG_32(res);\r
7563 FLAG_V = ((sint64)res != (sint32)res)<<7;\r
7564 REG_D[(word2 >> 12) & 7] = FLAG_Z;\r
7565 return;\r
7566 }\r
7567 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);\r
7568 FLAG_N = NFLAG_64(res);\r
7569 FLAG_V = VFLAG_CLEAR;\r
7570 REG_D[word2 & 7] = (res >> 32);\r
7571 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);\r
7572 return;\r
7573 }\r
7574\r
7575 res = src * dst;\r
7576 if(!BIT_A(word2))\r
7577 {\r
7578 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
7579 FLAG_N = NFLAG_32(res);\r
7580 FLAG_V = (res > 0xffffffff)<<7;\r
7581 REG_D[(word2 >> 12) & 7] = FLAG_Z;\r
7582 return;\r
7583 }\r
7584 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);\r
7585 FLAG_N = NFLAG_64(res);\r
7586 FLAG_V = VFLAG_CLEAR;\r
7587 REG_D[word2 & 7] = (res >> 32);\r
7588 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);\r
7589 return;\r
7590 }\r
7591 m68ki_exception_illegal();\r
7592\r
7593#else\r
7594\r
7595 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
7596 {\r
7597 uint word2 = OPER_I_16();\r
7598 uint src = DY;\r
7599 uint dst = REG_D[(word2 >> 12) & 7];\r
7600 uint neg = GET_MSB_32(src ^ dst);\r
7601 uint src1;\r
7602 uint src2;\r
7603 uint dst1;\r
7604 uint dst2;\r
7605 uint r1;\r
7606 uint r2;\r
7607 uint r3;\r
7608 uint r4;\r
7609 uint lo;\r
7610 uint hi;\r
7611\r
7612 FLAG_C = CFLAG_CLEAR;\r
7613\r
7614 if(BIT_B(word2)) /* signed */\r
7615 {\r
7616 if(GET_MSB_32(src))\r
7617 src = (uint)MASK_OUT_ABOVE_32(-(sint)src);\r
7618 if(GET_MSB_32(dst))\r
7619 dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);\r
7620 }\r
7621\r
7622 src1 = MASK_OUT_ABOVE_16(src);\r
7623 src2 = src>>16;\r
7624 dst1 = MASK_OUT_ABOVE_16(dst);\r
7625 dst2 = dst>>16;\r
7626\r
7627\r
7628 r1 = src1 * dst1;\r
7629 r2 = src1 * dst2;\r
7630 r3 = src2 * dst1;\r
7631 r4 = src2 * dst2;\r
7632\r
7633 lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);\r
7634 hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);\r
7635\r
7636 if(BIT_B(word2) && neg)\r
7637 {\r
7638 hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));\r
7639 lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);\r
7640 }\r
7641\r
7642 if(BIT_A(word2))\r
7643 {\r
7644 REG_D[word2 & 7] = hi;\r
7645 REG_D[(word2 >> 12) & 7] = lo;\r
7646 FLAG_N = NFLAG_32(hi);\r
7647 FLAG_Z = hi | lo;\r
7648 FLAG_V = VFLAG_CLEAR;\r
7649 return;\r
7650 }\r
7651\r
7652 REG_D[(word2 >> 12) & 7] = lo;\r
7653 FLAG_N = NFLAG_32(lo);\r
7654 FLAG_Z = lo;\r
7655 if(BIT_B(word2))\r
7656 FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;\r
7657 else\r
7658 FLAG_V = (hi != 0) << 7;\r
7659 return;\r
7660 }\r
7661 m68ki_exception_illegal();\r
7662\r
7663#endif\r
7664}\r
7665\r
7666\r
7667M68KMAKE_OP(mull, 32, ., .)\r
7668{\r
7669#if M68K_USE_64_BIT\r
7670\r
7671 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
7672 {\r
7673 uint word2 = OPER_I_16();\r
7674 uint64 src = M68KMAKE_GET_OPER_AY_32;\r
7675 uint64 dst = REG_D[(word2 >> 12) & 7];\r
7676 uint64 res;\r
7677\r
7678 FLAG_C = CFLAG_CLEAR;\r
7679\r
7680 if(BIT_B(word2)) /* signed */\r
7681 {\r
7682 res = (sint64)((sint32)src) * (sint64)((sint32)dst);\r
7683 if(!BIT_A(word2))\r
7684 {\r
7685 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
7686 FLAG_N = NFLAG_32(res);\r
7687 FLAG_V = ((sint64)res != (sint32)res)<<7;\r
7688 REG_D[(word2 >> 12) & 7] = FLAG_Z;\r
7689 return;\r
7690 }\r
7691 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);\r
7692 FLAG_N = NFLAG_64(res);\r
7693 FLAG_V = VFLAG_CLEAR;\r
7694 REG_D[word2 & 7] = (res >> 32);\r
7695 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);\r
7696 return;\r
7697 }\r
7698\r
7699 res = src * dst;\r
7700 if(!BIT_A(word2))\r
7701 {\r
7702 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
7703 FLAG_N = NFLAG_32(res);\r
7704 FLAG_V = (res > 0xffffffff)<<7;\r
7705 REG_D[(word2 >> 12) & 7] = FLAG_Z;\r
7706 return;\r
7707 }\r
7708 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);\r
7709 FLAG_N = NFLAG_64(res);\r
7710 FLAG_V = VFLAG_CLEAR;\r
7711 REG_D[word2 & 7] = (res >> 32);\r
7712 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);\r
7713 return;\r
7714 }\r
7715 m68ki_exception_illegal();\r
7716\r
7717#else\r
7718\r
7719 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
7720 {\r
7721 uint word2 = OPER_I_16();\r
7722 uint src = M68KMAKE_GET_OPER_AY_32;\r
7723 uint dst = REG_D[(word2 >> 12) & 7];\r
7724 uint neg = GET_MSB_32(src ^ dst);\r
7725 uint src1;\r
7726 uint src2;\r
7727 uint dst1;\r
7728 uint dst2;\r
7729 uint r1;\r
7730 uint r2;\r
7731 uint r3;\r
7732 uint r4;\r
7733 uint lo;\r
7734 uint hi;\r
7735\r
7736 FLAG_C = CFLAG_CLEAR;\r
7737\r
7738 if(BIT_B(word2)) /* signed */\r
7739 {\r
7740 if(GET_MSB_32(src))\r
7741 src = (uint)MASK_OUT_ABOVE_32(-(sint)src);\r
7742 if(GET_MSB_32(dst))\r
7743 dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);\r
7744 }\r
7745\r
7746 src1 = MASK_OUT_ABOVE_16(src);\r
7747 src2 = src>>16;\r
7748 dst1 = MASK_OUT_ABOVE_16(dst);\r
7749 dst2 = dst>>16;\r
7750\r
7751\r
7752 r1 = src1 * dst1;\r
7753 r2 = src1 * dst2;\r
7754 r3 = src2 * dst1;\r
7755 r4 = src2 * dst2;\r
7756\r
7757 lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);\r
7758 hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);\r
7759\r
7760 if(BIT_B(word2) && neg)\r
7761 {\r
7762 hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));\r
7763 lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);\r
7764 }\r
7765\r
7766 if(BIT_A(word2))\r
7767 {\r
7768 REG_D[word2 & 7] = hi;\r
7769 REG_D[(word2 >> 12) & 7] = lo;\r
7770 FLAG_N = NFLAG_32(hi);\r
7771 FLAG_Z = hi | lo;\r
7772 FLAG_V = VFLAG_CLEAR;\r
7773 return;\r
7774 }\r
7775\r
7776 REG_D[(word2 >> 12) & 7] = lo;\r
7777 FLAG_N = NFLAG_32(lo);\r
7778 FLAG_Z = lo;\r
7779 if(BIT_B(word2))\r
7780 FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;\r
7781 else\r
7782 FLAG_V = (hi != 0) << 7;\r
7783 return;\r
7784 }\r
7785 m68ki_exception_illegal();\r
7786\r
7787#endif\r
7788}\r
7789\r
7790\r
7791M68KMAKE_OP(nbcd, 8, ., d)\r
7792{\r
7793 uint* r_dst = &DY;\r
7794 uint dst = *r_dst;\r
7795 uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1());\r
7796\r
7797 if(res != 0x9a)\r
7798 {\r
7799 FLAG_V = ~res; /* Undefined V behavior */\r
7800\r
7801 if((res & 0x0f) == 0xa)\r
7802 res = (res & 0xf0) + 0x10;\r
7803\r
7804 res = MASK_OUT_ABOVE_8(res);\r
7805\r
7806 FLAG_V &= res; /* Undefined V behavior part II */\r
7807\r
7808 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
7809\r
7810 FLAG_Z |= res;\r
7811 FLAG_C = CFLAG_SET;\r
7812 FLAG_X = XFLAG_SET;\r
7813 }\r
7814 else\r
7815 {\r
7816 FLAG_V = VFLAG_CLEAR;\r
7817 FLAG_C = CFLAG_CLEAR;\r
7818 FLAG_X = XFLAG_CLEAR;\r
7819 }\r
7820 FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
7821}\r
7822\r
7823\r
7824M68KMAKE_OP(nbcd, 8, ., .)\r
7825{\r
7826 uint ea = M68KMAKE_GET_EA_AY_8;\r
7827 uint dst = m68ki_read_8(ea);\r
7828 uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1());\r
7829\r
7830 if(res != 0x9a)\r
7831 {\r
7832 FLAG_V = ~res; /* Undefined V behavior */\r
7833\r
7834 if((res & 0x0f) == 0xa)\r
7835 res = (res & 0xf0) + 0x10;\r
7836\r
7837 res = MASK_OUT_ABOVE_8(res);\r
7838\r
7839 FLAG_V &= res; /* Undefined V behavior part II */\r
7840\r
7841 m68ki_write_8(ea, MASK_OUT_ABOVE_8(res));\r
7842\r
7843 FLAG_Z |= res;\r
7844 FLAG_C = CFLAG_SET;\r
7845 FLAG_X = XFLAG_SET;\r
7846 }\r
7847 else\r
7848 {\r
7849 FLAG_V = VFLAG_CLEAR;\r
7850 FLAG_C = CFLAG_CLEAR;\r
7851 FLAG_X = XFLAG_CLEAR;\r
7852 }\r
7853 FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
7854}\r
7855\r
7856\r
7857M68KMAKE_OP(neg, 8, ., d)\r
7858{\r
7859 uint* r_dst = &DY;\r
7860 uint res = 0 - MASK_OUT_ABOVE_8(*r_dst);\r
7861\r
7862 FLAG_N = NFLAG_8(res);\r
7863 FLAG_C = FLAG_X = CFLAG_8(res);\r
7864 FLAG_V = *r_dst & res;\r
7865 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
7866\r
7867 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;\r
7868}\r
7869\r
7870\r
7871M68KMAKE_OP(neg, 8, ., .)\r
7872{\r
7873 uint ea = M68KMAKE_GET_EA_AY_8;\r
7874 uint src = m68ki_read_8(ea);\r
7875 uint res = 0 - src;\r
7876\r
7877 FLAG_N = NFLAG_8(res);\r
7878 FLAG_C = FLAG_X = CFLAG_8(res);\r
7879 FLAG_V = src & res;\r
7880 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
7881\r
7882 m68ki_write_8(ea, FLAG_Z);\r
7883}\r
7884\r
7885\r
7886M68KMAKE_OP(neg, 16, ., d)\r
7887{\r
7888 uint* r_dst = &DY;\r
7889 uint res = 0 - MASK_OUT_ABOVE_16(*r_dst);\r
7890\r
7891 FLAG_N = NFLAG_16(res);\r
7892 FLAG_C = FLAG_X = CFLAG_16(res);\r
7893 FLAG_V = (*r_dst & res)>>8;\r
7894 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
7895\r
7896 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
7897}\r
7898\r
7899\r
7900M68KMAKE_OP(neg, 16, ., .)\r
7901{\r
7902 uint ea = M68KMAKE_GET_EA_AY_16;\r
7903 uint src = m68ki_read_16(ea);\r
7904 uint res = 0 - src;\r
7905\r
7906 FLAG_N = NFLAG_16(res);\r
7907 FLAG_C = FLAG_X = CFLAG_16(res);\r
7908 FLAG_V = (src & res)>>8;\r
7909 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
7910\r
7911 m68ki_write_16(ea, FLAG_Z);\r
7912}\r
7913\r
7914\r
7915M68KMAKE_OP(neg, 32, ., d)\r
7916{\r
7917 uint* r_dst = &DY;\r
7918 uint res = 0 - *r_dst;\r
7919\r
7920 FLAG_N = NFLAG_32(res);\r
7921 FLAG_C = FLAG_X = CFLAG_SUB_32(*r_dst, 0, res);\r
7922 FLAG_V = (*r_dst & res)>>24;\r
7923 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
7924\r
7925 *r_dst = FLAG_Z;\r
7926}\r
7927\r
7928\r
7929M68KMAKE_OP(neg, 32, ., .)\r
7930{\r
7931 uint ea = M68KMAKE_GET_EA_AY_32;\r
7932 uint src = m68ki_read_32(ea);\r
7933 uint res = 0 - src;\r
7934\r
7935 FLAG_N = NFLAG_32(res);\r
7936 FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res);\r
7937 FLAG_V = (src & res)>>24;\r
7938 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
7939\r
7940 m68ki_write_32(ea, FLAG_Z);\r
7941}\r
7942\r
7943\r
7944M68KMAKE_OP(negx, 8, ., d)\r
7945{\r
7946 uint* r_dst = &DY;\r
7947 uint res = 0 - MASK_OUT_ABOVE_8(*r_dst) - XFLAG_AS_1();\r
7948\r
7949 FLAG_N = NFLAG_8(res);\r
7950 FLAG_X = FLAG_C = CFLAG_8(res);\r
7951 FLAG_V = *r_dst & res;\r
7952\r
7953 res = MASK_OUT_ABOVE_8(res);\r
7954 FLAG_Z |= res;\r
7955\r
7956 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
7957}\r
7958\r
7959\r
7960M68KMAKE_OP(negx, 8, ., .)\r
7961{\r
7962 uint ea = M68KMAKE_GET_EA_AY_8;\r
7963 uint src = m68ki_read_8(ea);\r
7964 uint res = 0 - src - XFLAG_AS_1();\r
7965\r
7966 FLAG_N = NFLAG_8(res);\r
7967 FLAG_X = FLAG_C = CFLAG_8(res);\r
7968 FLAG_V = src & res;\r
7969\r
7970 res = MASK_OUT_ABOVE_8(res);\r
7971 FLAG_Z |= res;\r
7972\r
7973 m68ki_write_8(ea, res);\r
7974}\r
7975\r
7976\r
7977M68KMAKE_OP(negx, 16, ., d)\r
7978{\r
7979 uint* r_dst = &DY;\r
7980 uint res = 0 - MASK_OUT_ABOVE_16(*r_dst) - XFLAG_AS_1();\r
7981\r
7982 FLAG_N = NFLAG_16(res);\r
7983 FLAG_X = FLAG_C = CFLAG_16(res);\r
7984 FLAG_V = (*r_dst & res)>>8;\r
7985\r
7986 res = MASK_OUT_ABOVE_16(res);\r
7987 FLAG_Z |= res;\r
7988\r
7989 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
7990}\r
7991\r
7992\r
7993M68KMAKE_OP(negx, 16, ., .)\r
7994{\r
7995 uint ea = M68KMAKE_GET_EA_AY_16;\r
7996 uint src = m68ki_read_16(ea);\r
7997 uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1();\r
7998\r
7999 FLAG_N = NFLAG_16(res);\r
8000 FLAG_X = FLAG_C = CFLAG_16(res);\r
8001 FLAG_V = (src & res)>>8;\r
8002\r
8003 res = MASK_OUT_ABOVE_16(res);\r
8004 FLAG_Z |= res;\r
8005\r
8006 m68ki_write_16(ea, res);\r
8007}\r
8008\r
8009\r
8010M68KMAKE_OP(negx, 32, ., d)\r
8011{\r
8012 uint* r_dst = &DY;\r
8013 uint res = 0 - MASK_OUT_ABOVE_32(*r_dst) - XFLAG_AS_1();\r
8014\r
8015 FLAG_N = NFLAG_32(res);\r
8016 FLAG_X = FLAG_C = CFLAG_SUB_32(*r_dst, 0, res);\r
8017 FLAG_V = (*r_dst & res)>>24;\r
8018\r
8019 res = MASK_OUT_ABOVE_32(res);\r
8020 FLAG_Z |= res;\r
8021\r
8022 *r_dst = res;\r
8023}\r
8024\r
8025\r
8026M68KMAKE_OP(negx, 32, ., .)\r
8027{\r
8028 uint ea = M68KMAKE_GET_EA_AY_32;\r
8029 uint src = m68ki_read_32(ea);\r
8030 uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1();\r
8031\r
8032 FLAG_N = NFLAG_32(res);\r
8033 FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res);\r
8034 FLAG_V = (src & res)>>24;\r
8035\r
8036 res = MASK_OUT_ABOVE_32(res);\r
8037 FLAG_Z |= res;\r
8038\r
8039 m68ki_write_32(ea, res);\r
8040}\r
8041\r
8042\r
8043M68KMAKE_OP(nop, 0, ., .)\r
8044{\r
8045 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
8046}\r
8047\r
8048\r
8049M68KMAKE_OP(not, 8, ., d)\r
8050{\r
8051 uint* r_dst = &DY;\r
8052 uint res = MASK_OUT_ABOVE_8(~*r_dst);\r
8053\r
8054 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
8055\r
8056 FLAG_N = NFLAG_8(res);\r
8057 FLAG_Z = res;\r
8058 FLAG_C = CFLAG_CLEAR;\r
8059 FLAG_V = VFLAG_CLEAR;\r
8060}\r
8061\r
8062\r
8063M68KMAKE_OP(not, 8, ., .)\r
8064{\r
8065 uint ea = M68KMAKE_GET_EA_AY_8;\r
8066 uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));\r
8067\r
8068 m68ki_write_8(ea, res);\r
8069\r
8070 FLAG_N = NFLAG_8(res);\r
8071 FLAG_Z = res;\r
8072 FLAG_C = CFLAG_CLEAR;\r
8073 FLAG_V = VFLAG_CLEAR;\r
8074}\r
8075\r
8076\r
8077M68KMAKE_OP(not, 16, ., d)\r
8078{\r
8079 uint* r_dst = &DY;\r
8080 uint res = MASK_OUT_ABOVE_16(~*r_dst);\r
8081\r
8082 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
8083\r
8084 FLAG_N = NFLAG_16(res);\r
8085 FLAG_Z = res;\r
8086 FLAG_C = CFLAG_CLEAR;\r
8087 FLAG_V = VFLAG_CLEAR;\r
8088}\r
8089\r
8090\r
8091M68KMAKE_OP(not, 16, ., .)\r
8092{\r
8093 uint ea = M68KMAKE_GET_EA_AY_16;\r
8094 uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea));\r
8095\r
8096 m68ki_write_16(ea, res);\r
8097\r
8098 FLAG_N = NFLAG_16(res);\r
8099 FLAG_Z = res;\r
8100 FLAG_C = CFLAG_CLEAR;\r
8101 FLAG_V = VFLAG_CLEAR;\r
8102}\r
8103\r
8104\r
8105M68KMAKE_OP(not, 32, ., d)\r
8106{\r
8107 uint* r_dst = &DY;\r
8108 uint res = *r_dst = MASK_OUT_ABOVE_32(~*r_dst);\r
8109\r
8110 FLAG_N = NFLAG_32(res);\r
8111 FLAG_Z = res;\r
8112 FLAG_C = CFLAG_CLEAR;\r
8113 FLAG_V = VFLAG_CLEAR;\r
8114}\r
8115\r
8116\r
8117M68KMAKE_OP(not, 32, ., .)\r
8118{\r
8119 uint ea = M68KMAKE_GET_EA_AY_32;\r
8120 uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea));\r
8121\r
8122 m68ki_write_32(ea, res);\r
8123\r
8124 FLAG_N = NFLAG_32(res);\r
8125 FLAG_Z = res;\r
8126 FLAG_C = CFLAG_CLEAR;\r
8127 FLAG_V = VFLAG_CLEAR;\r
8128}\r
8129\r
8130\r
8131M68KMAKE_OP(or, 8, er, d)\r
8132{\r
8133 uint res = MASK_OUT_ABOVE_8((DX |= MASK_OUT_ABOVE_8(DY)));\r
8134\r
8135 FLAG_N = NFLAG_8(res);\r
8136 FLAG_Z = res;\r
8137 FLAG_C = CFLAG_CLEAR;\r
8138 FLAG_V = VFLAG_CLEAR;\r
8139}\r
8140\r
8141\r
8142M68KMAKE_OP(or, 8, er, .)\r
8143{\r
8144 uint res = MASK_OUT_ABOVE_8((DX |= M68KMAKE_GET_OPER_AY_8));\r
8145\r
8146 FLAG_N = NFLAG_8(res);\r
8147 FLAG_Z = res;\r
8148 FLAG_C = CFLAG_CLEAR;\r
8149 FLAG_V = VFLAG_CLEAR;\r
8150}\r
8151\r
8152\r
8153M68KMAKE_OP(or, 16, er, d)\r
8154{\r
8155 uint res = MASK_OUT_ABOVE_16((DX |= MASK_OUT_ABOVE_16(DY)));\r
8156\r
8157 FLAG_N = NFLAG_16(res);\r
8158 FLAG_Z = res;\r
8159 FLAG_C = CFLAG_CLEAR;\r
8160 FLAG_V = VFLAG_CLEAR;\r
8161}\r
8162\r
8163\r
8164M68KMAKE_OP(or, 16, er, .)\r
8165{\r
8166 uint res = MASK_OUT_ABOVE_16((DX |= M68KMAKE_GET_OPER_AY_16));\r
8167\r
8168 FLAG_N = NFLAG_16(res);\r
8169 FLAG_Z = res;\r
8170 FLAG_C = CFLAG_CLEAR;\r
8171 FLAG_V = VFLAG_CLEAR;\r
8172}\r
8173\r
8174\r
8175M68KMAKE_OP(or, 32, er, d)\r
8176{\r
8177 uint res = DX |= DY;\r
8178\r
8179 FLAG_N = NFLAG_32(res);\r
8180 FLAG_Z = res;\r
8181 FLAG_C = CFLAG_CLEAR;\r
8182 FLAG_V = VFLAG_CLEAR;\r
8183}\r
8184\r
8185\r
8186M68KMAKE_OP(or, 32, er, .)\r
8187{\r
8188 uint res = DX |= M68KMAKE_GET_OPER_AY_32;\r
8189\r
8190 FLAG_N = NFLAG_32(res);\r
8191 FLAG_Z = res;\r
8192 FLAG_C = CFLAG_CLEAR;\r
8193 FLAG_V = VFLAG_CLEAR;\r
8194}\r
8195\r
8196\r
8197M68KMAKE_OP(or, 8, re, .)\r
8198{\r
8199 uint ea = M68KMAKE_GET_EA_AY_8;\r
8200 uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));\r
8201\r
8202 m68ki_write_8(ea, res);\r
8203\r
8204 FLAG_N = NFLAG_8(res);\r
8205 FLAG_Z = res;\r
8206 FLAG_C = CFLAG_CLEAR;\r
8207 FLAG_V = VFLAG_CLEAR;\r
8208}\r
8209\r
8210\r
8211M68KMAKE_OP(or, 16, re, .)\r
8212{\r
8213 uint ea = M68KMAKE_GET_EA_AY_16;\r
8214 uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea));\r
8215\r
8216 m68ki_write_16(ea, res);\r
8217\r
8218 FLAG_N = NFLAG_16(res);\r
8219 FLAG_Z = res;\r
8220 FLAG_C = CFLAG_CLEAR;\r
8221 FLAG_V = VFLAG_CLEAR;\r
8222}\r
8223\r
8224\r
8225M68KMAKE_OP(or, 32, re, .)\r
8226{\r
8227 uint ea = M68KMAKE_GET_EA_AY_32;\r
8228 uint res = DX | m68ki_read_32(ea);\r
8229\r
8230 m68ki_write_32(ea, res);\r
8231\r
8232 FLAG_N = NFLAG_32(res);\r
8233 FLAG_Z = res;\r
8234 FLAG_C = CFLAG_CLEAR;\r
8235 FLAG_V = VFLAG_CLEAR;\r
8236}\r
8237\r
8238\r
8239M68KMAKE_OP(ori, 8, ., d)\r
8240{\r
8241 uint res = MASK_OUT_ABOVE_8((DY |= OPER_I_8()));\r
8242\r
8243 FLAG_N = NFLAG_8(res);\r
8244 FLAG_Z = res;\r
8245 FLAG_C = CFLAG_CLEAR;\r
8246 FLAG_V = VFLAG_CLEAR;\r
8247}\r
8248\r
8249\r
8250M68KMAKE_OP(ori, 8, ., .)\r
8251{\r
8252 uint src = OPER_I_8();\r
8253 uint ea = M68KMAKE_GET_EA_AY_8;\r
8254 uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));\r
8255\r
8256 m68ki_write_8(ea, res);\r
8257\r
8258 FLAG_N = NFLAG_8(res);\r
8259 FLAG_Z = res;\r
8260 FLAG_C = CFLAG_CLEAR;\r
8261 FLAG_V = VFLAG_CLEAR;\r
8262}\r
8263\r
8264\r
8265M68KMAKE_OP(ori, 16, ., d)\r
8266{\r
8267 uint res = MASK_OUT_ABOVE_16(DY |= OPER_I_16());\r
8268\r
8269 FLAG_N = NFLAG_16(res);\r
8270 FLAG_Z = res;\r
8271 FLAG_C = CFLAG_CLEAR;\r
8272 FLAG_V = VFLAG_CLEAR;\r
8273}\r
8274\r
8275\r
8276M68KMAKE_OP(ori, 16, ., .)\r
8277{\r
8278 uint src = OPER_I_16();\r
8279 uint ea = M68KMAKE_GET_EA_AY_16;\r
8280 uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea));\r
8281\r
8282 m68ki_write_16(ea, res);\r
8283\r
8284 FLAG_N = NFLAG_16(res);\r
8285 FLAG_Z = res;\r
8286 FLAG_C = CFLAG_CLEAR;\r
8287 FLAG_V = VFLAG_CLEAR;\r
8288}\r
8289\r
8290\r
8291M68KMAKE_OP(ori, 32, ., d)\r
8292{\r
8293 uint res = DY |= OPER_I_32();\r
8294\r
8295 FLAG_N = NFLAG_32(res);\r
8296 FLAG_Z = res;\r
8297 FLAG_C = CFLAG_CLEAR;\r
8298 FLAG_V = VFLAG_CLEAR;\r
8299}\r
8300\r
8301\r
8302M68KMAKE_OP(ori, 32, ., .)\r
8303{\r
8304 uint src = OPER_I_32();\r
8305 uint ea = M68KMAKE_GET_EA_AY_32;\r
8306 uint res = src | m68ki_read_32(ea);\r
8307\r
8308 m68ki_write_32(ea, res);\r
8309\r
8310 FLAG_N = NFLAG_32(res);\r
8311 FLAG_Z = res;\r
8312 FLAG_C = CFLAG_CLEAR;\r
8313 FLAG_V = VFLAG_CLEAR;\r
8314}\r
8315\r
8316\r
8317M68KMAKE_OP(ori, 16, toc, .)\r
8318{\r
8319 m68ki_set_ccr(m68ki_get_ccr() | OPER_I_16());\r
8320}\r
8321\r
8322\r
8323M68KMAKE_OP(ori, 16, tos, .)\r
8324{\r
8325 if(FLAG_S)\r
8326 {\r
8327 uint src = OPER_I_16();\r
8328 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
8329 m68ki_set_sr(m68ki_get_sr() | src);\r
8330 return;\r
8331 }\r
8332 m68ki_exception_privilege_violation();\r
8333}\r
8334\r
8335\r
8336M68KMAKE_OP(pack, 16, rr, .)\r
8337{\r
8338 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
8339 {\r
8340 /* Note: DX and DY are reversed in Motorola's docs */\r
8341 uint src = DY + OPER_I_16();\r
8342 uint* r_dst = &DX;\r
8343\r
8344 *r_dst = MASK_OUT_BELOW_8(*r_dst) | ((src >> 4) & 0x00f0) | (src & 0x000f);\r
8345 return;\r
8346 }\r
8347 m68ki_exception_illegal();\r
8348}\r
8349\r
8350\r
8351M68KMAKE_OP(pack, 16, mm, ax7)\r
8352{\r
8353 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
8354 {\r
8355 /* Note: AX and AY are reversed in Motorola's docs */\r
8356 uint ea_src = EA_AY_PD_8();\r
8357 uint src = m68ki_read_8(ea_src);\r
8358 ea_src = EA_AY_PD_8();\r
8359 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();\r
8360\r
8361 m68ki_write_8(EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));\r
8362 return;\r
8363 }\r
8364 m68ki_exception_illegal();\r
8365}\r
8366\r
8367\r
8368M68KMAKE_OP(pack, 16, mm, ay7)\r
8369{\r
8370 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
8371 {\r
8372 /* Note: AX and AY are reversed in Motorola's docs */\r
8373 uint ea_src = EA_A7_PD_8();\r
8374 uint src = m68ki_read_8(ea_src);\r
8375 ea_src = EA_A7_PD_8();\r
8376 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();\r
8377\r
8378 m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));\r
8379 return;\r
8380 }\r
8381 m68ki_exception_illegal();\r
8382}\r
8383\r
8384\r
8385M68KMAKE_OP(pack, 16, mm, axy7)\r
8386{\r
8387 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
8388 {\r
8389 uint ea_src = EA_A7_PD_8();\r
8390 uint src = m68ki_read_8(ea_src);\r
8391 ea_src = EA_A7_PD_8();\r
8392 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();\r
8393\r
8394 m68ki_write_8(EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));\r
8395 return;\r
8396 }\r
8397 m68ki_exception_illegal();\r
8398}\r
8399\r
8400\r
8401M68KMAKE_OP(pack, 16, mm, .)\r
8402{\r
8403 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
8404 {\r
8405 /* Note: AX and AY are reversed in Motorola's docs */\r
8406 uint ea_src = EA_AY_PD_8();\r
8407 uint src = m68ki_read_8(ea_src);\r
8408 ea_src = EA_AY_PD_8();\r
8409 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();\r
8410\r
8411 m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));\r
8412 return;\r
8413 }\r
8414 m68ki_exception_illegal();\r
8415}\r
8416\r
8417\r
8418M68KMAKE_OP(pea, 32, ., .)\r
8419{\r
8420 uint ea = M68KMAKE_GET_EA_AY_32;\r
8421\r
8422 m68ki_push_32(ea);\r
8423}\r
8424\r
8425\r
8426M68KMAKE_OP(pflush, 32, ., .)\r
8427{\r
8428 if(CPU_TYPE_IS_040_PLUS(CPU_TYPE))\r
8429 {\r
8430 // Nothing to do, unless address translation cache is emulated\r
8431 return;\r
8432 }\r
8433 m68ki_exception_illegal();\r
8434}\r
8435\r
8436\r
8437M68KMAKE_OP(reset, 0, ., .)\r
8438{\r
8439 if(FLAG_S)\r
8440 {\r
8441 m68ki_output_reset(); /* auto-disable (see m68kcpu.h) */\r
8442 USE_CYCLES(CYC_RESET);\r
8443 return;\r
8444 }\r
8445 m68ki_exception_privilege_violation();\r
8446}\r
8447\r
8448\r
8449M68KMAKE_OP(ror, 8, s, .)\r
8450{\r
8451 uint* r_dst = &DY;\r
8452 uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
8453 uint shift = orig_shift & 7;\r
8454 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
8455 uint res = ROR_8(src, shift);\r
8456\r
8457 if(orig_shift != 0)\r
8458 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8459\r
8460 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
8461\r
8462 FLAG_N = NFLAG_8(res);\r
8463 FLAG_Z = res;\r
8464 FLAG_C = src << (9-orig_shift);\r
8465 FLAG_V = VFLAG_CLEAR;\r
8466}\r
8467\r
8468\r
8469M68KMAKE_OP(ror, 16, s, .)\r
8470{\r
8471 uint* r_dst = &DY;\r
8472 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
8473 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
8474 uint res = ROR_16(src, shift);\r
8475\r
8476 if(shift != 0)\r
8477 USE_CYCLES(shift<<CYC_SHIFT);\r
8478\r
8479 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
8480\r
8481 FLAG_N = NFLAG_16(res);\r
8482 FLAG_Z = res;\r
8483 FLAG_C = src << (9-shift);\r
8484 FLAG_V = VFLAG_CLEAR;\r
8485}\r
8486\r
8487\r
8488M68KMAKE_OP(ror, 32, s, .)\r
8489{\r
8490 uint* r_dst = &DY;\r
8491 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
8492 uint64 src = *r_dst;\r
8493 uint res = ROR_32(src, shift);\r
8494\r
8495 if(shift != 0)\r
8496 USE_CYCLES(shift<<CYC_SHIFT);\r
8497\r
8498 *r_dst = res;\r
8499\r
8500 FLAG_N = NFLAG_32(res);\r
8501 FLAG_Z = res;\r
8502 FLAG_C = src << (9-shift);\r
8503 FLAG_V = VFLAG_CLEAR;\r
8504}\r
8505\r
8506\r
8507M68KMAKE_OP(ror, 8, r, .)\r
8508{\r
8509 uint* r_dst = &DY;\r
8510 uint orig_shift = DX & 0x3f;\r
8511 uint shift = orig_shift & 7;\r
8512 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
8513 uint res = ROR_8(src, shift);\r
8514\r
8515 if(orig_shift != 0)\r
8516 {\r
8517 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8518\r
8519 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
8520 FLAG_C = src << (8-((shift-1)&7));\r
8521 FLAG_N = NFLAG_8(res);\r
8522 FLAG_Z = res;\r
8523 FLAG_V = VFLAG_CLEAR;\r
8524 return;\r
8525 }\r
8526\r
8527 FLAG_C = CFLAG_CLEAR;\r
8528 FLAG_N = NFLAG_8(src);\r
8529 FLAG_Z = src;\r
8530 FLAG_V = VFLAG_CLEAR;\r
8531}\r
8532\r
8533\r
8534M68KMAKE_OP(ror, 16, r, .)\r
8535{\r
8536 uint* r_dst = &DY;\r
8537 uint orig_shift = DX & 0x3f;\r
8538 uint shift = orig_shift & 15;\r
8539 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
8540 uint res = ROR_16(src, shift);\r
8541\r
8542 if(orig_shift != 0)\r
8543 {\r
8544 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8545\r
8546 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
8547 FLAG_C = (src >> ((shift - 1) & 15)) << 8;\r
8548 FLAG_N = NFLAG_16(res);\r
8549 FLAG_Z = res;\r
8550 FLAG_V = VFLAG_CLEAR;\r
8551 return;\r
8552 }\r
8553\r
8554 FLAG_C = CFLAG_CLEAR;\r
8555 FLAG_N = NFLAG_16(src);\r
8556 FLAG_Z = src;\r
8557 FLAG_V = VFLAG_CLEAR;\r
8558}\r
8559\r
8560\r
8561M68KMAKE_OP(ror, 32, r, .)\r
8562{\r
8563 uint* r_dst = &DY;\r
8564 uint orig_shift = DX & 0x3f;\r
8565 uint shift = orig_shift & 31;\r
8566 uint64 src = *r_dst;\r
8567 uint res = ROR_32(src, shift);\r
8568\r
8569 if(orig_shift != 0)\r
8570 {\r
8571 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8572\r
8573 *r_dst = res;\r
8574 FLAG_C = (src >> ((shift - 1) & 31)) << 8;\r
8575 FLAG_N = NFLAG_32(res);\r
8576 FLAG_Z = res;\r
8577 FLAG_V = VFLAG_CLEAR;\r
8578 return;\r
8579 }\r
8580\r
8581 FLAG_C = CFLAG_CLEAR;\r
8582 FLAG_N = NFLAG_32(src);\r
8583 FLAG_Z = src;\r
8584 FLAG_V = VFLAG_CLEAR;\r
8585}\r
8586\r
8587\r
8588M68KMAKE_OP(ror, 16, ., .)\r
8589{\r
8590 uint ea = M68KMAKE_GET_EA_AY_16;\r
8591 uint src = m68ki_read_16(ea);\r
8592 uint res = ROR_16(src, 1);\r
8593\r
8594 m68ki_write_16(ea, res);\r
8595\r
8596 FLAG_N = NFLAG_16(res);\r
8597 FLAG_Z = res;\r
8598 FLAG_C = src << 8;\r
8599 FLAG_V = VFLAG_CLEAR;\r
8600}\r
8601\r
8602\r
8603M68KMAKE_OP(rol, 8, s, .)\r
8604{\r
8605 uint* r_dst = &DY;\r
8606 uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
8607 uint shift = orig_shift & 7;\r
8608 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
8609 uint res = ROL_8(src, shift);\r
8610\r
8611 if(orig_shift != 0)\r
8612 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8613\r
8614 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
8615\r
8616 FLAG_N = NFLAG_8(res);\r
8617 FLAG_Z = res;\r
8618 FLAG_C = src << orig_shift;\r
8619 FLAG_V = VFLAG_CLEAR;\r
8620}\r
8621\r
8622\r
8623M68KMAKE_OP(rol, 16, s, .)\r
8624{\r
8625 uint* r_dst = &DY;\r
8626 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
8627 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
8628 uint res = ROL_16(src, shift);\r
8629\r
8630 if(shift != 0)\r
8631 USE_CYCLES(shift<<CYC_SHIFT);\r
8632\r
8633 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
8634\r
8635 FLAG_N = NFLAG_16(res);\r
8636 FLAG_Z = res;\r
8637 FLAG_C = src >> (8-shift);\r
8638 FLAG_V = VFLAG_CLEAR;\r
8639}\r
8640\r
8641\r
8642M68KMAKE_OP(rol, 32, s, .)\r
8643{\r
8644 uint* r_dst = &DY;\r
8645 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
8646 uint64 src = *r_dst;\r
8647 uint res = ROL_32(src, shift);\r
8648\r
8649 if(shift != 0)\r
8650 USE_CYCLES(shift<<CYC_SHIFT);\r
8651\r
8652 *r_dst = res;\r
8653\r
8654 FLAG_N = NFLAG_32(res);\r
8655 FLAG_Z = res;\r
8656 FLAG_C = src >> (24-shift);\r
8657 FLAG_V = VFLAG_CLEAR;\r
8658}\r
8659\r
8660\r
8661M68KMAKE_OP(rol, 8, r, .)\r
8662{\r
8663 uint* r_dst = &DY;\r
8664 uint orig_shift = DX & 0x3f;\r
8665 uint shift = orig_shift & 7;\r
8666 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
8667 uint res = ROL_8(src, shift);\r
8668\r
8669 if(orig_shift != 0)\r
8670 {\r
8671 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8672\r
8673 if(shift != 0)\r
8674 {\r
8675 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
8676 FLAG_C = src << shift;\r
8677 FLAG_N = NFLAG_8(res);\r
8678 FLAG_Z = res;\r
8679 FLAG_V = VFLAG_CLEAR;\r
8680 return;\r
8681 }\r
8682 FLAG_C = (src & 1)<<8;\r
8683 FLAG_N = NFLAG_8(src);\r
8684 FLAG_Z = src;\r
8685 FLAG_V = VFLAG_CLEAR;\r
8686 return;\r
8687 }\r
8688\r
8689 FLAG_C = CFLAG_CLEAR;\r
8690 FLAG_N = NFLAG_8(src);\r
8691 FLAG_Z = src;\r
8692 FLAG_V = VFLAG_CLEAR;\r
8693}\r
8694\r
8695\r
8696M68KMAKE_OP(rol, 16, r, .)\r
8697{\r
8698 uint* r_dst = &DY;\r
8699 uint orig_shift = DX & 0x3f;\r
8700 uint shift = orig_shift & 15;\r
8701 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
8702 uint res = MASK_OUT_ABOVE_16(ROL_16(src, shift));\r
8703\r
8704 if(orig_shift != 0)\r
8705 {\r
8706 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8707\r
8708 if(shift != 0)\r
8709 {\r
8710 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
8711 FLAG_C = (src << shift) >> 8;\r
8712 FLAG_N = NFLAG_16(res);\r
8713 FLAG_Z = res;\r
8714 FLAG_V = VFLAG_CLEAR;\r
8715 return;\r
8716 }\r
8717 FLAG_C = (src & 1)<<8;\r
8718 FLAG_N = NFLAG_16(src);\r
8719 FLAG_Z = src;\r
8720 FLAG_V = VFLAG_CLEAR;\r
8721 return;\r
8722 }\r
8723\r
8724 FLAG_C = CFLAG_CLEAR;\r
8725 FLAG_N = NFLAG_16(src);\r
8726 FLAG_Z = src;\r
8727 FLAG_V = VFLAG_CLEAR;\r
8728}\r
8729\r
8730\r
8731M68KMAKE_OP(rol, 32, r, .)\r
8732{\r
8733 uint* r_dst = &DY;\r
8734 uint orig_shift = DX & 0x3f;\r
8735 uint shift = orig_shift & 31;\r
8736 uint64 src = *r_dst;\r
8737 uint res = ROL_32(src, shift);\r
8738\r
8739 if(orig_shift != 0)\r
8740 {\r
8741 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8742\r
8743 *r_dst = res;\r
8744\r
c6a4c892 8745 FLAG_C = (src >> ((32 - shift) & 0x1f)) << 8;\r
cc68a136 8746 FLAG_N = NFLAG_32(res);\r
8747 FLAG_Z = res;\r
8748 FLAG_V = VFLAG_CLEAR;\r
8749 return;\r
8750 }\r
8751\r
8752 FLAG_C = CFLAG_CLEAR;\r
8753 FLAG_N = NFLAG_32(src);\r
8754 FLAG_Z = src;\r
8755 FLAG_V = VFLAG_CLEAR;\r
8756}\r
8757\r
8758\r
8759M68KMAKE_OP(rol, 16, ., .)\r
8760{\r
8761 uint ea = M68KMAKE_GET_EA_AY_16;\r
8762 uint src = m68ki_read_16(ea);\r
8763 uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1));\r
8764\r
8765 m68ki_write_16(ea, res);\r
8766\r
8767 FLAG_N = NFLAG_16(res);\r
8768 FLAG_Z = res;\r
8769 FLAG_C = src >> 7;\r
8770 FLAG_V = VFLAG_CLEAR;\r
8771}\r
8772\r
8773\r
8774M68KMAKE_OP(roxr, 8, s, .)\r
8775{\r
8776 uint* r_dst = &DY;\r
8777 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
8778 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
8779 uint res = ROR_9(src | (XFLAG_AS_1() << 8), shift);\r
8780\r
8781 if(shift != 0)\r
8782 USE_CYCLES(shift<<CYC_SHIFT);\r
8783\r
8784 FLAG_C = FLAG_X = res;\r
8785 res = MASK_OUT_ABOVE_8(res);\r
8786\r
8787 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
8788\r
8789 FLAG_N = NFLAG_8(res);\r
8790 FLAG_Z = res;\r
8791 FLAG_V = VFLAG_CLEAR;\r
8792}\r
8793\r
8794\r
8795M68KMAKE_OP(roxr, 16, s, .)\r
8796{\r
8797 uint* r_dst = &DY;\r
8798 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
8799 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
8800 uint res = ROR_17(src | (XFLAG_AS_1() << 16), shift);\r
8801\r
8802 if(shift != 0)\r
8803 USE_CYCLES(shift<<CYC_SHIFT);\r
8804\r
8805 FLAG_C = FLAG_X = res >> 8;\r
8806 res = MASK_OUT_ABOVE_16(res);\r
8807\r
8808 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
8809\r
8810 FLAG_N = NFLAG_16(res);\r
8811 FLAG_Z = res;\r
8812 FLAG_V = VFLAG_CLEAR;\r
8813}\r
8814\r
8815\r
8816M68KMAKE_OP(roxr, 32, s, .)\r
8817{\r
8818#if M68K_USE_64_BIT\r
8819\r
8820 uint* r_dst = &DY;\r
8821 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
8822 uint64 src = *r_dst;\r
8823 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);\r
8824\r
8825 if(shift != 0)\r
8826 USE_CYCLES(shift<<CYC_SHIFT);\r
8827\r
8828 res = ROR_33_64(res, shift);\r
8829\r
8830 FLAG_C = FLAG_X = res >> 24;\r
8831 res = MASK_OUT_ABOVE_32(res);\r
8832\r
8833 *r_dst = res;\r
8834\r
8835 FLAG_N = NFLAG_32(res);\r
8836 FLAG_Z = res;\r
8837 FLAG_V = VFLAG_CLEAR;\r
8838\r
8839#else\r
8840\r
8841 uint* r_dst = &DY;\r
8842 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
8843 uint src = *r_dst;\r
8844 uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift)));\r
8845 uint new_x_flag = src & (1 << (shift - 1));\r
8846\r
8847 if(shift != 0)\r
8848 USE_CYCLES(shift<<CYC_SHIFT);\r
8849\r
8850 *r_dst = res;\r
8851\r
8852 FLAG_C = FLAG_X = (new_x_flag != 0)<<8;\r
8853 FLAG_N = NFLAG_32(res);\r
8854 FLAG_Z = res;\r
8855 FLAG_V = VFLAG_CLEAR;\r
8856\r
8857#endif\r
8858}\r
8859\r
8860\r
8861M68KMAKE_OP(roxr, 8, r, .)\r
8862{\r
8863 uint* r_dst = &DY;\r
8864 uint orig_shift = DX & 0x3f;\r
8865\r
8866 if(orig_shift != 0)\r
8867 {\r
8868 uint shift = orig_shift % 9;\r
8869 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
8870 uint res = ROR_9(src | (XFLAG_AS_1() << 8), shift);\r
8871\r
8872 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8873\r
8874 FLAG_C = FLAG_X = res;\r
8875 res = MASK_OUT_ABOVE_8(res);\r
8876\r
8877 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
8878 FLAG_N = NFLAG_8(res);\r
8879 FLAG_Z = res;\r
8880 FLAG_V = VFLAG_CLEAR;\r
8881 return;\r
8882 }\r
8883\r
8884 FLAG_C = FLAG_X;\r
8885 FLAG_N = NFLAG_8(*r_dst);\r
8886 FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);\r
8887 FLAG_V = VFLAG_CLEAR;\r
8888}\r
8889\r
8890\r
8891M68KMAKE_OP(roxr, 16, r, .)\r
8892{\r
8893 uint* r_dst = &DY;\r
8894 uint orig_shift = DX & 0x3f;\r
8895\r
8896 if(orig_shift != 0)\r
8897 {\r
8898 uint shift = orig_shift % 17;\r
8899 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
8900 uint res = ROR_17(src | (XFLAG_AS_1() << 16), shift);\r
8901\r
8902 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8903\r
8904 FLAG_C = FLAG_X = res >> 8;\r
8905 res = MASK_OUT_ABOVE_16(res);\r
8906\r
8907 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
8908 FLAG_N = NFLAG_16(res);\r
8909 FLAG_Z = res;\r
8910 FLAG_V = VFLAG_CLEAR;\r
8911 return;\r
8912 }\r
8913\r
8914 FLAG_C = FLAG_X;\r
8915 FLAG_N = NFLAG_16(*r_dst);\r
8916 FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);\r
8917 FLAG_V = VFLAG_CLEAR;\r
8918}\r
8919\r
8920\r
8921M68KMAKE_OP(roxr, 32, r, .)\r
8922{\r
8923#if M68K_USE_64_BIT\r
8924\r
8925 uint* r_dst = &DY;\r
8926 uint orig_shift = DX & 0x3f;\r
8927\r
8928 if(orig_shift != 0)\r
8929 {\r
8930 uint shift = orig_shift % 33;\r
8931 uint64 src = *r_dst;\r
8932 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);\r
8933\r
8934 res = ROR_33_64(res, shift);\r
8935\r
8936 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8937\r
8938 FLAG_C = FLAG_X = res >> 24;\r
8939 res = MASK_OUT_ABOVE_32(res);\r
8940\r
8941 *r_dst = res;\r
8942 FLAG_N = NFLAG_32(res);\r
8943 FLAG_Z = res;\r
8944 FLAG_V = VFLAG_CLEAR;\r
8945 return;\r
8946 }\r
8947\r
8948 FLAG_C = FLAG_X;\r
8949 FLAG_N = NFLAG_32(*r_dst);\r
8950 FLAG_Z = *r_dst;\r
8951 FLAG_V = VFLAG_CLEAR;\r
8952\r
8953#else\r
8954\r
8955 uint* r_dst = &DY;\r
8956 uint orig_shift = DX & 0x3f;\r
8957 uint shift = orig_shift % 33;\r
8958 uint src = *r_dst;\r
8959 uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift)));\r
8960 uint new_x_flag = src & (1 << (shift - 1));\r
8961\r
8962 if(orig_shift != 0)\r
8963 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
8964\r
8965 if(shift != 0)\r
8966 {\r
8967 *r_dst = res;\r
8968 FLAG_X = (new_x_flag != 0)<<8;\r
8969 }\r
8970 else\r
8971 res = src;\r
8972 FLAG_C = FLAG_X;\r
8973 FLAG_N = NFLAG_32(res);\r
8974 FLAG_Z = res;\r
8975 FLAG_V = VFLAG_CLEAR;\r
8976\r
8977#endif\r
8978}\r
8979\r
8980\r
8981M68KMAKE_OP(roxr, 16, ., .)\r
8982{\r
8983 uint ea = M68KMAKE_GET_EA_AY_16;\r
8984 uint src = m68ki_read_16(ea);\r
8985 uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1);\r
8986\r
8987 FLAG_C = FLAG_X = res >> 8;\r
8988 res = MASK_OUT_ABOVE_16(res);\r
8989\r
8990 m68ki_write_16(ea, res);\r
8991\r
8992 FLAG_N = NFLAG_16(res);\r
8993 FLAG_Z = res;\r
8994 FLAG_V = VFLAG_CLEAR;\r
8995}\r
8996\r
8997\r
8998M68KMAKE_OP(roxl, 8, s, .)\r
8999{\r
9000 uint* r_dst = &DY;\r
9001 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
9002 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
9003 uint res = ROL_9(src | (XFLAG_AS_1() << 8), shift);\r
9004\r
9005 if(shift != 0)\r
9006 USE_CYCLES(shift<<CYC_SHIFT);\r
9007\r
9008 FLAG_C = FLAG_X = res;\r
9009 res = MASK_OUT_ABOVE_8(res);\r
9010\r
9011 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
9012\r
9013 FLAG_N = NFLAG_8(res);\r
9014 FLAG_Z = res;\r
9015 FLAG_V = VFLAG_CLEAR;\r
9016}\r
9017\r
9018\r
9019M68KMAKE_OP(roxl, 16, s, .)\r
9020{\r
9021 uint* r_dst = &DY;\r
9022 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
9023 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
9024 uint res = ROL_17(src | (XFLAG_AS_1() << 16), shift);\r
9025\r
9026 if(shift != 0)\r
9027 USE_CYCLES(shift<<CYC_SHIFT);\r
9028\r
9029 FLAG_C = FLAG_X = res >> 8;\r
9030 res = MASK_OUT_ABOVE_16(res);\r
9031\r
9032 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
9033\r
9034 FLAG_N = NFLAG_16(res);\r
9035 FLAG_Z = res;\r
9036 FLAG_V = VFLAG_CLEAR;\r
9037}\r
9038\r
9039\r
9040M68KMAKE_OP(roxl, 32, s, .)\r
9041{\r
9042#if M68K_USE_64_BIT\r
9043\r
9044 uint* r_dst = &DY;\r
9045 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
9046 uint64 src = *r_dst;\r
9047 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);\r
9048\r
9049 if(shift != 0)\r
9050 USE_CYCLES(shift<<CYC_SHIFT);\r
9051\r
9052 res = ROL_33_64(res, shift);\r
9053\r
9054 FLAG_C = FLAG_X = res >> 24;\r
9055 res = MASK_OUT_ABOVE_32(res);\r
9056\r
9057 *r_dst = res;\r
9058\r
9059 FLAG_N = NFLAG_32(res);\r
9060 FLAG_Z = res;\r
9061 FLAG_V = VFLAG_CLEAR;\r
9062\r
9063#else\r
9064\r
9065 uint* r_dst = &DY;\r
9066 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;\r
9067 uint src = *r_dst;\r
9068 uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1)));\r
9069 uint new_x_flag = src & (1 << (32 - shift));\r
9070\r
9071 if(shift != 0)\r
9072 USE_CYCLES(shift<<CYC_SHIFT);\r
9073\r
9074 *r_dst = res;\r
9075\r
9076 FLAG_C = FLAG_X = (new_x_flag != 0)<<8;\r
9077 FLAG_N = NFLAG_32(res);\r
9078 FLAG_Z = res;\r
9079 FLAG_V = VFLAG_CLEAR;\r
9080\r
9081#endif\r
9082}\r
9083\r
9084\r
9085M68KMAKE_OP(roxl, 8, r, .)\r
9086{\r
9087 uint* r_dst = &DY;\r
9088 uint orig_shift = DX & 0x3f;\r
9089\r
9090\r
9091 if(orig_shift != 0)\r
9092 {\r
9093 uint shift = orig_shift % 9;\r
9094 uint src = MASK_OUT_ABOVE_8(*r_dst);\r
9095 uint res = ROL_9(src | (XFLAG_AS_1() << 8), shift);\r
9096\r
9097 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
9098\r
9099 FLAG_C = FLAG_X = res;\r
9100 res = MASK_OUT_ABOVE_8(res);\r
9101\r
9102 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
9103 FLAG_N = NFLAG_8(res);\r
9104 FLAG_Z = res;\r
9105 FLAG_V = VFLAG_CLEAR;\r
9106 return;\r
9107 }\r
9108\r
9109 FLAG_C = FLAG_X;\r
9110 FLAG_N = NFLAG_8(*r_dst);\r
9111 FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);\r
9112 FLAG_V = VFLAG_CLEAR;\r
9113}\r
9114\r
9115\r
9116M68KMAKE_OP(roxl, 16, r, .)\r
9117{\r
9118 uint* r_dst = &DY;\r
9119 uint orig_shift = DX & 0x3f;\r
9120\r
9121 if(orig_shift != 0)\r
9122 {\r
9123 uint shift = orig_shift % 17;\r
9124 uint src = MASK_OUT_ABOVE_16(*r_dst);\r
9125 uint res = ROL_17(src | (XFLAG_AS_1() << 16), shift);\r
9126\r
9127 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
9128\r
9129 FLAG_C = FLAG_X = res >> 8;\r
9130 res = MASK_OUT_ABOVE_16(res);\r
9131\r
9132 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
9133 FLAG_N = NFLAG_16(res);\r
9134 FLAG_Z = res;\r
9135 FLAG_V = VFLAG_CLEAR;\r
9136 return;\r
9137 }\r
9138\r
9139 FLAG_C = FLAG_X;\r
9140 FLAG_N = NFLAG_16(*r_dst);\r
9141 FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);\r
9142 FLAG_V = VFLAG_CLEAR;\r
9143}\r
9144\r
9145\r
9146M68KMAKE_OP(roxl, 32, r, .)\r
9147{\r
9148#if M68K_USE_64_BIT\r
9149\r
9150 uint* r_dst = &DY;\r
9151 uint orig_shift = DX & 0x3f;\r
9152\r
9153 if(orig_shift != 0)\r
9154 {\r
9155 uint shift = orig_shift % 33;\r
9156 uint64 src = *r_dst;\r
9157 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);\r
9158\r
9159 res = ROL_33_64(res, shift);\r
9160\r
9161 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
9162\r
9163 FLAG_C = FLAG_X = res >> 24;\r
9164 res = MASK_OUT_ABOVE_32(res);\r
9165\r
9166 *r_dst = res;\r
9167 FLAG_N = NFLAG_32(res);\r
9168 FLAG_Z = res;\r
9169 FLAG_V = VFLAG_CLEAR;\r
9170 return;\r
9171 }\r
9172\r
9173 FLAG_C = FLAG_X;\r
9174 FLAG_N = NFLAG_32(*r_dst);\r
9175 FLAG_Z = *r_dst;\r
9176 FLAG_V = VFLAG_CLEAR;\r
9177\r
9178#else\r
9179\r
9180 uint* r_dst = &DY;\r
9181 uint orig_shift = DX & 0x3f;\r
9182 uint shift = orig_shift % 33;\r
9183 uint src = *r_dst;\r
9184 uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1)));\r
9185 uint new_x_flag = src & (1 << (32 - shift));\r
9186\r
9187 if(orig_shift != 0)\r
9188 USE_CYCLES(orig_shift<<CYC_SHIFT);\r
9189\r
9190 if(shift != 0)\r
9191 {\r
9192 *r_dst = res;\r
9193 FLAG_X = (new_x_flag != 0)<<8;\r
9194 }\r
9195 else\r
9196 res = src;\r
9197 FLAG_C = FLAG_X;\r
9198 FLAG_N = NFLAG_32(res);\r
9199 FLAG_Z = res;\r
9200 FLAG_V = VFLAG_CLEAR;\r
9201\r
9202#endif\r
9203}\r
9204\r
9205\r
9206M68KMAKE_OP(roxl, 16, ., .)\r
9207{\r
9208 uint ea = M68KMAKE_GET_EA_AY_16;\r
9209 uint src = m68ki_read_16(ea);\r
9210 uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1);\r
9211\r
9212 FLAG_C = FLAG_X = res >> 8;\r
9213 res = MASK_OUT_ABOVE_16(res);\r
9214\r
9215 m68ki_write_16(ea, res);\r
9216\r
9217 FLAG_N = NFLAG_16(res);\r
9218 FLAG_Z = res;\r
9219 FLAG_V = VFLAG_CLEAR;\r
9220}\r
9221\r
9222\r
9223M68KMAKE_OP(rtd, 32, ., .)\r
9224{\r
9225 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))\r
9226 {\r
9227 uint new_pc = m68ki_pull_32();\r
9228\r
9229 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
9230 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));\r
9231 m68ki_jump(new_pc);\r
9232 return;\r
9233 }\r
9234 m68ki_exception_illegal();\r
9235}\r
9236\r
9237\r
9238M68KMAKE_OP(rte, 32, ., .)\r
9239{\r
9240 if(FLAG_S)\r
9241 {\r
9242 uint new_sr;\r
9243 uint new_pc;\r
9244 uint format_word;\r
9245\r
9246 m68ki_rte_callback(); /* auto-disable (see m68kcpu.h) */\r
9247 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
9248\r
9249 if(CPU_TYPE_IS_000(CPU_TYPE))\r
9250 {\r
9251 new_sr = m68ki_pull_16();\r
9252 new_pc = m68ki_pull_32();\r
9253 m68ki_jump(new_pc);\r
9254 m68ki_set_sr(new_sr);\r
9255\r
9256 CPU_INSTR_MODE = INSTRUCTION_YES;\r
9257 CPU_RUN_MODE = RUN_MODE_NORMAL;\r
9258\r
9259 return;\r
9260 }\r
9261\r
9262 if(CPU_TYPE_IS_010(CPU_TYPE))\r
9263 {\r
9264 format_word = m68ki_read_16(REG_A[7]+6) >> 12;\r
9265 if(format_word == 0)\r
9266 {\r
9267 new_sr = m68ki_pull_16();\r
9268 new_pc = m68ki_pull_32();\r
9269 m68ki_fake_pull_16(); /* format word */\r
9270 m68ki_jump(new_pc);\r
9271 m68ki_set_sr(new_sr);\r
9272 CPU_INSTR_MODE = INSTRUCTION_YES;\r
9273 CPU_RUN_MODE = RUN_MODE_NORMAL;\r
9274 return;\r
9275 }\r
9276 CPU_INSTR_MODE = INSTRUCTION_YES;\r
9277 CPU_RUN_MODE = RUN_MODE_NORMAL;\r
9278 /* Not handling bus fault (9) */\r
9279 m68ki_exception_format_error();\r
9280 return;\r
9281 }\r
9282\r
9283 /* Otherwise it's 020 */\r
9284rte_loop:\r
9285 format_word = m68ki_read_16(REG_A[7]+6) >> 12;\r
9286 switch(format_word)\r
9287 {\r
9288 case 0: /* Normal */\r
9289 new_sr = m68ki_pull_16();\r
9290 new_pc = m68ki_pull_32();\r
9291 m68ki_fake_pull_16(); /* format word */\r
9292 m68ki_jump(new_pc);\r
9293 m68ki_set_sr(new_sr);\r
9294 CPU_INSTR_MODE = INSTRUCTION_YES;\r
9295 CPU_RUN_MODE = RUN_MODE_NORMAL;\r
9296 return;\r
9297 case 1: /* Throwaway */\r
9298 new_sr = m68ki_pull_16();\r
9299 m68ki_fake_pull_32(); /* program counter */\r
9300 m68ki_fake_pull_16(); /* format word */\r
9301 m68ki_set_sr_noint(new_sr);\r
9302 goto rte_loop;\r
9303 case 2: /* Trap */\r
9304 new_sr = m68ki_pull_16();\r
9305 new_pc = m68ki_pull_32();\r
9306 m68ki_fake_pull_16(); /* format word */\r
9307 m68ki_fake_pull_32(); /* address */\r
9308 m68ki_jump(new_pc);\r
9309 m68ki_set_sr(new_sr);\r
9310 CPU_INSTR_MODE = INSTRUCTION_YES;\r
9311 CPU_RUN_MODE = RUN_MODE_NORMAL;\r
9312 return;\r
9313 }\r
9314 /* Not handling long or short bus fault */\r
9315 CPU_INSTR_MODE = INSTRUCTION_YES;\r
9316 CPU_RUN_MODE = RUN_MODE_NORMAL;\r
9317 m68ki_exception_format_error();\r
9318 return;\r
9319 }\r
9320 m68ki_exception_privilege_violation();\r
9321}\r
9322\r
9323\r
9324M68KMAKE_OP(rtm, 32, ., .)\r
9325{\r
9326 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))\r
9327 {\r
9328 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
9329 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",\r
9330 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,\r
9331 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));\r
9332 return;\r
9333 }\r
9334 m68ki_exception_illegal();\r
9335}\r
9336\r
9337\r
9338M68KMAKE_OP(rtr, 32, ., .)\r
9339{\r
9340 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
9341 m68ki_set_ccr(m68ki_pull_16());\r
9342 m68ki_jump(m68ki_pull_32());\r
9343}\r
9344\r
9345\r
9346M68KMAKE_OP(rts, 32, ., .)\r
9347{\r
9348 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
9349 m68ki_jump(m68ki_pull_32());\r
9350}\r
9351\r
9352\r
9353M68KMAKE_OP(sbcd, 8, rr, .)\r
9354{\r
9355 uint* r_dst = &DX;\r
9356 uint src = DY;\r
9357 uint dst = *r_dst;\r
9358 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();\r
9359\r
9360// FLAG_V = ~res; /* Undefined V behavior */\r
9361 FLAG_V = VFLAG_CLEAR; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to assume cleared. */\r
9362\r
9363 if(res > 9)\r
9364 res -= 6;\r
9365 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);\r
9366 if(res > 0x99)\r
9367 {\r
9368 res += 0xa0;\r
9369 FLAG_X = FLAG_C = CFLAG_SET;\r
9370 FLAG_N = NFLAG_SET; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to follow carry. */\r
9371 }\r
9372 else\r
9373 FLAG_N = FLAG_X = FLAG_C = 0;\r
9374\r
9375 res = MASK_OUT_ABOVE_8(res);\r
9376\r
9377// FLAG_V &= res; /* Undefined V behavior part II */\r
9378// FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
9379 FLAG_Z |= res;\r
9380\r
9381 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
9382}\r
9383\r
9384\r
9385M68KMAKE_OP(sbcd, 8, mm, ax7)\r
9386{\r
9387 uint src = OPER_AY_PD_8();\r
9388 uint ea = EA_A7_PD_8();\r
9389 uint dst = m68ki_read_8(ea);\r
9390 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();\r
9391\r
9392// FLAG_V = ~res; /* Undefined V behavior */\r
9393 FLAG_V = VFLAG_CLEAR; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to return zero. */\r
9394\r
9395 if(res > 9)\r
9396 res -= 6;\r
9397 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);\r
9398 if(res > 0x99)\r
9399 {\r
9400 res += 0xa0;\r
9401 FLAG_X = FLAG_C = CFLAG_SET;\r
9402 FLAG_N = NFLAG_SET; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to follow carry. */\r
9403 }\r
9404 else\r
9405 FLAG_N = FLAG_X = FLAG_C = 0;\r
9406\r
9407 res = MASK_OUT_ABOVE_8(res);\r
9408\r
9409// FLAG_V &= res; /* Undefined V behavior part II */\r
9410// FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
9411 FLAG_Z |= res;\r
9412\r
9413 m68ki_write_8(ea, res);\r
9414}\r
9415\r
9416\r
9417M68KMAKE_OP(sbcd, 8, mm, ay7)\r
9418{\r
9419 uint src = OPER_A7_PD_8();\r
9420 uint ea = EA_AX_PD_8();\r
9421 uint dst = m68ki_read_8(ea);\r
9422 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();\r
9423\r
9424// FLAG_V = ~res; /* Undefined V behavior */\r
9425 FLAG_V = VFLAG_CLEAR; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to return zero. */\r
9426\r
9427 if(res > 9)\r
9428 res -= 6;\r
9429 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);\r
9430 if(res > 0x99)\r
9431 {\r
9432 res += 0xa0;\r
9433 FLAG_X = FLAG_C = CFLAG_SET;\r
9434 FLAG_N = NFLAG_SET; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to follow carry. */\r
9435 }\r
9436 else\r
9437 FLAG_N = FLAG_X = FLAG_C = 0;\r
9438\r
9439 res = MASK_OUT_ABOVE_8(res);\r
9440\r
9441// FLAG_V &= res; /* Undefined V behavior part II */\r
9442// FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
9443 FLAG_Z |= res;\r
9444\r
9445 m68ki_write_8(ea, res);\r
9446}\r
9447\r
9448\r
9449M68KMAKE_OP(sbcd, 8, mm, axy7)\r
9450{\r
9451 uint src = OPER_A7_PD_8();\r
9452 uint ea = EA_A7_PD_8();\r
9453 uint dst = m68ki_read_8(ea);\r
9454 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();\r
9455\r
9456// FLAG_V = ~res; /* Undefined V behavior */\r
9457 FLAG_V = VFLAG_CLEAR; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to return zero. */\r
9458\r
9459 if(res > 9)\r
9460 res -= 6;\r
9461 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);\r
9462 if(res > 0x99)\r
9463 {\r
9464 res += 0xa0;\r
9465 FLAG_X = FLAG_C = CFLAG_SET;\r
9466 FLAG_N = NFLAG_SET; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to follow carry. */\r
9467 }\r
9468 else\r
9469 FLAG_N = FLAG_X = FLAG_C = 0;\r
9470\r
9471 res = MASK_OUT_ABOVE_8(res);\r
9472\r
9473// FLAG_V &= res; /* Undefined V behavior part II */\r
9474// FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
9475 FLAG_Z |= res;\r
9476\r
9477 m68ki_write_8(ea, res);\r
9478}\r
9479\r
9480\r
9481M68KMAKE_OP(sbcd, 8, mm, .)\r
9482{\r
9483 uint src = OPER_AY_PD_8();\r
9484 uint ea = EA_AX_PD_8();\r
9485 uint dst = m68ki_read_8(ea);\r
9486 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();\r
9487\r
9488// FLAG_V = ~res; /* Undefined V behavior */\r
9489 FLAG_V = VFLAG_CLEAR; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to return zero. */\r
9490\r
9491 if(res > 9)\r
9492 res -= 6;\r
9493 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);\r
9494 if(res > 0x99)\r
9495 {\r
9496 res += 0xa0;\r
9497 FLAG_X = FLAG_C = CFLAG_SET;\r
9498 FLAG_N = NFLAG_SET; /* Undefined in Motorola's M68000PM/AD rev.1 and safer to follow carry. */\r
9499 }\r
9500 else\r
9501 FLAG_N = FLAG_X = FLAG_C = 0;\r
9502\r
9503 res = MASK_OUT_ABOVE_8(res);\r
9504\r
9505// FLAG_V &= res; /* Undefined V behavior part II */\r
9506// FLAG_N = NFLAG_8(res); /* Undefined N behavior */\r
9507 FLAG_Z |= res;\r
9508\r
9509 m68ki_write_8(ea, res);\r
9510}\r
9511\r
9512\r
9513M68KMAKE_OP(st, 8, ., d)\r
9514{\r
9515 DY |= 0xff;\r
9516}\r
9517\r
9518\r
9519M68KMAKE_OP(st, 8, ., .)\r
9520{\r
9521 m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0xff);\r
9522}\r
9523\r
9524\r
9525M68KMAKE_OP(sf, 8, ., d)\r
9526{\r
9527 DY &= 0xffffff00;\r
9528}\r
9529\r
9530\r
9531M68KMAKE_OP(sf, 8, ., .)\r
9532{\r
9533 m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0);\r
9534}\r
9535\r
9536\r
9537M68KMAKE_OP(scc, 8, ., d)\r
9538{\r
9539 if(M68KMAKE_CC)\r
9540 {\r
9541 DY |= 0xff;\r
9542 USE_CYCLES(CYC_SCC_R_TRUE);\r
9543 return;\r
9544 }\r
9545 DY &= 0xffffff00;\r
9546}\r
9547\r
9548\r
9549M68KMAKE_OP(scc, 8, ., .)\r
9550{\r
9551 m68ki_write_8(M68KMAKE_GET_EA_AY_8, M68KMAKE_CC ? 0xff : 0);\r
9552}\r
9553\r
9554\r
9555M68KMAKE_OP(stop, 0, ., .)\r
9556{\r
9557 if(FLAG_S)\r
9558 {\r
9559 uint new_sr = OPER_I_16();\r
9560 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */\r
9561 CPU_STOPPED |= STOP_LEVEL_STOP;\r
9562 m68ki_set_sr(new_sr);\r
9563 m68ki_remaining_cycles = 0;\r
9564 return;\r
9565 }\r
9566 m68ki_exception_privilege_violation();\r
9567}\r
9568\r
9569\r
9570M68KMAKE_OP(sub, 8, er, d)\r
9571{\r
9572 uint* r_dst = &DX;\r
9573 uint src = MASK_OUT_ABOVE_8(DY);\r
9574 uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
9575 uint res = dst - src;\r
9576\r
9577 FLAG_N = NFLAG_8(res);\r
9578 FLAG_X = FLAG_C = CFLAG_8(res);\r
9579 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
9580 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
9581\r
9582 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;\r
9583}\r
9584\r
9585\r
9586M68KMAKE_OP(sub, 8, er, .)\r
9587{\r
9588 uint* r_dst = &DX;\r
9589 uint src = M68KMAKE_GET_OPER_AY_8;\r
9590 uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
9591 uint res = dst - src;\r
9592\r
9593 FLAG_N = NFLAG_8(res);\r
9594 FLAG_X = FLAG_C = CFLAG_8(res);\r
9595 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
9596 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
9597\r
9598 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;\r
9599}\r
9600\r
9601\r
9602M68KMAKE_OP(sub, 16, er, d)\r
9603{\r
9604 uint* r_dst = &DX;\r
9605 uint src = MASK_OUT_ABOVE_16(DY);\r
9606 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
9607 uint res = dst - src;\r
9608\r
9609 FLAG_N = NFLAG_16(res);\r
9610 FLAG_X = FLAG_C = CFLAG_16(res);\r
9611 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
9612 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
9613\r
9614 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
9615}\r
9616\r
9617\r
9618M68KMAKE_OP(sub, 16, er, a)\r
9619{\r
9620 uint* r_dst = &DX;\r
9621 uint src = MASK_OUT_ABOVE_16(AY);\r
9622 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
9623 uint res = dst - src;\r
9624\r
9625 FLAG_N = NFLAG_16(res);\r
9626 FLAG_X = FLAG_C = CFLAG_16(res);\r
9627 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
9628 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
9629\r
9630 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
9631}\r
9632\r
9633\r
9634M68KMAKE_OP(sub, 16, er, .)\r
9635{\r
9636 uint* r_dst = &DX;\r
9637 uint src = M68KMAKE_GET_OPER_AY_16;\r
9638 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
9639 uint res = dst - src;\r
9640\r
9641 FLAG_N = NFLAG_16(res);\r
9642 FLAG_X = FLAG_C = CFLAG_16(res);\r
9643 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
9644 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
9645\r
9646 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
9647}\r
9648\r
9649\r
9650M68KMAKE_OP(sub, 32, er, d)\r
9651{\r
9652 uint* r_dst = &DX;\r
9653 uint src = DY;\r
9654 uint dst = *r_dst;\r
9655 uint res = dst - src;\r
9656\r
9657 FLAG_N = NFLAG_32(res);\r
9658 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
9659 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
9660 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
9661\r
9662 *r_dst = FLAG_Z;\r
9663}\r
9664\r
9665\r
9666M68KMAKE_OP(sub, 32, er, a)\r
9667{\r
9668 uint* r_dst = &DX;\r
9669 uint src = AY;\r
9670 uint dst = *r_dst;\r
9671 uint res = dst - src;\r
9672\r
9673 FLAG_N = NFLAG_32(res);\r
9674 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
9675 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
9676 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
9677\r
9678 *r_dst = FLAG_Z;\r
9679}\r
9680\r
9681\r
9682M68KMAKE_OP(sub, 32, er, .)\r
9683{\r
9684 uint* r_dst = &DX;\r
9685 uint src = M68KMAKE_GET_OPER_AY_32;\r
9686 uint dst = *r_dst;\r
9687 uint res = dst - src;\r
9688\r
9689 FLAG_N = NFLAG_32(res);\r
9690 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
9691 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
9692 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
9693\r
9694 *r_dst = FLAG_Z;\r
9695}\r
9696\r
9697\r
9698M68KMAKE_OP(sub, 8, re, .)\r
9699{\r
9700 uint ea = M68KMAKE_GET_EA_AY_8;\r
9701 uint src = MASK_OUT_ABOVE_8(DX);\r
9702 uint dst = m68ki_read_8(ea);\r
9703 uint res = dst - src;\r
9704\r
9705 FLAG_N = NFLAG_8(res);\r
9706 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
9707 FLAG_X = FLAG_C = CFLAG_8(res);\r
9708 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
9709\r
9710 m68ki_write_8(ea, FLAG_Z);\r
9711}\r
9712\r
9713\r
9714M68KMAKE_OP(sub, 16, re, .)\r
9715{\r
9716 uint ea = M68KMAKE_GET_EA_AY_16;\r
9717 uint src = MASK_OUT_ABOVE_16(DX);\r
9718 uint dst = m68ki_read_16(ea);\r
9719 uint res = dst - src;\r
9720\r
9721 FLAG_N = NFLAG_16(res);\r
9722 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
9723 FLAG_X = FLAG_C = CFLAG_16(res);\r
9724 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
9725\r
9726 m68ki_write_16(ea, FLAG_Z);\r
9727}\r
9728\r
9729\r
9730M68KMAKE_OP(sub, 32, re, .)\r
9731{\r
9732 uint ea = M68KMAKE_GET_EA_AY_32;\r
9733 uint src = DX;\r
9734 uint dst = m68ki_read_32(ea);\r
9735 uint res = dst - src;\r
9736\r
9737 FLAG_N = NFLAG_32(res);\r
9738 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
9739 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
9740 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
9741\r
9742 m68ki_write_32(ea, FLAG_Z);\r
9743}\r
9744\r
9745\r
9746M68KMAKE_OP(suba, 16, ., d)\r
9747{\r
9748 uint* r_dst = &AX;\r
9749\r
9750 *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(DY));\r
9751}\r
9752\r
9753\r
9754M68KMAKE_OP(suba, 16, ., a)\r
9755{\r
9756 uint* r_dst = &AX;\r
9757\r
9758 *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(AY));\r
9759}\r
9760\r
9761\r
9762M68KMAKE_OP(suba, 16, ., .)\r
9763{\r
9764 uint* r_dst = &AX;\r
c6a4c892 9765 uint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);\r
cc68a136 9766\r
c6a4c892 9767 *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);\r
cc68a136 9768}\r
9769\r
9770\r
9771M68KMAKE_OP(suba, 32, ., d)\r
9772{\r
9773 uint* r_dst = &AX;\r
9774\r
9775 *r_dst = MASK_OUT_ABOVE_32(*r_dst - DY);\r
9776}\r
9777\r
9778\r
9779M68KMAKE_OP(suba, 32, ., a)\r
9780{\r
9781 uint* r_dst = &AX;\r
9782\r
9783 *r_dst = MASK_OUT_ABOVE_32(*r_dst - AY);\r
9784}\r
9785\r
9786\r
9787M68KMAKE_OP(suba, 32, ., .)\r
9788{\r
9789 uint* r_dst = &AX;\r
3335750a 9790 uint src = M68KMAKE_GET_OPER_AY_32; // notaz\r
cc68a136 9791\r
3335750a 9792 *r_dst = MASK_OUT_ABOVE_32(*r_dst - src);\r
cc68a136 9793}\r
9794\r
9795\r
9796M68KMAKE_OP(subi, 8, ., d)\r
9797{\r
9798 uint* r_dst = &DY;\r
9799 uint src = OPER_I_8();\r
9800 uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
9801 uint res = dst - src;\r
9802\r
9803 FLAG_N = NFLAG_8(res);\r
9804 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
9805 FLAG_X = FLAG_C = CFLAG_8(res);\r
9806 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
9807\r
9808 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;\r
9809}\r
9810\r
9811\r
9812M68KMAKE_OP(subi, 8, ., .)\r
9813{\r
9814 uint src = OPER_I_8();\r
9815 uint ea = M68KMAKE_GET_EA_AY_8;\r
9816 uint dst = m68ki_read_8(ea);\r
9817 uint res = dst - src;\r
9818\r
9819 FLAG_N = NFLAG_8(res);\r
9820 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
9821 FLAG_X = FLAG_C = CFLAG_8(res);\r
9822 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
9823\r
9824 m68ki_write_8(ea, FLAG_Z);\r
9825}\r
9826\r
9827\r
9828M68KMAKE_OP(subi, 16, ., d)\r
9829{\r
9830 uint* r_dst = &DY;\r
9831 uint src = OPER_I_16();\r
9832 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
9833 uint res = dst - src;\r
9834\r
9835 FLAG_N = NFLAG_16(res);\r
9836 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
9837 FLAG_X = FLAG_C = CFLAG_16(res);\r
9838 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
9839\r
9840 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
9841}\r
9842\r
9843\r
9844M68KMAKE_OP(subi, 16, ., .)\r
9845{\r
9846 uint src = OPER_I_16();\r
9847 uint ea = M68KMAKE_GET_EA_AY_16;\r
9848 uint dst = m68ki_read_16(ea);\r
9849 uint res = dst - src;\r
9850\r
9851 FLAG_N = NFLAG_16(res);\r
9852 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
9853 FLAG_X = FLAG_C = CFLAG_16(res);\r
9854 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
9855\r
9856 m68ki_write_16(ea, FLAG_Z);\r
9857}\r
9858\r
9859\r
9860M68KMAKE_OP(subi, 32, ., d)\r
9861{\r
9862 uint* r_dst = &DY;\r
9863 uint src = OPER_I_32();\r
9864 uint dst = *r_dst;\r
9865 uint res = dst - src;\r
9866\r
9867 FLAG_N = NFLAG_32(res);\r
9868 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
9869 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
9870 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
9871\r
9872 *r_dst = FLAG_Z;\r
9873}\r
9874\r
9875\r
9876M68KMAKE_OP(subi, 32, ., .)\r
9877{\r
9878 uint src = OPER_I_32();\r
9879 uint ea = M68KMAKE_GET_EA_AY_32;\r
9880 uint dst = m68ki_read_32(ea);\r
9881 uint res = dst - src;\r
9882\r
9883 FLAG_N = NFLAG_32(res);\r
9884 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
9885 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
9886 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
9887\r
9888 m68ki_write_32(ea, FLAG_Z);\r
9889}\r
9890\r
9891\r
9892M68KMAKE_OP(subq, 8, ., d)\r
9893{\r
9894 uint* r_dst = &DY;\r
9895 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
9896 uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
9897 uint res = dst - src;\r
9898\r
9899 FLAG_N = NFLAG_8(res);\r
9900 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
9901 FLAG_X = FLAG_C = CFLAG_8(res);\r
9902 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
9903\r
9904 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;\r
9905}\r
9906\r
9907\r
9908M68KMAKE_OP(subq, 8, ., .)\r
9909{\r
9910 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
9911 uint ea = M68KMAKE_GET_EA_AY_8;\r
9912 uint dst = m68ki_read_8(ea);\r
9913 uint res = dst - src;\r
9914\r
9915 FLAG_N = NFLAG_8(res);\r
9916 FLAG_Z = MASK_OUT_ABOVE_8(res);\r
9917 FLAG_X = FLAG_C = CFLAG_8(res);\r
9918 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
9919\r
9920 m68ki_write_8(ea, FLAG_Z);\r
9921}\r
9922\r
9923\r
9924M68KMAKE_OP(subq, 16, ., d)\r
9925{\r
9926 uint* r_dst = &DY;\r
9927 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
9928 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
9929 uint res = dst - src;\r
9930\r
9931 FLAG_N = NFLAG_16(res);\r
9932 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
9933 FLAG_X = FLAG_C = CFLAG_16(res);\r
9934 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
9935\r
9936 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;\r
9937}\r
9938\r
9939\r
9940M68KMAKE_OP(subq, 16, ., a)\r
9941{\r
9942 uint* r_dst = &AY;\r
9943\r
9944 *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1));\r
9945}\r
9946\r
9947\r
9948M68KMAKE_OP(subq, 16, ., .)\r
9949{\r
9950 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
9951 uint ea = M68KMAKE_GET_EA_AY_16;\r
9952 uint dst = m68ki_read_16(ea);\r
9953 uint res = dst - src;\r
9954\r
9955 FLAG_N = NFLAG_16(res);\r
9956 FLAG_Z = MASK_OUT_ABOVE_16(res);\r
9957 FLAG_X = FLAG_C = CFLAG_16(res);\r
9958 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
9959\r
9960 m68ki_write_16(ea, FLAG_Z);\r
9961}\r
9962\r
9963\r
9964M68KMAKE_OP(subq, 32, ., d)\r
9965{\r
9966 uint* r_dst = &DY;\r
9967 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
9968 uint dst = *r_dst;\r
9969 uint res = dst - src;\r
9970\r
9971 FLAG_N = NFLAG_32(res);\r
9972 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
9973 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
9974 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
9975\r
9976 *r_dst = FLAG_Z;\r
9977}\r
9978\r
9979\r
9980M68KMAKE_OP(subq, 32, ., a)\r
9981{\r
9982 uint* r_dst = &AY;\r
9983\r
9984 *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1));\r
9985}\r
9986\r
9987\r
9988M68KMAKE_OP(subq, 32, ., .)\r
9989{\r
9990 uint src = (((REG_IR >> 9) - 1) & 7) + 1;\r
9991 uint ea = M68KMAKE_GET_EA_AY_32;\r
9992 uint dst = m68ki_read_32(ea);\r
9993 uint res = dst - src;\r
9994\r
9995 FLAG_N = NFLAG_32(res);\r
9996 FLAG_Z = MASK_OUT_ABOVE_32(res);\r
9997 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
9998 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
9999\r
10000 m68ki_write_32(ea, FLAG_Z);\r
10001}\r
10002\r
10003\r
10004M68KMAKE_OP(subx, 8, rr, .)\r
10005{\r
10006 uint* r_dst = &DX;\r
10007 uint src = MASK_OUT_ABOVE_8(DY);\r
10008 uint dst = MASK_OUT_ABOVE_8(*r_dst);\r
10009 uint res = dst - src - XFLAG_AS_1();\r
10010\r
10011 FLAG_N = NFLAG_8(res);\r
10012 FLAG_X = FLAG_C = CFLAG_8(res);\r
10013 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
10014\r
10015 res = MASK_OUT_ABOVE_8(res);\r
10016 FLAG_Z |= res;\r
10017\r
10018 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;\r
10019}\r
10020\r
10021\r
10022M68KMAKE_OP(subx, 16, rr, .)\r
10023{\r
10024 uint* r_dst = &DX;\r
10025 uint src = MASK_OUT_ABOVE_16(DY);\r
10026 uint dst = MASK_OUT_ABOVE_16(*r_dst);\r
10027 uint res = dst - src - XFLAG_AS_1();\r
10028\r
10029 FLAG_N = NFLAG_16(res);\r
10030 FLAG_X = FLAG_C = CFLAG_16(res);\r
10031 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
10032\r
10033 res = MASK_OUT_ABOVE_16(res);\r
10034 FLAG_Z |= res;\r
10035\r
10036 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;\r
10037}\r
10038\r
10039\r
10040M68KMAKE_OP(subx, 32, rr, .)\r
10041{\r
10042 uint* r_dst = &DX;\r
10043 uint src = DY;\r
10044 uint dst = *r_dst;\r
10045 uint res = dst - src - XFLAG_AS_1();\r
10046\r
10047 FLAG_N = NFLAG_32(res);\r
10048 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
10049 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
10050\r
10051 res = MASK_OUT_ABOVE_32(res);\r
10052 FLAG_Z |= res;\r
10053\r
10054 *r_dst = res;\r
10055}\r
10056\r
10057\r
10058M68KMAKE_OP(subx, 8, mm, ax7)\r
10059{\r
10060 uint src = OPER_AY_PD_8();\r
10061 uint ea = EA_A7_PD_8();\r
10062 uint dst = m68ki_read_8(ea);\r
10063 uint res = dst - src - XFLAG_AS_1();\r
10064\r
10065 FLAG_N = NFLAG_8(res);\r
10066 FLAG_X = FLAG_C = CFLAG_8(res);\r
10067 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
10068\r
10069 res = MASK_OUT_ABOVE_8(res);\r
10070 FLAG_Z |= res;\r
10071\r
10072 m68ki_write_8(ea, res);\r
10073}\r
10074\r
10075\r
10076M68KMAKE_OP(subx, 8, mm, ay7)\r
10077{\r
10078 uint src = OPER_A7_PD_8();\r
10079 uint ea = EA_AX_PD_8();\r
10080 uint dst = m68ki_read_8(ea);\r
10081 uint res = dst - src - XFLAG_AS_1();\r
10082\r
10083 FLAG_N = NFLAG_8(res);\r
10084 FLAG_X = FLAG_C = CFLAG_8(res);\r
10085 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
10086\r
10087 res = MASK_OUT_ABOVE_8(res);\r
10088 FLAG_Z |= res;\r
10089\r
10090 m68ki_write_8(ea, res);\r
10091}\r
10092\r
10093\r
10094M68KMAKE_OP(subx, 8, mm, axy7)\r
10095{\r
10096 uint src = OPER_A7_PD_8();\r
10097 uint ea = EA_A7_PD_8();\r
10098 uint dst = m68ki_read_8(ea);\r
10099 uint res = dst - src - XFLAG_AS_1();\r
10100\r
10101 FLAG_N = NFLAG_8(res);\r
10102 FLAG_X = FLAG_C = CFLAG_8(res);\r
10103 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
10104\r
10105 res = MASK_OUT_ABOVE_8(res);\r
10106 FLAG_Z |= res;\r
10107\r
10108 m68ki_write_8(ea, res);\r
10109}\r
10110\r
10111\r
10112M68KMAKE_OP(subx, 8, mm, .)\r
10113{\r
10114 uint src = OPER_AY_PD_8();\r
10115 uint ea = EA_AX_PD_8();\r
10116 uint dst = m68ki_read_8(ea);\r
10117 uint res = dst - src - XFLAG_AS_1();\r
10118\r
10119 FLAG_N = NFLAG_8(res);\r
10120 FLAG_X = FLAG_C = CFLAG_8(res);\r
10121 FLAG_V = VFLAG_SUB_8(src, dst, res);\r
10122\r
10123 res = MASK_OUT_ABOVE_8(res);\r
10124 FLAG_Z |= res;\r
10125\r
10126 m68ki_write_8(ea, res);\r
10127}\r
10128\r
10129\r
10130M68KMAKE_OP(subx, 16, mm, .)\r
10131{\r
10132 uint src = OPER_AY_PD_16();\r
10133 uint ea = EA_AX_PD_16();\r
10134 uint dst = m68ki_read_16(ea);\r
10135 uint res = dst - src - XFLAG_AS_1();\r
10136\r
10137 FLAG_N = NFLAG_16(res);\r
10138 FLAG_X = FLAG_C = CFLAG_16(res);\r
10139 FLAG_V = VFLAG_SUB_16(src, dst, res);\r
10140\r
10141 res = MASK_OUT_ABOVE_16(res);\r
10142 FLAG_Z |= res;\r
10143\r
10144 m68ki_write_16(ea, res);\r
10145}\r
10146\r
10147\r
10148M68KMAKE_OP(subx, 32, mm, .)\r
10149{\r
10150 uint src = OPER_AY_PD_32();\r
10151 uint ea = EA_AX_PD_32();\r
10152 uint dst = m68ki_read_32(ea);\r
10153 uint res = dst - src - XFLAG_AS_1();\r
10154\r
10155 FLAG_N = NFLAG_32(res);\r
10156 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);\r
10157 FLAG_V = VFLAG_SUB_32(src, dst, res);\r
10158\r
10159 res = MASK_OUT_ABOVE_32(res);\r
10160 FLAG_Z |= res;\r
10161\r
10162 m68ki_write_32(ea, res);\r
10163}\r
10164\r
10165\r
10166M68KMAKE_OP(swap, 32, ., .)\r
10167{\r
10168 uint* r_dst = &DY;\r
10169\r
10170 FLAG_Z = MASK_OUT_ABOVE_32(*r_dst<<16);\r
10171 *r_dst = (*r_dst>>16) | FLAG_Z;\r
10172\r
10173 FLAG_Z = *r_dst;\r
10174 FLAG_N = NFLAG_32(*r_dst);\r
10175 FLAG_C = CFLAG_CLEAR;\r
10176 FLAG_V = VFLAG_CLEAR;\r
10177}\r
10178\r
10179\r
10180M68KMAKE_OP(tas, 8, ., d)\r
10181{\r
10182 uint* r_dst = &DY;\r
10183\r
10184 FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);\r
10185 FLAG_N = NFLAG_8(*r_dst);\r
10186 FLAG_V = VFLAG_CLEAR;\r
10187 FLAG_C = CFLAG_CLEAR;\r
10188 *r_dst |= 0x80;\r
10189}\r
10190\r
10191\r
10192M68KMAKE_OP(tas, 8, ., .)\r
10193{\r
10194 uint ea = M68KMAKE_GET_EA_AY_8;\r
10195 uint dst = m68ki_read_8(ea);\r
c6a4c892 10196 uint allow_writeback;\r
cc68a136 10197\r
10198 FLAG_Z = dst;\r
10199 FLAG_N = NFLAG_8(dst);\r
10200 FLAG_V = VFLAG_CLEAR;\r
10201 FLAG_C = CFLAG_CLEAR;\r
c6a4c892 10202\r
10203 /* The Genesis/Megadrive games Gargoyles and Ex-Mutants need the TAS writeback\r
10204 disabled in order to function properly. Some Amiga software may also rely\r
10205 on this, but only when accessing specific addresses so additional functionality\r
10206 will be needed. */\r
10207 allow_writeback = m68ki_tas_callback();\r
10208\r
10209 if (allow_writeback==1) m68ki_write_8(ea, dst | 0x80);\r
cc68a136 10210}\r
10211\r
10212\r
10213M68KMAKE_OP(trap, 0, ., .)\r
10214{\r
10215 /* Trap#n stacks exception frame type 0 */\r
10216 m68ki_exception_trapN(EXCEPTION_TRAP_BASE + (REG_IR & 0xf)); /* HJB 990403 */\r
10217}\r
10218\r
10219\r
10220M68KMAKE_OP(trapt, 0, ., .)\r
10221{\r
10222 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10223 {\r
10224 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */\r
10225 return;\r
10226 }\r
10227 m68ki_exception_illegal();\r
10228}\r
10229\r
10230\r
10231M68KMAKE_OP(trapt, 16, ., .)\r
10232{\r
10233 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10234 {\r
10235 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */\r
10236 return;\r
10237 }\r
10238 m68ki_exception_illegal();\r
10239}\r
10240\r
10241\r
10242M68KMAKE_OP(trapt, 32, ., .)\r
10243{\r
10244 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10245 {\r
10246 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */\r
10247 return;\r
10248 }\r
10249 m68ki_exception_illegal();\r
10250}\r
10251\r
10252\r
10253M68KMAKE_OP(trapf, 0, ., .)\r
10254{\r
10255 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10256 {\r
10257 return;\r
10258 }\r
10259 m68ki_exception_illegal();\r
10260}\r
10261\r
10262\r
10263M68KMAKE_OP(trapf, 16, ., .)\r
10264{\r
10265 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10266 {\r
10267 REG_PC += 2;\r
10268 return;\r
10269 }\r
10270 m68ki_exception_illegal();\r
10271}\r
10272\r
10273\r
10274M68KMAKE_OP(trapf, 32, ., .)\r
10275{\r
10276 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10277 {\r
10278 REG_PC += 4;\r
10279 return;\r
10280 }\r
10281 m68ki_exception_illegal();\r
10282}\r
10283\r
10284\r
10285M68KMAKE_OP(trapcc, 0, ., .)\r
10286{\r
10287 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10288 {\r
10289 if(M68KMAKE_CC)\r
10290 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */\r
10291 return;\r
10292 }\r
10293 m68ki_exception_illegal();\r
10294}\r
10295\r
10296\r
10297M68KMAKE_OP(trapcc, 16, ., .)\r
10298{\r
10299 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10300 {\r
10301 if(M68KMAKE_CC)\r
10302 {\r
10303 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */\r
10304 return;\r
10305 }\r
10306 REG_PC += 2;\r
10307 return;\r
10308 }\r
10309 m68ki_exception_illegal();\r
10310}\r
10311\r
10312\r
10313M68KMAKE_OP(trapcc, 32, ., .)\r
10314{\r
10315 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10316 {\r
10317 if(M68KMAKE_CC)\r
10318 {\r
10319 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */\r
10320 return;\r
10321 }\r
10322 REG_PC += 4;\r
10323 return;\r
10324 }\r
10325 m68ki_exception_illegal();\r
10326}\r
10327\r
10328\r
10329M68KMAKE_OP(trapv, 0, ., .)\r
10330{\r
10331 if(COND_VC())\r
10332 {\r
10333 return;\r
10334 }\r
10335 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */\r
10336}\r
10337\r
10338\r
10339M68KMAKE_OP(tst, 8, ., d)\r
10340{\r
10341 uint res = MASK_OUT_ABOVE_8(DY);\r
10342\r
10343 FLAG_N = NFLAG_8(res);\r
10344 FLAG_Z = res;\r
10345 FLAG_V = VFLAG_CLEAR;\r
10346 FLAG_C = CFLAG_CLEAR;\r
10347}\r
10348\r
10349\r
10350M68KMAKE_OP(tst, 8, ., .)\r
10351{\r
10352 uint res = M68KMAKE_GET_OPER_AY_8;\r
10353\r
10354 FLAG_N = NFLAG_8(res);\r
10355 FLAG_Z = res;\r
10356 FLAG_V = VFLAG_CLEAR;\r
10357 FLAG_C = CFLAG_CLEAR;\r
10358}\r
10359\r
10360\r
10361M68KMAKE_OP(tst, 8, ., pcdi)\r
10362{\r
10363 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10364 {\r
10365 uint res = OPER_PCDI_8();\r
10366\r
10367 FLAG_N = NFLAG_8(res);\r
10368 FLAG_Z = res;\r
10369 FLAG_V = VFLAG_CLEAR;\r
10370 FLAG_C = CFLAG_CLEAR;\r
10371 return;\r
10372 }\r
10373 m68ki_exception_illegal();\r
10374}\r
10375\r
10376\r
10377M68KMAKE_OP(tst, 8, ., pcix)\r
10378{\r
10379 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10380 {\r
10381 uint res = OPER_PCIX_8();\r
10382\r
10383 FLAG_N = NFLAG_8(res);\r
10384 FLAG_Z = res;\r
10385 FLAG_V = VFLAG_CLEAR;\r
10386 FLAG_C = CFLAG_CLEAR;\r
10387 return;\r
10388 }\r
10389 m68ki_exception_illegal();\r
10390}\r
10391\r
10392\r
10393M68KMAKE_OP(tst, 8, ., i)\r
10394{\r
10395 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10396 {\r
10397 uint res = OPER_I_8();\r
10398\r
10399 FLAG_N = NFLAG_8(res);\r
10400 FLAG_Z = res;\r
10401 FLAG_V = VFLAG_CLEAR;\r
10402 FLAG_C = CFLAG_CLEAR;\r
10403 return;\r
10404 }\r
10405 m68ki_exception_illegal();\r
10406}\r
10407\r
10408\r
10409M68KMAKE_OP(tst, 16, ., d)\r
10410{\r
10411 uint res = MASK_OUT_ABOVE_16(DY);\r
10412\r
10413 FLAG_N = NFLAG_16(res);\r
10414 FLAG_Z = res;\r
10415 FLAG_V = VFLAG_CLEAR;\r
10416 FLAG_C = CFLAG_CLEAR;\r
10417}\r
10418\r
10419\r
10420M68KMAKE_OP(tst, 16, ., a)\r
10421{\r
10422 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10423 {\r
10424 uint res = MAKE_INT_16(AY);\r
10425\r
10426 FLAG_N = NFLAG_16(res);\r
10427 FLAG_Z = res;\r
10428 FLAG_V = VFLAG_CLEAR;\r
10429 FLAG_C = CFLAG_CLEAR;\r
10430 return;\r
10431 }\r
10432 m68ki_exception_illegal();\r
10433}\r
10434\r
10435\r
10436M68KMAKE_OP(tst, 16, ., .)\r
10437{\r
10438 uint res = M68KMAKE_GET_OPER_AY_16;\r
10439\r
10440 FLAG_N = NFLAG_16(res);\r
10441 FLAG_Z = res;\r
10442 FLAG_V = VFLAG_CLEAR;\r
10443 FLAG_C = CFLAG_CLEAR;\r
10444}\r
10445\r
10446\r
10447M68KMAKE_OP(tst, 16, ., pcdi)\r
10448{\r
10449 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10450 {\r
10451 uint res = OPER_PCDI_16();\r
10452\r
10453 FLAG_N = NFLAG_16(res);\r
10454 FLAG_Z = res;\r
10455 FLAG_V = VFLAG_CLEAR;\r
10456 FLAG_C = CFLAG_CLEAR;\r
10457 return;\r
10458 }\r
10459 m68ki_exception_illegal();\r
10460}\r
10461\r
10462\r
10463M68KMAKE_OP(tst, 16, ., pcix)\r
10464{\r
10465 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10466 {\r
10467 uint res = OPER_PCIX_16();\r
10468\r
10469 FLAG_N = NFLAG_16(res);\r
10470 FLAG_Z = res;\r
10471 FLAG_V = VFLAG_CLEAR;\r
10472 FLAG_C = CFLAG_CLEAR;\r
10473 return;\r
10474 }\r
10475 m68ki_exception_illegal();\r
10476}\r
10477\r
10478\r
10479M68KMAKE_OP(tst, 16, ., i)\r
10480{\r
10481 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10482 {\r
10483 uint res = OPER_I_16();\r
10484\r
10485 FLAG_N = NFLAG_16(res);\r
10486 FLAG_Z = res;\r
10487 FLAG_V = VFLAG_CLEAR;\r
10488 FLAG_C = CFLAG_CLEAR;\r
10489 return;\r
10490 }\r
10491 m68ki_exception_illegal();\r
10492}\r
10493\r
10494\r
10495M68KMAKE_OP(tst, 32, ., d)\r
10496{\r
10497 uint res = DY;\r
10498\r
10499 FLAG_N = NFLAG_32(res);\r
10500 FLAG_Z = res;\r
10501 FLAG_V = VFLAG_CLEAR;\r
10502 FLAG_C = CFLAG_CLEAR;\r
10503}\r
10504\r
10505\r
10506M68KMAKE_OP(tst, 32, ., a)\r
10507{\r
10508 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10509 {\r
10510 uint res = AY;\r
10511\r
10512 FLAG_N = NFLAG_32(res);\r
10513 FLAG_Z = res;\r
10514 FLAG_V = VFLAG_CLEAR;\r
10515 FLAG_C = CFLAG_CLEAR;\r
10516 return;\r
10517 }\r
10518 m68ki_exception_illegal();\r
10519}\r
10520\r
10521\r
10522M68KMAKE_OP(tst, 32, ., .)\r
10523{\r
10524 uint res = M68KMAKE_GET_OPER_AY_32;\r
10525\r
10526 FLAG_N = NFLAG_32(res);\r
10527 FLAG_Z = res;\r
10528 FLAG_V = VFLAG_CLEAR;\r
10529 FLAG_C = CFLAG_CLEAR;\r
10530}\r
10531\r
10532\r
10533M68KMAKE_OP(tst, 32, ., pcdi)\r
10534{\r
10535 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10536 {\r
10537 uint res = OPER_PCDI_32();\r
10538\r
10539 FLAG_N = NFLAG_32(res);\r
10540 FLAG_Z = res;\r
10541 FLAG_V = VFLAG_CLEAR;\r
10542 FLAG_C = CFLAG_CLEAR;\r
10543 return;\r
10544 }\r
10545 m68ki_exception_illegal();\r
10546}\r
10547\r
10548\r
10549M68KMAKE_OP(tst, 32, ., pcix)\r
10550{\r
10551 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10552 {\r
10553 uint res = OPER_PCIX_32();\r
10554\r
10555 FLAG_N = NFLAG_32(res);\r
10556 FLAG_Z = res;\r
10557 FLAG_V = VFLAG_CLEAR;\r
10558 FLAG_C = CFLAG_CLEAR;\r
10559 return;\r
10560 }\r
10561 m68ki_exception_illegal();\r
10562}\r
10563\r
10564\r
10565M68KMAKE_OP(tst, 32, ., i)\r
10566{\r
10567 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10568 {\r
10569 uint res = OPER_I_32();\r
10570\r
10571 FLAG_N = NFLAG_32(res);\r
10572 FLAG_Z = res;\r
10573 FLAG_V = VFLAG_CLEAR;\r
10574 FLAG_C = CFLAG_CLEAR;\r
10575 return;\r
10576 }\r
10577 m68ki_exception_illegal();\r
10578}\r
10579\r
10580\r
10581M68KMAKE_OP(unlk, 32, ., a7)\r
10582{\r
10583 REG_A[7] = m68ki_read_32(REG_A[7]);\r
10584}\r
10585\r
10586\r
10587M68KMAKE_OP(unlk, 32, ., .)\r
10588{\r
10589 uint* r_dst = &AY;\r
10590\r
10591 REG_A[7] = *r_dst;\r
10592 *r_dst = m68ki_pull_32();\r
10593}\r
10594\r
10595\r
10596M68KMAKE_OP(unpk, 16, rr, .)\r
10597{\r
10598 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10599 {\r
10600 /* Note: DX and DY are reversed in Motorola's docs */\r
10601 uint src = DY;\r
10602 uint* r_dst = &DX;\r
10603\r
10604 *r_dst = MASK_OUT_BELOW_16(*r_dst) | (((((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16()) & 0xffff);\r
10605 return;\r
10606 }\r
10607 m68ki_exception_illegal();\r
10608}\r
10609\r
10610\r
10611M68KMAKE_OP(unpk, 16, mm, ax7)\r
10612{\r
10613 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10614 {\r
10615 /* Note: AX and AY are reversed in Motorola's docs */\r
10616 uint src = OPER_AY_PD_8();\r
10617 uint ea_dst;\r
10618\r
10619 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();\r
10620 ea_dst = EA_A7_PD_8();\r
10621 m68ki_write_8(ea_dst, (src >> 8) & 0xff);\r
10622 ea_dst = EA_A7_PD_8();\r
10623 m68ki_write_8(ea_dst, src & 0xff);\r
10624 return;\r
10625 }\r
10626 m68ki_exception_illegal();\r
10627}\r
10628\r
10629\r
10630M68KMAKE_OP(unpk, 16, mm, ay7)\r
10631{\r
10632 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10633 {\r
10634 /* Note: AX and AY are reversed in Motorola's docs */\r
10635 uint src = OPER_A7_PD_8();\r
10636 uint ea_dst;\r
10637\r
10638 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();\r
10639 ea_dst = EA_AX_PD_8();\r
10640 m68ki_write_8(ea_dst, (src >> 8) & 0xff);\r
10641 ea_dst = EA_AX_PD_8();\r
10642 m68ki_write_8(ea_dst, src & 0xff);\r
10643 return;\r
10644 }\r
10645 m68ki_exception_illegal();\r
10646}\r
10647\r
10648\r
10649M68KMAKE_OP(unpk, 16, mm, axy7)\r
10650{\r
10651 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10652 {\r
10653 uint src = OPER_A7_PD_8();\r
10654 uint ea_dst;\r
10655\r
10656 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();\r
10657 ea_dst = EA_A7_PD_8();\r
10658 m68ki_write_8(ea_dst, (src >> 8) & 0xff);\r
10659 ea_dst = EA_A7_PD_8();\r
10660 m68ki_write_8(ea_dst, src & 0xff);\r
10661 return;\r
10662 }\r
10663 m68ki_exception_illegal();\r
10664}\r
10665\r
10666\r
10667M68KMAKE_OP(unpk, 16, mm, .)\r
10668{\r
10669 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))\r
10670 {\r
10671 /* Note: AX and AY are reversed in Motorola's docs */\r
10672 uint src = OPER_AY_PD_8();\r
10673 uint ea_dst;\r
10674\r
10675 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();\r
10676 ea_dst = EA_AX_PD_8();\r
10677 m68ki_write_8(ea_dst, (src >> 8) & 0xff);\r
10678 ea_dst = EA_AX_PD_8();\r
10679 m68ki_write_8(ea_dst, src & 0xff);\r
10680 return;\r
10681 }\r
10682 m68ki_exception_illegal();\r
10683}\r
10684\r
10685\r
10686\r
10687XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX\r
10688M68KMAKE_END\r
fast MegaDrive/MegaCD/32X emulator