notaz.gp2x.de / picodrive.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
sh2: sync sh2 core with latest mame
[picodrive.git] / cpu / sh2 / mame / sh2.c
CommitLineData
eaa10a6e 1/*****************************************************************************\r
2 *\r
3 * sh2.c\r
4 * Portable Hitachi SH-2 (SH7600 family) emulator\r
5 *\r
6 * Copyright Juergen Buchmueller <pullmoll@t-online.de>,\r
7 * all rights reserved.\r
8 *\r
9 * - This source code is released as freeware for non-commercial purposes.\r
10 * - You are free to use and redistribute this code in modified or\r
11 * unmodified form, provided you list me in the credits.\r
12 * - If you modify this source code, you must add a notice to each modified\r
13 * source file that it has been changed. If you're a nice person, you\r
14 * will clearly mark each change too. :)\r
15 * - If you wish to use this for commercial purposes, please contact me at\r
16 * pullmoll@t-online.de\r
17 * - The author of this copywritten work reserves the right to change the\r
18 * terms of its usage and license at any time, including retroactively\r
19 * - This entire notice must remain in the source code.\r
20 *\r
21 * This work is based on <tiraniddo@hotmail.com> C/C++ implementation of\r
22 * the SH-2 CPU core and was adapted to the MAME CPU core requirements.\r
23 * Thanks also go to Chuck Mason <chukjr@sundail.net> and Olivier Galibert\r
24 * <galibert@pobox.com> for letting me peek into their SEMU code :-)\r
25 *\r
26 *****************************************************************************/\r
27\r
28/*****************************************************************************\r
29 Changes\r
f4c0720c 30 20130129 Angelo Salese\r
31 - added illegal opcode exception handling, side effect of some Saturn games\r
32 on loading like Feda or Falcom Classics Vol. 1\r
33 (i.e. Master CPU Incautiously transfers memory from CD to work RAM H, and\r
34 wipes out Slave CPU program code too while at it).\r
35\r
eaa10a6e 36 20051129 Mariusz Wojcieszek\r
37 - introduced memory_decrypted_read_word() for opcode fetching\r
38\r
39 20050813 Mariusz Wojcieszek\r
40 - fixed 64 bit / 32 bit division in division unit\r
41\r
42 20031015 O. Galibert\r
43 - dma fixes, thanks to sthief\r
44\r
45 20031013 O. Galibert, A. Giles\r
46 - timer fixes\r
47 - multi-cpu simplifications\r
48\r
49 20030915 O. Galibert\r
50 - fix DMA1 irq vector\r
51 - ignore writes to DRCRx\r
52 - fix cpu number issues\r
53 - fix slave/master recognition\r
54 - fix wrong-cpu-in-context problem with the timers\r
55\r
56 20021020 O. Galibert\r
57 - DMA implementation, lightly tested\r
58 - delay slot in debugger fixed\r
59 - add divide box mirrors\r
60 - Nicola-ify the indentation\r
61 - Uncrapify sh2_internal_*\r
62 - Put back nmi support that had been lost somehow\r
63\r
64 20020914 R. Belmont\r
65 - Initial SH2 internal timers implementation, based on code by O. Galibert.\r
66 Makes music work in galspanic4/s/s2, panic street, cyvern, other SKNS games.\r
67 - Fix to external division, thanks to "spice" on the E2J board.\r
68 Corrects behavior of s1945ii turret boss.\r
69\r
70 20020302 Olivier Galibert (galibert@mame.net)\r
71 - Fixed interrupt in delay slot\r
72 - Fixed rotcr\r
73 - Fixed div1\r
74 - Fixed mulu\r
75 - Fixed negc\r
76\r
77 20020301 R. Belmont\r
78 - Fixed external division\r
79\r
80 20020225 Olivier Galibert (galibert@mame.net)\r
81 - Fixed interrupt handling\r
82\r
83 20010207 Sylvain Glaize (mokona@puupuu.org)\r
84\r
85 - Bug fix in INLINE void MOVBM(UINT32 m, UINT32 n) (see comment)\r
86 - Support of full 32 bit addressing (RB, RW, RL and WB, WW, WL functions)\r
87 reason : when the two high bits of the address are set, access is\r
88 done directly in the cache data array. The SUPER KANEKO NOVA SYSTEM\r
89 sets the stack pointer here, using these addresses as usual RAM access.\r
90\r
91 No real cache support has been added.\r
92 - Read/Write memory format correction (_bew to _bedw) (see also SH2\r
93 definition in cpuintrf.c and DasmSH2(..) in sh2dasm.c )\r
94\r
95 20010623 James Forshaw (TyRaNiD@totalise.net)\r
96\r
97 - Modified operation of sh2_exception. Done cause mame irq system is stupid, and\r
98 doesnt really seem designed for any more than 8 interrupt lines.\r
99\r
100 20010701 James Forshaw (TyRaNiD@totalise.net)\r
101\r
102 - Fixed DIV1 operation. Q bit now correctly generated\r
103\r
104 20020218 Added save states (mokona@puupuu.org)\r
105\r
106 *****************************************************************************/\r
107\r
108//#include "debugger.h"\r
41397701 109//#include "sh2.h"\r
eaa10a6e 110//#include "sh2comn.h"\r
111#define INLINE static\r
112\r
113//CPU_DISASSEMBLE( sh2 );\r
114\r
115#ifndef USE_SH2DRC\r
116\r
117/* speed up delay loops, bail out of tight loops */\r
118#define BUSY_LOOP_HACKS 1\r
119\r
120#define VERBOSE 0\r
121\r
122#define LOG(x) do { if (VERBOSE) logerror x; } while (0)\r
123\r
eaa10a6e 124#if 0\r
f4c0720c 125INLINE UINT8 RB(sh2_state *sh2, offs_t A)\r
eaa10a6e 126{\r
127 if (A >= 0xe0000000)\r
f4c0720c 128 return sh2_internal_r(*sh2->internal, (A & 0x1fc)>>2, 0xff << (((~A) & 3)*8)) >> (((~A) & 3)*8);\r
eaa10a6e 129\r
130 if (A >= 0xc0000000)\r
f4c0720c 131 return sh2->program->read_byte(A);\r
eaa10a6e 132\r
133 if (A >= 0x40000000)\r
134 return 0xa5;\r
135\r
f4c0720c 136 return sh2->program->read_byte(A & AM);\r
eaa10a6e 137}\r
138\r
f4c0720c 139INLINE UINT16 RW(sh2_state *sh2, offs_t A)\r
eaa10a6e 140{\r
141 if (A >= 0xe0000000)\r
f4c0720c 142 return sh2_internal_r(*sh2->internal, (A & 0x1fc)>>2, 0xffff << (((~A) & 2)*8)) >> (((~A) & 2)*8);\r
eaa10a6e 143\r
144 if (A >= 0xc0000000)\r
f4c0720c 145 return sh2->program->read_word(A);\r
eaa10a6e 146\r
147 if (A >= 0x40000000)\r
148 return 0xa5a5;\r
149\r
f4c0720c 150 return sh2->program->read_word(A & AM);\r
eaa10a6e 151}\r
152\r
f4c0720c 153INLINE UINT32 RL(sh2_state *sh2, offs_t A)\r
eaa10a6e 154{\r
155 if (A >= 0xe0000000)\r
f4c0720c 156 return sh2_internal_r(*sh2->internal, (A & 0x1fc)>>2, 0xffffffff);\r
eaa10a6e 157\r
158 if (A >= 0xc0000000)\r
f4c0720c 159 return sh2->program->read_dword(A);\r
eaa10a6e 160\r
161 if (A >= 0x40000000)\r
162 return 0xa5a5a5a5;\r
163\r
f4c0720c 164 return sh2->program->read_dword(A & AM);\r
eaa10a6e 165}\r
166\r
f4c0720c 167INLINE void WB(sh2_state *sh2, offs_t A, UINT8 V)\r
eaa10a6e 168{\r
eaa10a6e 169 if (A >= 0xe0000000)\r
170 {\r
f4c0720c 171 sh2_internal_w(*sh2->internal, (A & 0x1fc)>>2, V << (((~A) & 3)*8), 0xff << (((~A) & 3)*8));\r
eaa10a6e 172 return;\r
173 }\r
174\r
175 if (A >= 0xc0000000)\r
176 {\r
f4c0720c 177 sh2->program->write_byte(A,V);\r
eaa10a6e 178 return;\r
179 }\r
180\r
181 if (A >= 0x40000000)\r
182 return;\r
183\r
f4c0720c 184 sh2->program->write_byte(A & AM,V);\r
eaa10a6e 185}\r
186\r
f4c0720c 187INLINE void WW(sh2_state *sh2, offs_t A, UINT16 V)\r
eaa10a6e 188{\r
189 if (A >= 0xe0000000)\r
190 {\r
f4c0720c 191 sh2_internal_w(*sh2->internal, (A & 0x1fc)>>2, V << (((~A) & 2)*8), 0xffff << (((~A) & 2)*8));\r
eaa10a6e 192 return;\r
193 }\r
194\r
195 if (A >= 0xc0000000)\r
196 {\r
f4c0720c 197 sh2->program->write_word(A,V);\r
eaa10a6e 198 return;\r
199 }\r
200\r
201 if (A >= 0x40000000)\r
202 return;\r
203\r
f4c0720c 204 sh2->program->write_word(A & AM,V);\r
eaa10a6e 205}\r
206\r
f4c0720c 207INLINE void WL(sh2_state *sh2, offs_t A, UINT32 V)\r
eaa10a6e 208{\r
209 if (A >= 0xe0000000)\r
210 {\r
f4c0720c 211 sh2_internal_w(*sh2->internal, (A & 0x1fc)>>2, V, 0xffffffff);\r
eaa10a6e 212 return;\r
213 }\r
214\r
215 if (A >= 0xc0000000)\r
216 {\r
f4c0720c 217 sh2->program->write_dword(A,V);\r
eaa10a6e 218 return;\r
219 }\r
220\r
221 if (A >= 0x40000000)\r
222 return;\r
223\r
f4c0720c 224 sh2->program->write_dword(A & AM,V);\r
eaa10a6e 225}\r
226#endif\r
227\r
228/* code cycles t-bit\r
229 * 0011 nnnn mmmm 1100 1 -\r
230 * ADD Rm,Rn\r
231 */\r
f4c0720c 232INLINE void ADD(sh2_state *sh2, UINT32 m, UINT32 n)\r
eaa10a6e 233{\r
234 sh2->r[n] += sh2->r[m];\r
235}\r
236\r
237/* code cycles t-bit\r
238 * 0111 nnnn iiii iiii 1 -\r
239 * ADD #imm,Rn\r
240 */\r
f4c0720c 241INLINE void ADDI(sh2_state *sh2, UINT32 i, UINT32 n)\r
eaa10a6e 242{\r
243 sh2->r[n] += (INT32)(INT16)(INT8)i;\r
244}\r
245\r
246/* code cycles t-bit\r
247 * 0011 nnnn mmmm 1110 1 carry\r
248 * ADDC Rm,Rn\r
249 */\r
f4c0720c 250INLINE void ADDC(sh2_state *sh2, UINT32 m, UINT32 n)\r
eaa10a6e 251{\r
252 UINT32 tmp0, tmp1;\r
253\r
254 tmp1 = sh2->r[n] + sh2->r[m];\r
255 tmp0 = sh2->r[n];\r
256 sh2->r[n] = tmp1 + (sh2->sr & T);\r
257 if (tmp0 > tmp1)\r
258 sh2->sr |= T;\r
259 else\r
260 sh2->sr &= ~T;\r
261 if (tmp1 > sh2->r[n])\r
262 sh2->sr |= T;\r
263}\r
264\r
265/* code cycles t-bit\r
266 * 0011 nnnn mmmm 1111 1 overflow\r
267 * ADDV Rm,Rn\r
268 */\r
f4c0720c 269INLINE void ADDV(sh2_state *sh2, UINT32 m, UINT32 n)\r
eaa10a6e 270{\r
271 INT32 dest, src, ans;\r
272\r
273 if ((INT32) sh2->r[n] >= 0)\r
274 dest = 0;\r
275 else\r
276 dest = 1;\r
277 if ((INT32) sh2->r[m] >= 0)\r
278 src = 0;\r
279 else\r
280 src = 1;\r
281 src += dest;\r
282 sh2->r[n] += sh2->r[m];\r
283 if ((INT32) sh2->r[n] >= 0)\r
284 ans = 0;\r
285 else\r
286 ans = 1;\r
287 ans += dest;\r
288 if (src == 0 || src == 2)\r
289 {\r
290 if (ans == 1)\r
291 sh2->sr |= T;\r
292 else\r
293 sh2->sr &= ~T;\r
294 }\r
295 else\r
296 sh2->sr &= ~T;\r
297}\r
298\r
299/* code cycles t-bit\r
300 * 0010 nnnn mmmm 1001 1 -\r
301 * AND Rm,Rn\r
302 */\r
f4c0720c 303INLINE void AND(sh2_state *sh2, UINT32 m, UINT32 n)\r
eaa10a6e 304{\r
305 sh2->r[n] &= sh2->r[m];\r
306}\r
307\r
308\r
309/* code cycles t-bit\r
310 * 1100 1001 iiii iiii 1 -\r
311 * AND #imm,R0\r
312 */\r
f4c0720c 313INLINE void ANDI(sh2_state *sh2, UINT32 i)\r
eaa10a6e 314{\r
315 sh2->r[0] &= i;\r
316}\r
317\r
318/* code cycles t-bit\r
319 * 1100 1101 iiii iiii 1 -\r
320 * AND.B #imm,@(R0,GBR)\r
321 */\r
f4c0720c 322INLINE void ANDM(sh2_state *sh2, UINT32 i)\r
eaa10a6e 323{\r
324 UINT32 temp;\r
325\r
326 sh2->ea = sh2->gbr + sh2->r[0];\r
f4c0720c 327 temp = i & RB( sh2, sh2->ea );\r
328 WB( sh2, sh2->ea, temp );\r
329 sh2->icount -= 2;\r
eaa10a6e 330}\r
331\r
332/* code cycles t-bit\r
333 * 1000 1011 dddd dddd 3/1 -\r
334 * BF disp8\r
335 */\r
f4c0720c 336INLINE void BF(sh2_state *sh2, UINT32 d)\r
eaa10a6e 337{\r
338 if ((sh2->sr & T) == 0)\r
339 {\r
340 INT32 disp = ((INT32)d << 24) >> 24;\r
341 sh2->pc = sh2->ea = sh2->pc + disp * 2 + 2;\r
f4c0720c 342 sh2->icount -= 2;\r
eaa10a6e 343 }\r
344}\r
345\r
346/* code cycles t-bit\r
347 * 1000 1111 dddd dddd 3/1 -\r
348 * BFS disp8\r
349 */\r
f4c0720c 350INLINE void BFS(sh2_state *sh2, UINT32 d)\r
eaa10a6e 351{\r
352 if ((sh2->sr & T) == 0)\r
353 {\r
354 INT32 disp = ((INT32)d << 24) >> 24;\r
355 sh2->delay = sh2->pc;\r
356 sh2->pc = sh2->ea = sh2->pc + disp * 2 + 2;\r
f4c0720c 357 sh2->icount--;\r
eaa10a6e 358 }\r
359}\r
360\r
361/* code cycles t-bit\r
362 * 1010 dddd dddd dddd 2 -\r
363 * BRA disp12\r
364 */\r
f4c0720c 365INLINE void BRA(sh2_state *sh2, UINT32 d)\r
eaa10a6e 366{\r
367 INT32 disp = ((INT32)d << 20) >> 20;\r
368\r
369#if BUSY_LOOP_HACKS\r
370 if (disp == -2)\r
371 {\r
f4c0720c 372 UINT32 next_opcode = RW( sh2, sh2->ppc & AM );\r
eaa10a6e 373 /* BRA $\r
f4c0720c 374 * NOP\r
375 */\r
eaa10a6e 376 if (next_opcode == 0x0009)\r
f4c0720c 377 sh2->icount %= 3; /* cycles for BRA $ and NOP taken (3) */\r
eaa10a6e 378 }\r
379#endif\r
380 sh2->delay = sh2->pc;\r
381 sh2->pc = sh2->ea = sh2->pc + disp * 2 + 2;\r
f4c0720c 382 sh2->icount--;\r
eaa10a6e 383}\r
384\r
385/* code cycles t-bit\r
386 * 0000 mmmm 0010 0011 2 -\r
387 * BRAF Rm\r
388 */\r
f4c0720c 389INLINE void BRAF(sh2_state *sh2, UINT32 m)\r
eaa10a6e 390{\r
391 sh2->delay = sh2->pc;\r
392 sh2->pc += sh2->r[m] + 2;\r
f4c0720c 393 sh2->icount--;\r
eaa10a6e 394}\r
395\r
396/* code cycles t-bit\r
397 * 1011 dddd dddd dddd 2 -\r
398 * BSR disp12\r
399 */\r
f4c0720c 400INLINE void BSR(sh2_state *sh2, UINT32 d)\r
eaa10a6e 401{\r
402 INT32 disp = ((INT32)d << 20) >> 20;\r
403\r
404 sh2->pr = sh2->pc + 2;\r
405 sh2->delay = sh2->pc;\r
406 sh2->pc = sh2->ea = sh2->pc + disp * 2 + 2;\r
f4c0720c 407 sh2->icount--;\r
eaa10a6e 408}\r
409\r
410/* code cycles t-bit\r
411 * 0000 mmmm 0000 0011 2 -\r
412 * BSRF Rm\r
413 */\r
f4c0720c 414INLINE void BSRF(sh2_state *sh2, UINT32 m)\r
eaa10a6e 415{\r
416 sh2->pr = sh2->pc + 2;\r
417 sh2->delay = sh2->pc;\r
418 sh2->pc += sh2->r[m] + 2;\r
f4c0720c 419 sh2->icount--;\r
eaa10a6e 420}\r
421\r
422/* code cycles t-bit\r
423 * 1000 1001 dddd dddd 3/1 -\r
424 * BT disp8\r
425 */\r
f4c0720c 426INLINE void BT(sh2_state *sh2, UINT32 d)\r
eaa10a6e 427{\r
428 if ((sh2->sr & T) != 0)\r
429 {\r
430 INT32 disp = ((INT32)d << 24) >> 24;\r
431 sh2->pc = sh2->ea = sh2->pc + disp * 2 + 2;\r
f4c0720c 432 sh2->icount -= 2;\r
eaa10a6e 433 }\r
434}\r
435\r
436/* code cycles t-bit\r
437 * 1000 1101 dddd dddd 2/1 -\r
438 * BTS disp8\r
439 */\r
f4c0720c 440INLINE void BTS(sh2_state *sh2, UINT32 d)\r
eaa10a6e 441{\r
442 if ((sh2->sr & T) != 0)\r
443 {\r
444 INT32 disp = ((INT32)d << 24) >> 24;\r
445 sh2->delay = sh2->pc;\r
446 sh2->pc = sh2->ea = sh2->pc + disp * 2 + 2;\r
f4c0720c 447 sh2->icount--;\r
eaa10a6e 448 }\r
449}\r
450\r
451/* code cycles t-bit\r
452 * 0000 0000 0010 1000 1 -\r
453 * CLRMAC\r
454 */\r
f4c0720c 455INLINE void CLRMAC(sh2_state *sh2)\r
eaa10a6e 456{\r
457 sh2->mach = 0;\r
458 sh2->macl = 0;\r
459}\r
460\r
461/* code cycles t-bit\r
462 * 0000 0000 0000 1000 1 -\r
463 * CLRT\r
464 */\r
f4c0720c 465INLINE void CLRT(sh2_state *sh2)\r
eaa10a6e 466{\r
467 sh2->sr &= ~T;\r
468}\r
469\r
470/* code cycles t-bit\r
471 * 0011 nnnn mmmm 0000 1 comparison result\r
472 * CMP_EQ Rm,Rn\r
473 */\r
f4c0720c 474INLINE void CMPEQ(sh2_state *sh2, UINT32 m, UINT32 n)\r
eaa10a6e 475{\r
476 if (sh2->r[n] == sh2->r[m])\r
477 sh2->sr |= T;\r
478 else\r
479 sh2->sr &= ~T;\r
480}\r
481\r
482/* code cycles t-bit\r
483 * 0011 nnnn mmmm 0011 1 comparison result\r
484 * CMP_GE Rm,Rn\r
485 */\r
f4c0720c 486INLINE void CMPGE(sh2_state *sh2, UINT32 m, UINT32 n)\r
eaa10a6e 487{\r
488 if ((INT32) sh2->r[n] >= (INT32) sh2->r[m])\r
489 sh2->sr |= T;\r
490 else\r
491 sh2->sr &= ~T;\r
492}\r
493\r
494/* code cycles t-bit\r
495 * 0011 nnnn mmmm 0111 1 comparison result\r
496 * CMP_GT Rm,Rn\r
497 */\r
f4c0720c 498INLINE void CMPGT(sh2_state *sh2, UINT32 m, UINT32 n)\r
eaa10a6e 499{\r
500 if ((INT32) sh2->r[n] > (INT32) sh2->r[m])\r
501 sh2->sr |= T;\r
502 else\r
503 sh2->sr &= ~T;\r
504}\r
505\r
506/* code cycles t-bit\r
507 * 0011 nnnn mmmm 0110 1 comparison result\r
508 * CMP_HI Rm,Rn\r
509 */\r
f4c0720c 510INLINE void CMPHI(sh2_state *sh2, UINT32 m, UINT32 n)\r
eaa10a6e 511{\r
512 if ((UINT32) sh2->r[n] > (UINT32) sh2->r[m])\r
513 sh2->sr |= T;\r
514 else\r
515 sh2->sr &= ~T;\r
516}\r
517\r
518/* code cycles t-bit\r
519 * 0011 nnnn mmmm 0010 1 comparison result\r
520 * CMP_HS Rm,Rn\r
521 */\r
f4c0720c 522INLINE void CMPHS(sh2_state *sh2, UINT32 m, UINT32 n)\r
eaa10a6e 523{\r
524 if ((UINT32) sh2->r[n] >= (UINT32) sh2->r[m])\r
525 sh2->sr |= T;\r
526 else\r
527 sh2->sr &= ~T;\r
528}\r
529\r
530\r
531/* code cycles t-bit\r
532 * 0100 nnnn 0001 0101 1 comparison result\r
533 * CMP_PL Rn\r
534 */\r
f4c0720c 535INLINE void CMPPL(sh2_state *sh2, UINT32 n)\r
eaa10a6e 536{\r
537 if ((INT32) sh2->r[n] > 0)\r
538 sh2->sr |= T;\r
539 else\r
540 sh2->sr &= ~T;\r
541}\r
542\r
543/* code cycles t-bit\r
544 * 0100 nnnn 0001 0001 1 comparison result\r
545 * CMP_PZ Rn\r
546 */\r
f4c0720c 547INLINE void CMPPZ(sh2_state *sh2, UINT32 n)\r
eaa10a6e 548{\r
549 if ((INT32) sh2->r[n] >= 0)\r
550 sh2->sr |= T;\r
551 else\r
552 sh2->sr &= ~T;\r
553}\r
554\r
555/* code cycles t-bit\r
556 * 0010 nnnn mmmm 1100 1 comparison result\r
557 * CMP_STR Rm,Rn\r
558 */\r
f4c0720c 559INLINE void CMPSTR(sh2_state *sh2, UINT32 m, UINT32 n)\r
560 {\r
561 UINT32 temp;\r
562 INT32 HH, HL, LH, LL;\r
563 temp = sh2->r[n] ^ sh2->r[m];\r
564 HH = (temp >> 24) & 0xff;\r
565 HL = (temp >> 16) & 0xff;\r
566 LH = (temp >> 8) & 0xff;\r
567 LL = temp & 0xff;\r
568 if (HH && HL && LH && LL)\r
569 sh2->sr &= ~T;\r
570 else\r
571 sh2->sr |= T;\r
572 }\r
eaa10a6e 573\r
574\r
575/* code cycles t-bit\r
576 * 1000 1000 iiii iiii 1 comparison result\r
577 * CMP/EQ #imm,R0\r
578 */\r
f4c0720c 579INLINE void CMPIM(sh2_state *sh2, UINT32 i)\r
eaa10a6e 580{\r
581 UINT32 imm = (UINT32)(INT32)(INT16)(INT8)i;\r
582\r
583 if (sh2->r[0] == imm)\r
584 sh2->sr |= T;\r
585 else\r
586 sh2->sr &= ~T;\r
587}\r
588\r
589/* code cycles t-bit\r
590 * 0010 nnnn mmmm 0111 1 calculation result\r
591 * DIV0S Rm,Rn\r
592 */\r
f4c0720c 593INLINE void DIV0S(sh2_state *sh2, UINT32 m, UINT32 n)\r
eaa10a6e 594{\r
595 if ((sh2->r[n] & 0x80000000) == 0)\r
596 sh2->sr &= ~Q;\r
597 else\r
598 sh2->sr |= Q;\r
599 if ((sh2->r[m] & 0x80000000) == 0)\r
600 sh2->sr &= ~M;\r
601 else\r
602 sh2->sr |= M;\r
603 if ((sh2->r[m] ^ sh2->r[n]) & 0x80000000)\r
604 sh2->sr |= T;\r
605 else\r
606 sh2->sr &= ~T;\r
607}\r
608\r
609/* code cycles t-bit\r
610 * 0000 0000 0001 1001 1 0\r
611 * DIV0U\r
612 */\r
f4c0720c 613INLINE void DIV0U(sh2_state *sh2)\r
eaa10a6e 614{\r
615 sh2->sr &= ~(M | Q | T);\r
616}\r
617\r
618/* code cycles t-bit\r
619 * 0011 nnnn mmmm 0100 1 calculation result\r
620 * DIV1 Rm,Rn\r
621 */\r
f4c0720c 622INLINE void DIV1(sh2_state *sh2, UINT32 m, UINT32 n)\r
eaa10a6e 623{\r
624 UINT32 tmp0;\r
625 UINT32 old_q;\r
626\r
627 old_q = sh2->sr & Q;\r
628 if (0x80000000 & sh2->r[n])\r
629 sh2->sr |= Q;\r
630 else\r
631 sh2->sr &= ~Q;\r
632\r
633 sh2->r[n] = (sh2->r[n] << 1) | (sh2->sr & T);\r
634\r
635 if (!old_q)\r
636 {\r
637 if (!(sh2->sr & M))\r
638 {\r
639 tmp0 = sh2->r[n];\r
640 sh2->r[n] -= sh2->r[m];\r
641 if(!(sh2->sr & Q))\r
642 if(sh2->r[n] > tmp0)\r
643 sh2->sr |= Q;\r
644 else\r
645 sh2->sr &= ~Q;\r
646 else\r
647 if(sh2->r[n] > tmp0)\r
648 sh2->sr &= ~Q;\r
649 else\r
650 sh2->sr |= Q;\r
651 }\r
652 else\r
653 {\r
654 tmp0 = sh2->r[n];\r
655 sh2->r[n] += sh2->r[m];\r
656 if(!(sh2->sr & Q))\r
657 {\r
658 if(sh2->r[n] < tmp0)\r
659 sh2->sr &= ~Q;\r
660 else\r
661 sh2->sr |= Q;\r
662 }\r
663 else\r
664 {\r
665 if(sh2->r[n] < tmp0)\r
666 sh2->sr |= Q;\r
667 else\r
668 sh2->sr &= ~Q;\r
669 }\r
670 }\r
671 }\r
672 else\r
673 {\r
674 if (!(sh2->sr & M))\r
675 {\r
676 tmp0 = sh2->r[n];\r
677 sh2->r[n] += sh2->r[m];\r
678 if(!(sh2->sr & Q))\r
679 if(sh2->r[n] < tmp0)\r
680 sh2->sr |= Q;\r
681 else\r
682 sh2->sr &= ~Q;\r
683 else\r
684 if(sh2->r[n] < tmp0)\r
685 sh2->sr &= ~Q;\r
686 else\r
687 sh2->sr |= Q;\r
688 }\r
689 else\r
690 {\r
691 tmp0 = sh2->r[n];\r
692 sh2->r[n] -= sh2->r[m];\r
693 if(!(sh2->sr & Q))\r
694 if(sh2->r[n] > tmp0)\r
695 sh2->sr &= ~Q;\r
696 else\r
697 sh2->sr |= Q;\r
698 else\r
699 if(sh2->r[n] > tmp0)\r
700 sh2->sr |= Q;\r
701 else\r
702 sh2->sr &= ~Q;\r
703 }\r
704 }\r
705\r
706 tmp0 = (sh2->sr & (Q | M));\r
707 if((!tmp0) || (tmp0 == 0x300)) /* if Q == M set T else clear T */\r
708 sh2->sr |= T;\r
709 else\r
710 sh2->sr &= ~T;\r
711}\r
712\r
713/* DMULS.L Rm,Rn */\r
f4c0720c 714INLINE void DMULS(sh2_state *sh2, UINT32 m, UINT32 n)\r
eaa10a6e 715{\r
716 UINT32 RnL, RnH, RmL, RmH, Res0, Res1, Res2;\r
717 UINT32 temp0, temp1, temp2, temp3;\r
718 INT32 tempm, tempn, fnLmL;\r
719\r
720 tempn = (INT32) sh2->r[n];\r
721 tempm = (INT32) sh2->r[m];\r
722 if (tempn < 0)\r
723 tempn = 0 - tempn;\r
724 if (tempm < 0)\r
725 tempm = 0 - tempm;\r
726 if ((INT32) (sh2->r[n] ^ sh2->r[m]) < 0)\r
727 fnLmL = -1;\r
728 else\r
729 fnLmL = 0;\r
730 temp1 = (UINT32) tempn;\r
731 temp2 = (UINT32) tempm;\r
732 RnL = temp1 & 0x0000ffff;\r
733 RnH = (temp1 >> 16) & 0x0000ffff;\r
734 RmL = temp2 & 0x0000ffff;\r
735 RmH = (temp2 >> 16) & 0x0000ffff;\r
736 temp0 = RmL * RnL;\r
737 temp1 = RmH * RnL;\r
738 temp2 = RmL * RnH;\r
739 temp3 = RmH * RnH;\r
740 Res2 = 0;\r
741 Res1 = temp1 + temp2;\r
742 if (Res1 < temp1)\r
743 Res2 += 0x00010000;\r
744 temp1 = (Res1 << 16) & 0xffff0000;\r
745 Res0 = temp0 + temp1;\r
746 if (Res0 < temp0)\r
747 Res2++;\r
748 Res2 = Res2 + ((Res1 >> 16) & 0x0000ffff) + temp3;\r
749 if (fnLmL < 0)\r
750 {\r
751 Res2 = ~Res2;\r
752 if (Res0 == 0)\r
753 Res2++;\r
754 else\r
755 Res0 = (~Res0) + 1;\r
756 }\r
757 sh2->mach = Res2;\r
758 sh2->macl = Res0;\r
f4c0720c 759 sh2->icount--;\r
eaa10a6e 760}\r
761\r
762/* DMULU.L Rm,Rn */\r
f4c0720c 763INLINE void DMULU(sh2_state *sh2, UINT32 m, UINT32 n)\r
eaa10a6e 764{\r
765 UINT32 RnL, RnH, RmL, RmH, Res0, Res1, Res2;\r
766 UINT32 temp0, temp1, temp2, temp3;\r
767\r
768 RnL = sh2->r[n] & 0x0000ffff;\r
769 RnH = (sh2->r[n] >> 16) & 0x0000ffff;\r
770 RmL = sh2->r[m] & 0x0000ffff;\r
771 RmH = (sh2->r[m] >> 16) & 0x0000ffff;\r
772 temp0 = RmL * RnL;\r
773 temp1 = RmH * RnL;\r
774 temp2 = RmL * RnH;\r
775 temp3 = RmH * RnH;\r
776 Res2 = 0;\r
777 Res1 = temp1 + temp2;\r
778 if (Res1 < temp1)\r
779 Res2 += 0x00010000;\r
780 temp1 = (Res1 << 16) & 0xffff0000;\r
781 Res0 = temp0 + temp1;\r
782 if (Res0 < temp0)\r
783 Res2++;\r
784 Res2 = Res2 + ((Res1 >> 16) & 0x0000ffff) + temp3;\r
785 sh2->mach = Res2;\r
786 sh2->macl = Res0;\r
f4c0720c 787 sh2->icount--;\r
eaa10a6e 788}\r
789\r
790/* DT Rn */\r
f4c0720c 791INLINE void DT(sh2_state *sh2, UINT32 n)\r
eaa10a6e 792{\r
793 sh2->r[n]--;\r
794 if (sh2->r[n] == 0)\r
795 sh2->sr |= T;\r
796 else\r
797 sh2->sr &= ~T;\r
798#if BUSY_LOOP_HACKS\r
799 {\r
f4c0720c 800 UINT32 next_opcode = RW( sh2, sh2->ppc & AM );\r
eaa10a6e 801 /* DT Rn\r
f4c0720c 802 * BF $-2\r
803 */\r
eaa10a6e 804 if (next_opcode == 0x8bfd)\r
805 {\r
f4c0720c 806 while (sh2->r[n] > 1 && sh2->icount > 4)\r
eaa10a6e 807 {\r
808 sh2->r[n]--;\r
f4c0720c 809 sh2->icount -= 4; /* cycles for DT (1) and BF taken (3) */\r
eaa10a6e 810 }\r
811 }\r
812 }\r
813#endif\r
814}\r
815\r
816/* EXTS.B Rm,Rn */\r
f4c0720c 817INLINE void EXTSB(sh2_state *sh2, UINT32 m, UINT32 n)\r
eaa10a6e 818{\r
819 sh2->r[n] = ((INT32)sh2->r[m] << 24) >> 24;\r
820}\r
821\r
822/* EXTS.W Rm,Rn */\r
f4c0720c 823INLINE void EXTSW(sh2_state *sh2, UINT32 m, UINT32 n)\r
eaa10a6e 824{\r
825 sh2->r[n] = ((INT32)sh2->r[m] << 16) >> 16;\r
826}\r
827\r
828/* EXTU.B Rm,Rn */\r
f4c0720c 829INLINE void EXTUB(sh2_state *sh2, UINT32 m, UINT32 n)\r
eaa10a6e 830{\r
831 sh2->r[n] = sh2->r[m] & 0x000000ff;\r
832}\r
833\r
834/* EXTU.W Rm,Rn */\r
f4c0720c 835INLINE void EXTUW(sh2_state *sh2, UINT32 m, UINT32 n)\r
eaa10a6e 836{\r
837 sh2->r[n] = sh2->r[m] & 0x0000ffff;\r
838}\r
839\r
f4c0720c 840/* ILLEGAL */\r
841INLINE void ILLEGAL(sh2_state *sh2)\r
842{\r
843 logerror("SH2: Illegal opcode at %08x\n", sh2->pc - 2);\r
844 sh2->r[15] -= 4;\r
845 WL( sh2, sh2->r[15], sh2->sr ); /* push SR onto stack */\r
846 sh2->r[15] -= 4;\r
847 WL( sh2, sh2->r[15], sh2->pc - 2 ); /* push PC onto stack */\r
848\r
849 /* fetch PC */\r
850 sh2->pc = RL( sh2, sh2->vbr + 4 * 4 );\r
851\r
852 /* TODO: timing is a guess */\r
853 sh2->icount -= 5;\r
854}\r
855\r
856\r
eaa10a6e 857/* JMP @Rm */\r
f4c0720c 858INLINE void JMP(sh2_state *sh2, UINT32 m)\r
eaa10a6e 859{\r
860 sh2->delay = sh2->pc;\r
861 sh2->pc = sh2->ea = sh2->r[m];\r
862}\r
863\r
864/* JSR @Rm */\r
f4c0720c 865INLINE void JSR(sh2_state *sh2, UINT32 m)\r
eaa10a6e 866{\r
867 sh2->delay = sh2->pc;\r
868 sh2->pr = sh2->pc + 2;\r
869 sh2->pc = sh2->ea = sh2->r[m];\r
f4c0720c 870 sh2->icount--;\r
eaa10a6e 871}\r
872\r
873\r
874/* LDC Rm,SR */\r
f4c0720c 875INLINE void LDCSR(sh2_state *sh2, UINT32 m)\r
eaa10a6e 876{\r
f4c0720c 877 sh2->sr = sh2->r[m] & FLAGS;\r
eaa10a6e 878 sh2->test_irq = 1;\r
879}\r
880\r
881/* LDC Rm,GBR */\r
f4c0720c 882INLINE void LDCGBR(sh2_state *sh2, UINT32 m)\r
eaa10a6e 883{\r
884 sh2->gbr = sh2->r[m];\r
885}\r
886\r
887/* LDC Rm,VBR */\r
f4c0720c 888INLINE void LDCVBR(sh2_state *sh2, UINT32 m)\r
eaa10a6e 889{\r
890 sh2->vbr = sh2->r[m];\r
891}\r
892\r
893/* LDC.L @Rm+,SR */\r
f4c0720c 894INLINE void LDCMSR(sh2_state *sh2, UINT32 m)\r
eaa10a6e 895{\r
896 sh2->ea = sh2->r[m];\r
f4c0720c 897 sh2->sr = RL( sh2, sh2->ea ) & FLAGS;\r
eaa10a6e 898 sh2->r[m] += 4;\r
f4c0720c 899 sh2->icount -= 2;\r
eaa10a6e 900 sh2->test_irq = 1;\r
901}\r
902\r
903/* LDC.L @Rm+,GBR */\r
f4c0720c 904INLINE void LDCMGBR(sh2_state *sh2, UINT32 m)\r
eaa10a6e 905{\r
906 sh2->ea = sh2->r[m];\r
f4c0720c 907 sh2->gbr = RL( sh2, sh2->ea );\r
eaa10a6e 908 sh2->r[m] += 4;\r
f4c0720c 909 sh2->icount -= 2;\r
eaa10a6e 910}\r
911\r
912/* LDC.L @Rm+,VBR */\r
f4c0720c 913INLINE void LDCMVBR(sh2_state *sh2, UINT32 m)\r
eaa10a6e 914{\r
915 sh2->ea = sh2->r[m];\r
f4c0720c 916 sh2->vbr = RL( sh2, sh2->ea );\r
eaa10a6e 917 sh2->r[m] += 4;\r
f4c0720c 918 sh2->icount -= 2;\r
eaa10a6e 919}\r
920\r
921/* LDS Rm,MACH */\r
f4c0720c 922INLINE void LDSMACH(sh2_state *sh2, UINT32 m)\r
eaa10a6e 923{\r
924 sh2->mach = sh2->r[m];\r
925}\r
926\r
927/* LDS Rm,MACL */\r
f4c0720c 928INLINE void LDSMACL(sh2_state *sh2, UINT32 m)\r
eaa10a6e 929{\r
930 sh2->macl = sh2->r[m];\r
931}\r
932\r
933/* LDS Rm,PR */\r
f4c0720c 934INLINE void LDSPR(sh2_state *sh2, UINT32 m)\r
eaa10a6e 935{\r
936 sh2->pr = sh2->r[m];\r
937}\r
938\r
939/* LDS.L @Rm+,MACH */\r
f4c0720c 940INLINE void LDSMMACH(sh2_state *sh2, UINT32 m)\r
eaa10a6e 941{\r
942 sh2->ea = sh2->r[m];\r
f4c0720c 943 sh2->mach = RL( sh2, sh2->ea );\r
eaa10a6e 944 sh2->r[m] += 4;\r
945}\r
946\r
947/* LDS.L @Rm+,MACL */\r
f4c0720c 948INLINE void LDSMMACL(sh2_state *sh2, UINT32 m)\r
eaa10a6e 949{\r
950 sh2->ea = sh2->r[m];\r
f4c0720c 951 sh2->macl = RL( sh2, sh2->ea );\r
eaa10a6e 952 sh2->r[m] += 4;\r
953}\r
954\r
955/* LDS.L @Rm+,PR */\r
f4c0720c 956INLINE void LDSMPR(sh2_state *sh2, UINT32 m)\r
eaa10a6e 957{\r
958 sh2->ea = sh2->r[m];\r
f4c0720c 959 sh2->pr = RL( sh2, sh2->ea );\r
eaa10a6e 960 sh2->r[m] += 4;\r
961}\r
962\r
963/* MAC.L @Rm+,@Rn+ */\r
f4c0720c 964INLINE void MAC_L(sh2_state *sh2, UINT32 m, UINT32 n)\r
eaa10a6e 965{\r
966 UINT32 RnL, RnH, RmL, RmH, Res0, Res1, Res2;\r
967 UINT32 temp0, temp1, temp2, temp3;\r
968 INT32 tempm, tempn, fnLmL;\r
969\r
f4c0720c 970 tempn = (INT32) RL( sh2, sh2->r[n] );\r
eaa10a6e 971 sh2->r[n] += 4;\r
f4c0720c 972 tempm = (INT32) RL( sh2, sh2->r[m] );\r
eaa10a6e 973 sh2->r[m] += 4;\r
974 if ((INT32) (tempn ^ tempm) < 0)\r
975 fnLmL = -1;\r
976 else\r
977 fnLmL = 0;\r
978 if (tempn < 0)\r
979 tempn = 0 - tempn;\r
980 if (tempm < 0)\r
981 tempm = 0 - tempm;\r
982 temp1 = (UINT32) tempn;\r
983 temp2 = (UINT32) tempm;\r
984 RnL = temp1 & 0x0000ffff;\r
985 RnH = (temp1 >> 16) & 0x0000ffff;\r
986 RmL = temp2 & 0x0000ffff;\r
987 RmH = (temp2 >> 16) & 0x0000ffff;\r
988 temp0 = RmL * RnL;\r
989 temp1 = RmH * RnL;\r
990 temp2 = RmL * RnH;\r
991 temp3 = RmH * RnH;\r
992 Res2 = 0;\r
993 Res1 = temp1 + temp2;\r
994 if (Res1 < temp1)\r
995 Res2 += 0x00010000;\r
996 temp1 = (Res1 << 16) & 0xffff0000;\r
997 Res0 = temp0 + temp1;\r
998 if (Res0 < temp0)\r
999 Res2++;\r
1000 Res2 = Res2 + ((Res1 >> 16) & 0x0000ffff) + temp3;\r
1001 if (fnLmL < 0)\r
1002 {\r
1003 Res2 = ~Res2;\r
1004 if (Res0 == 0)\r
1005 Res2++;\r
1006 else\r
1007 Res0 = (~Res0) + 1;\r
1008 }\r
1009 if (sh2->sr & S)\r
1010 {\r
1011 Res0 = sh2->macl + Res0;\r
1012 if (sh2->macl > Res0)\r
1013 Res2++;\r
1014 Res2 += (sh2->mach & 0x0000ffff);\r
1015 if (((INT32) Res2 < 0) && (Res2 < 0xffff8000))\r
1016 {\r
1017 Res2 = 0x00008000;\r
1018 Res0 = 0x00000000;\r
1019 }\r
1020 else if (((INT32) Res2 > 0) && (Res2 > 0x00007fff))\r
1021 {\r
1022 Res2 = 0x00007fff;\r
1023 Res0 = 0xffffffff;\r
1024 }\r
1025 sh2->mach = Res2;\r
1026 sh2->macl = Res0;\r
1027 }\r
1028 else\r
1029 {\r
1030 Res0 = sh2->macl + Res0;\r
1031 if (sh2->macl > Res0)\r
1032 Res2++;\r
1033 Res2 += sh2->mach;\r
1034 sh2->mach = Res2;\r
1035 sh2->macl = Res0;\r
1036 }\r
f4c0720c 1037 sh2->icount -= 2;\r
eaa10a6e 1038}\r
1039\r
1040/* MAC.W @Rm+,@Rn+ */\r
f4c0720c 1041INLINE void MAC_W(sh2_state *sh2, UINT32 m, UINT32 n)\r
eaa10a6e 1042{\r
1043 INT32 tempm, tempn, dest, src, ans;\r
1044 UINT32 templ;\r
1045\r
f4c0720c 1046 tempn = (INT32) RW( sh2, sh2->r[n] );\r
eaa10a6e 1047 sh2->r[n] += 2;\r
f4c0720c 1048 tempm = (INT32) RW( sh2, sh2->r[m] );\r
eaa10a6e 1049 sh2->r[m] += 2;\r
1050 templ = sh2->macl;\r
1051 tempm = ((INT32) (short) tempn * (INT32) (short) tempm);\r
1052 if ((INT32) sh2->macl >= 0)\r
1053 dest = 0;\r
1054 else\r
1055 dest = 1;\r
1056 if ((INT32) tempm >= 0)\r
1057 {\r
1058 src = 0;\r
1059 tempn = 0;\r
1060 }\r
1061 else\r
1062 {\r
1063 src = 1;\r
1064 tempn = 0xffffffff;\r
1065 }\r
1066 src += dest;\r
1067 sh2->macl += tempm;\r
1068 if ((INT32) sh2->macl >= 0)\r
1069 ans = 0;\r
1070 else\r
1071 ans = 1;\r
1072 ans += dest;\r
1073 if (sh2->sr & S)\r
1074 {\r
1075 if (ans == 1)\r
1076 {\r
1077 if (src == 0)\r
1078 sh2->macl = 0x7fffffff;\r
1079 if (src == 2)\r
1080 sh2->macl = 0x80000000;\r
1081 }\r
1082 }\r
1083 else\r
1084 {\r
1085 sh2->mach += tempn;\r
1086 if (templ > sh2->macl)\r
1087 sh2->mach += 1;\r
f4c0720c 1088 }\r
1089 sh2->icount -= 2;\r
eaa10a6e 1090}\r
1091\r
1092/* MOV Rm,Rn */\r
f4c0720c 1093INLINE void MOV(sh2_state *sh2, UINT32 m, UINT32 n)\r
eaa10a6e 1094{\r
1095 sh2->r[n] = sh2->r[m];\r
1096}\r
1097\r
1098/* MOV.B Rm,@Rn */\r
f4c0720c 1099INLINE void MOVBS(sh2_state *sh2, UINT32 m, UINT32 n)\r
eaa10a6e 1100{\r
1101 sh2->ea = sh2->r[n];\r
f4c0720c 1102 WB( sh2, sh2->ea, sh2->r[m] & 0x000000ff);\r
eaa10a6e 1103}\r
1104\r
1105/* MOV.W Rm,@Rn */\r
f4c0720c 1106INLINE void MOVWS(sh2_state *sh2, UINT32 m, UINT32 n)\r
eaa10a6e 1107{\r
1108 sh2->ea = sh2->r[n];\r
f4c0720c 1109 WW( sh2, sh2->ea, sh2->r[m] & 0x0000ffff);\r
eaa10a6e 1110}\r
1111\r
1112/* MOV.L Rm,@Rn */\r
f4c0720c 1113INLINE void MOVLS(sh2_state *sh2, UINT32 m, UINT32 n)\r
eaa10a6e 1114{\r
1115 sh2->ea = sh2->r[n];\r
f4c0720c 1116 WL( sh2, sh2->ea, sh2->r[m] );\r
eaa10a6e 1117}\r
1118\r
1119/* MOV.B @Rm,Rn */\r
f4c0720c 1120INLINE void MOVBL(sh2_state *sh2, UINT32 m, UINT32 n)\r
eaa10a6e 1121{\r
1122 sh2->ea = sh2->r[m];\r
f4c0720c 1123 sh2->r[n] = (UINT32)(INT32)(INT16)(INT8) RB( sh2, sh2->ea );\r
eaa10a6e 1124}\r
1125\r
1126/* MOV.W @Rm,Rn */\r
f4c0720c 1127INLINE void MOVWL(sh2_state *sh2, UINT32 m, UINT32 n)\r
eaa10a6e 1128{\r
1129 sh2->ea = sh2->r[m];\r
f4c0720c 1130 sh2->r[n] = (UINT32)(INT32)(INT16) RW( sh2, sh2->ea );\r
eaa10a6e 1131}\r
1132\r
1133/* MOV.L @Rm,Rn */\r
f4c0720c 1134INLINE void MOVLL(sh2_state *sh2, UINT32 m, UINT32 n)\r
eaa10a6e 1135{\r
1136 sh2->ea = sh2->r[m];\r
f4c0720c 1137 sh2->r[n] = RL( sh2, sh2->ea );\r
eaa10a6e 1138}\r
1139\r
1140/* MOV.B Rm,@-Rn */\r
f4c0720c 1141INLINE void MOVBM(sh2_state *sh2, UINT32 m, UINT32 n)\r
eaa10a6e 1142{\r
1143 /* SMG : bug fix, was reading sh2->r[n] */\r
1144 UINT32 data = sh2->r[m] & 0x000000ff;\r
1145\r
1146 sh2->r[n] -= 1;\r
f4c0720c 1147 WB( sh2, sh2->r[n], data );\r
eaa10a6e 1148}\r
1149\r
1150/* MOV.W Rm,@-Rn */\r
f4c0720c 1151INLINE void MOVWM(sh2_state *sh2, UINT32 m, UINT32 n)\r
eaa10a6e 1152{\r
1153 UINT32 data = sh2->r[m] & 0x0000ffff;\r
1154\r
1155 sh2->r[n] -= 2;\r
f4c0720c 1156 WW( sh2, sh2->r[n], data );\r
eaa10a6e 1157}\r
1158\r
1159/* MOV.L Rm,@-Rn */\r
f4c0720c 1160INLINE void MOVLM(sh2_state *sh2, UINT32 m, UINT32 n)\r
eaa10a6e 1161{\r
1162 UINT32 data = sh2->r[m];\r
1163\r
1164 sh2->r[n] -= 4;\r
f4c0720c 1165 WL( sh2, sh2->r[n], data );\r
eaa10a6e 1166}\r
1167\r
1168/* MOV.B @Rm+,Rn */\r
f4c0720c 1169INLINE void MOVBP(sh2_state *sh2, UINT32 m, UINT32 n)\r
eaa10a6e 1170{\r
f4c0720c 1171 sh2->r[n] = (UINT32)(INT32)(INT16)(INT8) RB( sh2, sh2->r[m] );\r
eaa10a6e 1172 if (n != m)\r
1173 sh2->r[m] += 1;\r
1174}\r
1175\r
1176/* MOV.W @Rm+,Rn */\r
f4c0720c 1177INLINE void MOVWP(sh2_state *sh2, UINT32 m, UINT32 n)\r
eaa10a6e 1178{\r
f4c0720c 1179 sh2->r[n] = (UINT32)(INT32)(INT16) RW( sh2, sh2->r[m] );\r
eaa10a6e 1180 if (n != m)\r
1181 sh2->r[m] += 2;\r
1182}\r
1183\r
1184/* MOV.L @Rm+,Rn */\r
f4c0720c 1185INLINE void MOVLP(sh2_state *sh2, UINT32 m, UINT32 n)\r
eaa10a6e 1186{\r
f4c0720c 1187 sh2->r[n] = RL( sh2, sh2->r[m] );\r
eaa10a6e 1188 if (n != m)\r
1189 sh2->r[m] += 4;\r
1190}\r
1191\r
1192/* MOV.B Rm,@(R0,Rn) */\r
f4c0720c 1193INLINE void MOVBS0(sh2_state *sh2, UINT32 m, UINT32 n)\r
eaa10a6e 1194{\r
1195 sh2->ea = sh2->r[n] + sh2->r[0];\r
f4c0720c 1196 WB( sh2, sh2->ea, sh2->r[m] & 0x000000ff );\r
eaa10a6e 1197}\r
1198\r
1199/* MOV.W Rm,@(R0,Rn) */\r
f4c0720c 1200INLINE void MOVWS0(sh2_state *sh2, UINT32 m, UINT32 n)\r
eaa10a6e 1201{\r
1202 sh2->ea = sh2->r[n] + sh2->r[0];\r
f4c0720c 1203 WW( sh2, sh2->ea, sh2->r[m] & 0x0000ffff );\r
eaa10a6e 1204}\r
1205\r
1206/* MOV.L Rm,@(R0,Rn) */\r
f4c0720c 1207INLINE void MOVLS0(sh2_state *sh2, UINT32 m, UINT32 n)\r
eaa10a6e 1208{\r
1209 sh2->ea = sh2->r[n] + sh2->r[0];\r
f4c0720c 1210 WL( sh2, sh2->ea, sh2->r[m] );\r
eaa10a6e 1211}\r
1212\r
1213/* MOV.B @(R0,Rm),Rn */\r
f4c0720c 1214INLINE void MOVBL0(sh2_state *sh2, UINT32 m, UINT32 n)\r
eaa10a6e 1215{\r
1216 sh2->ea = sh2->r[m] + sh2->r[0];\r
f4c0720c 1217 sh2->r[n] = (UINT32)(INT32)(INT16)(INT8) RB( sh2, sh2->ea );\r
eaa10a6e 1218}\r
1219\r
1220/* MOV.W @(R0,Rm),Rn */\r
f4c0720c 1221INLINE void MOVWL0(sh2_state *sh2, UINT32 m, UINT32 n)\r
eaa10a6e 1222{\r
1223 sh2->ea = sh2->r[m] + sh2->r[0];\r
f4c0720c 1224 sh2->r[n] = (UINT32)(INT32)(INT16) RW( sh2, sh2->ea );\r
eaa10a6e 1225}\r
1226\r
1227/* MOV.L @(R0,Rm),Rn */\r
f4c0720c 1228INLINE void MOVLL0(sh2_state *sh2, UINT32 m, UINT32 n)\r
eaa10a6e 1229{\r
1230 sh2->ea = sh2->r[m] + sh2->r[0];\r
f4c0720c 1231 sh2->r[n] = RL( sh2, sh2->ea );\r
eaa10a6e 1232}\r
1233\r
1234/* MOV #imm,Rn */\r
f4c0720c 1235INLINE void MOVI(sh2_state *sh2, UINT32 i, UINT32 n)\r
eaa10a6e 1236{\r
1237 sh2->r[n] = (UINT32)(INT32)(INT16)(INT8) i;\r
1238}\r
1239\r
1240/* MOV.W @(disp8,PC),Rn */\r
f4c0720c 1241INLINE void MOVWI(sh2_state *sh2, UINT32 d, UINT32 n)\r
eaa10a6e 1242{\r
1243 UINT32 disp = d & 0xff;\r
1244 sh2->ea = sh2->pc + disp * 2 + 2;\r
f4c0720c 1245 sh2->r[n] = (UINT32)(INT32)(INT16) RW( sh2, sh2->ea );\r
eaa10a6e 1246}\r
1247\r
1248/* MOV.L @(disp8,PC),Rn */\r
f4c0720c 1249INLINE void MOVLI(sh2_state *sh2, UINT32 d, UINT32 n)\r
eaa10a6e 1250{\r
1251 UINT32 disp = d & 0xff;\r
1252 sh2->ea = ((sh2->pc + 2) & ~3) + disp * 4;\r
f4c0720c 1253 sh2->r[n] = RL( sh2, sh2->ea );\r
eaa10a6e 1254}\r
1255\r
1256/* MOV.B @(disp8,GBR),R0 */\r
f4c0720c 1257INLINE void MOVBLG(sh2_state *sh2, UINT32 d)\r
eaa10a6e 1258{\r
1259 UINT32 disp = d & 0xff;\r
1260 sh2->ea = sh2->gbr + disp;\r
f4c0720c 1261 sh2->r[0] = (UINT32)(INT32)(INT16)(INT8) RB( sh2, sh2->ea );\r
eaa10a6e 1262}\r
1263\r
1264/* MOV.W @(disp8,GBR),R0 */\r
f4c0720c 1265INLINE void MOVWLG(sh2_state *sh2, UINT32 d)\r
eaa10a6e 1266{\r
1267 UINT32 disp = d & 0xff;\r
1268 sh2->ea = sh2->gbr + disp * 2;\r
f4c0720c 1269 sh2->r[0] = (INT32)(INT16) RW( sh2, sh2->ea );\r
eaa10a6e 1270}\r
1271\r
1272/* MOV.L @(disp8,GBR),R0 */\r
f4c0720c 1273INLINE void MOVLLG(sh2_state *sh2, UINT32 d)\r
eaa10a6e 1274{\r
1275 UINT32 disp = d & 0xff;\r
1276 sh2->ea = sh2->gbr + disp * 4;\r
f4c0720c 1277 sh2->r[0] = RL( sh2, sh2->ea );\r
eaa10a6e 1278}\r
1279\r
1280/* MOV.B R0,@(disp8,GBR) */\r
f4c0720c 1281INLINE void MOVBSG(sh2_state *sh2, UINT32 d)\r
eaa10a6e 1282{\r
1283 UINT32 disp = d & 0xff;\r
1284 sh2->ea = sh2->gbr + disp;\r
f4c0720c 1285 WB( sh2, sh2->ea, sh2->r[0] & 0x000000ff );\r
eaa10a6e 1286}\r
1287\r
1288/* MOV.W R0,@(disp8,GBR) */\r
f4c0720c 1289INLINE void MOVWSG(sh2_state *sh2, UINT32 d)\r
eaa10a6e 1290{\r
1291 UINT32 disp = d & 0xff;\r
1292 sh2->ea = sh2->gbr + disp * 2;\r
f4c0720c 1293 WW( sh2, sh2->ea, sh2->r[0] & 0x0000ffff );\r
eaa10a6e 1294}\r
1295\r
1296/* MOV.L R0,@(disp8,GBR) */\r
f4c0720c 1297INLINE void MOVLSG(sh2_state *sh2, UINT32 d)\r
eaa10a6e 1298{\r
1299 UINT32 disp = d & 0xff;\r
1300 sh2->ea = sh2->gbr + disp * 4;\r
f4c0720c 1301 WL( sh2, sh2->ea, sh2->r[0] );\r
eaa10a6e 1302}\r
1303\r
1304/* MOV.B R0,@(disp4,Rn) */\r
f4c0720c 1305INLINE void MOVBS4(sh2_state *sh2, UINT32 d, UINT32 n)\r
eaa10a6e 1306{\r
1307 UINT32 disp = d & 0x0f;\r
1308 sh2->ea = sh2->r[n] + disp;\r
f4c0720c 1309 WB( sh2, sh2->ea, sh2->r[0] & 0x000000ff );\r
eaa10a6e 1310}\r
1311\r
1312/* MOV.W R0,@(disp4,Rn) */\r
f4c0720c 1313INLINE void MOVWS4(sh2_state *sh2, UINT32 d, UINT32 n)\r
eaa10a6e 1314{\r
1315 UINT32 disp = d & 0x0f;\r
1316 sh2->ea = sh2->r[n] + disp * 2;\r
f4c0720c 1317 WW( sh2, sh2->ea, sh2->r[0] & 0x0000ffff );\r
eaa10a6e 1318}\r
1319\r
1320/* MOV.L Rm,@(disp4,Rn) */\r
f4c0720c 1321INLINE void MOVLS4(sh2_state *sh2, UINT32 m, UINT32 d, UINT32 n)\r
eaa10a6e 1322{\r
1323 UINT32 disp = d & 0x0f;\r
1324 sh2->ea = sh2->r[n] + disp * 4;\r
f4c0720c 1325 WL( sh2, sh2->ea, sh2->r[m] );\r
eaa10a6e 1326}\r
1327\r
1328/* MOV.B @(disp4,Rm),R0 */\r
f4c0720c 1329INLINE void MOVBL4(sh2_state *sh2, UINT32 m, UINT32 d)\r
eaa10a6e 1330{\r
1331 UINT32 disp = d & 0x0f;\r
1332 sh2->ea = sh2->r[m] + disp;\r
f4c0720c 1333 sh2->r[0] = (UINT32)(INT32)(INT16)(INT8) RB( sh2, sh2->ea );\r
eaa10a6e 1334}\r
1335\r
1336/* MOV.W @(disp4,Rm),R0 */\r
f4c0720c 1337INLINE void MOVWL4(sh2_state *sh2, UINT32 m, UINT32 d)\r
eaa10a6e 1338{\r
1339 UINT32 disp = d & 0x0f;\r
1340 sh2->ea = sh2->r[m] + disp * 2;\r
f4c0720c 1341 sh2->r[0] = (UINT32)(INT32)(INT16) RW( sh2, sh2->ea );\r
eaa10a6e 1342}\r
1343\r
1344/* MOV.L @(disp4,Rm),Rn */\r
f4c0720c 1345INLINE void MOVLL4(sh2_state *sh2, UINT32 m, UINT32 d, UINT32 n)\r
eaa10a6e 1346{\r
1347 UINT32 disp = d & 0x0f;\r
1348 sh2->ea = sh2->r[m] + disp * 4;\r
f4c0720c 1349 sh2->r[n] = RL( sh2, sh2->ea );\r
eaa10a6e 1350}\r
1351\r
1352/* MOVA @(disp8,PC),R0 */\r
f4c0720c 1353INLINE void MOVA(sh2_state *sh2, UINT32 d)\r
eaa10a6e 1354{\r
1355 UINT32 disp = d & 0xff;\r
1356 sh2->ea = ((sh2->pc + 2) & ~3) + disp * 4;\r
1357 sh2->r[0] = sh2->ea;\r
1358}\r
1359\r
1360/* MOVT Rn */\r
f4c0720c 1361INLINE void MOVT(sh2_state *sh2, UINT32 n)\r
eaa10a6e 1362{\r
1363 sh2->r[n] = sh2->sr & T;\r
1364}\r
1365\r
1366/* MUL.L Rm,Rn */\r
f4c0720c 1367INLINE void MULL(sh2_state *sh2, UINT32 m, UINT32 n)\r
eaa10a6e 1368{\r
1369 sh2->macl = sh2->r[n] * sh2->r[m];\r
f4c0720c 1370 sh2->icount--;\r
eaa10a6e 1371}\r
1372\r
1373/* MULS Rm,Rn */\r
f4c0720c 1374INLINE void MULS(sh2_state *sh2, UINT32 m, UINT32 n)\r
eaa10a6e 1375{\r
1376 sh2->macl = (INT16) sh2->r[n] * (INT16) sh2->r[m];\r
1377}\r
1378\r
1379/* MULU Rm,Rn */\r
f4c0720c 1380INLINE void MULU(sh2_state *sh2, UINT32 m, UINT32 n)\r
eaa10a6e 1381{\r
1382 sh2->macl = (UINT16) sh2->r[n] * (UINT16) sh2->r[m];\r
1383}\r
1384\r
1385/* NEG Rm,Rn */\r
f4c0720c 1386INLINE void NEG(sh2_state *sh2, UINT32 m, UINT32 n)\r
eaa10a6e 1387{\r
1388 sh2->r[n] = 0 - sh2->r[m];\r
1389}\r
1390\r
1391/* NEGC Rm,Rn */\r
f4c0720c 1392INLINE void NEGC(sh2_state *sh2, UINT32 m, UINT32 n)\r
eaa10a6e 1393{\r
1394 UINT32 temp;\r
1395\r
1396 temp = sh2->r[m];\r
1397 sh2->r[n] = -temp - (sh2->sr & T);\r
1398 if (temp || (sh2->sr & T))\r
1399 sh2->sr |= T;\r
1400 else\r
1401 sh2->sr &= ~T;\r
1402}\r
1403\r
1404/* NOP */\r
1405INLINE void NOP(void)\r
1406{\r
1407}\r
1408\r
1409/* NOT Rm,Rn */\r
f4c0720c 1410INLINE void NOT(sh2_state *sh2, UINT32 m, UINT32 n)\r
eaa10a6e 1411{\r
1412 sh2->r[n] = ~sh2->r[m];\r
1413}\r
1414\r
1415/* OR Rm,Rn */\r
f4c0720c 1416INLINE void OR(sh2_state *sh2, UINT32 m, UINT32 n)\r
eaa10a6e 1417{\r
1418 sh2->r[n] |= sh2->r[m];\r
1419}\r
1420\r
1421/* OR #imm,R0 */\r
f4c0720c 1422INLINE void ORI(sh2_state *sh2, UINT32 i)\r
eaa10a6e 1423{\r
1424 sh2->r[0] |= i;\r
f4c0720c 1425 sh2->icount -= 2;\r
eaa10a6e 1426}\r
1427\r
1428/* OR.B #imm,@(R0,GBR) */\r
f4c0720c 1429INLINE void ORM(sh2_state *sh2, UINT32 i)\r
eaa10a6e 1430{\r
1431 UINT32 temp;\r
1432\r
1433 sh2->ea = sh2->gbr + sh2->r[0];\r
f4c0720c 1434 temp = RB( sh2, sh2->ea );\r
eaa10a6e 1435 temp |= i;\r
f4c0720c 1436 WB( sh2, sh2->ea, temp );\r
eaa10a6e 1437}\r
1438\r
1439/* ROTCL Rn */\r
f4c0720c 1440INLINE void ROTCL(sh2_state *sh2, UINT32 n)\r
eaa10a6e 1441{\r
1442 UINT32 temp;\r
1443\r
1444 temp = (sh2->r[n] >> 31) & T;\r
1445 sh2->r[n] = (sh2->r[n] << 1) | (sh2->sr & T);\r
1446 sh2->sr = (sh2->sr & ~T) | temp;\r
1447}\r
1448\r
1449/* ROTCR Rn */\r
f4c0720c 1450INLINE void ROTCR(sh2_state *sh2, UINT32 n)\r
eaa10a6e 1451{\r
1452 UINT32 temp;\r
1453 temp = (sh2->sr & T) << 31;\r
1454 if (sh2->r[n] & T)\r
1455 sh2->sr |= T;\r
1456 else\r
1457 sh2->sr &= ~T;\r
1458 sh2->r[n] = (sh2->r[n] >> 1) | temp;\r
1459}\r
1460\r
1461/* ROTL Rn */\r
f4c0720c 1462INLINE void ROTL(sh2_state *sh2, UINT32 n)\r
eaa10a6e 1463{\r
1464 sh2->sr = (sh2->sr & ~T) | ((sh2->r[n] >> 31) & T);\r
1465 sh2->r[n] = (sh2->r[n] << 1) | (sh2->r[n] >> 31);\r
1466}\r
1467\r
1468/* ROTR Rn */\r
f4c0720c 1469INLINE void ROTR(sh2_state *sh2, UINT32 n)\r
eaa10a6e 1470{\r
1471 sh2->sr = (sh2->sr & ~T) | (sh2->r[n] & T);\r
1472 sh2->r[n] = (sh2->r[n] >> 1) | (sh2->r[n] << 31);\r
1473}\r
1474\r
1475/* RTE */\r
f4c0720c 1476INLINE void RTE(sh2_state *sh2)\r
eaa10a6e 1477{\r
1478 sh2->ea = sh2->r[15];\r
1479 sh2->delay = sh2->pc;\r
f4c0720c 1480 sh2->pc = RL( sh2, sh2->ea );\r
eaa10a6e 1481 sh2->r[15] += 4;\r
1482 sh2->ea = sh2->r[15];\r
f4c0720c 1483 sh2->sr = RL( sh2, sh2->ea ) & FLAGS;\r
eaa10a6e 1484 sh2->r[15] += 4;\r
f4c0720c 1485 sh2->icount -= 3;\r
eaa10a6e 1486 sh2->test_irq = 1;\r
1487}\r
1488\r
1489/* RTS */\r
f4c0720c 1490INLINE void RTS(sh2_state *sh2)\r
eaa10a6e 1491{\r
1492 sh2->delay = sh2->pc;\r
1493 sh2->pc = sh2->ea = sh2->pr;\r
f4c0720c 1494 sh2->icount--;\r
eaa10a6e 1495}\r
1496\r
1497/* SETT */\r
f4c0720c 1498INLINE void SETT(sh2_state *sh2)\r
eaa10a6e 1499{\r
1500 sh2->sr |= T;\r
1501}\r
1502\r
1503/* SHAL Rn (same as SHLL) */\r
f4c0720c 1504INLINE void SHAL(sh2_state *sh2, UINT32 n)\r
eaa10a6e 1505{\r
1506 sh2->sr = (sh2->sr & ~T) | ((sh2->r[n] >> 31) & T);\r
1507 sh2->r[n] <<= 1;\r
1508}\r
1509\r
1510/* SHAR Rn */\r
f4c0720c 1511INLINE void SHAR(sh2_state *sh2, UINT32 n)\r
eaa10a6e 1512{\r
1513 sh2->sr = (sh2->sr & ~T) | (sh2->r[n] & T);\r
1514 sh2->r[n] = (UINT32)((INT32)sh2->r[n] >> 1);\r
1515}\r
1516\r
1517/* SHLL Rn (same as SHAL) */\r
f4c0720c 1518INLINE void SHLL(sh2_state *sh2, UINT32 n)\r
eaa10a6e 1519{\r
1520 sh2->sr = (sh2->sr & ~T) | ((sh2->r[n] >> 31) & T);\r
1521 sh2->r[n] <<= 1;\r
1522}\r
1523\r
1524/* SHLL2 Rn */\r
f4c0720c 1525INLINE void SHLL2(sh2_state *sh2, UINT32 n)\r
eaa10a6e 1526{\r
1527 sh2->r[n] <<= 2;\r
1528}\r
1529\r
1530/* SHLL8 Rn */\r
f4c0720c 1531INLINE void SHLL8(sh2_state *sh2, UINT32 n)\r
eaa10a6e 1532{\r
1533 sh2->r[n] <<= 8;\r
1534}\r
1535\r
1536/* SHLL16 Rn */\r
f4c0720c 1537INLINE void SHLL16(sh2_state *sh2, UINT32 n)\r
eaa10a6e 1538{\r
1539 sh2->r[n] <<= 16;\r
1540}\r
1541\r
1542/* SHLR Rn */\r
f4c0720c 1543INLINE void SHLR(sh2_state *sh2, UINT32 n)\r
eaa10a6e 1544{\r
1545 sh2->sr = (sh2->sr & ~T) | (sh2->r[n] & T);\r
1546 sh2->r[n] >>= 1;\r
1547}\r
1548\r
1549/* SHLR2 Rn */\r
f4c0720c 1550INLINE void SHLR2(sh2_state *sh2, UINT32 n)\r
eaa10a6e 1551{\r
1552 sh2->r[n] >>= 2;\r
1553}\r
1554\r
1555/* SHLR8 Rn */\r
f4c0720c 1556INLINE void SHLR8(sh2_state *sh2, UINT32 n)\r
eaa10a6e 1557{\r
1558 sh2->r[n] >>= 8;\r
1559}\r
1560\r
1561/* SHLR16 Rn */\r
f4c0720c 1562INLINE void SHLR16(sh2_state *sh2, UINT32 n)\r
eaa10a6e 1563{\r
1564 sh2->r[n] >>= 16;\r
1565}\r
1566\r
1567/* SLEEP */\r
f4c0720c 1568INLINE void SLEEP(sh2_state *sh2)\r
eaa10a6e 1569{\r
f4c0720c 1570 //if(sh2->sleep_mode != 2)\r
1571 sh2->pc -= 2;\r
1572 sh2->icount -= 2;\r
eaa10a6e 1573 /* Wait_for_exception; */\r
f4c0720c 1574 /*if(sh2->sleep_mode == 0)\r
1575 sh2->sleep_mode = 1;\r
1576 else if(sh2->sleep_mode == 2)\r
1577 sh2->sleep_mode = 0;*/\r
eaa10a6e 1578}\r
1579\r
1580/* STC SR,Rn */\r
f4c0720c 1581INLINE void STCSR(sh2_state *sh2, UINT32 n)\r
eaa10a6e 1582{\r
f4c0720c 1583 sh2->r[n] = sh2->sr;\r
eaa10a6e 1584}\r
1585\r
1586/* STC GBR,Rn */\r
f4c0720c 1587INLINE void STCGBR(sh2_state *sh2, UINT32 n)\r
eaa10a6e 1588{\r
1589 sh2->r[n] = sh2->gbr;\r
1590}\r
1591\r
1592/* STC VBR,Rn */\r
f4c0720c 1593INLINE void STCVBR(sh2_state *sh2, UINT32 n)\r
eaa10a6e 1594{\r
1595 sh2->r[n] = sh2->vbr;\r
1596}\r
1597\r
1598/* STC.L SR,@-Rn */\r
f4c0720c 1599INLINE void STCMSR(sh2_state *sh2, UINT32 n)\r
eaa10a6e 1600{\r
1601 sh2->r[n] -= 4;\r
1602 sh2->ea = sh2->r[n];\r
f4c0720c 1603 WL( sh2, sh2->ea, sh2->sr );\r
1604 sh2->icount--;\r
eaa10a6e 1605}\r
1606\r
1607/* STC.L GBR,@-Rn */\r
f4c0720c 1608INLINE void STCMGBR(sh2_state *sh2, UINT32 n)\r
eaa10a6e 1609{\r
1610 sh2->r[n] -= 4;\r
1611 sh2->ea = sh2->r[n];\r
f4c0720c 1612 WL( sh2, sh2->ea, sh2->gbr );\r
1613 sh2->icount--;\r
eaa10a6e 1614}\r
1615\r
1616/* STC.L VBR,@-Rn */\r
f4c0720c 1617INLINE void STCMVBR(sh2_state *sh2, UINT32 n)\r
eaa10a6e 1618{\r
1619 sh2->r[n] -= 4;\r
1620 sh2->ea = sh2->r[n];\r
f4c0720c 1621 WL( sh2, sh2->ea, sh2->vbr );\r
1622 sh2->icount--;\r
eaa10a6e 1623}\r
1624\r
1625/* STS MACH,Rn */\r
f4c0720c 1626INLINE void STSMACH(sh2_state *sh2, UINT32 n)\r
eaa10a6e 1627{\r
1628 sh2->r[n] = sh2->mach;\r
1629}\r
1630\r
1631/* STS MACL,Rn */\r
f4c0720c 1632INLINE void STSMACL(sh2_state *sh2, UINT32 n)\r
eaa10a6e 1633{\r
1634 sh2->r[n] = sh2->macl;\r
1635}\r
1636\r
1637/* STS PR,Rn */\r
f4c0720c 1638INLINE void STSPR(sh2_state *sh2, UINT32 n)\r
eaa10a6e 1639{\r
1640 sh2->r[n] = sh2->pr;\r
1641}\r
1642\r
1643/* STS.L MACH,@-Rn */\r
f4c0720c 1644INLINE void STSMMACH(sh2_state *sh2, UINT32 n)\r
eaa10a6e 1645{\r
1646 sh2->r[n] -= 4;\r
1647 sh2->ea = sh2->r[n];\r
f4c0720c 1648 WL( sh2, sh2->ea, sh2->mach );\r
eaa10a6e 1649}\r
1650\r
1651/* STS.L MACL,@-Rn */\r
f4c0720c 1652INLINE void STSMMACL(sh2_state *sh2, UINT32 n)\r
eaa10a6e 1653{\r
1654 sh2->r[n] -= 4;\r
1655 sh2->ea = sh2->r[n];\r
f4c0720c 1656 WL( sh2, sh2->ea, sh2->macl );\r
eaa10a6e 1657}\r
1658\r
1659/* STS.L PR,@-Rn */\r
f4c0720c 1660INLINE void STSMPR(sh2_state *sh2, UINT32 n)\r
eaa10a6e 1661{\r
1662 sh2->r[n] -= 4;\r
1663 sh2->ea = sh2->r[n];\r
f4c0720c 1664 WL( sh2, sh2->ea, sh2->pr );\r
eaa10a6e 1665}\r
1666\r
1667/* SUB Rm,Rn */\r
f4c0720c 1668INLINE void SUB(sh2_state *sh2, UINT32 m, UINT32 n)\r
eaa10a6e 1669{\r
1670 sh2->r[n] -= sh2->r[m];\r
1671}\r
1672\r
1673/* SUBC Rm,Rn */\r
f4c0720c 1674INLINE void SUBC(sh2_state *sh2, UINT32 m, UINT32 n)\r
eaa10a6e 1675{\r
1676 UINT32 tmp0, tmp1;\r
1677\r
1678 tmp1 = sh2->r[n] - sh2->r[m];\r
1679 tmp0 = sh2->r[n];\r
1680 sh2->r[n] = tmp1 - (sh2->sr & T);\r
1681 if (tmp0 < tmp1)\r
1682 sh2->sr |= T;\r
1683 else\r
1684 sh2->sr &= ~T;\r
1685 if (tmp1 < sh2->r[n])\r
1686 sh2->sr |= T;\r
1687}\r
1688\r
1689/* SUBV Rm,Rn */\r
f4c0720c 1690INLINE void SUBV(sh2_state *sh2, UINT32 m, UINT32 n)\r
eaa10a6e 1691{\r
1692 INT32 dest, src, ans;\r
1693\r
1694 if ((INT32) sh2->r[n] >= 0)\r
1695 dest = 0;\r
1696 else\r
1697 dest = 1;\r
1698 if ((INT32) sh2->r[m] >= 0)\r
1699 src = 0;\r
1700 else\r
1701 src = 1;\r
1702 src += dest;\r
1703 sh2->r[n] -= sh2->r[m];\r
1704 if ((INT32) sh2->r[n] >= 0)\r
1705 ans = 0;\r
1706 else\r
1707 ans = 1;\r
1708 ans += dest;\r
1709 if (src == 1)\r
1710 {\r
1711 if (ans == 1)\r
1712 sh2->sr |= T;\r
1713 else\r
1714 sh2->sr &= ~T;\r
1715 }\r
1716 else\r
1717 sh2->sr &= ~T;\r
1718}\r
1719\r
1720/* SWAP.B Rm,Rn */\r
f4c0720c 1721INLINE void SWAPB(sh2_state *sh2, UINT32 m, UINT32 n)\r
eaa10a6e 1722{\r
1723 UINT32 temp0, temp1;\r
1724\r
1725 temp0 = sh2->r[m] & 0xffff0000;\r
1726 temp1 = (sh2->r[m] & 0x000000ff) << 8;\r
1727 sh2->r[n] = (sh2->r[m] >> 8) & 0x000000ff;\r
1728 sh2->r[n] = sh2->r[n] | temp1 | temp0;\r
1729}\r
1730\r
1731/* SWAP.W Rm,Rn */\r
f4c0720c 1732INLINE void SWAPW(sh2_state *sh2, UINT32 m, UINT32 n)\r
eaa10a6e 1733{\r
1734 UINT32 temp;\r
1735\r
1736 temp = (sh2->r[m] >> 16) & 0x0000ffff;\r
1737 sh2->r[n] = (sh2->r[m] << 16) | temp;\r
1738}\r
1739\r
1740/* TAS.B @Rn */\r
f4c0720c 1741INLINE void TAS(sh2_state *sh2, UINT32 n)\r
eaa10a6e 1742{\r
1743 UINT32 temp;\r
1744 sh2->ea = sh2->r[n];\r
1745 /* Bus Lock enable */\r
f4c0720c 1746 temp = RB( sh2, sh2->ea );\r
eaa10a6e 1747 if (temp == 0)\r
1748 sh2->sr |= T;\r
1749 else\r
1750 sh2->sr &= ~T;\r
1751 temp |= 0x80;\r
1752 /* Bus Lock disable */\r
f4c0720c 1753 WB( sh2, sh2->ea, temp );\r
1754 sh2->icount -= 3;\r
eaa10a6e 1755}\r
1756\r
1757/* TRAPA #imm */\r
f4c0720c 1758INLINE void TRAPA(sh2_state *sh2, UINT32 i)\r
eaa10a6e 1759{\r
1760 UINT32 imm = i & 0xff;\r
1761\r
1762 sh2->ea = sh2->vbr + imm * 4;\r
1763\r
1764 sh2->r[15] -= 4;\r
f4c0720c 1765 WL( sh2, sh2->r[15], sh2->sr );\r
eaa10a6e 1766 sh2->r[15] -= 4;\r
f4c0720c 1767 WL( sh2, sh2->r[15], sh2->pc );\r
eaa10a6e 1768\r
f4c0720c 1769 sh2->pc = RL( sh2, sh2->ea );\r
eaa10a6e 1770\r
f4c0720c 1771 sh2->icount -= 7;\r
eaa10a6e 1772}\r
1773\r
1774/* TST Rm,Rn */\r
f4c0720c 1775INLINE void TST(sh2_state *sh2, UINT32 m, UINT32 n)\r
eaa10a6e 1776{\r
1777 if ((sh2->r[n] & sh2->r[m]) == 0)\r
1778 sh2->sr |= T;\r
1779 else\r
1780 sh2->sr &= ~T;\r
1781}\r
1782\r
1783/* TST #imm,R0 */\r
f4c0720c 1784INLINE void TSTI(sh2_state *sh2, UINT32 i)\r
eaa10a6e 1785{\r
1786 UINT32 imm = i & 0xff;\r
1787\r
1788 if ((imm & sh2->r[0]) == 0)\r
1789 sh2->sr |= T;\r
1790 else\r
1791 sh2->sr &= ~T;\r
1792}\r
1793\r
1794/* TST.B #imm,@(R0,GBR) */\r
f4c0720c 1795INLINE void TSTM(sh2_state *sh2, UINT32 i)\r
eaa10a6e 1796{\r
1797 UINT32 imm = i & 0xff;\r
1798\r
1799 sh2->ea = sh2->gbr + sh2->r[0];\r
f4c0720c 1800 if ((imm & RB( sh2, sh2->ea )) == 0)\r
eaa10a6e 1801 sh2->sr |= T;\r
1802 else\r
1803 sh2->sr &= ~T;\r
f4c0720c 1804 sh2->icount -= 2;\r
eaa10a6e 1805}\r
1806\r
1807/* XOR Rm,Rn */\r
f4c0720c 1808INLINE void XOR(sh2_state *sh2, UINT32 m, UINT32 n)\r
eaa10a6e 1809{\r
1810 sh2->r[n] ^= sh2->r[m];\r
1811}\r
1812\r
1813/* XOR #imm,R0 */\r
f4c0720c 1814INLINE void XORI(sh2_state *sh2, UINT32 i)\r
eaa10a6e 1815{\r
1816 UINT32 imm = i & 0xff;\r
1817 sh2->r[0] ^= imm;\r
1818}\r
1819\r
1820/* XOR.B #imm,@(R0,GBR) */\r
f4c0720c 1821INLINE void XORM(sh2_state *sh2, UINT32 i)\r
eaa10a6e 1822{\r
1823 UINT32 imm = i & 0xff;\r
1824 UINT32 temp;\r
1825\r
1826 sh2->ea = sh2->gbr + sh2->r[0];\r
f4c0720c 1827 temp = RB( sh2, sh2->ea );\r
eaa10a6e 1828 temp ^= imm;\r
f4c0720c 1829 WB( sh2, sh2->ea, temp );\r
1830 sh2->icount -= 2;\r
eaa10a6e 1831}\r
1832\r
1833/* XTRCT Rm,Rn */\r
f4c0720c 1834INLINE void XTRCT(sh2_state *sh2, UINT32 m, UINT32 n)\r
eaa10a6e 1835{\r
1836 UINT32 temp;\r
1837\r
1838 temp = (sh2->r[m] << 16) & 0xffff0000;\r
1839 sh2->r[n] = (sh2->r[n] >> 16) & 0x0000ffff;\r
1840 sh2->r[n] |= temp;\r
1841}\r
1842\r
1843/*****************************************************************************\r
1844 * OPCODE DISPATCHERS\r
1845 *****************************************************************************/\r
1846\r
f4c0720c 1847INLINE void op0000(sh2_state *sh2, UINT16 opcode)\r
eaa10a6e 1848{\r
1849 switch (opcode & 0x3F)\r
1850 {\r
f4c0720c 1851 case 0x00: ILLEGAL(sh2); rlog(0); break;\r
1852 case 0x01: ILLEGAL(sh2); rlog(0); break;\r
1853 case 0x02: STCSR(sh2, Rn); rlog(LRN); break;\r
1854 case 0x03: BSRF(sh2, Rn); rlog(LRN); break;\r
1855 case 0x04: MOVBS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
1856 case 0x05: MOVWS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
1857 case 0x06: MOVLS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
1858 case 0x07: MULL(sh2, Rm, Rn); rlog(LRNM); rlog1(SHR_MACL); break;\r
1859 case 0x08: CLRT(sh2); rlog(0); break;\r
71f68165 1860 case 0x09: NOP(); rlog(0); break;\r
f4c0720c 1861 case 0x0a: STSMACH(sh2, Rn); rlog(LRN); rlog1(SHR_MACH); break;\r
1862 case 0x0b: RTS(sh2); rlog(0); rlog1(SHR_PR); break;\r
1863 case 0x0c: MOVBL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
1864 case 0x0d: MOVWL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
1865 case 0x0e: MOVLL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
1866 case 0x0f: MAC_L(sh2, Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;\r
1867\r
1868 case 0x10: ILLEGAL(sh2); rlog(0); break;\r
1869 case 0x11: ILLEGAL(sh2); rlog(0); break;\r
1870 case 0x12: STCGBR(sh2, Rn); rlog(LRN); rlog1(SHR_GBR); break;\r
1871 case 0x13: ILLEGAL(sh2); rlog(0); break;\r
1872 case 0x14: MOVBS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
1873 case 0x15: MOVWS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
1874 case 0x16: MOVLS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
1875 case 0x17: MULL(sh2, Rm, Rn); rlog(LRNM); rlog1(SHR_MACL); break;\r
1876 case 0x18: SETT(sh2); rlog(0); break;\r
1877 case 0x19: DIV0U(sh2); rlog(0); break;\r
1878 case 0x1a: STSMACL(sh2, Rn); rlog(LRN); rlog1(SHR_MACL); break;\r
1879 case 0x1b: SLEEP(sh2); rlog(0); break;\r
1880 case 0x1c: MOVBL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
1881 case 0x1d: MOVWL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
1882 case 0x1e: MOVLL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
1883 case 0x1f: MAC_L(sh2, Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;\r
1884\r
1885 case 0x20: ILLEGAL(sh2); rlog(0); break;\r
1886 case 0x21: ILLEGAL(sh2); rlog(0); break;\r
1887 case 0x22: STCVBR(sh2, Rn); rlog(LRN); rlog1(SHR_VBR); break;\r
1888 case 0x23: BRAF(sh2, Rn); rlog(LRN); break;\r
1889 case 0x24: MOVBS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
1890 case 0x25: MOVWS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
1891 case 0x26: MOVLS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
1892 case 0x27: MULL(sh2, Rm, Rn); rlog(LRNM); rlog1(SHR_MACL); break;\r
1893 case 0x28: CLRMAC(sh2); rlog(0); rlog2(SHR_MACL,SHR_MACH); break;\r
1894 case 0x29: MOVT(sh2, Rn); rlog(LRN); break;\r
1895 case 0x2a: STSPR(sh2, Rn); rlog(LRN); rlog1(SHR_PR); break;\r
1896 case 0x2b: RTE(sh2); rlog(0); break;\r
1897 case 0x2c: MOVBL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
1898 case 0x2d: MOVWL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
1899 case 0x2e: MOVLL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
1900 case 0x2f: MAC_L(sh2, Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;\r
1901\r
1902 case 0x30: ILLEGAL(sh2); rlog(0); break;\r
1903 case 0x31: ILLEGAL(sh2); rlog(0); break;\r
1904 case 0x32: ILLEGAL(sh2); rlog(0); break;\r
1905 case 0x33: ILLEGAL(sh2); rlog(0); break;\r
1906 case 0x34: MOVBS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
1907 case 0x35: MOVWS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
1908 case 0x36: MOVLS0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
1909 case 0x37: MULL(sh2, Rm, Rn); rlog(LRNM); rlog1(SHR_MACL); break;\r
1910 case 0x38: ILLEGAL(sh2); rlog(0); break;\r
1911 case 0x39: ILLEGAL(sh2); rlog(0); break;\r
1912 case 0x3c: MOVBL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
1913 case 0x3d: MOVWL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
1914 case 0x3e: MOVLL0(sh2, Rm, Rn); rlog(LRNM); rlog1(0); break;\r
1915 case 0x3f: MAC_L(sh2, Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;\r
1916 case 0x3a: ILLEGAL(sh2); rlog(0); break;\r
1917 case 0x3b: ILLEGAL(sh2); rlog(0); break;\r
eaa10a6e 1918 }\r
1919}\r
1920\r
f4c0720c 1921INLINE void op0001(sh2_state *sh2, UINT16 opcode)\r
eaa10a6e 1922{\r
f4c0720c 1923 MOVLS4(sh2, Rm, opcode & 0x0f, Rn);\r
71f68165 1924 rlog(LRNM);\r
eaa10a6e 1925}\r
1926\r
f4c0720c 1927INLINE void op0010(sh2_state *sh2, UINT16 opcode)\r
eaa10a6e 1928{\r
1929 switch (opcode & 15)\r
1930 {\r
f4c0720c 1931 case 0: MOVBS(sh2, Rm, Rn); rlog(LRNM); break;\r
1932 case 1: MOVWS(sh2, Rm, Rn); rlog(LRNM); break;\r
1933 case 2: MOVLS(sh2, Rm, Rn); rlog(LRNM); break;\r
1934 case 3: ILLEGAL(sh2); rlog(0); break;\r
1935 case 4: MOVBM(sh2, Rm, Rn); rlog(LRNM); break;\r
1936 case 5: MOVWM(sh2, Rm, Rn); rlog(LRNM); break;\r
1937 case 6: MOVLM(sh2, Rm, Rn); rlog(LRNM); break;\r
1938 case 7: DIV0S(sh2, Rm, Rn); rlog(LRNM); break;\r
1939 case 8: TST(sh2, Rm, Rn); rlog(LRNM); break;\r
1940 case 9: AND(sh2, Rm, Rn); rlog(LRNM); break;\r
1941 case 10: XOR(sh2, Rm, Rn); rlog(LRNM); break;\r
1942 case 11: OR(sh2, Rm, Rn); rlog(LRNM); break;\r
1943 case 12: CMPSTR(sh2, Rm, Rn); rlog(LRNM); break;\r
1944 case 13: XTRCT(sh2, Rm, Rn); rlog(LRNM); break;\r
1945 case 14: MULU(sh2, Rm, Rn); rlog(LRNM); rlog1(SHR_MACL); break;\r
1946 case 15: MULS(sh2, Rm, Rn); rlog(LRNM); rlog1(SHR_MACL); break;\r
eaa10a6e 1947 }\r
1948}\r
1949\r
f4c0720c 1950INLINE void op0011(sh2_state *sh2, UINT16 opcode)\r
eaa10a6e 1951{\r
1952 switch (opcode & 15)\r
1953 {\r
f4c0720c 1954 case 0: CMPEQ(sh2, Rm, Rn); rlog(LRNM); break;\r
1955 case 1: ILLEGAL(sh2); rlog(0); break;\r
1956 case 2: CMPHS(sh2, Rm, Rn); rlog(LRNM); break;\r
1957 case 3: CMPGE(sh2, Rm, Rn); rlog(LRNM); break;\r
1958 case 4: DIV1(sh2, Rm, Rn); rlog(LRNM); break;\r
1959 case 5: DMULU(sh2, Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;\r
1960 case 6: CMPHI(sh2, Rm, Rn); rlog(LRNM); break;\r
1961 case 7: CMPGT(sh2, Rm, Rn); rlog(LRNM); break;\r
1962 case 8: SUB(sh2, Rm, Rn); rlog(LRNM); break;\r
1963 case 9: ILLEGAL(sh2); rlog(0); break;\r
1964 case 10: SUBC(sh2, Rm, Rn); rlog(LRNM); break;\r
1965 case 11: SUBV(sh2, Rm, Rn); rlog(LRNM); break;\r
1966 case 12: ADD(sh2, Rm, Rn); rlog(LRNM); break;\r
1967 case 13: DMULS(sh2, Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;\r
1968 case 14: ADDC(sh2, Rm, Rn); rlog(LRNM); break;\r
1969 case 15: ADDV(sh2, Rm, Rn); rlog(LRNM); break;\r
eaa10a6e 1970 }\r
1971}\r
1972\r
f4c0720c 1973INLINE void op0100(sh2_state *sh2, UINT16 opcode)\r
eaa10a6e 1974{\r
1975 switch (opcode & 0x3F)\r
1976 {\r
f4c0720c 1977 case 0x00: SHLL(sh2, Rn); rlog(LRN); break;\r
1978 case 0x01: SHLR(sh2, Rn); rlog(LRN); break;\r
1979 case 0x02: STSMMACH(sh2, Rn); rlog(LRN); rlog1(SHR_MACH); break;\r
1980 case 0x03: STCMSR(sh2, Rn); rlog(LRN); break;\r
1981 case 0x04: ROTL(sh2, Rn); rlog(LRN); break;\r
1982 case 0x05: ROTR(sh2, Rn); rlog(LRN); break;\r
1983 case 0x06: LDSMMACH(sh2, Rn); rlog(LRN); rlog1(SHR_MACH); break;\r
1984 case 0x07: LDCMSR(sh2, Rn); rlog(LRN); break;\r
1985 case 0x08: SHLL2(sh2, Rn); rlog(LRN); break;\r
1986 case 0x09: SHLR2(sh2, Rn); rlog(LRN); break;\r
1987 case 0x0a: LDSMACH(sh2, Rn); rlog(LRN); rlog1(SHR_MACH); break;\r
1988 case 0x0b: JSR(sh2, Rn); rlog(LRN); rlog1(SHR_PR); break;\r
1989 case 0x0c: ILLEGAL(sh2); rlog(0); break;\r
1990 case 0x0d: ILLEGAL(sh2); rlog(0); break;\r
1991 case 0x0e: LDCSR(sh2, Rn); rlog(LRN); break;\r
1992 case 0x0f: MAC_W(sh2, Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;\r
1993\r
1994 case 0x10: DT(sh2, Rn); rlog(LRN); break;\r
1995 case 0x11: CMPPZ(sh2, Rn); rlog(LRN); break;\r
1996 case 0x12: STSMMACL(sh2, Rn); rlog(LRN); rlog1(SHR_MACL); break;\r
1997 case 0x13: STCMGBR(sh2, Rn); rlog(LRN); rlog1(SHR_GBR); break;\r
1998 case 0x14: ILLEGAL(sh2); rlog(0); break;\r
1999 case 0x15: CMPPL(sh2, Rn); rlog(LRN); break;\r
2000 case 0x16: LDSMMACL(sh2, Rn); rlog(LRN); rlog1(SHR_MACL); break;\r
2001 case 0x17: LDCMGBR(sh2, Rn); rlog(LRN); rlog1(SHR_GBR); break;\r
2002 case 0x18: SHLL8(sh2, Rn); rlog(LRN); break;\r
2003 case 0x19: SHLR8(sh2, Rn); rlog(LRN); break;\r
2004 case 0x1a: LDSMACL(sh2, Rn); rlog(LRN); rlog1(SHR_MACL); break;\r
2005 case 0x1b: TAS(sh2, Rn); rlog(LRN); break;\r
2006 case 0x1c: ILLEGAL(sh2); rlog(0); break;\r
2007 case 0x1d: ILLEGAL(sh2); rlog(0); break;\r
2008 case 0x1e: LDCGBR(sh2, Rn); rlog(LRN); rlog1(SHR_GBR); break;\r
2009 case 0x1f: MAC_W(sh2, Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;\r
2010\r
2011 case 0x20: SHAL(sh2, Rn); rlog(LRN); break;\r
2012 case 0x21: SHAR(sh2, Rn); rlog(LRN); break;\r
2013 case 0x22: STSMPR(sh2, Rn); rlog(LRN); rlog1(SHR_PR); break;\r
2014 case 0x23: STCMVBR(sh2, Rn); rlog(LRN); rlog1(SHR_VBR); break;\r
2015 case 0x24: ROTCL(sh2, Rn); rlog(LRN); break;\r
2016 case 0x25: ROTCR(sh2, Rn); rlog(LRN); break;\r
2017 case 0x26: LDSMPR(sh2, Rn); rlog(LRN); rlog1(SHR_PR); break;\r
2018 case 0x27: LDCMVBR(sh2, Rn); rlog(LRN); rlog1(SHR_VBR); break;\r
2019 case 0x28: SHLL16(sh2, Rn); rlog(LRN); break;\r
2020 case 0x29: SHLR16(sh2, Rn); rlog(LRN); break;\r
2021 case 0x2a: LDSPR(sh2, Rn); rlog(LRN); rlog1(SHR_PR); break;\r
2022 case 0x2b: JMP(sh2, Rn); rlog(LRN); break;\r
2023 case 0x2c: ILLEGAL(sh2); rlog(0); break;\r
2024 case 0x2d: ILLEGAL(sh2); rlog(0); break;\r
2025 case 0x2e: LDCVBR(sh2, Rn); rlog(LRN); rlog1(SHR_VBR); break;\r
2026 case 0x2f: MAC_W(sh2, Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;\r
71f68165 2027\r
2028 case 0x30:\r
2029 case 0x31:\r
2030 case 0x32:\r
2031 case 0x33:\r
2032 case 0x34:\r
2033 case 0x35:\r
2034 case 0x36:\r
2035 case 0x37:\r
2036 case 0x38:\r
2037 case 0x39:\r
2038 case 0x3a:\r
2039 case 0x3b:\r
2040 case 0x3c:\r
2041 case 0x3d:\r
f4c0720c 2042 case 0x3e: ILLEGAL(sh2); rlog(0); break;\r
2043 case 0x3f: MAC_W(sh2, Rm, Rn); rlog(LRNM); rlog2(SHR_MACL,SHR_MACH); break;\r
eaa10a6e 2044 }\r
2045}\r
2046\r
f4c0720c 2047INLINE void op0101(sh2_state *sh2, UINT16 opcode)\r
eaa10a6e 2048{\r
f4c0720c 2049 MOVLL4(sh2, Rm, opcode & 0x0f, Rn);\r
71f68165 2050 rlog(LRNM);\r
eaa10a6e 2051}\r
2052\r
f4c0720c 2053INLINE void op0110(sh2_state *sh2, UINT16 opcode)\r
eaa10a6e 2054{\r
2055 switch (opcode & 15)\r
2056 {\r
f4c0720c 2057 case 0: MOVBL(sh2, Rm, Rn); break;\r
2058 case 1: MOVWL(sh2, Rm, Rn); break;\r
2059 case 2: MOVLL(sh2, Rm, Rn); break;\r
2060 case 3: MOV(sh2, Rm, Rn); break;\r
2061 case 4: MOVBP(sh2, Rm, Rn); break;\r
2062 case 5: MOVWP(sh2, Rm, Rn); break;\r
2063 case 6: MOVLP(sh2, Rm, Rn); break;\r
2064 case 7: NOT(sh2, Rm, Rn); break;\r
2065 case 8: SWAPB(sh2, Rm, Rn); break;\r
2066 case 9: SWAPW(sh2, Rm, Rn); break;\r
2067 case 10: NEGC(sh2, Rm, Rn); break;\r
2068 case 11: NEG(sh2, Rm, Rn); break;\r
2069 case 12: EXTUB(sh2, Rm, Rn); break;\r
2070 case 13: EXTUW(sh2, Rm, Rn); break;\r
2071 case 14: EXTSB(sh2, Rm, Rn); break;\r
2072 case 15: EXTSW(sh2, Rm, Rn); break;\r
eaa10a6e 2073 }\r
71f68165 2074 rlog(LRNM);\r
eaa10a6e 2075}\r
2076\r
f4c0720c 2077INLINE void op0111(sh2_state *sh2, UINT16 opcode)\r
eaa10a6e 2078{\r
f4c0720c 2079 ADDI(sh2, opcode & 0xff, Rn);\r
71f68165 2080 rlog(LRN);\r
eaa10a6e 2081}\r
2082\r
f4c0720c 2083INLINE void op1000(sh2_state *sh2, UINT16 opcode)\r
eaa10a6e 2084{\r
2085 switch ( opcode & (15<<8) )\r
2086 {\r
f4c0720c 2087 case 0<< 8: MOVBS4(sh2, opcode & 0x0f, Rm); rlog(LRM); rlog1(0); break;\r
2088 case 1<< 8: MOVWS4(sh2, opcode & 0x0f, Rm); rlog(LRM); rlog1(0); break;\r
2089 case 2<< 8: ILLEGAL(sh2); rlog(0); break;\r
2090 case 3<< 8: ILLEGAL(sh2); rlog(0); break;\r
2091 case 4<< 8: MOVBL4(sh2, Rm, opcode & 0x0f); rlog(LRM); rlog1(0); break;\r
2092 case 5<< 8: MOVWL4(sh2, Rm, opcode & 0x0f); rlog(LRM); rlog1(0); break;\r
2093 case 6<< 8: ILLEGAL(sh2); rlog(0); break;\r
2094 case 7<< 8: ILLEGAL(sh2); rlog(0); break;\r
2095 case 8<< 8: CMPIM(sh2, opcode & 0xff); rlog(0); rlog1(0); break;\r
2096 case 9<< 8: BT(sh2, opcode & 0xff); rlog(0); break;\r
2097 case 10<< 8: ILLEGAL(sh2); rlog(0); break;\r
2098 case 11<< 8: BF(sh2, opcode & 0xff); rlog(0); break;\r
2099 case 12<< 8: ILLEGAL(sh2); rlog(0); break;\r
2100 case 13<< 8: BTS(sh2, opcode & 0xff); rlog(0); break;\r
2101 case 14<< 8: ILLEGAL(sh2); rlog(0); break;\r
2102 case 15<< 8: BFS(sh2, opcode & 0xff); rlog(0); break;\r
eaa10a6e 2103 }\r
2104}\r
2105\r
2106\r
f4c0720c 2107INLINE void op1001(sh2_state *sh2, UINT16 opcode)\r
eaa10a6e 2108{\r
f4c0720c 2109 MOVWI(sh2, opcode & 0xff, Rn);\r
71f68165 2110 rlog(LRN);\r
eaa10a6e 2111}\r
2112\r
f4c0720c 2113INLINE void op1010(sh2_state *sh2, UINT16 opcode)\r
eaa10a6e 2114{\r
f4c0720c 2115 BRA(sh2, opcode & 0xfff);\r
71f68165 2116 rlog(0);\r
eaa10a6e 2117}\r
2118\r
f4c0720c 2119INLINE void op1011(sh2_state *sh2, UINT16 opcode)\r
eaa10a6e 2120{\r
f4c0720c 2121 BSR(sh2, opcode & 0xfff);\r
71f68165 2122 rlog(0);\r
2123 rlog1(SHR_PR);\r
eaa10a6e 2124}\r
2125\r
f4c0720c 2126INLINE void op1100(sh2_state *sh2, UINT16 opcode)\r
eaa10a6e 2127{\r
2128 switch (opcode & (15<<8))\r
2129 {\r
f4c0720c 2130 case 0<<8: MOVBSG(sh2, opcode & 0xff); rlog2(0, SHR_GBR); break;\r
2131 case 1<<8: MOVWSG(sh2, opcode & 0xff); rlog2(0, SHR_GBR); break;\r
2132 case 2<<8: MOVLSG(sh2, opcode & 0xff); rlog2(0, SHR_GBR); break;\r
2133 case 3<<8: TRAPA(sh2, opcode & 0xff); rlog1(SHR_VBR); break;\r
2134 case 4<<8: MOVBLG(sh2, opcode & 0xff); rlog2(0, SHR_GBR); break;\r
2135 case 5<<8: MOVWLG(sh2, opcode & 0xff); rlog2(0, SHR_GBR); break;\r
2136 case 6<<8: MOVLLG(sh2, opcode & 0xff); rlog2(0, SHR_GBR); break;\r
2137 case 7<<8: MOVA(sh2, opcode & 0xff); rlog1(0); break;\r
2138 case 8<<8: TSTI(sh2, opcode & 0xff); rlog1(0); break;\r
2139 case 9<<8: ANDI(sh2, opcode & 0xff); rlog1(0); break;\r
2140 case 10<<8: XORI(sh2, opcode & 0xff); rlog1(0); break;\r
2141 case 11<<8: ORI(sh2, opcode & 0xff); rlog1(0); break;\r
2142 case 12<<8: TSTM(sh2, opcode & 0xff); rlog2(0, SHR_GBR); break;\r
2143 case 13<<8: ANDM(sh2, opcode & 0xff); rlog2(0, SHR_GBR); break;\r
2144 case 14<<8: XORM(sh2, opcode & 0xff); rlog2(0, SHR_GBR); break;\r
2145 case 15<<8: ORM(sh2, opcode & 0xff); rlog2(0, SHR_GBR); break;\r
eaa10a6e 2146 }\r
71f68165 2147 rlog(0);\r
eaa10a6e 2148}\r
2149\r
f4c0720c 2150INLINE void op1101(sh2_state *sh2, UINT16 opcode)\r
eaa10a6e 2151{\r
f4c0720c 2152 MOVLI(sh2, opcode & 0xff, Rn);\r
71f68165 2153 rlog(LRN);\r
eaa10a6e 2154}\r
2155\r
f4c0720c 2156INLINE void op1110(sh2_state *sh2, UINT16 opcode)\r
eaa10a6e 2157{\r
f4c0720c 2158 MOVI(sh2, opcode & 0xff, Rn);\r
71f68165 2159 rlog(LRN);\r
eaa10a6e 2160}\r
2161\r
f4c0720c 2162INLINE void op1111(sh2_state *sh2, UINT16 opcode)\r
eaa10a6e 2163{\r
f4c0720c 2164 ILLEGAL(sh2);\r
71f68165 2165 rlog(0);\r
eaa10a6e 2166}\r
2167\r
2168#endif\r
fast MegaDrive/MegaCD/32X emulator