32x: change irq hadling, make it more drc friendly
[picodrive.git] / cpu / sh2 / mame / sh2pico.c
CommitLineData
41397701 1#include "../sh2.h"
eaa10a6e 2
3// MAME types
4typedef signed char INT8;
5typedef signed short INT16;
6typedef signed int INT32;
7typedef unsigned int UINT32;
8typedef unsigned short UINT16;
9typedef unsigned char UINT8;
10
b78efee2 11#define RB(a) p32x_sh2_read8(a,sh2->is_slave)
12#define RW(a) p32x_sh2_read16(a,sh2->is_slave)
13#define RL(a) p32x_sh2_read32(a,sh2->is_slave)
14#define WB(a,d) p32x_sh2_write8(a,d,sh2->is_slave)
15#define WW(a,d) p32x_sh2_write16(a,d,sh2->is_slave)
16#define WL(a,d) p32x_sh2_write32(a,d,sh2->is_slave)
eaa10a6e 17
18// some stuff from sh2comn.h
19#define T 0x00000001
20#define S 0x00000002
21#define I 0x000000f0
22#define Q 0x00000100
23#define M 0x00000200
24
25#define AM 0xc7ffffff
26
27#define FLAGS (M|Q|I|S|T)
28
29#define Rn ((opcode>>8)&15)
30#define Rm ((opcode>>4)&15)
31
41397701 32#define sh2_icount sh2->icount
1d7a28a7 33
41397701 34#include "sh2.c"
1d7a28a7 35
679af8a3 36#ifndef DRC_TMP
37
41397701 38void sh2_execute(SH2 *sh2_, int cycles)
eaa10a6e 39{
40 sh2 = sh2_;
2ea2cbfe 41 sh2->cycles_aim += cycles;
41397701 42 sh2->icount = cycles = sh2->cycles_aim - sh2->cycles_done;
43
44 if (sh2->icount <= 0)
45 return;
eaa10a6e 46
47 do
48 {
49 UINT32 opcode;
50
6add7875 51 if (sh2->test_irq && !sh2->delay && sh2->pending_level > ((sh2->sr >> 4) & 0x0f))
52 {
53 if (sh2->pending_irl > sh2->pending_int_irq)
54 sh2_do_irq(sh2, sh2->pending_irl, 64 + sh2->pending_irl/2);
55 else {
56 sh2_do_irq(sh2, sh2->pending_int_irq, sh2->pending_int_vector);
57 sh2->pending_int_irq = 0; // auto-clear
58 sh2->pending_level = sh2->pending_irl;
59 }
60 sh2->test_irq = 0;
61 }
62
3cf9570b 63 if (sh2->delay)
64 {
a44737c1 65 sh2->ppc = sh2->delay;
3cf9570b 66 opcode = RW(sh2->delay);
67 sh2->pc -= 2;
68 }
69 else
a44737c1 70 {
71 sh2->ppc = sh2->pc;
3cf9570b 72 opcode = RW(sh2->pc);
a44737c1 73 }
eaa10a6e 74
75 sh2->delay = 0;
76 sh2->pc += 2;
eaa10a6e 77
78 switch (opcode & ( 15 << 12))
79 {
80 case 0<<12: op0000(opcode); break;
81 case 1<<12: op0001(opcode); break;
82 case 2<<12: op0010(opcode); break;
83 case 3<<12: op0011(opcode); break;
84 case 4<<12: op0100(opcode); break;
85 case 5<<12: op0101(opcode); break;
86 case 6<<12: op0110(opcode); break;
87 case 7<<12: op0111(opcode); break;
88 case 8<<12: op1000(opcode); break;
89 case 9<<12: op1001(opcode); break;
90 case 10<<12: op1010(opcode); break;
91 case 11<<12: op1011(opcode); break;
92 case 12<<12: op1100(opcode); break;
93 case 13<<12: op1101(opcode); break;
94 case 14<<12: op1110(opcode); break;
95 default: op1111(opcode); break;
96 }
97
41397701 98 sh2->icount--;
eaa10a6e 99 }
41397701 100 while (sh2->icount > 0 || sh2->delay); /* can't interrupt before delay */
4ea707e1 101
41397701 102 sh2->cycles_done += cycles - sh2->icount;
4ea707e1 103}
eaa10a6e 104
679af8a3 105#else // DRC_TMP
106
107// tmp
108void __attribute__((regparm(2))) sh2_do_op(SH2 *sh2_, int opcode)
109{
110 sh2 = sh2_;
111 sh2->pc += 2;
112
113 switch (opcode & ( 15 << 12))
114 {
115 case 0<<12: op0000(opcode); break;
116 case 1<<12: op0001(opcode); break;
117 case 2<<12: op0010(opcode); break;
118 case 3<<12: op0011(opcode); break;
119 case 4<<12: op0100(opcode); break;
120 case 5<<12: op0101(opcode); break;
121 case 6<<12: op0110(opcode); break;
122 case 7<<12: op0111(opcode); break;
123 case 8<<12: op1000(opcode); break;
124 case 9<<12: op1001(opcode); break;
125 case 10<<12: op1010(opcode); break;
126 case 11<<12: op1011(opcode); break;
127 case 12<<12: op1100(opcode); break;
128 case 13<<12: op1101(opcode); break;
129 case 14<<12: op1110(opcode); break;
130 default: op1111(opcode); break;
131 }
679af8a3 132}
133
134#endif
135